//     Copyright (c) 2022 SMIC             
//     Filename:      RAM512.mbist
//     IP code:       S018RF2P
//     Version:       0.2.b
//     CreateDate:    Oct 31, 2022        
                    
//    Mentor Mbist for 2-PORT Register File
//    SMIC 0.18um G Logic Process

//    Configuration: -instname RAM512 -rows 128 -bits 24 -mux 4 
//    Redundancy: Off
 //   Bit-Write: Off

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model RAM512(QA, AA, CLKA, CENA, AB, DB, CLKB, CENB)
(
   bist_definition (
      address        AA (array = 8:0;);
      data_out       QA (array = 23:0;);
      read_enable    CENA low;
      clock          CLKA high;
      address        AB (array = 8:0;);
      data_in        DB (array = 23:0;);
      write_enable   CENB low;
      clock          CLKB high;
      
      

      tech        = "SRAM (0.18um)";
      vendor      = SMIC;
      min_address = 0;
      max_address = 511;
      message     = "Synchronous 2-Port 512x24 SRAM";

      top_column  = 4;
      addr_inc    = 4;
      top_word    = 1;

     read_write_port (
         read_cycle (
            change AA;
            assert CENA;
            wait;
            wait;
            expect QA move;
            wait;
         )
         write_cycle (
            change AB;
            change DB;
            assert CENB;
             wait;
             wait;
         )
      )

   )
)