# Rule: # Power/Ground naming start with VDD/VSS # next step to do: # 1. add all the Power/Group . e.g PLL/ # 2. add macro connection (/home/xian001/temp_work/upf/macro.upf) # 3. iso setting : /home/xian001/temp_work/upf/syn13_upf_var.tcl source /home/xian001/temp_work/upf/syn13_upf_var.tcl ###################### set_design_top sy13 set_scope . ################################ #######create power domain ################################# # ae210_chip is power_domian 1 # sys_top is power_domain 2 # create_power_domain PD_TOP -include_scope create_power_domain PD_sys -elements {u_mcu/u_sys_top} create_power_domain PD_ae210 -elements {ae210_chip/ae210_core} #################### ###create_power_supply port ################## create_supply_port VDD -domain PD_TOP -direction in create_supply_port VSS -domain PD_TOP -direction in # create_supply_port VDD_IO -domain PD_TOP -direction in #################### ###create_power_supply net ################## create_supply_net VDD -domain PD_TOP create_supply_net VSS -domain PD_TOP create_supply_net VDD_IO -domain PD_TOP create_supply_net VDD_sys -domain PD_sys create_supply_net VSS -domain PD_sys -reuse create_supply_net VDD -domain PD_sys -reuse create_supply_net VDD_ae210 -domain PD_ae210 create_supply_net VSS -domain PD_ae210 -reuse create_supply_net VDD -domain PD_ae210 -reuse ##################### #connect power supplu net with power supply port ##################### connect_supply_net VDD -ports {VDD} connect_supply_net VSS -ports {VSS} connect_supply_net VDD_IO -ports {VDD_IO} ##################### #set domain supply net ##################### set_domain_supply_net PD_TOP -primary_power_net {VDD} -primary_ground_net {VSS} set_domain_supply_net PD_sys -primary_power_net {VDD_sys} -primary_ground_net {VSS} set_domain_supply_net PD_ae210 -primary_power_net {VDD_ae210} -primary_ground_net {VSS} ########################## #create power switch ########################## create_power_switch ps_ae210 -domain PD_ae210 \ -input_supply_port {VDDP VDD } \ -output_supply_port {VDDC VDD_ae210 } \ -control_port {ENXB u_mcu/u_aoss_wrap/N10PwrReq } \ -control_port {EN u_mcu/u_aoss_wrap/N10PwrReq } \ -on_state {ON VDDP {!ENXB & EN}} \ -off_state {OFF {ENXB & !EN}} create_power_switch ps_sys -domain PD_sys \ -input_supply_port {VDDP VDD } \ -output_supply_port {VDDC VDD_sys } \ -control_port {ENXB u_mcu/u_aoss_wrap/sp_pwroff_req } \ -control_port {EN u_mcu/u_aoss_wrap/sp_pwroff_req } \ -on_state {ON VDDP {!ENXB & EN}} \ -off_state {OFF {ENXB & !EN}} ############################ #map power switch ############## map_power_switch ps_sys -domain PD_sys -lib_cells {ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 \ ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12} map_power_switch ps_ae210 -domain PD_ae210 -lib_cells {ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 \ ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12} # Warning: The library cell ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 specified in the command is not found and is ignored. (UPF-126) # Warning: The library cell ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12 specified in the command is not found and is ignored. (UPF-126) # Warning: Unable to find a match for some of the library cells specified. (UPF-091) ############################### #creat_isolation_cell ####################### ################################ set_isolation PD_sys_clamp_low -domain PD_sys \ -clamp_value 0 \ -applies_to outputs \ -elements $PD_sys_ISO_0 \ -isolation_power_net VDD \ -isolation_ground_net VSS set_isolation_control PD_sys_clamp_low -domain PD_sys \ -isolation_signal {u_mcu/u_aoss_wrap/u_pmu/pmu_ctrl_iso_en} \ -isolation_sense {low} \ -location {parent} map_isolation_cell PD_sys_clamp_low -domain PD_sys -lib_cells {PEH_ISOS1CL0_W_8} ################################ set_isolation PD_ae210_clamp_low -domain PD_ae210 \ -isolation_power_net VDD \ -isolation_ground_net VSS \ -clamp_value 0 \ -applies_to outputs \ -elements $PD_ae120_ISO_0 #set_isolation PD_ae210_clamp_high -domain PD_ae210 \ # -isolation_power_net VDD \ # -isolation_ground_net VSS \ # -clamp_value 1 \ # -applies_to outputs # -element {} set_isolation_control PD_ae210_clamp_low -domain PD_ae210 \ -isolation_signal {u_mcu/u_aoss_wrap/N10IsoEn} \ -isolation_sense {low} \ -location {parent} #set_isolation_control PD_ae210_clamp_high -domain PD_ae210 \ # -isolation_signal {u_mcu/u_sys_top/SppIsoEn} \ # -isolation_sense {low} \ # -location {parent} map_isolation_cell PD_ae210_clamp_low -domain PD_ae210 -lib_cells {PEH_ISOS1CL0_W_8} #map_isolation_cell PD_ae210_clamp_high -domain PD_ae210 -lib_cells {PEH_ISOS0CL1_W_8} ################################ #set_design_attributes -attribute SNPS_reinit TRUE ################################ # PST add_port_state VDD -state {as_fast 1.21} -state {as_slow 0.99} -state {dis off} add_port_state VSS -state {ena 0} -state {dis off} add_port_state ps_sys/VDDC -state {as_fast 1.21} -state {as_slow 0.99} -state {dis off} add_port_state ps_ae210/VDDC -state {as_fast 1.21} -state {as_slow 0.99} -state {dis off} create_pst syn13_pst \ -supplies {VDD VDD_sys VDD_ae210 VSS} add_pst_state all_on -pst syn13_pst -state {as_fast as_fast as_fast ena} add_pst_state sys_off -pst syn13_pst -state {as_fast dis as_fast ena} add_pst_state all_off -pst syn13_pst -state {dis dis dis dis}