16 lines
226 B
Verilog
16 lines
226 B
Verilog
module main();
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// outports wire
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wire clkout;
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clkdiv u_clkdiv(
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.clk50 ( clk50 ),
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.rst_n ( rst_n ),
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.clkout ( clkout )
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);
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endmodule //main
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