26 lines
422 B
Verilog
26 lines
422 B
Verilog
`include "../src/MyCpu.v"
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module testBench();
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reg clock;
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reg reset;
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initial begin
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$display("begin simulate");
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$dumpfile("../simulation/icarus/wave.vcd");
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$dumpvars;
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clock = 0;
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reset = 0;
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#20 reset = ~reset;
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#30000 $finish;
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end
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MyCpu u_MyCpu(
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.clock(clock),
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.reset(reset)
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);
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always #20 clock = ~clock;
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endmodule
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