448 lines
19 KiB
Plaintext
448 lines
19 KiB
Plaintext
2. Synopsys Commands Command Reference
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report_constraint
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NAME
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report_constraint
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Displays constraint-related information about a design.
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SYNTAX
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status report_constraint
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[-all_violators]
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[-verbose]
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[-significant_digits digits]
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[-max_area]
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[-max_delay]
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[-critical_range]
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[-min_delay]
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[-max_capacitance]
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[-min_capacitance]
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[-max_transition]
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[-max_fanout]
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[-cell_degradation]
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[-max_toggle_rate]
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[-min_porosity]
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[-max_dynamic_power]
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[-max_leakage_power]
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[-max_total_power]
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[-max_net_length]
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[-connection_class]
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[-multiport_net]
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[-nosplit]
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[-min_pulse_width]
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[-min_period]
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[-scenarios scenario_list]
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[-ignore_infeasible_paths]
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Data Types
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digits integer
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scenario_list list
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ARGUMENTS
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-all_violators
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Displays a summary of all of the optimization and design rule
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constraints with violations in the current design. The -verbose
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option provides detailed information about constraint viola-
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tions. Multiple violations for a given constraint are listed in
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order from largest to smallest violation.
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-verbose
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Displays more detail about constraint calculations.
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-significant_digits digits
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Specifies the number of digits to the right of the decimal point
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that are to be reported. The digits value must be between 0 and
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13. The default is 2. This option overrides the value set by
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the report_default_significant_digits variable.
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-max_area
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Displays only the max_area constraint information. The default
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behavior (without this option and similar options) is to display
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all optimization and design rule constraints.
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-max_delay
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Displays only the max_delay and setup information.
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-critical_range
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Displays only the critical_range information. The criti-
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cal_range is a design rule that directs the tool to optimize
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near-critical paths along with the most critical path.
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-min_delay
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Displays only the min_delay and hold information.
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-max_capacitance
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Displays only the max_capacitance constraint information. The
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max_capacitance constraint is a design rule that limits the
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total capacitance on a net.
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-min_capacitance
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Displays only the min_capacitance constraint information. The
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min_capacitance constraint is a design rule that ensures a mini-
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mum total capacitance on a net.
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-max_transition
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Displays only the max_transition constraint information. The
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max_transition constraint is a design rule that limits the tran-
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sition time on a net. If the library uses the cmos2 delay
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model, this option shows the max_edge_rate information.
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-max_fanout
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Displays only the max_fanout constraint information. The con-
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straint is a design rule that limits the fanout_load on a net.
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-cell_degradation
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Displays only the cell_degradation constraint information. The
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cell_degradation constraint is a design rule that limits the
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total capacitance on a net, with the limit depending on the
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transition times at the inputs of the cell.
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-max_toggle_rate
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Displays only the max_toggle_rate constraint information.
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-min_porosity
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Displays only the min_porosity constraint information. The
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min_porosity constraint is an optimization constraint for
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routability.
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-max_dynamic_power
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Displays only the max_dynamic_power constraint information. The
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default behavior (without this option and similar power-related
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options) is to display all types of power constraint informa-
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tion. Queries for power constraint information are valid only
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if a power-related license is available.
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-max_leakage_power
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Displays only the max_leakage_power constraint information.
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-max_total_power
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Displays only the max_total_power constraint information.
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-max_net_length
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Displays only max_net_length constraint information. The
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max_net_length constraint is a design rule that limits the route
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length of a net. For more information, see the man page for the
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set_max_net_length command.
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-connection_class
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Displays only the connection_class constraint information. The
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connection_class constraint is displayed only if there is a con-
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nection_class violation. For more information, see the man page
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for the set_connection_class command.
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-multiport_net
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Displays only the multiport_net constraint information. This
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constraint specifies whether multiple output ports can be con-
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nected to a given net. For more information, see the man page
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for the set_fix_multiple_port_nets command.
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-nosplit
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Prevents line splitting and facilitates writing applications to
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extract information from the report output. Most of the design
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information is listed in fixed-width columns. If the informa-
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tion for a given field exceeds the width of the column, the next
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field begins on a new line, starting in the correct column.
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-min_pulse_width
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Displays only the min_pulse_width constraint information. The
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min_pulse_width constraint is a design rule that limits the min-
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imum duration of clock pulses in the clock network.
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-min_period
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Displays only the minimum period constraint information. The
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min_period constraint is a design rule that sets a minimum
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period on a clock signal. The min_period check is supported only
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for ideal clocks.
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-scenarios scenario_list
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Reports constraints for the specified scenarios of a multi-sce-
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nario design. Each scenario is reported separately. Inactive
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scenarios are not reported.
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If you do not use this option, the report_constraint command
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reports constraints on all active scenarios, except when you use
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the -all_violators or -verbose option. If you use these options
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but not the -scenarios option, the report_constraint command
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reports constraints only on the current scenario.
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-ignore_infeasible_paths
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Ignores all the paths flagged as infeasible during the latest
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compilation.
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DESCRIPTION
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The report_constraint command displays the following information for
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the constraints on the current design:
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o Whether the constraint was violated or met
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o By how much the constraint value was violated or met
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o The design object that was the worst violator
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The maximum delay information shows cost by path group. This includes
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violations of setup time on registers or ports with output delay, as
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well as violations of set_max_delay commands. The total maximum delay
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cost is the sum of each group's weighted cost. For details on creating
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path groups, refer to the group_path command man page. To see the cur-
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rent path groups in the design, use the report_path_group command.
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The minimum delay cost includes violations of hold time on registers or
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ports with output delay as well as violations of set_min_delay com-
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mands.
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In the path delay reports, if a pin drives a high-fanout net, this is
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indicated in the report by a # symbol between the incremental and path
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timing values. Creation and usage of scenarios is available with
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Design Compiler Graphical.
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Multicorner-Multimode Support
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By default, this command uses information from all active scenarios.
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You can select different scenarios by using the -scenarios option.
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EXAMPLES
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The following example shows brief constraint information for the cur-
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rent design:
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prompt> report_constraint
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****************************************
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Report : constraint
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Design : counter
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Version: 1998.02
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Date : Fri Dec 26 15:49:46 1997
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****************************************
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Weighted
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Group (max_delay/setup) Cost Weight Cost
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-----------------------------------------------------
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CLK 0.00 1.00 0.00
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default 0.00 1.00 0.00
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-----------------------------------------------------
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max_delay/setup 0.00
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Total Neg Critical
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Group (critical_range) Slack Endpoints Cost
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-----------------------------------------------------
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CLK 0.00 0 0.00
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default 0.00 0 0.00
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-----------------------------------------------------
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critical_range 0.00
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Constraint Cost
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-----------------------------------------------------
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max_transition 0.00 (MET)
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max_fanout 0.00 (MET)
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max_delay/setup 0.00 (MET)
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sequential_clock_pulse_width 0.00 (MET)
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critical_range 0.00 (MET)
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min_delay/hold 0.40 (VIOLATED)
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max_leakage_power 6.00 (VIOLATED)
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max_dynamic_power 14.03 (VIOLATED)
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max_area 48.00 (VIOLATED)
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The following example displays detailed constraint information for the
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current design:
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prompt> report_constraint -verbose
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****************************************
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Report : constraint
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-verbose
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Design : counter
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Version: v3.1a
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Date : Tue 1992
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****************************************
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Startpoint: ffb (rising edge-triggered flip-flop clocked by CLK)
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Endpoint: ffd (rising edge-triggered flip-flop clocked by CLK)
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Path Group: CLK
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Path Type: max
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Point Incr Path
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-----------------------------------------------------------
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clock CLK (rise edge) 0.00 0.00
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startpoint clock skew (ideal) 0.00 0.00
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startpoint clock uncertainty 0.00 0.00
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ffb/CP (FD3) 0.00 0.00 r
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ffb/QN (FD3) 2.42 2.42 r
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w/Z (ND4) 0.59 3.01 f
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q/Z (EO) 1.13 4.14 f
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j/Z (AO2) 1.08 5.22 r
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ffd/D (FDS2) 0.00 5.22 r
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data arrival time 5.22
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clock CLK (rise edge) 10.00 10.00
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endpoint clock skew (ideal) 0.00 10.00
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endpoint clock uncertainty 0.00 10.00
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ffd/CP (FDS2) 0.00 10.00 r
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library setup time -0.90 9.10
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data required time 9.10
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-----------------------------------------------------------
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data required time 9.10
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data arrival time -5.22
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-----------------------------------------------------------
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slack (MET) 3.88
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Design: counter
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max_area 30.00
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- Current Area 78.00
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------------------------------
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Slack -48.00 (VIOLATED)
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Design: counter
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max_leakage_power 70.00
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- Current Leakage Power 76.00
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----------------------------------
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Slack -6.00 (VIOLATED)
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Design: counter
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max_dynamic_power 500.00
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- Current Dynamic Power 514.03
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----------------------------------
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Slack -14.03 (VIOLATED)
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The following example displays detailed information on only those con-
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straints that have violations:
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prompt> report_constraint -all_violators -verbose
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****************************************
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Report : constraint
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-all_violators
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-verbose
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Design : led
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Version: v3.2a
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Date : Tue Jan 3 13:00:45 1995
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****************************************
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Startpoint: b (input port)
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Endpoint: z5 (output port)
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Path Group: default
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Path Type: max
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Point Incr Path
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-----------------------------------------------------------
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input external delay 0.00 0.00 r
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b (in) 0.00 0.00 r
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U5/Z (IV) 1.32 1.32 f
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U3/Z (NR2) 3.35 4.67 r
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U18/Z (AO6) 0.73 5.40 f
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U22/Z (AO4) 1.42 6.82 r
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z5 (out) 0.00 6.82 r
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data arrival time 6.82
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max_delay 6.50 6.50
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output external delay 0.00 6.50
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data required time 6.50
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-----------------------------------------------------------
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data required time 6.50
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data arrival time -6.82
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-----------------------------------------------------------
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slack (VIOLATED) -0.32
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Startpoint: c (input port)
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Endpoint: z3 (output port)
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Path Group: default
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Path Type: max
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Point Incr Path
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-----------------------------------------------------------
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input external delay 0.00 0.00 r
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c (in) 0.00 0.00 r
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U6/Z (IV) 1.34 1.34 f
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U2/Z (NR2) 3.35 4.69 r
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U15/Z (AO7) 0.87 5.56 f
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U24/Z (AO3) 1.02 6.57 r
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z3 (out) 0.00 6.57 r
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data arrival time 6.57
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max_delay 6.50 6.50
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output external delay 0.00 6.50
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data required time 6.50
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-----------------------------------------------------------
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data required time 6.50
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data arrival time -6.57
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-----------------------------------------------------------
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slack (VIOLATED) -0.07
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Net: a
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max_transition 1.00
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- Transition Time 1.26
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------------------------------
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Slack -0.26 (VIOLATED)
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Net: a
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max_fanout 5.00
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- Fanout 7.00
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------------------------------
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Slack -2.00 (VIOLATED)
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Design: led
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max_area 30.00
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- Current Area 36.00
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------------------------------
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Slack -6.00 (VIOLATED)
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Design: led
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max_dynamic_power 1000.00
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- Current Dynamic Power 1254.81
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----------------------------------
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Slack -254.81 (VIOLATED)
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The following example displays the max_area, max_delay/setup,
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min_delay/hold, and max_leakage_power constraint information:
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prompt> report_constraint -max_area -max_delay -min_delay \
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-max_leakage_power
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****************************************
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Report : constraint
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-max_area
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-max_delay
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-min_delay
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-max_leakage_power
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Design : led
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Version: v3.2a
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Date : Tue Jan 3 13:00:56 1995
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****************************************
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Weighted
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Group (max_delay/setup) Cost Weight Cost
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-----------------------------------------------------
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default 0.32 1.00 0.32
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-----------------------------------------------------
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max_delay/setup 0.32
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Constraint Cost
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-----------------------------------------------------
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max_delay/setup 0.32 (VIOLATED)
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max_area 6.00 (VIOLATED)
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--------------------------------------------------------------------
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SEE ALSO
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create_clock(2)
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group_path(2)
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report_clock(2)
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report_design(2)
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report_path_group(2)
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report_timing(2)
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report_timing_requirements(2)
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report_min_pulse_width(2)
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set_critical_range(2)
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set_fix_multiple_port_nets(2)
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set_max_area(2)
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set_max_delay(2)
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set_max_dynamic_power(2)
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set_max_leakage_power(2)
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set_max_net_length(2)
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Version J-2014.09-SP3
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Copyright (c) 2015 Synopsys, Inc. All rights reserved.
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