50 lines
2.3 KiB
Tcl
50 lines
2.3 KiB
Tcl
reset_scan_configuration
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## ******************** 进行scan chain的插入 ******************** ##
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set_dft_insertion_configuration -preserve_design_name true
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set_dft_insertion_configuration -synthesis_optimization none
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set_scan_configuration -clock_mixing mix_clocks
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set_dft_signal -view spec -type ScanDataIn -port { SI0 } -hookup_pin SI0_PAD/C
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set_dft_signal -view spec -type ScanDataIn -port { SI1 } -hookup_pin SI1_PAD/C
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set_dft_signal -view spec -type ScanDataIn -port { SI2 } -hookup_pin SI2_PAD/C
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set_dft_signal -view spec -type ScanDataIn -port { SI3 } -hookup_pin SI3_PAD/C
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set_dft_signal -view spec -type ScanDataIn -port { SI4 } -hookup_pin SI4_PAD/C
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set_dft_signal -view spec -type ScanDataOut -port { SO0 } -hookup_pin SO0_PAD/I
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set_dft_signal -view spec -type ScanDataOut -port { SO1 } -hookup_pin SO1_PAD/I
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set_dft_signal -view spec -type ScanDataOut -port { SO2 } -hookup_pin SO2_PAD/I
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set_dft_signal -view spec -type ScanDataOut -port { SO3 } -hookup_pin SO3_PAD/I
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set_dft_signal -view spec -type ScanDataOut -port { SO4 } -hookup_pin SO4_PAD/I
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set_dft_signal -view spec -type ScanEnable -port { SEN } -hookup_pin SEN_PAD/C
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# set_dft_signal -view existing_dft -type ScanEnable -port SEN -hookup_pin SEN_PAD/C
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set_dft_signal -view existing_dft -type TestMode -port SMODE -hookup_pin SMODE_PAD/C
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set_dft_signal -view existing_dft -type Reset -port SRESET -hookup_pin SRESET_PAD/C -active 0
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set_dft_signal -view existing_dft -type ScanClock -port CLK -timing {45 55}
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set_dft_signal -view spec -type TestMode -port SMODE
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set_dft_signal -view spec -type TestData -port CLK
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set_dft_signal -view spec -type TestData -port SRESET
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set_dft_configuration -fix_clock enable
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set_dft_configuration -fix_set enable
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set_dft_configuration -fix_reset enable
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set_scan_configuration -chain_count 5
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set_autofix_configuration -method mux -type clock -fix_data enable -control_signal SMODE
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set_autofix_configuration -method mux -type reset -fix_data enable -control_signal SMODE -test_data SRESET
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create_test_protocol
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insert_dft
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change_names -rules verilog -hierarchy
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#保存综合后的设计
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write -format ddc -hierarchy -output $RES_OUT/${CURR_DESIGN}.mapped.scan.ddc
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#输出网表，自动布局布线需要
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write -f verilog -hierarchy -output $RES_OUT/${CURR_DESIGN}.mapped.scan.v |