161 lines
4.4 KiB
Verilog
161 lines
4.4 KiB
Verilog
`timescale 1ns/100ps
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// `define win 1
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`ifdef win
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`define ireal "d:/project/ASIC/FFT_IFFT_IP/user/sim/test/in/real.vec"
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`define iimag "d:/project/ASIC/FFT_IFFT_IP/user/sim/test/in/imag.vec"
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`define oreal "d:/project/ASIC/FFT_IFFT_IP/user/sim/test/out/real.vec"
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`define oimag "d:/project/ASIC/FFT_IFFT_IP/user/sim/test/out/imag.vec"
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`else
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`define ireal "/home/project/ASIC/FFT_IFFT_IP/user/sim/test/in/real.vec"
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`define iimag "/home/project/ASIC/FFT_IFFT_IP/user/sim/test/in/imag.vec"
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`define oreal "/home/project/ASIC/FFT_IFFT_IP/user/sim/test/out/real.vec"
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`define oimag "/home/project/ASIC/FFT_IFFT_IP/user/sim/test/out/imag.vec"
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`endif
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module top_tb();
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localparam FFT_STAGE = 11;
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localparam FFT_MAX = 1<<FFT_STAGE;
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localparam IEN_TIME = FFT_MAX*20;
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reg CLK = 0;
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reg RSTN = 0;
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reg IEN = 0;
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reg [11:0] IREAL = 0;
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reg [11:0] IIMAG = 0;
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wire OEN;
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wire CS;
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wire SCK;
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wire MOSI;
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wire [11:0] OREAL;
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wire [11:0] OIMAG;
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reg [11:0] Ireal_r [FFT_MAX-1:0];
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reg [11:0] Iimag_r [FFT_MAX-1:0];
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initial begin
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$sdf_annotate("/home/project/ASIC/FFT_IFFT_IP/user/sim/tb_file/top_scan_lt_cbest_m40c.sdf", u_top);
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end
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initial begin
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CLK <= 1'b0;
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IEN <= 1'b0;
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RSTN <= 1'b0;
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#20 RSTN <= 1'b1;
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forever
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#2.5 CLK = ~CLK;
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end
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integer index = 0;
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integer count = 0;
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initial begin
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$readmemb(`ireal, Ireal_r);
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$readmemb(`iimag, Iimag_r);
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#1092
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IEN = 1'b1;
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repeat(2000) begin
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for(index=0; index<FFT_MAX; index=index+1) begin
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#5
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IREAL <= Ireal_r[index];
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IIMAG <= Iimag_r[index];
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end
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count = count + 1;
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// $display("%d", count);
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if (count == 1500) begin
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$finish;
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end
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end
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end
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integer wre, wim;
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initial begin
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wre = $fopen(`oreal);
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wim = $fopen(`oimag);
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end
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// only print first FFT output
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always @(posedge CLK) begin
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if (RSTN && OEN && (count<1)) begin
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$fdisplay(wre, "%d", $signed(OREAL));
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$fdisplay(wim, "%d", $signed(OIMAG));
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end
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end
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top u_top(
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//ports
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.CLK ( CLK ),
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.RSTN ( RSTN ),
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.SEN ( 1'b0 ),
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.SMODE ( 1'b0 ),
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.IEN ( IEN ),
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.IREAL0 ( IREAL[0] ),
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.IREAL1 ( IREAL[1] ),
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.IREAL2 ( IREAL[2] ),
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.IREAL3 ( IREAL[3] ),
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.IREAL4 ( IREAL[4] ),
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.IREAL5 ( IREAL[5] ),
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.IREAL6 ( IREAL[6] ),
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.IREAL7 ( IREAL[7] ),
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.IREAL8 ( IREAL[8] ),
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.IREAL9 ( IREAL[9] ),
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.IREAL10 ( IREAL[10] ),
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.IREAL11 ( IREAL[11] ),
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.IIMAG0 ( IIMAG[0] ),
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.IIMAG1 ( IIMAG[1] ),
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.IIMAG2 ( IIMAG[2] ),
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.IIMAG3 ( IIMAG[3] ),
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.IIMAG4 ( IIMAG[4] ),
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.IIMAG5 ( IIMAG[5] ),
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.IIMAG6 ( IIMAG[6] ),
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.IIMAG7 ( IIMAG[7] ),
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.IIMAG8 ( IIMAG[8] ),
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.IIMAG9 ( IIMAG[9] ),
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.IIMAG10 ( IIMAG[10] ),
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.IIMAG11 ( IIMAG[11] ),
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.OEN ( OEN ),
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.OREAL0 ( OREAL[0] ),
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.OREAL1 ( OREAL[1] ),
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.OREAL2 ( OREAL[2] ),
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.OREAL3 ( OREAL[3] ),
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.OREAL4 ( OREAL[4] ),
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.OREAL5 ( OREAL[5] ),
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.OREAL6 ( OREAL[6] ),
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.OREAL7 ( OREAL[7] ),
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.OREAL8 ( OREAL[8] ),
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.OREAL9 ( OREAL[9] ),
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.OREAL10 ( OREAL[10] ),
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.OREAL11 ( OREAL[11] ),
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.OIMAG0 ( OIMAG[0] ),
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.OIMAG1 ( OIMAG[1] ),
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.OIMAG2 ( OIMAG[2] ),
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.OIMAG3 ( OIMAG[3] ),
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.OIMAG4 ( OIMAG[4] ),
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.OIMAG5 ( OIMAG[5] ),
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.OIMAG6 ( OIMAG[6] ),
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.OIMAG7 ( OIMAG[7] ),
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.OIMAG8 ( OIMAG[8] ),
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.OIMAG9 ( OIMAG[9] ),
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.OIMAG10 ( OIMAG[10] ),
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.OIMAG11 ( OIMAG[11] ),
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.CS ( CS ),
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.SCK ( SCK ),
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.MOSI ( MOSI )
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);
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receive u_receive(
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//ports
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.iclk ( CLK ),
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.rstn ( RSTN ),
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.CS ( CS ),
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.SCK ( SCK ),
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.MOSI ( MOSI )
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);
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endmodule
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