101 lines
2.5 KiB
Verilog
101 lines
2.5 KiB
Verilog
//从机接收MOSI的数据 在上升沿的时候采样数据
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module SPI_S2M(
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input iclk,
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input rstn,
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input CS,
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input SCK,
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input MOSI,
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output finish,
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output [7:0] out
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);
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localparam D7 = 4'd0;
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localparam D6 = 4'd1;
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localparam D5 = 4'd2;
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localparam D4 = 4'd3;
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localparam D3 = 4'd4;
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localparam D2 = 4'd5;
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localparam D1 = 4'd6;
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localparam D0 = 4'd7;
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reg rfinish;
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reg [7:0] rec = 8'd0;
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reg [3:0] state = 4'd0;
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assign out = rec;
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assign finish = rfinish;
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reg gate;
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reg gate_buf;
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reg mosi_buf;
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wire gate_pose = gate & ~gate_buf;
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always@(posedge iclk or negedge rstn) begin
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if(!rstn) begin
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gate <= 0;
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gate_buf <= 0;
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mosi_buf <= 0;
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end
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else begin
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gate <= SCK;
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gate_buf <= gate;
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mosi_buf <= MOSI;
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end
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end
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always @(posedge iclk or negedge rstn) begin
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if(!rstn) begin
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rec <= 0;
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state <= 0;
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rfinish <= 0;
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end
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else begin
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if (gate_pose) begin
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case(state)
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D7: begin
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rec[7] <= mosi_buf;
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state<= D6;
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end
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D6: begin
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rec[6] <= mosi_buf;
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state<= D5;
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end
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D5: begin
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rec[5] <= mosi_buf;
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state<= D4;
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end
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D4: begin
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rec[4] <= mosi_buf;
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state<= D3;
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end
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D3: begin
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rec[3] <= mosi_buf;
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state<= D2;
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end
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D2: begin
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rec[2] <= mosi_buf;
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state<= D1;
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end
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D1: begin
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rec[1] <= mosi_buf;
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state<= D0;
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end
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D0: begin
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rec[0] <= mosi_buf;
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state<= D7;
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rfinish <= 1'b1;
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end
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default: begin
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state<= D7;
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end
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endcase
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end
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else begin
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rfinish <= 1'b0;
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end
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end
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end
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endmodule
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