56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
module receive (
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input iclk,
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input rstn,
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input CS,
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input SCK,
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input MOSI
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);
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wire finish;
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wire [7:0] out;
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SPI_S2M u_SPI_S2M(
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//ports
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.iclk ( iclk ),
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.rstn ( rstn ),
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.CS ( CS ),
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.SCK ( SCK ),
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.MOSI ( MOSI ),
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.finish ( finish ),
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.out ( out )
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);
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reg [47:0] data;
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reg [10:0] addr;
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reg [10:0] index;
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always @(posedge iclk or negedge rstn) begin
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if(!rstn) begin
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addr <= 0;
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data <= 0;
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index <= 0;
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end
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else begin
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if (finish) begin
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if (index == 5) begin
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index <= 0;
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$display("%d", data);
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end
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else begin
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index <= index + 1'b1;
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end
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case (index)
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0 : begin data[7:0] <= out; end
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1 : begin data[15:8] <= out; end
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2 : begin data[23:16] <= out; end
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3 : begin data[31:24] <= out; end
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4 : begin data[39:32] <= out; end
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5 : begin data[47:39] <= out; end
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endcase
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end
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end
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end
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endmodule //receive
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