175 lines
8.0 KiB
Tcl
175 lines
8.0 KiB
Tcl
## ******************** 设置综合环境 ******************** ##
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source /home/project/ASIC/FFT_IFFT_IP/user/script/setup.tcl
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set DO_SCAN 0
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## ******************** common setting ******************** ##
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#dc common setting
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set_host_options -max_cores 8
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set compile_enable_register_merging false
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set svf_file_records_change_names_changes true
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set enable_recovery_removal_arcs true
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set case_analysis_with_logic_constants true
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set timing_enable_multiple_clocks_per_reg "true"
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set compile_instance_name_prefix "U"
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set verilogout_no_tri true
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set verilogout_show_unconnected_pins true
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set bind_unused_hierarchical_pins false
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#CLOCK gating setting
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set compile_clock_gating_through_hierarchy false
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#->set power_cg_auto_identify true
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#->positive_edge_logic integrated
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set_clock_gating_style \
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-sequential_cell latch \
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-control_point before \
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-control_signal scan_enable \
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-observation_point false \
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-max_fanout 16 \
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-minimum_bitwidth 4
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#--append --------------------------------------------
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set pwr_hdlc_split_cg_cells true
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set timing_scgc_override_library_setup_hold true
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set power_keep_license_after_power_commands true
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set verilogout_equation false
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set compile_seqmap_propagate_constants false
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set compile_seqmap_propagate_high_effort false
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set set_ultra_optimization "true"
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set compile_seqmap_identify_shift_registers false
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set compile_seqmap_no_scan_cell true
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set compile_seqmap_propagate_constants false
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set compile_delete_unloaded_seqential_cells false
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set timing_report_unconstrained_paths true
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set hdlin_enable_vpp true
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set power_keep_license_after_power_command true
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set single_group_per_sheet true
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set auto_wire_load_selection false
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set timing_disable_recovery_removal_checks false
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set enable_recovery_removal_arcs true
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# 开始记录DC综合的变动
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set_svf $RES_OUT/$CURR_DESIGN.svf
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set_app_var dc_allow_rtl_pg true
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## ******************** 读取设计源文件 ******************** ##
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#读入设计
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analyze -format verilog { \
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/home/project/ASIC/FFT_IFFT_IP/user/src/top.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/FFT_FLOW.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/send.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/sum.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/utils/ram.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/utils/SPI_M2S.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/utils/math/cmult.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/utils/RAM/2048FP/RAM2048.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/top/FFT_IFFT.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/top/fft.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/stage/BF_stage.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/stage/fft_stage.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/BF_op.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftrans_I.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftrans_II.v \
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/home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftwiddle.v \
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}
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elaborate $CURR_DESIGN -architecture verilog
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current_design $CURR_DESIGN
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set_fix_multiple_port_nets -all -buffer_constants
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set hdlout_internal_busses true
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set bus_inference_style "%s\[%d\]"
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# define_name rules verilog -check_bus_indexing -allowed {a-XA-Z0-9_}
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link > $RPT_OUT/00_link_design.log
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set uniquify_naming_style ${CURR_DESIGN}_%s_%d
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uniquify -force
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check_design > $RPT_OUT/01_check_design.log
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report_attributes -design
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set_dont_touch u_FFT_FLOW/u_FFT_IFFT/FFT_INST.fft_ins/stagX[*].u_fft_stage/LARGER_THAN_2.BF_inst_I/u_ram/RAM_GEN.RAM*_IP.u_RAM*
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set_dont_touch *_PAD*
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set_dont_touch [get_ports CLK -filter {@port_direction == in} -quiet]
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set_dont_touch u_FFT_FLOW/u_sum/u*_RAM2048/u*_FRAM512
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set_dont_use scc018ug_hd_rvt_ff_v1p98_-40c_basic/PULLHD0
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set_dont_use scc018ug_hd_rvt_ff_v1p98_-40c_basic/PULLHD1
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## ******************** 进行设计约束 ******************** ##
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# sdc
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read_sdc /home/project/ASIC/FFT_IFFT_IP/user/data/constraint/timing.sdc
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set_operating_conditions -max ff_v1p98_${F_TEMP}c -library $lib_fast
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set_app_var auto_wire_load_selection false
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# set_wire_load_model -name ForQA
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# set_wire_load_mode enclosed
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# 设置输入transtion，注：需要将输入时钟信号去除
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set_input_transition 0.89 [remove_from_collection [all_inputs] [get_clocks clk]]
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echo "INFO : Defining Reset : RSTN"
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set_drive 0 [get_ports RSTN -filter {@port_direction == in} -quiet]
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set_false_path -from [get_ports RSTN -filter {@port_direction == in} -quiet]
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set_ideal_network -no_propagate [get_nets -of_object [get_ports RSTN -filter {@port_direction == in} -quiet] -quiet]
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set_ideal_network -no_propagate [get_nets -of_object [get_ports CLK -filter {@port_direction == in} -quiet] -quiet]
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# set_ideal_network -no_propagate [get_nets -of_object [get_ports rstn -filter {@port_direction == in} -quiet] -quiet]
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# set_ideal_network -no_propagate [get_nets -of_object [get_ports iclk -filter {@port_direction == in} -quiet] -quiet]
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# 对时序进行分组
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# set ports_clock_root [filter_collection [get_attribute [get_clocks] sources] object_class==port]
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# group_path -name reg2out -from [all_registers -clock_pins] -to [all_outputs]
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# group_path -name in2reg -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_registers -data_pins]
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# group_path -name in2out -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]
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set clock_ports [get_ports -quiet [all_fanout -clock_tree -flat]]
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set all_inputs [all_inputs]
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set all_outputs [all_outputs]
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set all_nonclk_inputs [remove_from_collection $all_inputs $clock_ports]
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set all_nonclk_outputs [remove_from_collection $all_outputs $clock_ports]
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set all_icgs [get_cells -hier -filter "is_integrated_clock_gating_cell == true"]
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set all_reg [all_registers]
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set all_reg [remove_from_collection $all_reg $all_icgs]
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group_path -from $all_reg -to $all_reg -name reg2reg
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group_path -from $all_reg -to $all_nonclk_outputs -name reg2out
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group_path -from $all_nonclk_inputs -to $all_reg -name in2reg
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group_path -from $all_nonclk_inputs -to $all_nonclk_outputs -name in2out
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#group_path -from $all_reg -to $all_icgs -name reg2gate
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report_path_group
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set_critical_range 3 [current_design]
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#设置在RTL代码中用上升沿沿触发的寄存器采用使用集成门控时钟单元。
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#设置该门控单元在DFT时的控制点放在门逻辑中的锁存器之前。
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#设置一个门控单元所驱动的最大负载数目，定义CG单元最大扇出的一个目的是减少CG后面的时钟延迟
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#门控时钟单元的扇出越大，它到达寄存器的延迟越长
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#此外，还有用来约束重新平衡
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#设置进行时钟门控的寄存器阵列的最小宽度（一个门控时钟至少要触发4个寄存器）
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#基于锁存器的离散门控单元
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# set_clock_gating_style \
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# -positive_edge_logic {integrated:saed90nm_max_hth_cg_lvt/CGLPPRX8_LVT} \
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# -control_point before \
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# -max_fanout 32 \
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# -no_sharing \
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# -minimum_bitwidth 4 \
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# -sequential_cell latch
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## ******************** 映射门级单元及优化 ******************** ##
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#综合并插入门控时钟单元
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compile_ultra -incremental -scan -gate_clock
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## ******************** 检查综合结果并输出报告 ******************** ##
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#报出所有违规，包括setup, hold check, drv, clock gating check等
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report_constraint -all_violators > $RPT_OUT/all_vios.rpt
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check_design > $RPT_OUT/05_check_design.log
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check_timing > $RPT_OUT/06_check_timing.rpt
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#为formality进行停止记录数据（形式验证）
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set_svf -off
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#因为DC和其它的XX命名规则不同，为了避免出现问题，在产生网表之前先要定义一些命名规则。
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change_names -rules verilog -hierarchy
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uniquify -force
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#保存综合后的设计
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write -format ddc -hierarchy -output $RES_OUT/${CURR_DESIGN}.ddc
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#输出网表，自动布局布线需要
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write -f verilog -hierarchy -output $RES_OUT/${CURR_DESIGN}.v
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## ******************** 进行scan chain的插入 ******************** ##
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source /home/project/ASIC/FFT_IFFT_IP/user/script/scan.tcl
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exit |