83 lines
4.5 KiB
Tcl
83 lines
4.5 KiB
Tcl
#read sdc constraints
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remove_sdc
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source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180502_sdc/sy13_top_con.tcl > ./rpt/02_read_sdc.log
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source -echo -verbose ./scr/sdc/get_mem.tcl >> ./rpt/02_read_sdc.log
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source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/update_0410/scan_dont_touch.tcl >> ./rpt/02_read_sdc.log
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#->source /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/sdc_update.tcl >> ./rpt/02_read_sdc.log
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#->source ./scr/group_path.tcl
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#group_path -name REG2REG -from [all_registers] -to [all_registers] -critical_range 0.5 -weight 10
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#group_path -name FROM_MEM -from [all_registers] to [all_registers] -critical_range 0.5 -weight 10
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#--dont touch --------------------------------------------
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#set_dont_touch ae210_chip
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#set_dont_touch [get_cells * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
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#set_dont_touch [get_nets * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
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set_dont_touch ae210_chip
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set_dont_touch u_mcu/u_sys_top
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set_dont_touch u_mcu/u_aoss_wrap
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set_operating_condition SS0P99V125C
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#--add upf --------------------------------------------
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set mv_enabke_power_domain_power_net_check false
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set upf_create_implicit_supply_sets false
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set upf_iso_filter_elements_with_applies_to ENABLE
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remove_upf
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#->load_upf /home/xian001/SY1301_XIAN/backend/user/slpeng/pr/20180326/scripts/upf/rtl_20170721.upf > ./rpt/03_read_upf.log
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#->load_upf /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/syn13.0422.upf > ./rpt/03_read_upf.log
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source -echo -verbose ./scr/create_vddq_en_pin.tcl > ./rpt/03_read_upf.log
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load_upf /home/xian001/temp_work/upf/0423/sy13.upf >> ./rpt/03_read_upf.log
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source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/modify/set_voltage.0429.tcl >> ./rpt/03_read_upf.log
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set mv_upf_check_pg_pins_of_target_lib_cells true
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check_mv_design > ./rpt/check_mv_design.rpt
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#start to compile
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#setting
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set_fix_multiple_port_nets -all -buffer_constants
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set_max_area 0
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set verilogout_equation false
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set compile_seqmap_propagate_constants false
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set compile_seqmap_propagate_high_effort false
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set set_ultra_optimization "true"
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set compile_seqmap_identify_shift_registers false
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#--dont touch false for iso --------------------------------------------
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#->source ./scr/dont_touch_port.lst
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#->set_dont_touch [get_nets -of [get_ports $iso_ports]] false
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#compile
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check_timing > ./rpt/03_check_timing.rpt
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#-- first compile --------------------------------------------
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#compile_ultra -timing_high_effort_script -no_autoungroup -no_seq_output_inversion -gate_clock -scan -no_design_rule
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#compile_ultra -no_autoungroup -gate_clock -scan -no_auto_layer_optimization
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compile_ultra -gate_clock -no_seq_output_inversion -scan -no_autoungroup -timing_high_effort_script
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#->save_upf ./result/syn_done_v1.upf
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#report
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#change name & output verilog
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source ./scr/change_name.tcl
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write -hier -format verilog -out ./result/${TOP}.v
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write -format ddc -h -out ./result/${TOP}.ddc
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report_constraint -max_delay -nosplit -all_violators -significant_digits 3 > ./rpt/${TOP}.report_constraint.rpt
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report_constraint -max_delay -nosplit -all_violators -max_delay -verbose > ./rpt/${TOP}.report_constraint_verbose.rpt
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report_qor > ./rpt/${TOP}.qor
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write_sdc -nosplit ./result/${TOP}.sdc
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save_upf ./result/${TOP}.upf
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#--dont touch list --------------------------------------------
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set_dont_touch [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"] true
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set_dont_touch [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]] true
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#set_dont_touch [get_nets -of [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"]] true
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set dont_touch_cells [get_cells -hier * -filter {@is_hierarchical==false && @dont_touch == true}]
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foreach_in_collection cell $dont_touch_cells {
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redirect -append ./result/dont_touch.lst {puts [get_att [get_cells $cell] full_name]}
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}
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#set dont_touch_nets [get_nets -hierarchical -filter "dont_touch == true"]
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set dont_touch_dly_nets [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]]
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foreach_in_collection net $dont_touch_dly_nets {
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redirect -append ./result/dont_touch.lst {puts [get_att [get_nets $net] full_name]}
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}
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report_clock_gating -nosplit > ./rpt/04_report_clock_gating.rpt
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check_design > ./rpt/05_check_design.log
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check_timing > ./rpt/06_check_timing.rpt
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source ./scr/gpio_timing.tcl
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source ./scr/disconnect_net.tcl
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write -hier -format verilog -out ./result/${TOP}_disconnect.v
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set_svf -off
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