631 lines
23 KiB
Verilog
631 lines
23 KiB
Verilog
/*
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Copyright (c) 2022 SMIC
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Filename: RAM256.v
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IP code : S018RF2P
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Version: 0.2.b
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CreateDate: Oct 31, 2022
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Verilog Model for 2-PORT Register File
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SMIC 0.18um G Logic Process
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Configuration: -instname RAM256 -rows 64 -bits 24 -mux 4
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Redundancy: Off
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Bit-Write: Off
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*/
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/* DISCLAIMER */
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/* */
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/* SMIC hereby provides the quality information to you but makes no claims, */
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/* promises or guarantees about the accuracy, completeness, or adequacy of the */
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/* information herein. The information contained herein is provided on an "AS IS" */
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/* basis without any warranty, and SMIC assumes no obligation to provide support */
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/* of any kind or otherwise maintain the information. */
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/* SMIC disclaims any representation that the information does not infringe any */
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/* intellectual property rights or proprietary rights of any third parties. SMIC */
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/* makes no other warranty, whether express, implied or statutory as to any */
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/* matter whatsoever, including but not limited to the accuracy or sufficiency of */
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/* any information or the merchantability and fitness for a particular purpose. */
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/* Neither SMIC nor any of its representatives shall be liable for any cause of */
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/* action incurred to connect to this service. */
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/* */
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/* STATEMENT OF USE AND CONFIDENTIALITY */
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/* */
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/* The following/attached material contains confidential and proprietary */
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/* information of SMIC. This material is based upon information which SMIC */
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/* considers reliable, but SMIC neither represents nor warrants that such */
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/* information is accurate or complete, and it must not be relied upon as such. */
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/* This information was prepared for informational purposes and is for the use */
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/* by SMIC's customer only. SMIC reserves the right to make changes in the */
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/* information at any time without notice. */
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/* No part of this information may be reproduced, transmitted, transcribed, */
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/* stored in a retrieval system, or translated into any human or computer */
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/* language, in any form or by any means, electronic, mechanical, magnetic, */
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/* optical, chemical, manual, or otherwise, without the prior written consent of */
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/* SMIC. Any unauthorized use or disclosure of this material is strictly */
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/* prohibited and may be unlawful. By accepting this material, the receiving */
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/* party shall be deemed to have acknowledged, accepted, and agreed to be bound */
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/* by the foregoing limitations and restrictions. Thank you. */
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/* */
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`timescale 1ns/1ps
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`celldefine
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module RAM256 (
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QA,
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CLKA,
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CLKB,
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CENA,
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CENB,
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AA,
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AB,
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DB);
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parameter Bits = 24;
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parameter Word_Depth = 256;
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parameter Add_Width = 8;
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`ifdef MEM_CHECK_OFF
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parameter disable_display = 1'b1;
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`else
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parameter disable_display = 1'b0;
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`endif
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output [Bits-1:0] QA;
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input CLKA;
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input CLKB;
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input CENA;
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input CENB;
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input [Add_Width-1:0] AA;
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input [Add_Width-1:0] AB;
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input [Bits-1:0] DB;
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wire [Bits-1:0] QA_int;
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wire [Add_Width-1:0] AA_int;
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wire [Add_Width-1:0] AB_int;
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wire CLKA_int;
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wire CLKB_int;
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wire CENA_int;
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wire CENB_int;
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wire [Bits-1:0] DB_int;
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reg [Bits-1:0] QA_latched;
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reg [Add_Width-1:0] AA_latched;
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reg [Add_Width-1:0] AB_latched;
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reg [Bits-1:0] DB_latched;
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reg CENA_latched;
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reg CENB_latched;
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reg LAST_CLKA;
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reg LAST_CLKB;
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reg AA0_flag;
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reg AA1_flag;
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reg AA2_flag;
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reg AA3_flag;
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reg AA4_flag;
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reg AA5_flag;
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reg AA6_flag;
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reg AA7_flag;
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reg AB0_flag;
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reg AB1_flag;
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reg AB2_flag;
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reg AB3_flag;
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reg AB4_flag;
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reg AB5_flag;
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reg AB6_flag;
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reg AB7_flag;
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reg CENA_flag;
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reg CENB_flag;
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reg CLKA_CYC_flag;
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reg CLKB_CYC_flag;
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reg CLKA_H_flag;
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reg CLKB_H_flag;
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reg CLKA_L_flag;
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reg CLKB_L_flag;
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reg DB0_flag;
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reg DB1_flag;
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reg DB2_flag;
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reg DB3_flag;
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reg DB4_flag;
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reg DB5_flag;
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reg DB6_flag;
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reg DB7_flag;
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reg DB8_flag;
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reg DB9_flag;
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reg DB10_flag;
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reg DB11_flag;
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reg DB12_flag;
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reg DB13_flag;
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reg DB14_flag;
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reg DB15_flag;
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reg DB16_flag;
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reg DB17_flag;
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reg DB18_flag;
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reg DB19_flag;
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reg DB20_flag;
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reg DB21_flag;
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reg DB22_flag;
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reg DB23_flag;
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reg A_flag;
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reg B_flag;
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reg VIOA_flag;
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reg VIOB_flag;
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reg LAST_VIOA_flag;
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reg LAST_VIOB_flag;
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reg [Add_Width-1:0] AA_flag;
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reg [Add_Width-1:0] AB_flag;
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reg [Bits-1:0] DB_flag;
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reg LAST_CENA_flag;
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reg LAST_CENB_flag;
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reg [Add_Width-1:0] LAST_AA_flag;
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reg [Add_Width-1:0] LAST_AB_flag;
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reg [Bits-1:0] LAST_DB_flag;
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reg LAST_CLKA_CYC_flag;
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reg LAST_CLKB_CYC_flag;
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reg LAST_CLKA_H_flag;
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reg LAST_CLKB_H_flag;
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reg LAST_CLKA_L_flag;
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reg LAST_CLKB_L_flag;
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wire CEA_flag;
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wire CEB_flag;
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wire clkconfA_flag;
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wire clkconfB_flag;
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wire clkconf_flag;
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reg [Bits-1:0] mem_array[Word_Depth-1:0];
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integer i;
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integer n;
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buf dout_buf[Bits-1:0] (QA, QA_int);
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buf (CLKA_int, CLKA);
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buf (CLKB_int, CLKB);
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buf (CENA_int, CENA);
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buf (CENB_int, CENB);
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buf aa_buf[Add_Width-1:0] (AA_int, AA);
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buf ab_buf[Add_Width-1:0] (AB_int, AB);
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buf din_buf[Bits-1:0] (DB_int, DB);
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assign QA_int=QA_latched;
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assign CEA_flag=(CENA_int !== 1'b1);
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assign CEB_flag=(CENB_int !== 1'b1);
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assign clkconfA_flag=((AA_int===AB_latched) || (^AA_int === 1'bx) || (^AB_latched === 1'bx) || CLKA_int === 1'bx || CLKB_int === 1'bx) && (CENA_int!==1'b1) && (CENB_latched!==1'b1);
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assign clkconfB_flag=((AB_int===AA_latched) || (^AA_latched === 1'bx) || (^AB_int === 1'bx) || CLKA_int === 1'bx || CLKB_int === 1'bx) && (CENB_int!==1'b1) && (CENA_latched!==1'b1);
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assign clkconf_flag=((AA_int===AB_int)|| (^AA_int === 1'bx) || (^AB_int === 1'bx) || CLKA_int === 1'bx || CLKB_int === 1'bx) && (CENA_int!==1'b1) && (CENB_int!==1'b1);
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always @(CLKA_int)
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begin
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casez({LAST_CLKA, CLKA_int})
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2'b01: begin
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CENA_latched = CENA_int;
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AA_latched = AA_int;
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rw_memA;
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end
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2'b10,
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2'bx?,
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2'b00,
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2'b11: ;
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2'b?x: begin
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for(i=0;i<Word_Depth;i=i+1)
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mem_array[i]={Bits{1'bx}};
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QA_latched={Bits{1'bx}};
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rw_memA;
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end
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endcase
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LAST_CLKA=CLKA_int;
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end
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always @(CLKB_int)
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begin
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casez({LAST_CLKB, CLKB_int})
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2'b01: begin
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CENB_latched = CENB_int;
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AB_latched = AB_int;
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DB_latched = DB_int;
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rw_memB;
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end
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2'b10,
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2'bx?,
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2'b00,
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2'b11: ;
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2'b?x: begin
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for(i=0;i<Word_Depth;i=i+1)
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mem_array[i]={Bits{1'bx}};
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rw_memA;
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end
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endcase
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LAST_CLKB=CLKB_int;
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end
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always @(CENA_flag
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or AA0_flag
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or AA1_flag
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or AA2_flag
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or AA3_flag
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or AA4_flag
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or AA5_flag
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or AA6_flag
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or AA7_flag
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or VIOA_flag)
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begin
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update_flag_busA;
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CENA_latched = (CENA_flag!==LAST_CENA_flag) ? 1'bx : CENA_latched ;
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for (n=0; n<Add_Width; n=n+1)
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AA_latched[n] = (AA_flag[n]!==LAST_AA_flag[n]) ? 1'bx : AA_latched[n] ;
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LAST_CENA_flag = CENA_flag;
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LAST_AA_flag = AA_flag;
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if(VIOA_flag!==LAST_VIOA_flag)
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begin
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if(disable_display == 0) $display("**MEM_Error Timing Violation between posedge CLKB and posedge CLKA, in %m at %0t", $time);
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if(CLKA === 1'bx || CLKB=== 1'bx) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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end
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else begin
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if(B_flag===1'b0)
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QA_latched={Bits{1'bx}};
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end
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LAST_VIOA_flag=VIOA_flag;
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end
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else
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rw_memA;
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end
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always @( CLKA_CYC_flag
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or CLKA_H_flag
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or CLKA_L_flag)
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begin
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if(LAST_CLKA_CYC_flag !== CLKA_CYC_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKA_CYC_flag = CLKA_CYC_flag;
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end
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if(LAST_CLKA_H_flag !== CLKA_H_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKA_H_flag = CLKA_H_flag;
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end
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if(LAST_CLKA_L_flag !== CLKA_L_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKA_L_flag = CLKA_L_flag;
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end
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end
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always @( CLKB_CYC_flag
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or CLKB_H_flag
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or CLKB_L_flag)
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begin
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if(LAST_CLKB_CYC_flag !== CLKB_CYC_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKB_CYC_flag = CLKB_CYC_flag;
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end
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if(LAST_CLKB_H_flag !== CLKB_H_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKB_H_flag = CLKB_H_flag;
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end
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if(LAST_CLKB_L_flag !== CLKB_L_flag) begin
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x_mem;
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QA_latched={Bits{1'bx}};
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LAST_CLKB_L_flag = CLKB_L_flag;
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end
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end
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always @(CENB_flag
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or AB0_flag
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or AB1_flag
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or AB2_flag
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or AB3_flag
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or AB4_flag
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or AB5_flag
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or AB6_flag
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or AB7_flag
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or DB0_flag
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or DB1_flag
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or DB2_flag
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or DB3_flag
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or DB4_flag
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or DB5_flag
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or DB6_flag
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or DB7_flag
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or DB8_flag
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or DB9_flag
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or DB10_flag
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or DB11_flag
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or DB12_flag
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or DB13_flag
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or DB14_flag
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or DB15_flag
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or DB16_flag
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or DB17_flag
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or DB18_flag
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or DB19_flag
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or DB20_flag
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or DB21_flag
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or DB22_flag
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or DB23_flag
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or VIOB_flag)
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begin
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update_flag_busB;
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CENB_latched = (CENB_flag!==LAST_CENB_flag) ? 1'bx : CENB_latched ;
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for (n=0; n<Add_Width; n=n+1)
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AB_latched[n] = (AB_flag[n]!==LAST_AB_flag[n]) ? 1'bx : AB_latched[n] ;
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for (n=0; n<Bits; n=n+1)
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DB_latched[n] = (DB_flag[n]!==LAST_DB_flag[n]) ? 1'bx : DB_latched[n] ;
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LAST_CENB_flag = CENB_flag;
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LAST_AB_flag = AB_flag;
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LAST_DB_flag = DB_flag;
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if(VIOB_flag!==LAST_VIOB_flag)
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begin
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if(disable_display == 0) $display("**MEM_Error Timing Violation between posedge CLKA and posedge CLKB, in %m at %0t", $time);
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if(CLKA === 1'bx || CLKB=== 1'bx) begin //if
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x_mem;
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QA_latched={Bits{1'bx}};
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end // if end
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else begin
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if(A_flag===1'b1)
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QA_latched={Bits{1'bx}};
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end
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LAST_VIOB_flag=VIOB_flag;
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end
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else
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rw_memB;
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end
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task rw_memA;
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begin
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A_flag=1'bx;
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if(CLKA !== 1'bx && CLKB!== 1'bx) begin
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if(CENA_latched===1'b0)
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begin
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A_flag=1;
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if(^(AA_latched)===1'bx)
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QA_latched={Bits{1'bx}};
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else
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QA_latched=mem_array[AA_latched];
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end
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else if(CENA_latched===1'bx)
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begin
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A_flag=1;
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QA_latched={Bits{1'bx}};
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end
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end // clk = x
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else begin
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x_mem;
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QA_latched={Bits{1'bx}};
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end
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end
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endtask
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task rw_memB;
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begin
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B_flag=1'bx;
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if(CLKB !== 1'bx && CLKA !== 1'bx) begin
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if(CENB_latched===1'b0)
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begin
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B_flag=0;
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if(^(AB_latched)===1'bx)
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x_mem;
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else
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mem_array[AB_latched]=DB_latched;
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end
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else if(CENB_latched===1'bx)
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begin
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B_flag=0;
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if(^(AB_latched)===1'bx)
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x_mem;
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else
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mem_array[AB_latched]={Bits{1'bx}};
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end
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end // clk = x
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else begin
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x_mem;
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QA_latched={Bits{1'bx}};
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end
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end
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endtask
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task x_mem;
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begin
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for(i=0;i<Word_Depth;i=i+1)
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mem_array[i]={Bits{1'bx}};
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end
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endtask
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task update_flag_busA;
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begin
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AA_flag = {
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AA7_flag,
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AA6_flag,
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AA5_flag,
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AA4_flag,
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AA3_flag,
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AA2_flag,
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AA1_flag,
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AA0_flag};
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end
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endtask
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task update_flag_busB;
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begin
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AB_flag = {
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AB7_flag,
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AB6_flag,
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AB5_flag,
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AB4_flag,
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AB3_flag,
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AB2_flag,
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AB1_flag,
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AB0_flag};
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DB_flag = {
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DB23_flag,
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DB22_flag,
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DB21_flag,
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DB20_flag,
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DB19_flag,
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DB18_flag,
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DB17_flag,
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DB16_flag,
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DB15_flag,
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DB14_flag,
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DB13_flag,
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DB12_flag,
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DB11_flag,
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DB10_flag,
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DB9_flag,
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DB8_flag,
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DB7_flag,
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DB6_flag,
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DB5_flag,
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DB4_flag,
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DB3_flag,
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DB2_flag,
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DB1_flag,
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DB0_flag};
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end
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endtask
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// specify
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// (posedge CLKA => (QA[0] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[1] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[2] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[3] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[4] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[5] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[6] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[7] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[8] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[9] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[10] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[11] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[12] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[13] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[14] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[15] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[16] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[17] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[18] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[19] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[20] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[21] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[22] : 1'bx))=(1.000,1.000);
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// (posedge CLKA => (QA[23] : 1'bx))=(1.000,1.000);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[0],0.500,0.250,AA0_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[0],0.500,0.250,AA0_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[1],0.500,0.250,AA1_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[1],0.500,0.250,AA1_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[2],0.500,0.250,AA2_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[2],0.500,0.250,AA2_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[3],0.500,0.250,AA3_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[3],0.500,0.250,AA3_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[4],0.500,0.250,AA4_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[4],0.500,0.250,AA4_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[5],0.500,0.250,AA5_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[5],0.500,0.250,AA5_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[6],0.500,0.250,AA6_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[6],0.500,0.250,AA6_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,posedge AA[7],0.500,0.250,AA7_flag);
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// $setuphold(posedge CLKA &&& CEA_flag,negedge AA[7],0.500,0.250,AA7_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[0],0.500,0.250,AB0_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[0],0.500,0.250,AB0_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[1],0.500,0.250,AB1_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[1],0.500,0.250,AB1_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[2],0.500,0.250,AB2_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[2],0.500,0.250,AB2_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[3],0.500,0.250,AB3_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[3],0.500,0.250,AB3_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[4],0.500,0.250,AB4_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[4],0.500,0.250,AB4_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[5],0.500,0.250,AB5_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[5],0.500,0.250,AB5_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[6],0.500,0.250,AB6_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[6],0.500,0.250,AB6_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,posedge AB[7],0.500,0.250,AB7_flag);
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// $setuphold(posedge CLKB &&& CEB_flag,negedge AB[7],0.500,0.250,AB7_flag);
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|
|
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// $setuphold(posedge CLKA,posedge CENA,0.500,0.250,CENA_flag);
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|
// $setuphold(posedge CLKA,negedge CENA,0.500,0.250,CENA_flag);
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|
// $period(posedge CLKA,2.722,CLKA_CYC_flag);
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|
// $width(posedge CLKA,0.817,0,CLKA_H_flag);
|
|
// $width(negedge CLKA,0.817,0,CLKA_L_flag);
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|
|
|
// $setuphold(posedge CLKB,posedge CENB,0.500,0.250,CENB_flag);
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|
// $setuphold(posedge CLKB,negedge CENB,0.500,0.250,CENB_flag);
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|
// $period(posedge CLKB,2.722,CLKB_CYC_flag);
|
|
// $width(posedge CLKB,0.817,0,CLKB_H_flag);
|
|
// $width(negedge CLKB,0.817,0,CLKB_L_flag);
|
|
|
|
// $setup(posedge CLKA,posedge CLKB &&& clkconfB_flag,1.000,VIOB_flag);
|
|
// $hold(posedge CLKA,posedge CLKB &&& clkconf_flag,0.010,VIOB_flag);
|
|
// $setup(posedge CLKB,posedge CLKA &&& clkconfA_flag,1.000,VIOA_flag);
|
|
// $hold(posedge CLKB,posedge CLKA &&& clkconf_flag,0.010,VIOA_flag);
|
|
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[0],0.500,0.250,DB0_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[0],0.500,0.250,DB0_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[1],0.500,0.250,DB1_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[1],0.500,0.250,DB1_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[2],0.500,0.250,DB2_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[2],0.500,0.250,DB2_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[3],0.500,0.250,DB3_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[3],0.500,0.250,DB3_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[4],0.500,0.250,DB4_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[4],0.500,0.250,DB4_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[5],0.500,0.250,DB5_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[5],0.500,0.250,DB5_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[6],0.500,0.250,DB6_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[6],0.500,0.250,DB6_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[7],0.500,0.250,DB7_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[7],0.500,0.250,DB7_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[8],0.500,0.250,DB8_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[8],0.500,0.250,DB8_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[9],0.500,0.250,DB9_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[9],0.500,0.250,DB9_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[10],0.500,0.250,DB10_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[10],0.500,0.250,DB10_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[11],0.500,0.250,DB11_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[11],0.500,0.250,DB11_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[12],0.500,0.250,DB12_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[12],0.500,0.250,DB12_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[13],0.500,0.250,DB13_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[13],0.500,0.250,DB13_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[14],0.500,0.250,DB14_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[14],0.500,0.250,DB14_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[15],0.500,0.250,DB15_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[15],0.500,0.250,DB15_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[16],0.500,0.250,DB16_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[16],0.500,0.250,DB16_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[17],0.500,0.250,DB17_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[17],0.500,0.250,DB17_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[18],0.500,0.250,DB18_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[18],0.500,0.250,DB18_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[19],0.500,0.250,DB19_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[19],0.500,0.250,DB19_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[20],0.500,0.250,DB20_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[20],0.500,0.250,DB20_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[21],0.500,0.250,DB21_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[21],0.500,0.250,DB21_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[22],0.500,0.250,DB22_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[22],0.500,0.250,DB22_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,posedge DB[23],0.500,0.250,DB23_flag);
|
|
// $setuphold(posedge CLKB &&& CEB_flag,negedge DB[23],0.500,0.250,DB23_flag);
|
|
// endspecify
|
|
|
|
endmodule
|
|
|
|
`endcelldefine
|