47 lines
901 B
Verilog
47 lines
901 B
Verilog
module clkdiv(
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input clk50,
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input rst_n,
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output reg clkout
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);
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reg [15:0] cnt;
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always @(posedge clk50 or negedge rst_n)
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begin
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if(!rst_n)
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begin
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cnt <= 16'b0;
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clkout <= 1'b0;
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end
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else if(cnt == 16'd162)
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begin
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clkout <= 1'b1;
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cnt <= cnt + 16'd1;
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end
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else if(cnt == 16'd325)
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begin
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clkout <= 1'b0;
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cnt <= 16'd0;
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end
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else
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begin
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cnt <= cnt + 16'd1;
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end
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end
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endmodule
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// module des_sample (
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// input clk,
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// input rst,
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// output reg [7:0] nums
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// );
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// always @(posedge clk or negedge rst) begin
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// if (!rst) begin
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// nums = 8'h00;
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// end else begin
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// nums = nums + 1;
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// end
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// end
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// endmodule
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