15 lines
377 B
Verilog
15 lines
377 B
Verilog
module im_8k (
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input clock,
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input reset,
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input [31: 0] pc_out,
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output [31: 0] im_out
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);
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reg [31: 0] im[2047: 0]; // instruction memory, which is an instruction pool
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always @(posedge reset) begin
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// $readmemh("./data/r_text", im, 0, 2047);
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end
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assign im_out = im[pc_out[11: 2]];
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endmodule // im_8k
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