28 lines
879 B
Verilog
28 lines
879 B
Verilog
module MEM_WB (
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input clock,
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input reset,
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input EX_MEM_MemtoReg,
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input EX_MEM_RegWrite,
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input [31: 0] dm_out,
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input [31: 0] EX_MEM_mux5_out,
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input [ 5: 0] EX_MEM_mux1_out,
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input [63: 0] EX_MEM_prod,
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output reg MEM_WB_MemtoReg,
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output reg MEM_WB_RegWrite,
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output reg [31: 0] MEM_WB_dm_out,
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output reg [31: 0] MEM_WB_mux5_out,
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output reg [ 5: 0] MEM_WB_mux1_out,
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output reg [63: 0] MEM_WB_prod
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);
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always @(posedge clock) begin
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MEM_WB_MemtoReg <= EX_MEM_MemtoReg;
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MEM_WB_RegWrite <= EX_MEM_RegWrite;
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MEM_WB_dm_out <= dm_out;
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MEM_WB_mux5_out <= EX_MEM_mux5_out;
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MEM_WB_mux1_out <= EX_MEM_mux1_out;
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MEM_WB_prod <= EX_MEM_prod;
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end
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endmodule //MEM_WB
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