52 lines
1.6 KiB
Verilog
52 lines
1.6 KiB
Verilog
module regfile (
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input clock,
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input reset,
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input MEM_WB_RegWrite,
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input [ 4: 0] rs,
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input [ 4: 0] rt,
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input [ 5: 0] MEM_WB_mux1_out, // rd
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input [31: 0] mux6_out, // data
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input [63: 0] MEM_WB_prod, // prod
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output reg [31: 0] low_out,
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output reg [31: 0] high_out,
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output reg [31: 0] regfile_out1,
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output reg [31: 0] regfile_out2
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);
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/*
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0~31 : general registers
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32 : $hi
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33 : $lo
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*/
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reg [31: 0] registers[34: 0];
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integer i;
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// load data from regfile
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always @(negedge clock) begin // we should load data in the latter half of the cycle in order to let update appear first
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// half of the cycle
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high_out = registers[32];
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low_out = registers[33];
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regfile_out1 = (rs == 0) ? 0 : registers[rs];
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regfile_out2 = (rt == 0) ? 0 : registers[rt];
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end
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always @(posedge reset) begin
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for (i = 0; i < 34; i = i + 1)
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registers[i] = 0;
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end
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// Write mux6_out to regfile
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always @(posedge clock) begin
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if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0)
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begin
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if (MEM_WB_mux1_out == 34) // result of mult of div
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begin
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registers[32] = MEM_WB_prod[63:32]; // high
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registers[33] = MEM_WB_prod[31: 0]; // low
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end
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else
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registers[MEM_WB_mux1_out] = mux6_out;
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end
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end
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endmodule //regfile
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