62 lines
1.8 KiB
Tcl
62 lines
1.8 KiB
Tcl
# 设置周期 curr : 200MHz
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set T 5
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set_case_analysis 1 [get_ports MODE]
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# 首先创建时钟
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create_clock -name clk -period $T [get_ports CLK]
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### note: ------ margin 余量约束设置严格一点
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# 路径、器件等造成的延迟
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set_clock_latency 1.2 [get_clocks clk]
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# 边沿跳变的压摆率导致的延迟与不确定
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set_clock_transition 0.4 [get_clocks clk]
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# jitter抖动造成的不稳定
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set_clock_uncertainty [expr $T*0.25] [get_clocks clk]
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# reg_to_reg
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# input/output_to_reg
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# 告诉EDA，模块外部有多大的延迟，软件自动计算内部的延迟(设置的值一般都是经验值)
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# Tclk-q : FF传输时间
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# Tm : 最大外部延迟
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# clk : 同步的时钟
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# A : 输入的端口
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# B : 输出的端口
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# max 60% min 0
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set InputMaxDelay [ expr $T * 0.6 ]
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set OutputMaxDelay [ expr $T * 0.6 ]
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#--Option
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set InputMinDelay [ expr $T * 0 ]
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set OutputMinDelay [ expr $T * 0 ]
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set_input_delay $InputMaxDelay -max [all_inputs] -clock [get_clocks clk]
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set_input_delay $InputMinDelay -min [all_inputs] -clock [get_clocks clk]
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set_output_delay $OutputMaxDelay -max [all_outputs] -clock [get_clocks clk]
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set_output_delay $OutputMinDelay -min [all_outputs] -clock [get_clocks clk]
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# env attributes
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# 导入模型的R&C，让DC去估算延迟
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# set_load [load of lib/cell_pin] [all_port]
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# set_driving_cell -lib_cell and2a0 [all_port]
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set_max_transition 0.5 [current_design]
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# set_max_capacitance # 不必设置直接遵循lib里的约束即可
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set_max_fanout 64 [current_design]
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# false path
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# set_false_path -from [get_ports RSTN]
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#set_multicycle_path -setup 2 -from A -to B
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#set_multicycle_path -hold 1 -from A -to B
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set compile_enable_constant_propagation_with_no_boundary_opt false
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set timing_enable_multiple_clocks_per_reg true
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set enable_recovery_removal_arcs true
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set_max_leakage_power 0
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set_max_area 0
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