43 lines
1.2 KiB
Tcl
43 lines
1.2 KiB
Tcl
source /home/project/ASIC/FFT_IFFT_IP/user/script/setup.tcl
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## ******************** 设置综合环境 ******************** ##
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set PR_PATH /home/project/ASIC/FFT_IFFT_IP/prj/P&R
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set LIB_PATH /home/project/ASIC/library/smic180/std
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set STD_NAME SCC018UG_UHD_RVT_V0p4a
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#导入milkway
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set tf_path $LIB_PATH/$STD_NAME/astro/tf
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set mw_path $LIB_PATH/$STD_NAME/astro/scc018ug_uhd_rvt
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set tluplus $LIB_PATH/$STD_NAME/astro/tluplus
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create_mw_lib MWlib.mw \
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-technology $tf_path \
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-mw_reference_library $mw_path -open
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#导入网表文件
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import_designs $RES_OUT/$CURR_DESIGN.ddc \
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-format ddc \
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-top $CURR_DESIGN
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uniquify_fp_mw_cel
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current_design $CURR_DESIGN
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#导入RC参数文件和.map文件
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set_tlu_plus_files \
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-max_tluplus $tluplus/smiclog018_6lm_cell_max.tluplus \
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-min_tluplus $tluplus/smiclog018_6lm_cell_min.tluplus \
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-tech2itf_map $tluplus/smic18_6lm_lef_smic18_6lm_tf.map
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report_tlu_plus_files > $RPT_OUT/report_tlu_plus.rpt
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check_tlu_plus_files > $RPT_OUT/check_tlu_plus.rpt
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remove_sdc
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read_sdc /home/project/ASIC/FFT_IFFT_IP/user/data/constraint/timing.sdc
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set_clock_uncertainty 2 [all_clocks]
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remove_propagated_clock [all_clocks]
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check_timing
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save_mw_cel
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start_gui |