7 lines
351 B
Tcl
7 lines
351 B
Tcl
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
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set hdlout_internal_busses true
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set bus_inference_style "%s\[%d\]"
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set veriligout_no_tri true
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define_name_rules verilog -check_bus_indexing -allowed {a-zA-Z0-9_} -remove_internal_net_bus -flatten_multi_dimension_busses -first_restricted "\\"
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change_names -rules verilog -hier -verbose
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