23 lines
493 B
Verilog
23 lines
493 B
Verilog
`define cow 34
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module dependence_1 (
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input port_a, port_b, port_c,
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output out_q
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);
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// a & b | ((b & c) & (b | c))
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// &=*, |=+ AB + BC(B+C)
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// Distribute AB + BBC + BCC
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// Simplify AA = A AB + BC + BC
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// Simplify A + A = A AB + BC
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// Factor B(A+C)
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assign out_q = port_b & (port_a | port_c);
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endmodule
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module test_1 (
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input port_a, port_b,
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output Q
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);
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assign Q = port_b & port_a;
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endmodule |