35 lines
522 B
Verilog
35 lines
522 B
Verilog
module dependence_1 (
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input a, b, c,
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output Q
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);
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// a & b | ((b & c) & (b | c))
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// &=*, |=+ AB + BC(B+C)
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// Distribute AB + BBC + BCC
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// Simplify AA = A AB + BC + BC
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// Simplify A + A = A AB + BC
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// Factor B(A+C)
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assign Q = a & (b | c);
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endmodule
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`include "adwada"
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`define main dwwds
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`define ada wss
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/*
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*/
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`main
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module dependence_2 (
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input a, b, c,
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output Q
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);
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assign Q = a & b | ((b & c) & (b | c));
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endmodule |