106 lines
2.7 KiB
VHDL
106 lines
2.7 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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entity genericmap is
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generic(
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rst_val : std_logic := '0';
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thing_size: integer := 201 rem 2;
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bus_width : integer := 201 mod 32);
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port(
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clk, rstn : in std_logic;
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en, start_dec : in std_logic;
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addr : in std_logic_vector(2 downto 0);
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din : in std_logic_vector(25 downto 0);
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we : in std_logic;
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pixel_in : in std_logic_vector(7 downto 0);
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pix_req : in std_logic;
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bip : in std_logic;
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a, b : in std_logic_vector(7 downto 0);
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c, load : in std_logic_vector(7 downto 0);
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pack : in std_logic_vector(6 downto 0);
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base : in std_logic_vector(2 downto 0);
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qtd : in std_logic_vector(21 downto 0);
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-- Outputs
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dout : out std_logic_vector(25 downto 0);
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pixel_out : out std_logic_vector(7 downto 0);
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pixel_valid : out std_logic;
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code : out std_logic_vector(9 downto 0);
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complex : out std_logic_vector(23 downto 0);
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eno : out std_logic
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);
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end genericmap;
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architecture rtl of genericmap is
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component dsp
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generic(
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rst_val : std_logic := '0';
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thing_size: integer := 201;
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bus_width : integer := 24);
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port(
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-- Inputs
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clk, rstn : in std_logic;
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en, start : in std_logic;
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param : in std_logic_vector(7 downto 0);
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addr : in std_logic_vector(2 downto 0);
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din : in std_logic_vector(bus_width-1 downto 0);
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we : in std_logic;
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memdin : out std_logic_vector(13 downto 0);
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-- Outputs
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dout : out std_logic_vector(bus_width-1 downto 0);
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memaddr : out std_logic_vector(5 downto 0);
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memdout : out std_logic_vector(13 downto 0)
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);
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end component;
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signal param : std_logic_vector(7 downto 0);
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signal selection : std_logic;
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signal start, enf : std_logic; -- Start and enable signals
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signal memdin : std_logic_vector(13 downto 0);
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signal memaddr : std_logic_vector(5 downto 0);
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signal memdout : std_logic_vector(13 downto 0);
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signal colour : std_logic_vector(1 downto 0);
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begin
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dsp_inst0 : dsp
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-- default bus_width is 24
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port map(
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-- Inputs
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clk => clk,
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rstn => rstn,
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en => '1',
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start => '0',
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param => X"42",
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addr => "101",
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din => "000100010001000100010001",
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we => '0',
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-- Outputs
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dout => dout(23 downto 0),
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memaddr => memaddr,
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memdout => memdout
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);
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dsp_inst1 : dsp
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generic map(
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rst_val => '1',
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bus_width => 16)
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port map(
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-- Inputs
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clk => clk,
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rstn => rstn,
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en => '1',
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start => '0',
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param => X"42",
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addr => "101",
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din => "0001000100010001",
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we => '0',
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-- Outputs
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dout => dout(15 downto 0),
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memaddr => memaddr,
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memdout => memdout
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);
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signextend_inst2 : entity work.signextend
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port map (
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i => "0000000000000000",
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o => open
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);
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end rtl;
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