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@ -16,11 +16,22 @@ module.exports = {
|
||||
* ref：https://v1.vuepress.vuejs.org/config/#head
|
||||
*/
|
||||
head: [
|
||||
['meta', { name: 'theme-color', content: '#3eaf7c' }],
|
||||
['meta', { name: 'theme-color', content: '#cb81da' }],
|
||||
['meta', { name: 'apple-mobile-web-app-capable', content: 'yes' }],
|
||||
['meta', { name: 'apple-mobile-web-app-status-bar-style', content: 'black' }]
|
||||
],
|
||||
|
||||
locales: {
|
||||
// The key is the path for the locale to be nested under.
|
||||
// As a special case, the default locale can use '/' as its path.
|
||||
'/': {
|
||||
lang: 'English', // this will be set as the lang attribute on <html>
|
||||
},
|
||||
'/zh/': {
|
||||
lang: '简体中文',
|
||||
}
|
||||
},
|
||||
|
||||
/**
|
||||
* Theme configuration, here is the default theme configuration for VuePress.
|
||||
*
|
||||
@ -29,17 +40,12 @@ module.exports = {
|
||||
themeConfig: {
|
||||
repo: '',
|
||||
editLinks: false,
|
||||
docsDir: '',
|
||||
editLinkText: '',
|
||||
logo: '/icon.png',
|
||||
lastUpdated: false,
|
||||
nav: [
|
||||
{
|
||||
text: 'Guide',
|
||||
link: '/guide/',
|
||||
},
|
||||
{
|
||||
text: 'Config',
|
||||
link: '/config/'
|
||||
link: '/guide/introduction',
|
||||
},
|
||||
{
|
||||
text: 'Github',
|
||||
@ -52,8 +58,68 @@ module.exports = {
|
||||
title: 'Guide',
|
||||
collapsable: false,
|
||||
children: [
|
||||
'',
|
||||
'using-vue',
|
||||
'introduction',
|
||||
'installation',
|
||||
'todo',
|
||||
]
|
||||
},
|
||||
{
|
||||
title: 'Language Services',
|
||||
collapsable: false,
|
||||
children: [
|
||||
"language-service"
|
||||
]
|
||||
},
|
||||
{
|
||||
title: 'Project Management',
|
||||
collapsable: false,
|
||||
children: [
|
||||
'pm-introduction',
|
||||
'pm-project-building',
|
||||
'pm-simulation-building',
|
||||
'pm-design-assistance'
|
||||
]
|
||||
},
|
||||
{
|
||||
title: 'About',
|
||||
collapsable: false,
|
||||
children: [
|
||||
"about"
|
||||
]
|
||||
}
|
||||
],
|
||||
'/zh/guide/': [
|
||||
{
|
||||
title: '指南',
|
||||
collapsable: false,
|
||||
children: [
|
||||
'introduction',
|
||||
'installation',
|
||||
'todo',
|
||||
]
|
||||
},
|
||||
{
|
||||
title: '语言服务',
|
||||
collapsable: false,
|
||||
children: [
|
||||
"language-service"
|
||||
]
|
||||
},
|
||||
{
|
||||
title: '项目管理',
|
||||
collapsable: false,
|
||||
children: [
|
||||
'pm-introduction',
|
||||
'pm-project-building',
|
||||
'pm-simulation-building',
|
||||
'pm-design-assistance'
|
||||
]
|
||||
},
|
||||
{
|
||||
title: '关于',
|
||||
collapsable: false,
|
||||
children: [
|
||||
"about"
|
||||
]
|
||||
}
|
||||
],
|
||||
|
||||
BIN
src/.vuepress/public/images/1.1.gif
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BIN
src/.vuepress/public/images/1.1.gif
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After Width: | Height: | Size: 2.2 MiB |
BIN
src/.vuepress/public/images/1.2.gif
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src/.vuepress/public/images/1.2.gif
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After Width: | Height: | Size: 1.3 MiB |
BIN
src/.vuepress/public/videos/1.1.mp4
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src/.vuepress/public/videos/1.1.mp4
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src/.vuepress/public/videos/1.2.mp4
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src/.vuepress/public/videos/1.2.mp4
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src/.vuepress/public/videos/2.1.mp4
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src/.vuepress/public/videos/2.2.mp4
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src/.vuepress/public/videos/2.4.mp4
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src/.vuepress/public/videos/code2doc.mp4
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src/.vuepress/public/videos/code2doc.mp4
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src/.vuepress/public/videos/exportpdf.mp4
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src/.vuepress/public/videos/exportpdf.mp4
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src/.vuepress/public/videos/fsm.mp4
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src/.vuepress/public/videos/fsm.mp4
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src/.vuepress/public/videos/linter.1.mp4
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src/.vuepress/public/videos/linter.1.mp4
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src/.vuepress/public/videos/linter.2.mp4
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src/.vuepress/public/videos/netlist.mp4
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src/.vuepress/public/videos/netlist.mp4
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src/.vuepress/public/videos/project.mp4
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src/.vuepress/public/videos/project.mp4
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src/.vuepress/public/videos/treeview.mp4
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src/.vuepress/public/videos/treeview.mp4
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@ -6,3 +6,25 @@
|
||||
|
||||
.home .hero img
|
||||
max-width 450px!important
|
||||
|
||||
|
||||
html {
|
||||
scrollbar-width: none;
|
||||
/* firefox */
|
||||
-ms-overflow-style: none;
|
||||
/* IE 10+ */
|
||||
overflow-x: hidden;
|
||||
overflow-y: auto;
|
||||
}
|
||||
|
||||
html::-webkit-scrollbar {
|
||||
width: 6px;
|
||||
}
|
||||
|
||||
html::-webkit-scrollbar-track {
|
||||
background: var(0, 0, 0, 0.1);
|
||||
}
|
||||
|
||||
html::-webkit-scrollbar-thumb {
|
||||
background: #cb81da;
|
||||
}
|
||||
@ -1,15 +0,0 @@
|
||||
---
|
||||
sidebar: auto
|
||||
---
|
||||
|
||||
# Config
|
||||
|
||||
## foo
|
||||
|
||||
- Type: `string`
|
||||
- Default: `/`
|
||||
|
||||
## bar
|
||||
|
||||
- Type: `string`
|
||||
- Default: `/`
|
||||
22
src/guide/about.md
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22
src/guide/about.md
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@ -0,0 +1,22 @@
|
||||
---
|
||||
title: about
|
||||
---
|
||||
|
||||
## Developers (Github Account)
|
||||
|
||||
- Nitcloud: Product Optimization and Requirements Engineering.
|
||||
- Kylin: HDL Syntax Parser and Wasm Construction.
|
||||
|
||||
- LSTM-Kirigaya: Digital-IDE kernel implementation and UI design.
|
||||
|
||||
|
||||
---
|
||||
|
||||
## Acknowledgements
|
||||
|
||||
* [VHDL](https://github.com/puorc/awesome-vhdl)
|
||||
* [yosys](http://www.clifford.at/yosys)
|
||||
* [TerosHDL](https://github.com/TerosTechnology/vscode-terosHDL)
|
||||
* [TCL Language Support](https://github.com/go2sh/tcl-language-support)
|
||||
* [Verilog HDL/SystemVerilog](https://github.com/mshr-h/vscode-verilog-hdl-support)
|
||||
* [SystemVerilog - Language Support](https://github.com/eirikpre/VSCode-SystemVerilog)
|
||||
@ -1,5 +1,5 @@
|
||||
---
|
||||
title: installation
|
||||
title: Installation
|
||||
---
|
||||
|
||||
## Install from Vscode
|
||||
@ -9,11 +9,12 @@ Search for “Digital IDE” in the Vscode plugin store and click download.
|
||||
> Note: The plug-in itself has been optimized to a size of 11MB. The plugin is download-to-use, and no environment is required unless other third-party tools (such as: vivado, iverilog, etc.) are needed, which need to be installed by yourself.
|
||||
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://img1.imgtp.com/2023/08/17/x957j0Ml.gif" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/1.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
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||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
## Install beta version
|
||||
@ -23,4 +24,12 @@ If you want to use the newest beta version of our plugin, you can get access to
|
||||
1. Download `fpga-support-{version}.vsix` from [releases](https://github.com/Digital-EDA/Digital-IDE/releases) .
|
||||
2. Join our QQ Group and get `fpga-support-{version}.vsix` .
|
||||
|
||||
Once you download the vsix, run the
|
||||
Once you download the vsix, you can install from vsix:
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/1.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
@ -2,11 +2,9 @@
|
||||
title: Introduction
|
||||
---
|
||||
|
||||
#! https://zhuanlan.zhihu.com/p/365805011
|
||||
## Welcome
|
||||
|
||||
## Digital IDE - version 0.3.2
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -16,12 +14,10 @@ The purpose of this extension is to provide a friendly and convenient developmen
|
||||
|
||||
|
||||
[GitHub](https://github.com/Digital-EDA/Digital-IDE)
|
||||
[Get Started](#Get-Started-Quickly)
|
||||
[中文](https://digital-eda.github.io/DIDE-doc-Cn/#/)
|
||||
|
||||
## Preface
|
||||
|
||||
- Installation address[Installation address](https://marketplace.visualstudio.com/items?itemName=sterben.fpga-support)
|
||||
- Installation address [Installation address](https://marketplace.visualstudio.com/items?itemName=sterben.fpga-support)
|
||||
- If you have any questions, please leave a message on the [issues](https://github.com/Bestduan/Digital-IDE/issues)
|
||||
- If you like it, click on the[star](https://github.com/Bestduan/Digital-IDE)
|
||||
- email： sterben.nitcloud@gmail.com | zhelonghuang@mail.ustc.edu.cn
|
||||
172
src/guide/language-service.md
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172
src/guide/language-service.md
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@ -0,0 +1,172 @@
|
||||
---
|
||||
title: Introduction
|
||||
---
|
||||
|
||||
Provide the basic language services required for front-end code design
|
||||
|
||||
|
||||
## Language Highlight
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://picx.zhimg.com/80/v2-0b3740ecd3e9fd2d77e73595c20a7c5a_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
The following languages are now supported for highlighting
|
||||
1. HDL
|
||||
- verilog
|
||||
- systemverilog
|
||||
- VHDL
|
||||
2. TCL
|
||||
- xdc
|
||||
- sdc
|
||||
- fdc (including xdc、sdc、fdc)
|
||||
|
||||
---
|
||||
|
||||
## Syntax Diagnosis
|
||||
|
||||
We provide different linter for verilog, vhdl, systemverilog to diagnose your code.
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/linter.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/linter.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
After version 0.3.0, the plugin will support a built-in syntax diagnostic tool that does not require downloading any third-party tools. The supported syntax includes:
|
||||
- verilog
|
||||
- vhdl (bugs remain)
|
||||
- systemverilog (developing)
|
||||
|
||||
---
|
||||
|
||||
## Outline
|
||||
|
||||
The outline of the current HDL code can be seen on the left side of the workspace to quickly locate the module or variable you need to see.
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://picx.zhimg.com/80/v2-1a7702db958deed33dfd9d218efc241f_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
---
|
||||
|
||||
## Hover Tips
|
||||
|
||||
When you move the mouse over a variable, macro, example module, etc. that you want to view, the declaration definition of the current variable is displayed.
|
||||
|
||||
> If it is a module, information such as the number of ports of each type for the module is also displayed.
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://pic1.zhimg.com/80/v2-3548c2344be35b502ec46d8a6c0a6165_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
The prompts are as follows:
|
||||
1. `mark corresponding comment` + `mark corresponding content`
|
||||
2. binary, hexadecimal -> decimal
|
||||
|
||||
where contents of the comment corresponding to the marker are
|
||||
1. line comments after the line where the marker is defined
|
||||
2. line comments and block comments (stopping when a non-commented part is encountered) before the marker is defined
|
||||
|
||||
> Hover tips use the built-in vlog and vhdl parser, which currently only support simple hover tips
|
||||
|
||||
---
|
||||
|
||||
## Completion
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
The auto-completion provided by the plugin is divided into two parts:
|
||||
1. snippet file provided by the auto-complete, support for user-added
|
||||
2. keyword triggered auto-completion
|
||||
1. `. `. Keyword triggers the completion of the port or parameter name of the exemplified module.
|
||||
2. `\`` Keyword triggers the completion of macro definition identifiers.
|
||||
3. `/` key triggers path completion in include.
|
||||
|
||||
> Currently, auto-completion is only supported in verilog and systemverilog for port parameter routines.
|
||||
|
||||
A description of the parameters that can be set for auto-completion:
|
||||
|
||||
1. `function.lsp.completion.vlog.autoAddInclude`
|
||||
- Whether or not to automatically add an include to the beginning of a file when instantiating a module, default is true.
|
||||
2. `function.lsp.completion.vlog.completeWholeInstante`
|
||||
- Whether or not to complete all parameters and ports needed for the whole instantiation, default is true.
|
||||
3. `function.instantiation.addComment`
|
||||
- Whether to add some comments after the instantiation, default is true.
|
||||
4. `function.instantiation.autoNetOutputDeclaration`
|
||||
- Whether to automatically complete the definition of all output ports after instantiation, default is true.
|
||||
|
||||
---
|
||||
|
||||
## Definition Jumps
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
If the hover tip support is valid, then it can support the definition jump.
|
||||
However, there are some times when the definition jump cannot be done because the interpreter does not interpret the code correctly, so you can set `linter` to `default` and use the interpreter to check the correctness of the code syntax.
|
||||
|
||||
|
||||
---
|
||||
|
||||
## Code Formatter
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.3.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
You can format the document with selected characters or full text. Vscode comes with shortcuts to open：`shift + alt + f`. Related setting description:
|
||||
- verilog and systemverilog
|
||||
1. `function.lsp.formatter.vlog.default.style`
|
||||
- verilog and systemverilog formatting types, supporting three types `kr`, `ansi`, `gun`
|
||||
2. `function.lsp.formatter.vlog.default.args`
|
||||
- Other parameter inputs and vlog formatting use istyle's webassembly, so please refer to istyle for the parameters to be entered.
|
||||
> This function is based on istyle to achieve, so the full-text formatting is still not perfect, it is recommended to check the always statement block to format, and later will continue to fix related problems.
|
||||
|
||||
- vhdl
|
||||
1. `function.lsp.formatter.vhdl.default.align-comments`
|
||||
- whether need to align comments
|
||||
2. `function.lsp.formatter.vhdl.default.indentation`
|
||||
- the number of spaces corresponding to the tab
|
||||
|
||||
---
|
||||
|
||||
## Vhdl to Verilog Translation
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.4.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
Currently only vhdl to Verilog translation is supported.
|
||||
If there is no output, it means that the syntax of vhdl is wrong, or there is a syntax that the plugin cannot parse.
|
||||
78
src/guide/pm-design-assistance.md
Normal file
78
src/guide/pm-design-assistance.md
Normal file
@ -0,0 +1,78 @@
|
||||
---
|
||||
title: Design Assistance
|
||||
---
|
||||
|
||||
## Tree View
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/treeview.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
Display the project structure of the current workspace in terms of modules, show the containment and inclusion relationship between HDL files in terms of hierarchy, and click to open the corresponding file.
|
||||
|
||||
> Note: The treeView only displays the HDL files in the user-specified or default workspace folder in property.json, the modules in other files will not be displayed in the treeView.
|
||||
|
||||
---
|
||||
|
||||
## Netlist Preview
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/netlist.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
The plugin uses `yosys 0.21` kernel (open source yosysjs 0.5 version) to synthesize the specified project (can run on all platforms), display the synthesized network diagram and support `include` and multi-file projects.
|
||||
|
||||
How to use
|
||||
1. Click the icon in the upper right corner to create the panel
|
||||
2. Or select the module you want to display in the project structure, or right click in the file and select `show netlist`.
|
||||
|
||||
> The current version of the netlist front-end is not perfect, future versions will optimize the front-end UI.
|
||||
|
||||
---
|
||||
|
||||
## Code to Doc
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/code2doc.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
Auto-documentation currently only supports verilog and wavedrom visualization, and also supports the following three export formats:
|
||||
|
||||
- markdown
|
||||
- html
|
||||
- pdf
|
||||
|
||||
If you need to export pdf, please fill the startup path of your local Google Chrome or Edge browser into the parameter **markdown-pdf executable path**. As most pdf readers do not support color changing background, please export your pdf in light color theme:
|
||||
|
||||
> > In windows 11, the default startup path for Edge is `C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe`.
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/exportpdf.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
---
|
||||
|
||||
## FSM Preview
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/fsm.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
This feature visualizes the finite state machine in a project and allows you to click on the shapes in the diagram to jump around.
|
||||
|
||||
> The front-end is currently quite minimal and the front-end UI of the FSM feature will be optimized in the future.
|
||||
18
src/guide/pm-introduction.md
Normal file
18
src/guide/pm-introduction.md
Normal file
@ -0,0 +1,18 @@
|
||||
---
|
||||
title: Introduction
|
||||
---
|
||||
|
||||
Project management mainly needs to realize the following operations:
|
||||
1. Project construction
|
||||
1. project Manager (PS & PL)
|
||||
2. lib Manager (IP & bd)
|
||||
2. Simulation construction
|
||||
1. generate instance & tb file
|
||||
2. fast simulate
|
||||
3. Design support
|
||||
1. [x] tree Structure
|
||||
2. [x] netlist preview
|
||||
3. [x] Code to doc
|
||||
4. [x] fsm preview
|
||||
5. [ ] fsm designer
|
||||
6. [ ] waveform preview
|
||||
118
src/guide/pm-project-building.md
Normal file
118
src/guide/pm-project-building.md
Normal file
@ -0,0 +1,118 @@
|
||||
---
|
||||
title: Project Building
|
||||
---
|
||||
|
||||
The purpose of project building is to help users quickly build their own third-party projects, especially `project Manager` is related to third-party tool chain. Currently, the only compatible third-party tool is xilinx's vivado (other third-parties will continue to be supported in the future). However, `lib Manager` is to avoid repeatedly build a wheel and provide a function to facilitate the user to use some common HDL libraries provided by plugin, but also support the user to accumulate their own library.
|
||||
|
||||
## Project Manager
|
||||
Main purposes of the `project manager` are as follows:
|
||||
1. abstract out the function to reduce the learning cost of other three-party tools
|
||||
2. erase version differences, allowing more focus on the source code design
|
||||
- Because as long as you have the configuration file and design source, you can restore the project under any vivado version.
|
||||
|
||||
`[Note]`: `project Manager` is strongly dependent on the property configuration file `property.json`, if missing, it will directly use the default (template) configuration.
|
||||
|
||||
For project management on the PL side, I have abstracted the following functions:
|
||||
1. launch ------ to start the whole project, or create it if there is no project, or open it directly if there is
|
||||
2. refresh ----- to refresh the whole project and update the design of the whole project
|
||||
3. simulate ---- to simulate the whole project, without opening the GUI interface by default *`(using the simulator in TOOL_CHAIN)*
|
||||
1. simGUI ----- open the GUI interface after successful simulation
|
||||
2. simCLI ----- does not open the GUI interface after successful simulation
|
||||
4. build ------- to build the whole project and finally output the bit stream file
|
||||
1. synth ------ to synthesize the project
|
||||
2. impl ------- to implement the project
|
||||
3. bit -------- to export the project's bitstream file
|
||||
5. program ----- download the bitstream file to the FPGA/zynq board *`(download and burn, but not solidify)`*
|
||||
6. gui --------- open the GUI interface of the tool chain
|
||||
1. After opening the GUI, the terminal named *`HardWare`* is not recommended to close by itself.
|
||||
- The whole GUI interface will be closed automatically after direct closure, and if not saved then the design may be lost.
|
||||
- The plugin will not move your `IP and bd design` to the same level of `Hardware/src/` after closing directly.
|
||||
7. exit -------- Closing the project is only valid under the CLI, after opening the GUI, terminal control is taken over by the GUI.
|
||||
1. After clicking `exit` the plugin will move your `IP and bd design` to the same level of `Hardware/src/`.
|
||||
2. If you close the terminal named *`HardWare`* directly, the move of `IP and bd designs` will not take place.
|
||||
3. Note: You can also move your `IP and bd designs` to the same level of `Hardware/src/` when *Clean* is in the function bar *TOOL*.
|
||||
|
||||
In addition to the above explicit functions, there are two implicit functions each in the `architecture` column, which are
|
||||
1. `Set as Top` -------------- sets this file as the top-level design module of the current project
|
||||
2. `Set as Testbench Top` ---- sets the file as the top-level module of the simulation for the current project
|
||||
|
||||
Specially, *`Zynq`* devices support mixed PS+PL development. To cope with the mixed development, the plugin gives the `soc` configuration as follows:
|
||||
```json
|
||||
"soc": {
|
||||
"core": "ps7_cortexa9_0",
|
||||
"bd" : "zynq_default"
|
||||
}
|
||||
```
|
||||
Using the configuration plugin as above will automatically build a bd project containing the zynq design to help users quickly build the platform.
|
||||
|
||||
Finally, about device selection, it can be configured in the `property.json` file under the *device* property.
|
||||
The following are currently available:
|
||||
- xc7z020clg400-2
|
||||
- xc7a35tftg256-1
|
||||
- xc7a35tcsg324-1
|
||||
- xc7z035ffg676-2
|
||||
- xc7z020clg484-1
|
||||
|
||||
But the supported devices are not limited to these, theoretically all the devices that vivado can support can be supported. You can write your device directly to the *Device* attribute, which will give you a warning if the device is not in the database, but will not prevent you from running. To remove the warning you need to add your device to the database with the *FPGA:Add devices to the database* command. Unneeded devices can also be removed from the database with *FPGA:Remove the device from the database*.
|
||||
|
||||
**Related setting**
|
||||
`prj.vivado.install.path` --- Installation path of vivado
|
||||
When vivado is installed, you can configure the installation path of vivado directly inside the plugin, or you can add vivado to the environment variables (recommended). If the path is not found by mistake, it is already added to the environment variables by default.
|
||||
*e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin/*
|
||||
`[Note]`: Use `/` to separate the paths and configure them to the bin directory.
|
||||
|
||||
`prj.xilinx.IP.repo.path` ---- User-designed IP libraries from xilinx
|
||||
After configuring this property, the plugin will automatically add the path to the IP repo of vivado.
|
||||
*e.g. : D:/project/FPGA/.Lib/xIP*
|
||||
|
||||
`prj.xilinx.BD.repo.path` ---- User-defined placement path for xilinx block design files
|
||||
*e.g. : D:/project/FPGA/.Lib/xbd*
|
||||
|
||||
|
||||
## lib Manager
|
||||
The plugin comes with HDL function library linking function.
|
||||
The `property.json` file is configured as follows:
|
||||
```json
|
||||
"library" : {
|
||||
"state": "", // local | remote(default)
|
||||
"hardware" : {
|
||||
"common": [],
|
||||
"custom": []
|
||||
}
|
||||
},
|
||||
|
||||
"IP_REPO": [
|
||||
"arm", // including ip CM3DbgAXI & DAPLink_to_Arty_shield
|
||||
"adi" // containing all device ip's under the adi company, with the included absolute paths removed Taken from adi2019_r1
|
||||
],
|
||||
```
|
||||
|
||||
It is not recommended that users configure the library properties in the `property.json` file by themselves. It is recommended to use the *import library* command, or the icon activation command in the following figure to do so.
|
||||
|
||||
The *state* represents whether the library file is loaded into the local workspace, or linked as a remote.
|
||||
- `remote` represents virtual inclusion from a remote (anything not under the workspace is considered remote, not remote on the network).
|
||||
- remote library files can be opened and changed *(`Note: `If the next import after the change is the code after the change)* .
|
||||
- `local` means import the remote file into the project locally
|
||||
1. placed in the lib under `arch.hardware.src`, the changes will not affect the code in the remote library.
|
||||
2. *`[Note]`: When changing from local back to remote the lib folder will be deleted (plugin will remind), please note*.
|
||||
|
||||
The property *common* represents the HDL function library that comes with the plugin, *the code of this library is less mature and is for reference only*.
|
||||
The lib paths that have been simulated and tested so far are as follows
|
||||
- Soc
|
||||
- Math/Cordic.v
|
||||
- Math/Sort3.v
|
||||
- Math/Sqrt.v
|
||||
- Malloc/RAM/Shift_RAM
|
||||
- Apply/DSP/Advance/Communicate/Modulate
|
||||
- Apply/DSP/Base/DDS
|
||||
- Apply/Image (need to include Sort3, Sqrt, Shift_RAM)
|
||||
|
||||
`[Note]`: When the input is a folder then it contains all the files under that folder. In addition, it is not recommended to change the code in this library directly, otherwise it will be overwritten again after the next plugin update, please be careful.
|
||||
|
||||
The property *custom* represents a user-defined HDL function library.
|
||||
The use of this property requires the root directory of the user-defined library to be configured for *prj.lib.custom.path* under *setting*, and the absolute path of the file (folder) with the configuration under the *custom* property. The representation is as follows:
|
||||
*`prj.lib.custom.path`*`/`*`${custom}`*
|
||||
|
||||
`[Note]`: When the input is a folder then it contains all the files under that folder.
|
||||
|
||||
Finally, for the `IP_REPO` property, this is the two official xilinx IP repo provided by the plugin to users, choose the one you want to configure, and the plugin will automatically add it to the IP repo of Vivado, which is convenient for users to develop directly without having to compile and import it by themselves.
|
||||
67
src/guide/pm-simulation-building.md
Normal file
67
src/guide/pm-simulation-building.md
Normal file
@ -0,0 +1,67 @@
|
||||
---
|
||||
title: Simulation Building
|
||||
---
|
||||
|
||||
The purpose of simulation building is to help users to build their own simulation framework quickly and get simulation results quickly.
|
||||
|
||||
## Generate instance & tb file
|
||||
|
||||
Although auto-completion can realize the automatic completion of the example, but it can not view the entire project all the available modules and select from them, so we provide automatic example of the function; In addition, we also provide automatic generation of the selected module testbench function.
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://img1.imgtp.com/2023/08/18/bA4ybk5Z.gif" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
The plugin supports cross instantiation between different languages, such as instantiating verilog and vhdl modules in a verilog file, or Verilog and vhdl modules in a vhdl file.
|
||||
|
||||
The steps are as follows:
|
||||
1. Place the cursor where the text needs to be instantiated.
|
||||
2. Start the command box by `F1`, type *Instance*, and select `TOOL:Instance`.
|
||||
1. or use the shortcut `Alt + I`
|
||||
2. or right-click on the module to be instantiated and select `Instance`
|
||||
3. Enter the keyword of the module to be instantiated (the plugin will automatically match it).
|
||||
4. Select the module you want to instantiate.
|
||||
|
||||
`[Note]`: When using shortcut keys, you need to check if there is a shortcut key conflict.
|
||||
|
||||
In addition to automatic instantiation, the plugin also provides a simulation template for verilog, which is used as follows:
|
||||
1. Start the command box by `F1`, type *Testbench*, and select `TOOL:Testbench`.
|
||||
1. or right-click under the file to be generated and instantiated and select `Testbench`.
|
||||
2. Select the type of simulation file and the location where you want to store it, and replace it directly if it exists.
|
||||
|
||||
If you want to change the template of testbench, proceed as follows:
|
||||
Use the shortcut `F1` to start the command box, then select TOOL:Overwrite the template of testbench to choose the type of simulation file you want to change. This will open the initialization file of the testbench file, what you need to do is saving the changes based on this. In addition, please keep the `//Instance` flag, which is used to identify the location to be instantiated.
|
||||
|
||||
The intelligent connection between the tb file and the instantiated module will be considered later.
|
||||
|
||||
## Fast Simulate
|
||||
The purpose of this feature is to enable fast simulation of a single module, or a small project consisting of several modules.
|
||||
Currently the only supported simulation tool is iverilog, which will be continuously updated to add new support.
|
||||
|
||||
**Iverilog Fast Simulation**
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://img1.imgtp.com/2023/08/18/7PS5Cp37.gif" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
- If you want to use this feature, please download iverilog by yourself and add environment variables.
|
||||
- VCD rendering is currently using wavetrace, a vscode plugin, the next version will introduce an embedded waveform renderer that we have developed, and it is completely free.
|
||||
- In term of Multi-file simulation, we recommend not to write include, if you write include, please add the folder path of all included files in property.json, for example:
|
||||
|
||||
```json
|
||||
{
|
||||
...
|
||||
"iverilogCompileOptions": {
|
||||
"standard": "2012",
|
||||
"includes": [
|
||||
"${workspace}/src",
|
||||
"${workspace}/src/Controller",
|
||||
"${workspace}/src/DataPath"
|
||||
]
|
||||
},
|
||||
...
|
||||
}
|
||||
```
|
||||
124
src/guide/project-configuration.md
Normal file
124
src/guide/project-configuration.md
Normal file
@ -0,0 +1,124 @@
|
||||
---
|
||||
title: Project Configuration
|
||||
---
|
||||
|
||||
Before the introduction of functions, it is important to know the basic structure of the project.
|
||||
|
||||
## Project Configuration File Generation
|
||||
Use * TOOL: generate property file * to generate the initial ` property. json ` template file. The generated file will be placed directly in the .vscode folder.
|
||||
If you have your own template, you can customize the template file using * TOOL: Overwrite the InitPropertyParam *.
|
||||
|
||||
> After version 0.3.0, the plugin will automatically ask users whether to create property.json every time it starts.
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/project.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
## Description Of the Project Configuration File
|
||||
> New configuration properties will be used after version 0.3.0
|
||||
```json
|
||||
// porperty.json All attributes explained
|
||||
{
|
||||
// Third-party tool chains currently in use
|
||||
"toolChain": "xilinx",
|
||||
|
||||
// Project naming
|
||||
// PL : Programming logic design part is FPGA before
|
||||
// PL : Processing system design part is the previous SOC
|
||||
"prjName": {
|
||||
"PL": "template",
|
||||
"PS": "template"
|
||||
},
|
||||
|
||||
// Custom project structure, without this attribute it is considered as a standard file structure (see below for details)
|
||||
// Project path, hardware and software design path
|
||||
// All properties support ${workspace}, ${plname}, ${psname}, relative paths
|
||||
// ${workspace} ： path to the current workspace
|
||||
// ${plname}、${psname} ：the name of the PL or PS project
|
||||
"arch" : {
|
||||
"prjPath": "",
|
||||
"hardware" : {
|
||||
"src" : "", // Place the design source file, note: src is one level below IP&bd
|
||||
"sim" : "", // Place the simulation file, which will be directly reflected in the tree structure
|
||||
"data" : "" // Place constraints and data files, constraints will be automatically added to the vivado project
|
||||
},
|
||||
"software" : {
|
||||
"src" : "",
|
||||
"data" : ""
|
||||
}
|
||||
},
|
||||
|
||||
// Code library management, support for remote and local two kinds of call (see the following library management for details)
|
||||
// Use UI to configure, not recommended for users to change directly
|
||||
"library" : {
|
||||
"state": "", // local | remote
|
||||
"hardware" : {
|
||||
"common": [], // Common libraries provided by the plugin
|
||||
"custom": [] // User's own design library
|
||||
}
|
||||
},
|
||||
|
||||
// Xilinx IP repository can be add directly to the IP repo of vivado
|
||||
// Only IP repositories of ADI and ARM are supported currently（adi | arm）
|
||||
"IP_REPO" : [],
|
||||
|
||||
// When the design uses PL + PS that is SOC development
|
||||
// Mixed development when the core is not none
|
||||
"soc": {
|
||||
"core": "none",
|
||||
"bd": "",
|
||||
"os": "",
|
||||
"app": ""
|
||||
},
|
||||
|
||||
// Whether the information is output at the terminal when the project is realized synthetically
|
||||
"enableShowLog": false,
|
||||
|
||||
// 设备类型 可以是如下几种：
|
||||
// "none",
|
||||
// "xc7z020clg400-2",
|
||||
// "xc7a35tftg256-1",
|
||||
// "xc7a35tcsg324-1",
|
||||
// "xc7z035ffg676-2",
|
||||
// "xc7z020clg484-1"
|
||||
"device": "none"
|
||||
}
|
||||
```
|
||||
|
||||
One of the most important attributes is the `arch` attribute, which is considered a user-defined project structure when configured. For user-defined structures, all file changes are managed by the user. When the `arch` attribute is not configured, it is considered to use the standard file structure recommended by the plugin. The description of the standard file structure is as follows.
|
||||
```
|
||||
.vscode
|
||||
└── property.json -- Project configuration file user-defined (or stored in the root of the workspace)
|
||||
prj -- Store project files
|
||||
├── simulation -- Store intermediate files for third-party simulation tool runtime
|
||||
├── intel -- Store intel project files
|
||||
└── xilinx -- Store xilinx project files
|
||||
user -- Store user-designed source files which are user-defined
|
||||
├── ip -- Store project ip code (managed by vendor tools, but moved to the same level of src by the plugin)
|
||||
├── bd -- Store the source code of project block designer(managed by vendor tools, but moved to the same level of src by the plugin)
|
||||
├── data -- mainly for data files and constraint files
|
||||
├── sim -- Store user's simulation code
|
||||
└── src -- Store user's design source code
|
||||
└─ lib -- Store user's hardware library source code
|
||||
```
|
||||
|
||||
When the `SOC.core` in the `property.json` file is not set to "none" and the configuration file is saved, the file structure will be automatically changed to a hybrid PS+PL design structure. Under this structure the user folder will change to the following structure:
|
||||
```
|
||||
user -- Store user-designed source files, user-defined
|
||||
Hardware -- mainly for hardware logic design
|
||||
├── ip -- Store project ip code (managed by vendor tools, but moved by the plugin to the same level directory as src)
|
||||
├── bd -- Store project block designer source code (managed by vendor tools, but moved to src sibling directory by plugins)
|
||||
├── data -- mainly for data files and constraint files
|
||||
├── sim -- Store user's simulation code
|
||||
└── src -- Store user's design source code
|
||||
└─ lib -- Store user's hardware library source code
|
||||
Software -- Store software-driven designs
|
||||
├── data -- mainly for data files and constraint files
|
||||
└── src -- Store user's project source code
|
||||
```
|
||||
`[Note]`: When the value of `SOC.core` is changed from non-none to none, the Software folder is not needed by default and will be deleted (the plugin will also give a prompt accordingly), so please make a backup. Also, *IP and bd design will be placed to the directory above src, so it is better not to set src as the root path of the workspace*.
|
||||
|
||||
In addition, if the path configured by the user under arch is wrong or invalid, the plugin will directly change to the structure path under standard. *When the user does not configure the `property.json` file, the file structure will default to the path of the workspace, and this behavior may cause a lot of performance consumption, please pay attention to it*.
|
||||
@ -1,9 +0,0 @@
|
||||
# Using Vue in Markdown
|
||||
|
||||
## Browser API Access Restrictions
|
||||
|
||||
Because VuePress applications are server-rendered in Node.js when generating static builds, any Vue usage must conform to the [universal code requirements](https://ssr.vuejs.org/en/universal.html). In short, make sure to only access Browser / DOM APIs in `beforeMount` or `mounted` hooks.
|
||||
|
||||
If you are using or demoing components that are not SSR friendly (for example containing custom directives), you can wrap them inside the built-in `<ClientOnly>` component:
|
||||
|
||||
##
|
||||
12
src/index.md
12
src/index.md
@ -2,13 +2,17 @@
|
||||
home: true
|
||||
heroImage: /icon.png
|
||||
description: ASIC & FPGA Development Extension on Vscode
|
||||
actionText: Quick Start →
|
||||
actionLink: /guide/
|
||||
actionText: Quick Start 🐳
|
||||
actionLink: /guide/introduction
|
||||
features:
|
||||
- title: ✨ HDL Language Support
|
||||
details: Support verilog, vhdl, systemverilog, tcl scripts etc.
|
||||
- title: 🎯 Project Management
|
||||
details: View Structured HDL files in your project
|
||||
details: View Structured HDL files in your project.
|
||||
- title: 🛠️ Extra Tools
|
||||
details: FSM, Netlist, Simulation etc.
|
||||
details: FSM, Netlist, Fast Simulation, Code 2 Doc. Make you an amazing coding experience.
|
||||
---
|
||||
|
||||
::: slot footer
|
||||
MIT Licensed | Copyright © 2018-present [Digital-EDA](https://github.com/Digital-EDA)
|
||||
:::
|
||||
24
src/zh/guide/about.md
Normal file
24
src/zh/guide/about.md
Normal file
@ -0,0 +1,24 @@
|
||||
---
|
||||
title: 关于
|
||||
---
|
||||
|
||||
## 开发人员
|
||||
|
||||
- 夜云(Nitcloud)：产品优化与需求工程
|
||||
- 启示(Kylin)：HDL语法解析器与Wasm构建
|
||||
|
||||
- 锦恢(LSTM-Kirigaya)：Digital-IDE内核实现与UI设计
|
||||
|
||||
> 括号内为Github用户名
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 鸣谢
|
||||
|
||||
* [VHDL](https://github.com/puorc/awesome-vhdl)
|
||||
* [yosys](http://www.clifford.at/yosys)
|
||||
* [TerosHDL](https://github.com/TerosTechnology/vscode-terosHDL)
|
||||
* [TCL Language Support](https://github.com/go2sh/tcl-language-support)
|
||||
* [Verilog HDL/SystemVerilog](https://github.com/mshr-h/vscode-verilog-hdl-support)
|
||||
* [SystemVerilog - Language Support](https://github.com/eirikpre/VSCode-SystemVerilog)
|
||||
36
src/zh/guide/installation.md
Normal file
36
src/zh/guide/installation.md
Normal file
@ -0,0 +1,36 @@
|
||||
---
|
||||
title: 安装
|
||||
---
|
||||
|
||||
## 从 Vscode 安装
|
||||
|
||||
|
||||
在Vscode插件商店中搜索“Digital IDE”，点击下载即可。
|
||||
|
||||
> 注：插件本体已经优化到了11MB大小。本插件是下载即用，无需做任何环境，除非需要其他三方工具（如：vivado、iverilog等）时，要自行安装软件。
|
||||
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/1.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
## 安装最新测试版
|
||||
|
||||
如果您想使用我们插件的最新测试版，您可以通过以下方式获得最新版本:
|
||||
|
||||
1. 从 [releases](https://github.com/Digital-EDA/Digital-IDE/releases) 下载 `fpga-support-{version}.vsix` .
|
||||
2. 加入我们的QQ讨论群，并下载 `fpga-support-{version}.vsix` .
|
||||
|
||||
您一旦下载得到了 vsix 文件，就可以按照如下步骤安装：
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/1.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
42
src/zh/guide/introduction.md
Normal file
42
src/zh/guide/introduction.md
Normal file
@ -0,0 +1,42 @@
|
||||
---
|
||||
title: 介绍
|
||||
---
|
||||
|
||||
## 欢迎
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
本插件的开发目的首先在于为数字前端设计提供友好便捷的开发工具，在此之后，再在对FPGA的开发过程中进行去平台化，同时规范文件结构，完成完整统一友好的数字前后端设计链。紧接着兼容多家FPGA原厂后端设计，完成一条完整的数字设计链。最后，提供在FPGA上的soc设计方案，兼容soc调试工具。
|
||||
|
||||
|
||||
[GitHub](https://github.com/Digital-EDA/Digital-IDE)
|
||||
|
||||
|
||||
## 前言
|
||||
|
||||
- 安装地址 [插件市场](https://marketplace.visualstudio.com/items?itemName=sterben.fpga-support)。
|
||||
- 如有问题的话欢迎在 [issues](https://github.com/Bestduan/Digital-IDE/issues)上发表。
|
||||
- 喜欢的话请给个 [star](https://github.com/Bestduan/Digital-IDE)吧。
|
||||
- 邮箱： sterben.nitcloud@gmail.com | zhelonghuang@mail.ustc.edu.cn
|
||||
|
||||
- QQ群： 932987873
|
||||
|
||||
在使用过程中遇到问题的可以进QQ群与我联系，在群里我看到即回复。
|
||||
|
||||
## 关于反馈
|
||||
|
||||
首先感谢您的使用与反馈，首先如果您有关于此插件更好的想法在知乎和github下均可发表，但如果是使用中出现的问题请移步至[github](https://github.com/Bestduan/Digital-IDE/issues)发表，请勿在知乎下发表，感谢您的配合。
|
||||
|
||||
此外在发表issue的时候，请详细说明您所遇到的问题，重点包含以下部分
|
||||
- 更好看的图标
|
||||
- 运行环境
|
||||
- 使用版本
|
||||
- 报错信息 (来源：vscode本身以及Toggle Developer Tool)
|
||||
- 具体问题，以及出现的原因
|
||||
- 如果是特殊情况请粘贴源码 (为了更好的能复现问题)
|
||||
|
||||
- 请尽量截图展示
|
||||
177
src/zh/guide/language-service.md
Normal file
177
src/zh/guide/language-service.md
Normal file
@ -0,0 +1,177 @@
|
||||
---
|
||||
title: 介绍
|
||||
---
|
||||
|
||||
提供前端代码设计所需的基本语言服务。
|
||||
|
||||
|
||||
## 语言高亮
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://picx.zhimg.com/80/v2-0b3740ecd3e9fd2d77e73595c20a7c5a_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
现支持以下语言的高亮
|
||||
1. HDL
|
||||
- verilog
|
||||
- systemverilog
|
||||
- VHDL
|
||||
2. TCL
|
||||
- xdc
|
||||
- sdc
|
||||
- fdc (包括xdc、sdc、fdc约束文件)
|
||||
|
||||
---
|
||||
|
||||
## 语法诊断
|
||||
|
||||
我们为 verilog, vhdl, systemverilog 提供了不同的代码诊断器。
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/linter.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/linter.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
在该插件0.3.0版本之后将支持自带的语法诊断器，无需下载任何第三方工具支持的语法有：
|
||||
- verilog
|
||||
- vhdl (仍然有bug)
|
||||
- systemverilog (正在开发)
|
||||
|
||||
---
|
||||
|
||||
## 文件大纲
|
||||
|
||||
工作区左侧可以看到当前HDL代码的文件大纲，以便快速定位需要查看的模块或变量。
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://picx.zhimg.com/80/v2-1a7702db958deed33dfd9d218efc241f_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
---
|
||||
|
||||
## 悬停提示
|
||||
|
||||
将鼠标移动到需要查看的变量、宏、例化模块等上时，会显示当前变量的申明定义。
|
||||
|
||||
> 如果是模块，还会显示该模块的各种类型的端口数量等信息
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://pic1.zhimg.com/80/v2-3548c2344be35b502ec46d8a6c0a6165_1440w.png" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
主要提示的内容为当前文件内定义的数据类型以及例化模块的相关信息。
|
||||
提示内容如下：
|
||||
1. `标识对应的注释` + `标识对应的内容`
|
||||
2. 二进制、十六进制 -> 十进制
|
||||
|
||||
其中标识对应的注释的内容为
|
||||
1. 标识被定义的所在行后的行注释
|
||||
2. 标识被定义之前的行注释以及块注释(遇到非注释部分即停止)
|
||||
|
||||
> 悬停提示使用的是内置的vlog和vhdl解析器，目前暂时只支持简单的悬停提示
|
||||
|
||||
---
|
||||
|
||||
## 自动补全
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.1.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
该插件所提供的自动补全分两部分：
|
||||
1. snippet文件提供的自动补全，支持用户添加
|
||||
2. 关键符触发自动补全
|
||||
1. `.`关键符触发例化模块的端口或者参数名的补全
|
||||
2. ` 关键符触发宏定义标识的补全
|
||||
3. `/`关键符触发include中路径的补全
|
||||
|
||||
> 目前自动补全只支持在verilog和systemverilog中例化模块里进行端口参数例化时的补全
|
||||
|
||||
有关自动补全的几个可以设置的参数的说明：
|
||||
|
||||
1. `function.lsp.completion.vlog.autoAddInclude`
|
||||
- 是否在例化模块时自动在文件开头加入include，默认为true
|
||||
2. `function.lsp.completion.vlog.completeWholeInstante`
|
||||
- 是否完整地自动补全整个例化所需要的所有parameters和ports，默认为true
|
||||
3. `function.instantiation.addComment`
|
||||
- 是否在例化后加入一些注释，默认为true
|
||||
4. `function.instantiation.autoNetOutputDeclaration`
|
||||
- 是否在例化后自动完成所有output端口的定义，默认为true
|
||||
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 定义跳转
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.2.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
如果悬停提示支持有效那就能支持定义的跳转。
|
||||
但有些时候无法完成定义的跳转，其原因是解释器没有正确的解释出代码，这时候可以将`linter`设置为`default`，使用解释器进行检查查看代码语法的正确性。
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 代码格式化
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.3.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
|
||||
|
||||
可以对选中的字符或者全文进行文档的格式化 vscode自带快捷键打开方式：`shift + alt + f`。支持Verilog和VHDL。
|
||||
相关设置(setting)说明:
|
||||
- verilog and systemverilog
|
||||
1. `function.lsp.formatter.vlog.default.style`
|
||||
- verilog 和 systemverilog格式化类型，支持三种类型 `kr`、`ansi`、`gun`
|
||||
2. `function.lsp.formatter.vlog.default.args`
|
||||
- 其他参数输入，vlog的格式化使用的是istyle的webassembly因此要输入的参数请参考istyle
|
||||
> 由于该功能是基于istyle来实现的因此对全文格式化依旧不是很完善，建议选中always语句块来进行格式化，后期会持续修复相关问题。
|
||||
|
||||
- vhdl
|
||||
1. `function.lsp.formatter.vhdl.default.align-comments`
|
||||
- 是否需要对齐注释
|
||||
2. `function.lsp.formatter.vhdl.default.indentation`
|
||||
- tab所对应的空格数量
|
||||
|
||||
---
|
||||
|
||||
## VHDL 自动翻译为 Verilog
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/2.4.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
目前只支持vhdl转Verilog的翻译功能。
|
||||
如果没有输出的话，则意味着vhdl的语法错误，或者有插件无法解析的语法。转换后的verilog文件已经经过了格式化，不需要再次格式化。
|
||||
80
src/zh/guide/pm-design-assistance.md
Normal file
80
src/zh/guide/pm-design-assistance.md
Normal file
@ -0,0 +1,80 @@
|
||||
---
|
||||
title: 设计辅助
|
||||
---
|
||||
|
||||
## Tree View
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/treeview.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
以模块为单位，展示当前工作区的工程结构，以层级关系显示出HDL文件之间包含与被包含关系，单击后可打开对应的文件。
|
||||
|
||||
> 注意：treeView只展示property.json中用户指定或者默认的工作区文件夹的HDL文件，其他文件中的模块不会显示在treeView中
|
||||
|
||||
---
|
||||
|
||||
## Netlist 预览
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/netlist.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
The plugin uses `yosys 0.21` kernel (open source yosysjs 0.5 version) to synthesize the specified project (can run on all platforms), display the synthesized network diagram and support `include` and multi-file projects.
|
||||
|
||||
插件使用了`yosys 0.21`版本的内核(开源的yosysjs为0.5版本)进行指定工程的综合(可全平台运行)，并展示综合后的网络图，支持 `include` 以及多文件工程。
|
||||
|
||||
使用方式
|
||||
1. 点击右上角的图标进行面板的创建
|
||||
2. 或者在project structure中选择需要显示的模块，或者在文件中右击选择 `show netlist`
|
||||
|
||||
> 目前版本的netlist前端还不完善，未来的版本将会对前端UI进行优化
|
||||
|
||||
---
|
||||
|
||||
## 代码文档化
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/code2doc.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
自动文档化目前只支持verilog，并且支持wavedrom可视化，还支持如下三种导出格式：
|
||||
|
||||
- markdown
|
||||
- html
|
||||
- pdf
|
||||
|
||||
如果需要导出pdf，请将你本机的Google Chrome或者Edge浏览器的启动路径填入参数**markdown-pdf executable path**中。由于大部分pdf阅读器都不支持变色背景，请在浅色主题下导出你的pdf：
|
||||
|
||||
> windows 11 中，Edge的默认启动路径为 `C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe`
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/exportpdf.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
---
|
||||
|
||||
## FSM 预览
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/fsm.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
该功能可以可视化出项目中的有限状态机，并可以点击图中的形状进行跳转。
|
||||
|
||||
> 目前前端还比较简陋，未来会对FSM功能的前端UI进行优化。
|
||||
18
src/zh/guide/pm-introduction.md
Normal file
18
src/zh/guide/pm-introduction.md
Normal file
@ -0,0 +1,18 @@
|
||||
---
|
||||
title: 介绍
|
||||
---
|
||||
|
||||
工程管理主要需要实现以下几个业务
|
||||
1. 工程搭建类
|
||||
1. project Manager (PS & PL)
|
||||
2. lib Manager (IP & bd)
|
||||
2. 仿真搭建类
|
||||
1. generate instance & tb file
|
||||
2. fast simulate
|
||||
3. 设计辅助类
|
||||
1. [x]tree Structure
|
||||
2. [x]netlist preview
|
||||
3. [x]Code to doc
|
||||
4. [x]fsm preview
|
||||
5. []fsm designer
|
||||
6. []waveform preview
|
||||
117
src/zh/guide/pm-project-building.md
Normal file
117
src/zh/guide/pm-project-building.md
Normal file
@ -0,0 +1,117 @@
|
||||
---
|
||||
title: 工程搭建
|
||||
---
|
||||
|
||||
工程搭建的目的是帮助用户快速搭建属于自己第三方工程的，尤其是`project Manager`和第三方工具链相关，目前兼容的第三方工具只有xilinx的vivado（后续会继续支持其他三方）。而`lib Manager`则是为了避免重复造轮子而提供的一个功能，方便用户使用插件提供的一些常见HDL library，也支持用户自己积累library。
|
||||
|
||||
## Project Manager
|
||||
`project Manager`的主要目的如下：
|
||||
1. 抽象出功能，减少其他三方工具的学习成本
|
||||
2. 抹除版本差异，使得更加专注源码的设计
|
||||
- 因为只要有配置文件和设计源就能在任意一个vivado版本下还原工程
|
||||
|
||||
注：`project Manager`是强依赖属性配置文件`property.json`的，如果省缺会直接使用默认(模板)配置
|
||||
|
||||
对于PL端的工程管理，我抽象出以下几个功能：
|
||||
1. launch ------ 启动整个工程，如果没有工程则创建，有的话则直接打开
|
||||
2. refresh ----- 刷新整个工程，更新整个工程的设计
|
||||
3. simulate ---- 仿真整个工程，默认不打开GUI界面 *`（使用的是TOOL_CHAIN里的仿真器）`*
|
||||
1. simGUI ----- 仿真成功后打开GUI界面
|
||||
2. simCLI ----- 仿真成功后不打开GUI界面
|
||||
4. build ------- 构建整个工程，并最后输出bit流文件
|
||||
1. synth ------ 进行工程的综合
|
||||
2. impl ------- 进行工程的实现
|
||||
3. bit -------- 输出工程的bit流文件
|
||||
5. program ----- 比特流文件下载到FPGA/zynq板子中去 *`（下载烧写，但不固化）`*
|
||||
6. gui --------- 打开工具链的GUI界面
|
||||
1. 打开GUI后，名为 *`HardWare`* 的终端不建议自行关闭
|
||||
- 直接关闭后整个GUI界面会自动关闭，若不保存则可能会导致设计丢失。
|
||||
- 直接关闭后插件不会将你的`IP和bd设计`移动`Hardware/src/`的同级目录下
|
||||
7. exit -------- 关闭工程，仅在CLI下有效，在打开GUI之后，终端控制权被GUI接管。
|
||||
1. 在点击`exit`之后插件会将你的`IP和bd设计`移动`Hardware/src/`的同级目录下
|
||||
2. 如果直接关闭名为 *`HardWare`* 的终端则不会进行`IP和bd设计`的移动。
|
||||
3. 注：功能栏 *TOOL* 中的 *Clean* 时也可以将你的`IP和bd设计`移动`Hardware/src/`的同级目录下
|
||||
|
||||
除了以上几个显性功能外，还有两个隐性功能分别在`architecture`栏中，分别为
|
||||
1. `Set as Top` -------------- 将该文件设置为当前工程的设计顶层模块
|
||||
2. `Set as Testbench Top` ---- 将该文件设置为当前工程的仿真顶层模块
|
||||
|
||||
特殊地，*`Zynq`*器件支持PS+PL混合开发，为了应对混合开发的情况，插件给出`soc`配置如下：
|
||||
```json
|
||||
"soc": {
|
||||
"core": "ps7_cortexa9_0",
|
||||
"bd" : "zynq_default"
|
||||
}
|
||||
```
|
||||
使用如上配置插件会自动构建一个包含zynq设计的bd工程，帮助用户快速搭建平台。
|
||||
|
||||
最后关于设备选型，在`property.json`文件中的*Device*属性下配置即可。
|
||||
目前已有的如下：
|
||||
- xc7z020clg400-2
|
||||
- xc7a35tftg256-1
|
||||
- xc7a35tcsg324-1
|
||||
- xc7z035ffg676-2
|
||||
- xc7z020clg484-1
|
||||
|
||||
但支持的器件并不仅限于此，理论上可以支持vivado所能支持的所有器件，你可以直接将你的器件直接写在*device*属性中，此时由于数据库中没有该设备会报警告，但不妨碍运行。如果要消除警告需要将你的器件通过*FPGA:Add devices to the database*命令将其添加到数据库中。对于不需要的设备也可以通过 *FPGA:Remove the device from the database* 将其从数据库中删除。
|
||||
|
||||
**相关设置**
|
||||
`prj.vivado.install.path` --- vivado的安装路径
|
||||
当安装好vivado之后，可以直接在插件内部直接配置vivado的安装路径，也可以将vivado添加到环境变量中去（推荐）。如果路径错误找不到则默认为已经添加到环境变量中去了。
|
||||
*e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin/*
|
||||
注意：在路径中使用斜杠`/`分隔，并且配置到bin目录下。
|
||||
|
||||
`prj.xilinx.IP.repo.path` ---- 用户自行设计的xilinx的IP仓库配置该属性后插件会自动将该路径添加到vivado的IP repo中去
|
||||
*e.g. : D:/project/FPGA/.Lib/xIP*
|
||||
|
||||
`prj.xilinx.BD.repo.path` ---- 用户自定义xilinx block design文件的放置路径
|
||||
*e.g. : D:/project/FPGA/.Lib/xbd*
|
||||
|
||||
|
||||
## lib Manager
|
||||
该插件自带HDL功能库链接功能。
|
||||
`property.json`文件中配置如下：
|
||||
```json
|
||||
"library" : {
|
||||
"state": "", // local | remote(default)
|
||||
"hardware" : {
|
||||
"common": [],
|
||||
"custom": []
|
||||
}
|
||||
},
|
||||
|
||||
"IP_REPO": [
|
||||
"arm", // 包含ip CM3DbgAXI & DAPLink_to_Arty_shield
|
||||
"adi" // 包含 adi 公司下所有器件ip，已去除所包含的绝对路径 取自 adi2019_r1
|
||||
],
|
||||
```
|
||||
|
||||
对于`property.json`文件中的library属性不建议用户自己配置，建议使用*import library*命令，或者下图中的图标激活命令进行配置。
|
||||
|
||||
*state* 属性代表是库文件是加载到本地工作区，还是作为远程进行链接。
|
||||
- `remote` 代表从远程虚拟包含（不在工作区下的都被认为远程，而不是网络上的远程）。
|
||||
- 远程库文件可以打开并更改 *(`注：`如果更改之后下次导入就是更改之后的代码)* 。
|
||||
- `local` 代表将远程文件导入到该工程本地
|
||||
1. 放置到`arch.hardware.src`下的lib中，此时更改不会影响远程库中的代码。
|
||||
2. *`注：`当从local改回remote时lib文件夹会被删除（插件会提醒），请注意*。
|
||||
|
||||
*common* 属性代表插件自带的HDL功能库，*该库的代码不太成熟，仅供参考*。
|
||||
目前已经经过仿真测试的lib路径如下
|
||||
- Soc
|
||||
- Math/Cordic.v
|
||||
- Math/Sort3.v
|
||||
- Math/Sqrt.v
|
||||
- Malloc/RAM/Shift_RAM
|
||||
- Apply/DSP/Advance/Communicate/Modulate
|
||||
- Apply/DSP/Base/DDS
|
||||
- Apply/Image (需要包含 Sort3, Sqrt, Shift_RAM)
|
||||
|
||||
`【注】`：当输入的是文件夹时则包含该文件夹下所有的文件。此外不建议直接更改该库中的代码，更改之后再在下一次插件更新之后会被重新覆盖，请慎重。
|
||||
|
||||
*custom* 属性代表用户自定义HDL功能库。
|
||||
该属性的使用需要对*setting*下的*PRJ.customer.Lib.repo.path*进行配置用户自定义库的根目录，并与*custom*属性下的配置组成文件(夹)的绝对路径。表示如下：
|
||||
*`PRJ.customer.Lib.repo.path`*`/`*`${custom}`*
|
||||
|
||||
`【注】`：当输入的是文件夹时则包含该文件夹下所有的文件。
|
||||
|
||||
最后，对于`IP_REPO`属性，这是插件向用户提供的两个官方xilinx IP repo，选择自己想要的进行配置，插件会自动添加到vivado的IP repo中去，方便用户直接开发，不用自己去编译导入。
|
||||
71
src/zh/guide/pm-simulation-building.md
Normal file
71
src/zh/guide/pm-simulation-building.md
Normal file
@ -0,0 +1,71 @@
|
||||
---
|
||||
title: 仿真搭建
|
||||
---
|
||||
|
||||
仿真搭建的目的是帮助用户能快速搭建起自己的仿真框架，并快速的获得仿真结果。
|
||||
|
||||
|
||||
## 产生例化 & tb file
|
||||
|
||||
虽然自动补全可以实现例化的自动补全，但是无法阅览整个项目所有可用的模块并从中选择，因此我们提供了自动例化的功能；除此之外我们还提供了自动生成选定模块testbench的功能。
|
||||
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://img1.imgtp.com/2023/08/18/bA4ybk5Z.gif" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
该插件支持不同语言间的交叉例化，比如在verilog文件中例化verilog和vhdl模块，或者在vhdl文件中例化Verilog和vhdl模块。
|
||||
|
||||
步骤如下:
|
||||
1. 将光标放置在文本需要例化处。
|
||||
2. 使用快捷键`F1`启动命令框，输入*Instance*，选择`Instance`。
|
||||
1. 或者使用快捷键`Alt + I`。
|
||||
2. 或者在需要例化处右击选择`Instance`
|
||||
3. 输入需要例化的模块的关键字（插件会自动匹配）。
|
||||
4. 选择需要例化的模块。
|
||||
|
||||
`【注】`：在使用快捷键时，需检查是否存在快捷键键冲突。
|
||||
|
||||
除了自动例化外，插件还提供了一个verilog的仿真模板，使用方式如下：
|
||||
1. `F1`启动命令框，输入*Testbench*, 选择`testbench`
|
||||
1. 或者在需要生成并例化的文件下右击选择`Testbench`。
|
||||
2. 选择仿真文件的类型以及需要存储的位置，如果存在直接替换即可。
|
||||
|
||||
如果想要更改testbench模板的话步骤如下：
|
||||
使用快捷键`F1`启动命令框，选择TOOL:Overwrite the template of testbench，选择要更改的仿真文件的类型，这时会打开testbench file的初始化文件在此基础上更改保存即可。此外请保留 `//Instance` 标志，该标志是用于识别需要例化的位置。
|
||||
|
||||
后期会考虑tb文件与例化模块间的智能连线。
|
||||
|
||||
## 快速仿真
|
||||
该功能的目的是为了能快速地对单个模块，或几个模块组成的小工程进行快速地仿真。
|
||||
|
||||
|
||||
**iverilog快速仿真**
|
||||
|
||||
<br>
|
||||
<div align=center>
|
||||
<img src="https://img1.imgtp.com/2023/08/18/7PS5Cp37.gif" style="width: 90%;"/>
|
||||
</div>
|
||||
<br>
|
||||
|
||||
|
||||
- 如果想要使用该功能，请自行下载iverilog，并加入环境变量。
|
||||
- VCD渲染目前使用的是wavetrace这个vscode插件，下一个版本会推出我们开发的内嵌波形渲染器，而且完全免费。
|
||||
- 多文件仿真我们建议不要写include，如果写了include，请在property.json中加入所有include的文件的文件夹路径，例如：
|
||||
|
||||
```json
|
||||
{
|
||||
...
|
||||
"iverilogCompileOptions": {
|
||||
"standard": "2012",
|
||||
"includes": [
|
||||
"${workspace}/src",
|
||||
"${workspace}/src/Controller",
|
||||
"${workspace}/src/DataPath"
|
||||
]
|
||||
},
|
||||
...
|
||||
}
|
||||
```
|
||||
126
src/zh/guide/project-configuration.md
Normal file
126
src/zh/guide/project-configuration.md
Normal file
@ -0,0 +1,126 @@
|
||||
---
|
||||
title: 工程配置
|
||||
---
|
||||
|
||||
本插件定义工程配置文件为`property.json`，只放置于`.vscode`文件夹下。如果您能有耐心阅读完这个文件的作用，强烈推荐您选择创建property.json用于配置你的HDL项目。
|
||||
|
||||
|
||||
## 工程配置文件的生成
|
||||
|
||||
使用 *TOOL:generate property file* 可以生成初始的 `property.json` 模板文件。生成的配置文件会直接放置于.vscode的文件夹下
|
||||
如果你有属于自己的模板可以使用*TOOL:Overwrite the InitPropertyParam* 来自定义模板文件。
|
||||
|
||||
> 0.3.0版本后，插件每次启动都会自动询问用户是否要创建property.json
|
||||
|
||||
<center>
|
||||
<video width="90%" controls>
|
||||
<source src="/videos/project.mp4" type="video/mp4">
|
||||
您的浏览器不支持视频标签。
|
||||
</video>
|
||||
</center>
|
||||
|
||||
## 工程配置文件的说明
|
||||
> 注：在0.3.0版本之后将使用全新的配置属性
|
||||
```json
|
||||
// porperty.json 所有属性解说
|
||||
{
|
||||
// 当前使用的第三方工具链
|
||||
"toolChain": "xilinx",
|
||||
|
||||
// 工程命名
|
||||
// PL : 编程逻辑设计部分即之前的FPGA
|
||||
// PL : 处理系统设计部分即之前的SOC
|
||||
"prjName": {
|
||||
"PL": "template",
|
||||
"PS": "template"
|
||||
},
|
||||
|
||||
// 自定义工程结构，若无该属性则认为是标准文件结构（详见下文说明）
|
||||
// 工程路径，软硬件设计路径
|
||||
// 所有属性均支持${workspace}、${plname}、${psname}、相对路径的写法
|
||||
// ${workspace} ： 当前工作区的路径
|
||||
// ${plname}、${psname} ：PL或PS的工程的名字
|
||||
"arch" : {
|
||||
"prjPath": "",
|
||||
"hardware" : {
|
||||
"src" : "", // 放置设计源文件，注: src上一级为IP&bd
|
||||
"sim" : "", // 放置仿真文件，会直接反应在树状结构上
|
||||
"data" : "" // 放置约束、数据文件，约束会自动添加进vivado工程
|
||||
},
|
||||
"software" : {
|
||||
"src" : "",
|
||||
"data" : ""
|
||||
}
|
||||
},
|
||||
|
||||
// 代码库管理，支持远程和本地两种调用方式（详见下文库管理）
|
||||
// 使用UI来进行配置，不建议用户直接更改
|
||||
"library" : {
|
||||
"state": "", // local | remote
|
||||
"hardware" : {
|
||||
"common": [], // 插件提供的常见库
|
||||
"custom": [] // 用户自己的设计库
|
||||
}
|
||||
},
|
||||
|
||||
// xilinx的IP仓库，直接添加到vivado的IP repo中
|
||||
// 目前支持ADI和ARM提供的IP repo （adi | arm）
|
||||
"IP_REPO" : [],
|
||||
|
||||
// 当设计时用到PL+PS即为SOC开发
|
||||
// 当其中core不为none的时候即为混合开发
|
||||
"soc": {
|
||||
"core": "none",
|
||||
"bd": "",
|
||||
"os": "",
|
||||
"app": ""
|
||||
},
|
||||
|
||||
// 工程综合实现时，是否在终端输出信息
|
||||
"enableShowLog": false,
|
||||
|
||||
// 设备类型 可以是如下几种：
|
||||
// "none",
|
||||
// "xc7z020clg400-2",
|
||||
// "xc7a35tftg256-1",
|
||||
// "xc7a35tcsg324-1",
|
||||
// "xc7z035ffg676-2",
|
||||
// "xc7z020clg484-1"
|
||||
"device": "none"
|
||||
}
|
||||
```
|
||||
|
||||
其中最重要的属性是`arch`属性，配置了`arch`属性则认为是用户自定义工程结构。对于用户自定义结构，一切文件变动均由用户自行管理。当不进行`arch`属性配置的时候则认为使用本插件推荐的标准文件结构。对于标准文件结构的说明如下：
|
||||
```
|
||||
.vscode
|
||||
└── property.json -- 工程配置文件 用户自定义 (或者存放于工作区的根目录也可)
|
||||
prj -- 用于存放工程文件
|
||||
├── simulation -- 用于存放第三方仿真工具运行时的中间文件
|
||||
├── intel -- 用于存放Intel的工程文件
|
||||
└── xilinx -- 用于存放xilinx的工程文件
|
||||
user -- 用于存放用户设计的源文件 用户自定义
|
||||
├── ip -- 用于存放工程ip代码 (厂商工具管理，但由插件搬移至src同级目录)
|
||||
├── bd -- 用于存放工程block designer源码 (厂商工具管理，但由插件搬移至src同级目录)
|
||||
├── data -- 主要存放数据文件，以及约束文件
|
||||
├── sim -- 用于存放用户仿真代码
|
||||
└── src -- 用于存放用户的设计源码
|
||||
└─ lib -- 用于存放用户的硬件库源码
|
||||
```
|
||||
|
||||
当 `property.json` 文件中 `soc.core` 设置不为 "none" 后保存配置文件时，文件结构会自动更改为PS+PL的混合设计结构。在该结构下user文件夹会发生改变，变为如下结构：
|
||||
```
|
||||
user -- 用于存放用户设计的源文件 用户自定义
|
||||
Hardware -- 主要存放硬件逻辑设计
|
||||
├── ip -- 用于存放工程ip代码 (厂商工具管理，但由插件搬移至src同级目录)
|
||||
├── bd -- 用于存放工程block designer源码 (厂商工具管理，但由插件搬移至src同级目录)
|
||||
├── data -- 主要存放数据文件，以及约束文件
|
||||
├── sim -- 用于存放用户仿真代码
|
||||
└── src -- 用于存放用户的设计源码
|
||||
└─ lib -- 用于存放用户的硬件库源码
|
||||
Software -- 主要存放软件驱动设计
|
||||
├── data -- 主要存放数据文件，以及约束文件
|
||||
└── src -- 用于存放用户的工程源码
|
||||
```
|
||||
注：在`soc.core`的值由非none变为none时，Software文件夹默认为不需要，会被删除（插件也会给出相应的提示），请做好备份。另外，*IP和bd设计会被放置到src的上一级目录，因此src最好不要设置为工作区的根路径*。
|
||||
|
||||
此外，如果用户在ARCH下配置的路径错误或者无效，插件会直接改为标准下的结构路径。*当用户不去配置`property.json`文件时，文件结构全部默认为工作区的路径，该行为可能会造成大量的性能消耗，请用户注意*。
|
||||
12
src/zh/guide/todo.md
Normal file
12
src/zh/guide/todo.md
Normal file
@ -0,0 +1,12 @@
|
||||
---
|
||||
title: TODO
|
||||
---
|
||||
|
||||
If you have some suggestions, just [propose a issue](https://github.com/Digital-EDA/Digital-IDE/issues).
|
||||
|
||||
- [ ] Embedded VCD waveform display
|
||||
- [ ] Optimized Yosys integrated interface
|
||||
- [ ] More friendly finite state machine interface
|
||||
- [ ] More comprehensive syntax checking
|
||||
- [ ] Port checking
|
||||
- [ ] Embedded cross-platform iverilog simulator
|
||||
18
src/zh/index.md
Normal file
18
src/zh/index.md
Normal file
@ -0,0 +1,18 @@
|
||||
---
|
||||
home: true
|
||||
heroImage: /icon.png
|
||||
description: Vscode 平台上的 ASIC & FPGA 开发扩展
|
||||
actionText: 快速开始 🐳
|
||||
actionLink: /guide/introduction
|
||||
features:
|
||||
- title: ✨ HDL 语言支持
|
||||
details: 支持 verilog, vhdl, systemverilog, tcl 脚本等
|
||||
- title: 🎯 项目管理
|
||||
details: 在你的项目中查看结构化的 HDL 文件
|
||||
- title: 🛠️ 额外的工具
|
||||
details: FSM, Netlist, 一键仿真, 文档化，让你的编程体验更加舒坦。
|
||||
---
|
||||
|
||||
::: slot footer
|
||||
MIT Licensed | Copyright © 2018-present [Digital-EDA](https://github.com/Digital-EDA)
|
||||
:::
|
||||
Loading…
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Reference in New Issue
Block a user