{
    "digital-ide.property-json.generate.title": "Generate property.json",
    "digital-ide.property-json.overwrite.title": "Overwrite property.json template",
    "digital-ide.hdlDoc.exportFile.title": "Export the document of current file",
    "digital-ide.hdlDoc.exportProject.title": "Export the document of current project",
    "digital-ide.hdlDoc.showWebview.title": "Show the document of current file in a webview",
    "digital-ide.tool.instance.title": "Generate instance template from selected module",
    "digital-ide.tool.testbench.title": "Generate testbench template from current file",
    "digital-ide.tool.icarus.simulateFile.title": "Do simulation for current file",
    "digital-ide.treeView.arch.expand.title": "Expand all the items in tree view",
    "digital-ide.treeView.arch.collapse.title": "Collapse all the items in tree view",
    "digital-ide.treeView.arch.refresh.title": "Refresh the tree view",
    "digital-ide.treeView.arch.openFile.title": "Open the corresponding file in tree view",
    "digital-ide.tool.clean.title": "Clean the current project",
    "digital-ide.soft.launch.title": "Launch SDK development assist function",
    "digital-ide.soft.build.title": "Build the current SDK project",
    "digital-ide.soft.download.title": "Download the boot file into the device",
    "digital-ide.hard.launch.title": "Launch FPGA development assist function",
    "digital-ide.hard.simulate.title": "Launch the manufacturer Simulation",
    "digital-ide.hard.simulate.cli.title": "Launch the manufacturer Simulation in CLI",
    "digital-ide.hard.simulate.gui.title": "Launch the manufacturer Simulation in GUI",
    "digital-ide.hard.refresh.title": "Refresh the current project file",
    "digital-ide.hard.build.title": "Build the current fpga project",
    "digital-ide.hard.build.synth.title": "Synth the current project",
    "digital-ide.hard.build.impl.title": "Impl the current project",
    "digital-ide.hard.build.bitstream.title": "Generate the BIT File",
    "digital-ide.hard.program.title": "Download the bit file into the device",
    "digital-ide.hard.gui.title": "Open the GUI",
    "digital-ide.hard.exit.title": "Exit the current project",
    "digital-ide.pickLibrary.title": "Select lib from custom & common",
    "digital-ide.pl.setSrcTop.title": "Set as top file of src",
    "digital-ide.pl.setSimTop.title": "Set as top file of sim",
    "digital-ide.pl.addDevice.title": "Add device",
    "digital-ide.pl.delDevice.title": "Del device",
    "digital-ide.pl.addFile.title": "Add file",
    "digital-ide.pl.delFile.title": "Del file",
    "digital-ide.netlist.title": "Netlist",
    "digital-ide.fsm.title": "Finite state machine",
    "digital-ide.lsp.tool.insertTextToUri.title": "Insert text to uri",
    "digital-ide.lsp.tool.transformOldPropertyFile.title": "Transform configure file from previous version to new version",
    "digital-ide.vhdl2vlog.title": "Translate vhdl code to verilog code",
    "digital-ide.fsm.show.title": "Show FSM graph of current file",
    "digital-ide.netlist.show.title": "Show netlist of current file",
    "digital-ide.waveviewer.show.title": "Render the vcd in the dide viewer",
    "digital-ide.lsp.vlog.linter.pick.title": "select a diagnostic for verilog",
    "digital-ide.lsp.svlog.linter.pick.title": "select a diagnostic for systemverilog verilog",
    "digital-ide.lsp.vhdl.linter.pick.title": "select a diagnostic for vhdl",
    "digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog",
    "digital-ide.tool.export-filelist.title": "export filelist",
    "digital-ide.treeview": "Digital IDE: TreeView",
    "digital-ide.digital-lsp.download.title": "Download Digital LSP Language Server",
    "digital-ide.welcome.show.title": "Show welcome text in Digital-IDE",
    "digital-ide.dont-show-again.propose.issue.title": "Show welcome text in Digital-IDE",
    "digital-ide.lib.custom.path.title": "Path of the user-defined lib directory",
    "digital-ide.prj.file.structure.notice.title": "Show a notice when a local file is deleted",
    "digital-ide.prj.vivado.install.path.title": "Set the Xilinx Vivado installation path. For example: D:/APP/vivado_18_3/Vivado/2018.3/bin. The default path is C:/Xilinx/Vivado/2018.3/bin\nIgnore this setting if you add a relative path to the environment variable PATH",
    "digital-ide.prj.modelsim.install.path.title": "Set the Modelsim installation path. The default path is C:/modeltech64_10.4/win64\nIgnore this setting if you add a relative path to the environment variable PATH",
    "digital-ide.prj.xilinx.IP.repo.path.title": "Path of the user-designed Xilinx IP library. After configuring this property, the plugin will automatically add the path to the Vivado IP library.",
    "digital-ide.prj.xilinx.BD.repo.path.title": "User-defined placement path for Xilinx BD files",
    "digital-ide.prj.xsdk.install.path.title": "",
    "digital-ide.function.doc.webview.backgroundImage.title": "URL of the background image",
    "digital-ide.function.doc.pdf.scale.title": "Scale of the exported PDF",
    "digital-ide.function.doc.pdf.printBackground.title": "Whether to print the background",
    "digital-ide.function.doc.pdf.landscape.title": "Whether to export the PDF in landscape style",
    "digital-ide.function.doc.pdf.format.title": "Format of the PDF size",
    "digital-ide.function.doc.pdf.displayHeaderFooter.title": "Display header and footer in the exported PDF",
    "digital-ide.function.doc.pdf.browserPath.title": "Absolute path of Edge or Chrome, we need a browser to render the PDF. The default path is C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
    "digital-ide.function.doc.pdf.margin.top.title": "Top margin of the exported PDF, unit cm",
    "digital-ide.function.doc.pdf.margin.right.title": "Right margin of the exported PDF, unit cm",
    "digital-ide.function.doc.pdf.margin.bottom.title": "Bottom margin of the exported PDF, unit cm",
    "digital-ide.function.doc.pdf.margin.left.title": "Left margin of the exported PDF, unit cm",
    "digital-ide.function.doc.pdf.headerTemplate.title": "HTML template of the header, if displayHeaderFooter is set to false, this setting will be ignored",
    "digital-ide.function.doc.pdf.footerTemplate.title": "HTML template of the footer, if displayHeaderFooter is set to false, this setting will be ignored",
    "digital-ide.function.simulate.icarus.installPath.title": "Installation path of Icarus Verilog components, if set to empty, the iverilog and vvp in the environment will be used for simulation. Otherwise, the components in the installation path will be used.",
    "digital-ide.function.simulate.simulationHome.title": "Path of the simulation folder, .vvp and other files during simulation will be generated here",
    "digital-ide.function.simulate.gtkwavePath.title": "Absolute path of the launch path of the gtkwave software",
    "digital-ide.function.simulate.xilinxLibPath.title": "Path of the Xilinx library for simulation",
    "digital-ide.function.simulate.runInTerminal.title": "Run the simulation command in the terminal instead of the output",
    "digital-ide.function.lsp.formatter.vlog.default.style.title": "Select the Verilog and SystemVerilog formatter style.",
    "digital-ide.function.lsp.formatter.vlog.default.args.title": "Add Verilog formatter arguments here (like istyle).",
    "digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "Keyword case",
    "digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "Align comments",
    "digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "Type name case",
    "digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
    "digital-ide.function.lsp.completion.vlog.auto-add-include.title": "When triggering module auto-completion, if the top include macro does not include the file where the instantiated module is located, automatically add `include \"xxx.v\" at the top of the file",
    "digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "When triggering module auto-completion, automatically generate the declaration of output type signals above the instantiated module",
    "digital-ide.function.lsp.linter.vlog.diagnostor.title": "Choose the diagnostor to do linter in editing Verilog",
    "digital-ide.function.lsp.linter.svlog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
    "digital-ide.function.lsp.linter.vhdl.diagnostor.title": "Choose the diagnostor to do linter in editing VHDL",
    "digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
    "digital-ide.function.instantiation.addComment.title": "Add comments like // ports, // input, // output when doing instantiation, including completion for module invoking",
    "digital-ide.function.instantiation.autoNetOutputDeclaration.title": "Automatically declare output type nets in the scope when instantiation happens.",
    "fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
    "digital-ide.function.lsp.file-parse-maxsize.title": ""
}