{
    "digital-ide.property-json.generate.title": "Generate property.json",
    "digital-ide.property-json.overwrite.title": "Overwrite property.json template",
    "digital-ide.hdlDoc.exportFile.title": "Export the document of current file",
    "digital-ide.hdlDoc.exportProject.title": "Export the document of current project",
    "digital-ide.hdlDoc.showWebview.title": "Show the document of current file in a webview",
    "digital-ide.tool.instance.title": "Generate instance template from selected module",
    "digital-ide.tool.testbench.title": "Generate testbench template from current file",
    "digital-ide.tool.icarus.simulateFile.title": "Do simulation for current file",
    "digital-ide.treeView.arch.expand.title": "Expand all the items in tree view",
    "digital-ide.treeView.arch.collapse.title": "Collapse all the items in tree view",
    "digital-ide.treeView.arch.refresh.title": "Refresh the tree view",
    "digital-ide.treeView.arch.openFile.title": "Open the corresponding file in tree view",
    "digital-ide.tool.clean.title": "Clean the current project",
    "digital-ide.soft.launch.title": "Launch SDK development assist function",
    "digital-ide.soft.build.title": "Build the current SDK project",
    "digital-ide.soft.download.title": "Download the boot file into the device",
    "digital-ide.hard.launch.title": "Launch FPGA development assist function",
    "digital-ide.hard.simulate.title": "Launch the manufacturer Simulation",
    "digital-ide.hard.simulate.cli.title": "Launch the manufacturer Simulation in CLI",
    "digital-ide.hard.simulate.gui.title": "Launch the manufacturer Simulation in GUI",
    "digital-ide.hard.refresh.title": "Refresh the current project file",
    "digital-ide.hard.build.title": "Build the current fpga project",
    "digital-ide.hard.build.synth.title": "Synth the current project",
    "digital-ide.hard.build.impl.title": "Impl the current project",
    "digital-ide.hard.build.bitstream.title": "Generate the BIT File",
    "digital-ide.hard.program.title": "Download the bit file into the device",
    "digital-ide.hard.gui.title": "Open the GUI",
    "digital-ide.hard.exit.title": "Exit the current project",
    "digital-ide.pickLibrary.title": "Select lib from custom & common",
    "digital-ide.pl.setSrcTop.title": "Set as top file of src",
    "digital-ide.pl.setSimTop.title": "Set as top file of sim",
    "digital-ide.pl.addDevice.title": "Add device",
    "digital-ide.pl.delDevice.title": "Del device",
    "digital-ide.pl.addFile.title": "Add file",
    "digital-ide.pl.delFile.title": "Del file",
    "digital-ide.netlist.title": "Netlist",
    "digital-ide.fsm.title": "Finite state machine",
    "digital-ide.lsp.tool.insertTextToUri.title": "Insert text to uri",
    "digital-ide.lsp.tool.transformOldPropertyFile.title": "Transform configure file from previous version to new version",
    "digital-ide.vhdl2vlog.title": "Translate vhdl code to verilog code",
    "digital-ide.fsm.show.title": "Show FSM graph of current file",
    "digital-ide.netlist.show.title": "Show netlist of current file",
    "digital-ide.waveviewer.show.title": "Render the vcd in the dide viewer",
    "digital-ide.lsp.vlog.linter.pick.title": "select a diagnostic for verilog",
    "digital-ide.lsp.svlog.linter.pick.title": "select a diagnostic for systemverilog verilog",
    "digital-ide.lsp.vhdl.linter.pick.title": "select a diagnostic for vhdl",
    "digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog",
    "digital-ide.tool.export-filelist.title": "export filelist"
}