#fix ppy soc.core reaction
This commit is contained in:
parent
2ad67933b1
commit
0354723711
@ -412,7 +412,16 @@ class PrjInfo implements PrjInfoMeta {
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this.setDefaultValue(this.arch.software, 'data', workspacePath);
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this.setDefaultValue(this.arch, 'prjPath', workspacePath);
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// check existence & make dir
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// // check existence & make dir
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// this.checkDirExist(this.arch.hardware.sim);
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// this.checkDirExist(this.arch.hardware.src);
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// this.checkDirExist(this.arch.hardware.data);
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// this.checkDirExist(this.arch.software.src);
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// this.checkDirExist(this.arch.software.data);
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// this.checkDirExist(this.arch.prjPath);
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}
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public checkArchDirExist() {
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this.checkDirExist(this.arch.hardware.sim);
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this.checkDirExist(this.arch.hardware.src);
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this.checkDirExist(this.arch.hardware.data);
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@ -301,9 +301,9 @@ class HdlParam {
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}
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}
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public addHdlFile(path: AbsPath) {
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public async addHdlFile(path: AbsPath) {
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path = hdlPath.toSlash(path);
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this.initHdlFiles([path]);
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await this.initHdlFiles([path]);
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const moduleFile = this.getHdlFile(path);
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if (!moduleFile) {
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@ -162,6 +162,8 @@ class PrjManage {
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// configure by default
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await this.createFolderByDefault(rawPrjInfo);
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}
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opeParam.prjInfo.checkArchDirExist();
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}
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public async createFolderByRawPrjInfo(rawPrjInfo: RawPrjInfo) {
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@ -181,7 +183,6 @@ class PrjManage {
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hdlDir.mkdir(software.src);
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hdlDir.mkdir(software.data);
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}
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return;
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}
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}
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@ -197,8 +198,12 @@ class PrjManage {
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const hardwarePath = hdlPath.join(userPath, 'Hardware');
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const nextmode = this.getNextMode(rawPrjInfo);
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console.log(softwarePath, fs.existsSync(softwarePath));
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console.log(hardwarePath, fs.existsSync(hardwarePath));
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const currmode = this.getCurrentMode(softwarePath, hardwarePath);
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console.log(currmode, nextmode);
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if (currmode === nextmode) {
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const hardware = opeParam.prjInfo.arch.hardware;
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@ -76,7 +76,7 @@ class HdlAction extends BaseAction {
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}
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// create corresponding moduleFile
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hdlParam.addHdlFile(path);
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await hdlParam.addHdlFile(path);
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refreshArchTree();
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}
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@ -207,20 +207,6 @@ class PpyAction extends BaseAction {
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opeParam.mergePrjInfo(rawPrjInfo);
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// // when delete, make ws path to be main parse path
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// if (e === Event.Unlink) {
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// const prjInfoArch = opeParam.prjInfo.arch;
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// const workspacePath = opeParam.workspacePath;
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// // TODO : more elegant ?
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// prjInfoArch.hardware.src = workspacePath;
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// prjInfoArch.hardware.sim = workspacePath;
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// prjInfoArch.hardware.data = workspacePath;
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// prjInfoArch.prjPath = workspacePath;
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// prjInfoArch.software.data = workspacePath;
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// prjInfoArch.software.src = workspacePath;
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// }
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const currentPathSet = this.getImportantPathSet();
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const currentLibState = opeParam.prjInfo.library.state;
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258
src/test/user/src/Cordic.v
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258
src/test/user/src/Cordic.v
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@ -0,0 +1,258 @@
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`timescale 1ns / 1ps
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module Cordic #(
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parameter XY_BITS = 12,
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parameter PH_BITS = 32,
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parameter ITERATIONS = 32,
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parameter CORDIC_STYLE = "ROTATE",
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parameter PHASE_ACC = "ON"
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)(
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input clk,
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input RST,
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input signed [XY_BITS-1:0] x_i,
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input signed [XY_BITS-1:0] y_i,
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input signed [PH_BITS-1:0] phase_in,
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output signed [XY_BITS-1:0] x_o,
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output signed [XY_BITS-1:0] y_o,
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output signed [PH_BITS-1:0] phase_out,
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input valid_in,
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output valid_out
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);
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localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2;
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/*
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//360°--2^16,phase_in = 16bits (input [15:0] phase_in)
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//1°--2^16/360
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*/
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function [PH_BITS-1:0] tanangle;
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input [4:0] i;
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begin
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case (i)
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5'b00000: tanangle = (32'h20000000 >> (32 - PH_BITS)); //tan = 1/2^1 = 1/2
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5'b00001: tanangle = (32'h12e4051e >> (32 - PH_BITS)); //tan = 1/2^2 = 1/4
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5'b00010: tanangle = (32'h09fb385b >> (32 - PH_BITS)); //tan = 1/2^3 = 1/8
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5'b00011: tanangle = (32'h051111d4 >> (32 - PH_BITS)); //tan = 1/2^4 = 1/16
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5'b00100: tanangle = (32'h028b0d43 >> (32 - PH_BITS)); //tan = 1/2^5 = 1/32
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5'b00101: tanangle = (32'h0145d7e1 >> (32 - PH_BITS)); //tan = 1/2^6 = 1/64
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5'b00110: tanangle = (32'h00a2f61e >> (32 - PH_BITS)); //tan = 1/2^7 = 1/128
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5'b00111: tanangle = (32'h00517c55 >> (32 - PH_BITS)); //tan = 1/2^8 = 1/256
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5'b01000: tanangle = (32'h0028be53 >> (32 - PH_BITS)); //tan = 1/2^9 = 1/512
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5'b01001: tanangle = (32'h00145f2f >> (32 - PH_BITS)); //tan = 1/2^10 = 1/1024
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5'b01010: tanangle = (32'h000a2f98 >> (32 - PH_BITS)); //tan = 1/2^11 = 1/2048
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5'b01011: tanangle = (32'h000517cc >> (32 - PH_BITS)); //tan = 1/2^12 = 1/4096
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5'b01100: tanangle = (32'h00028be6 >> (32 - PH_BITS)); //tan = 1/2^13 = 1/8192
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5'b01101: tanangle = (32'h000145f3 >> (32 - PH_BITS)); //tan = 1/2^14 = 1/16384
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5'b01110: tanangle = (32'h0000a2fa >> (32 - PH_BITS)); //tan = 1/2^15 = 1/32768
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5'b01111: tanangle = (32'h0000517d >> (32 - PH_BITS)); //tan = 1/2^16 = 1/65536
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5'b10000: tanangle = (32'h000028be >> (32 - PH_BITS)); //tan = 1/2^17 = 1/131072
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5'b10001: tanangle = (32'h0000145f >> (32 - PH_BITS)); //tan = 1/2^18 = 1/262144
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5'b10010: tanangle = (32'h00000a30 >> (32 - PH_BITS)); //tan = 1/2^19 = 1/524288
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5'b10011: tanangle = (32'h00000518 >> (32 - PH_BITS)); //tan = 1/2^20 = 1/1048576
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5'b10100: tanangle = (32'h0000028c >> (32 - PH_BITS)); //tan = 1/2^21 = 1/2097152
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5'b10101: tanangle = (32'h00000146 >> (32 - PH_BITS)); //tan = 1/2^22 = 1/4194304
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5'b10110: tanangle = (32'h000000a3 >> (32 - PH_BITS)); //tan = 1/2^23 = 1/8388608
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5'b10111: tanangle = (32'h00000051 >> (32 - PH_BITS)); //tan = 1/2^24 = 1/16777216
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5'b11000: tanangle = (32'h00000029 >> (32 - PH_BITS)); //tan = 1/2^25 = 1/33554432
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5'b11001: tanangle = (32'h00000014 >> (32 - PH_BITS)); //tan = 1/2^26 = 1/67108864
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5'b11010: tanangle = (32'h0000000a >> (32 - PH_BITS)); //tan = 1/2^27 = 1/134217728
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5'b11011: tanangle = (32'h00000005 >> (32 - PH_BITS)); //tan = 1/2^28 = 1/268435456
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5'b11100: tanangle = (32'h00000003 >> (32 - PH_BITS)); //tan = 1/2^29 = 1/536870912
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5'b11101: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^30 = 1/1073741824
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5'b11110: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^31 = 1/2147483648
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5'b11111: tanangle = (32'h00000000 >> (32 - PH_BITS)); //tan = 1/2^32 = 1/4294967296
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endcase
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end
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endfunction
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reg [1:0] data_in_buff [ITERATIONS:0];
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reg signed [XY_BITS-1:0] x [ITERATIONS:0];
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reg signed [XY_BITS-1:0] y [ITERATIONS:0];
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reg signed [PH_BITS-1:0] z [ITERATIONS:0];
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integer m;
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initial begin
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for (m = 0; m<=ITERATIONS; m=m+1) begin
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x[m] = 0;
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end
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end
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integer n;
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initial begin
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for (n = 0; n<=ITERATIONS; n=n+1) begin
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y[n] = 0;
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end
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end
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integer s;
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initial begin
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for (s = 0; s<=ITERATIONS; s=s+1) begin
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z[s] = 0;
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end
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end
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integer k;
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initial begin
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for (k = 0; k<=ITERATIONS; k=k+1) begin
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data_in_buff[k] = 0;
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end
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end
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genvar i;
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generate for(i=0;i<ITERATIONS;i=i+1) begin : CORDIC
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always @ (posedge clk) begin
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if (RST) begin
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x[i+1] <= 0;
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y[i+1] <= 0;
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z[i+1] <= 0;
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end
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else begin
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if (CORDIC_STYLE == "ROTATE") begin
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if (z[i] < 0) begin
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x[i+1] <= x[i] + (y[i]>>>i);
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y[i+1] <= y[i] - (x[i]>>>i);
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z[i+1] <= z[i] + tanangle(i);
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end
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else begin
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x[i+1] <= x[i] - (y[i]>>>i);
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y[i+1] <= y[i] + (x[i]>>>i);
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z[i+1] <= z[i] - tanangle(i);
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end
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end
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else if(CORDIC_STYLE == "VECTOR") begin
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if (y[i] > 0) begin
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x[i+1] <= x[i] + (y[i]>>>i);
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y[i+1] <= y[i] - (x[i]>>>i);
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z[i+1] <= z[i] + tanangle(i);
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end else begin
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x[i+1] <= x[i] - (y[i]>>>i);
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y[i+1] <= y[i] + (x[i]>>>i);
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z[i+1] <= z[i] - tanangle(i);
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end
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end
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end
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end
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always @ (posedge clk) begin
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data_in_buff[i+1] <= data_in_buff[i];
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end
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end
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endgenerate
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generate if (CORDIC_STYLE == "ROTATE") begin : IQ_Gen
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reg [PH_BITS - 1 : 0] Phase_input = 0;
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if (PHASE_ACC == "ON") begin
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reg [PH_BITS - 1 : 0] addr_r0 = 0;
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always @(posedge clk) begin
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addr_r0 <= addr_r0 + phase_in;
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end
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always @(posedge clk) begin
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Phase_input <= addr_r0;
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end
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end
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else if (PHASE_ACC == "OFF") begin
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always @(posedge clk) begin
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Phase_input <= phase_in;
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end
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end
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always @(posedge clk) begin
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if(valid_in & (~RST)) begin
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x[0] <= K_COS;
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y[0] <= 0;
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z[0] <= Phase_input[PH_BITS - 3 : 0];
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data_in_buff[0] <= Phase_input[PH_BITS - 1 : PH_BITS - 2];
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end
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else begin
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x[0] <= 0;
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y[0] <= 0;
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z[0] <= 0;
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data_in_buff[0] <= 0;
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end
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end
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reg signed [XY_BITS-1:0] cos = 0;
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reg signed [XY_BITS-1:0] sin = 0;
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always @ (posedge clk) begin
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case(data_in_buff[ITERATIONS])
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2'b00:begin //if the phase is in first quadrant,the sin(X)=sin(A),cos(X)=cos(A)
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cos <= x[ITERATIONS];
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sin <= y[ITERATIONS];
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end
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2'b01:begin //if the phase is in second quadrant,the sin(X)=sin(A+90)=cosA,cos(X)=cos(A+90)=-sinA
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cos <= ~(y[ITERATIONS]) + 1'b1;//-sin
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sin <= x[ITERATIONS];//cos
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end
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2'b10:begin //if the phase is in third quadrant,the sin(X)=sin(A+180)=-sinA,cos(X)=cos(A+180)=-cosA
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cos <= ~(x[ITERATIONS]) + 1'b1;//-cos
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sin <= ~(y[ITERATIONS]) + 1'b1;//-sin
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end
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2'b11:begin //if the phase is in forth quadrant,the sin(X)=sin(A+270)=-cosA,cos(X)=cos(A+270)=sinA
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cos <= y[ITERATIONS];//sin
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sin <= ~(x[ITERATIONS]) + 1'b1;//-cos
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end
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endcase
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end
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assign x_o = cos;
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assign y_o = sin;
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assign phase_out = z[ITERATIONS];
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end
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endgenerate
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generate if (CORDIC_STYLE == "VECTOR") begin : Demodule_Gen
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localparam signed [PH_BITS-1:0] PHASE_COE = (2**(PH_BITS-2)) - 1;
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//localparam MODUIUS_COE = ;
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always @(posedge clk) begin
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if(valid_in & (~RST)) begin
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case ({x_i[XY_BITS-1],y_i[XY_BITS-1]})
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2'b00 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
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y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
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2'b01 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
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y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
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2'b10 : begin x[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
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y[0] <= -{x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
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2'b11 : begin x[0] <= -{y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
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y[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
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default : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
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y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
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endcase
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z[0] <= phase_in;
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data_in_buff[0] <= {x_i[XY_BITS-1],y_i[XY_BITS-1]};
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end
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else begin
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x[0] <= 0;
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y[0] <= 0;
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z[0] <= 0;
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data_in_buff[0] <= 0;
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end
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end
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reg [XY_BITS*2-1:0] Modulus = 0;
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wire [XY_BITS*2-1:0] Modulus_buf;
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reg signed [PH_BITS - 1:0] phase_r = 0;
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always @ (posedge clk) begin
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case(data_in_buff[ITERATIONS])
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2'b00:begin phase_r <= $signed(z[ITERATIONS]); end
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2'b01:begin phase_r <= $signed(z[ITERATIONS]); end
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2'b10:begin phase_r <= $signed(z[ITERATIONS]) + $signed(PHASE_COE); end
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2'b11:begin phase_r <= $signed(z[ITERATIONS]) - $signed(PHASE_COE); end
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endcase
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Modulus[XY_BITS:0] <= x[ITERATIONS];
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end
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assign Modulus_buf = (Modulus * 32'd39797)>>15;
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assign x_o = Modulus_buf[XY_BITS-1:0];
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assign y_o = y[ITERATIONS];
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assign phase_out = phase_r;
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end
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endgenerate
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reg [ITERATIONS+1:0] v = 0;
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always @ (posedge clk) begin
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if (RST)
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v <= 0;
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else begin
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v <= v << 1;
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v[0] <= valid_in;
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end
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end
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assign valid_out = v[ITERATIONS+1];
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endmodule
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58
src/test/user/src/fsm_test.v
Normal file
58
src/test/user/src/fsm_test.v
Normal file
@ -0,0 +1,58 @@
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module fsm_test(
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input clock,
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input reset,
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input [2 : 0] req_0,
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input [2 : 0] req_1,
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output reg [2 : 0] gnt_0,
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output reg [2 : 0] gnt_1
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);
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reg [2:0] state;
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parameter IDLE = 3'h1;
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parameter GNT0 = 3'd2;
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parameter GNT1 = 3'b100;
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always @ (posedge clock) begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end
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else
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case(state)
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IDLE :
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if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end
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else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT1;
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end
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else begin
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state <= #1 IDLE; //example comment
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end
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GNT0 :
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if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end
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else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
|
||||
GNT1 :
|
||||
if (req_1 == 1'b1) begin
|
||||
state <= #1 GNT1;
|
||||
end
|
||||
else begin
|
||||
gnt_1 <= 0;
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
default :
|
||||
state <= #1 IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
endmodule //module_name
|
||||
Loading…
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Reference in New Issue
Block a user