From 131380f1f5b90e59f64196960c1958c1e23d0041 Mon Sep 17 00:00:00 2001 From: Kirigaya <1193466151@qq.com> Date: Sun, 19 Nov 2023 22:26:11 +0800 Subject: [PATCH] add icon to all kinds of file --- CHANGELOG.md | 109 +++++++++++++++++++++-- config/bd.configuration.json | 29 ++++++ images/svg/dark/bd.svg | 1 + images/svg/dark/systemverilog.backup.svg | 1 + images/svg/dark/systemverilog.svg | 2 +- images/svg/light/bd.svg | 1 + images/svg/light/systemverilog.svg | 1 + package.json | 35 ++++++-- snippets/tcl.json | 29 +++++- src/function/index.ts | 5 ++ src/function/lsp/completion/index.ts | 4 +- src/function/lsp/completion/tcl.ts | 42 +++++++++ src/function/lsp/linter/vivado.ts | 0 src/function/lsp/util/keyword.ts | 33 ++++++- 14 files changed, 276 insertions(+), 16 deletions(-) create mode 100644 config/bd.configuration.json create mode 100644 images/svg/dark/bd.svg create mode 100644 images/svg/dark/systemverilog.backup.svg create mode 100644 images/svg/light/bd.svg create mode 100644 images/svg/light/systemverilog.svg create mode 100644 src/function/lsp/completion/tcl.ts create mode 100644 src/function/lsp/linter/vivado.ts diff --git a/CHANGELOG.md b/CHANGELOG.md index 99254bb..ec0d5ac 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,14 +4,111 @@ All notable changes to the "digital-ide" extension will be documented in this fi Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how to structure this file. -## [Unreleased] - -- Initial release - - -## [2023.11.1] +## [0.3.2] - 2023-11-01 Bug 修复 - 修复文档化input, output处注释无法正常显示到文档的 bug - 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug - 修复 iverilog 仿真功能中，将 `include 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性） + +Feat +- 增加对 XDC，TCL 等脚本的 LSP 支持 +- 增加 verilog, vhdl, xdc, tcl 等语言的图标 +- 增加对于 vivado 的支持，用户可以通过添加 vivado 路径的方式来使用 vivado 的仿真和自动纠错 + + +## [0.1.23] - 2022-12-24 +- Finish the css of documentation, see `./css/documentation.css` for detail. + +## [0.1.23] - 2022-12-23 +- Finish the function of documentation, webview display +- Finish the function of documentation, support export markdown and html + +## [0.1.23] - 2022-12-22 +- Rename partial tokens of verilog, make highlighting more colorful + +## [0.1.23] - 2022-12-05 +- Tree View can display the module that has not solved the dependence +- Finish the function of Instance and add icon for each solved module + +## [0.1.23] - 2022-12-02 +- Add unit test for most of logic + +## [0.1.23] - 2022-12-01 +- Finish reconstruction of HDLparam +- Finish the implementation of tree view + +## [0.1.22] - 2022-01-20 + +- Fix lib files do not display in tree view + +## [0.1.21] - 2022-01-20 + +- Fix issue [#26](https://github.com/Bestduan/Digital-IDE/issues/26) +- Rename as Digital-IDE +- Fix generate property.json file + +## [0.1.20] - 2022-01-12 + +- Fix issue [#32](https://github.com/Bestduan/Digital-IDE/issues/32) + +## [0.1.18] - 2021-09-12 + +- delete generate tb file +- add function netlist show +- Fix issue [#25](https://github.com/Bestduan/fpga_support_plug/issues/25) +- Fix issue [#24](https://github.com/Bestduan/fpga_support_plug/issues/24) + +## [0.1.17] - 2021-09-04 + +- Fix issue [#22](https://github.com/Bestduan/fpga_support_plug/issues/22) +- Fix issue [#21](https://github.com/Bestduan/fpga_support_plug/issues/21) +- Fix issue [#20](https://github.com/Bestduan/fpga_support_plug/issues/20) + + +## [0.1.16] - 2021-07-26 + +- Optimization of the kernel, fix High CPU usage +- Fix some other known bugs +- Add Formatter function + +## [0.1.15] - 2021-05-02 + +- Fix some bugs and add instructions + +## [0.1.12] - 2021-04-28 + +- Added simulation function, automatically pop up error message + +## [0.1.10] - 2020-04-16 + +- Added simulation function, automatically pop up error message + +## [0.1.8] - 2020-03-30 + +- Fixed the problem of repeatedly opening a new project and supported adding devices directly from the Makefile + +## [0.1.6] - 2020-03-19 + +- Add support for IP design and bd design +- Add module jump (`Alt + F12` or `F12`) +- Change the startup shortcut key +- Fix some bugs to enhance robustness + +## [0.1.4] - 2020-03-10 + +- Address the BUG existing in 0.1.3 + +## [0.1.2] - 2020-03-03 + +- Add Xilinx IP of Soc's cortexM3 +- Provide an example for `m3_for_xilinx.bd` +- Resolve the file structure conversion problem + +## [0.0.2] - 2020-02-28 + +- Added testbench / instance function + +## [0.0.1] - 2020-02-15 + +- Initial Release \ No newline at end of file diff --git a/config/bd.configuration.json b/config/bd.configuration.json new file mode 100644 index 0000000..f831368 --- /dev/null +++ b/config/bd.configuration.json @@ -0,0 +1,29 @@ +{ + "comments": { + "lineComment": "#" + }, + "brackets": [ + ["{", "}"], + ["[", "]"], + ["(", ")"] + ], + "autoClosingPairs": [ + ["{", "}"], + ["[", "]"], + ["(", ")"], + ["\"", "\""] + ], + "surroundingPairs": [ + ["{", "}"], + ["[", "]"], + ["(", ")"], + ["\"", "\""] + ], + "folding": { + "markers": { + "start": "{", + "end": "}" + } + }, + "wordPattern": "(?:(?:[^\\s\\{\\$\\\"]+|(?:\\$(?:\\w+|\\{[^\\}]+\\})))+)" +} diff --git a/images/svg/dark/bd.svg b/images/svg/dark/bd.svg new file mode 100644 index 0000000..daada7e --- /dev/null +++ b/images/svg/dark/bd.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/images/svg/dark/systemverilog.backup.svg b/images/svg/dark/systemverilog.backup.svg new file mode 100644 index 0000000..73b7fcf --- /dev/null +++ b/images/svg/dark/systemverilog.backup.svg @@ -0,0 +1 @@ + diff --git a/images/svg/dark/systemverilog.svg b/images/svg/dark/systemverilog.svg index 73b7fcf..d90710d 100644 --- a/images/svg/dark/systemverilog.svg +++ b/images/svg/dark/systemverilog.svg @@ -1 +1 @@ - + \ No newline at end of file diff --git a/images/svg/light/bd.svg b/images/svg/light/bd.svg new file mode 100644 index 0000000..daada7e --- /dev/null +++ b/images/svg/light/bd.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/images/svg/light/systemverilog.svg b/images/svg/light/systemverilog.svg new file mode 100644 index 0000000..d90710d --- /dev/null +++ b/images/svg/light/systemverilog.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/package.json b/package.json index 03d33ae..71f0714 100644 --- a/package.json +++ b/package.json @@ -452,6 +452,10 @@ "title": "%digital-ide.lsp.tool.transformOldPropertyFile.title%", "category": "Digital-IDE" }, + { + "command": "digital-ide.lsp.verilog.linter", + "title": "%digital-ide.lsp.verilog.linter.title%" + }, { "command": "digital-ide.vhdl2vlog", "title": "%digital-ide.vhdl2vlog.title%", @@ -685,13 +689,22 @@ ".xdc", ".fdc" ], - "configuration": "./config/tcl.configuration.json" + "configuration": "./config/tcl.configuration.json", + "icon": { + "dark": "./images/svg/dark/tcl.svg", + "light": "./images/svg/light/tcl.svg" + } }, { "id": "bd", "extensions": [ ".bd" - ] + ], + "configuration": "./config/bd.configuration.json", + "icon": { + "dark": "./images/svg/dark/bd.svg", + "light": "./images/svg/light/bd.svg" + } }, { "id": "vhdl", @@ -705,7 +718,11 @@ ".vho", ".vht" ], - "configuration": "./config/vhdl.configuration.json" + "configuration": "./config/vhdl.configuration.json", + "icon": { + "dark": "./images/svg/dark/vhdl.svg", + "light": "./images/svg/light/vhdl.svg" + } }, { "id": "verilog", @@ -719,7 +736,11 @@ ".vh", ".vl" ], - "configuration": "./config/verilog.configuration.json" + "configuration": "./config/verilog.configuration.json", + "icon": { + "dark": "./images/svg/dark/verilog.svg", + "light": "./images/svg/light/verilog.svg" + } }, { "id": "systemverilog", @@ -731,7 +752,11 @@ ".sv", ".SV" ], - "configuration": "./config/systemverilog.configuration.json" + "configuration": "./config/systemverilog.configuration.json", + "icon": { + "dark": "./images/svg/dark/systemverilog.svg", + "light": "./images/svg/light/systemverilog.svg" + } }, { "id": "arm", diff --git a/snippets/tcl.json b/snippets/tcl.json index 59d4083..d9ff82f 100644 --- a/snippets/tcl.json +++ b/snippets/tcl.json @@ -135,8 +135,33 @@ "tk_messageBox": { "prefix": "tk_messageBox", "body": [ - "tk_messageBox ${-message msg}" + "tk_messageBox ${0:message}" ], "description": "Message Box" - } + }, + "set_property": { + "prefix": "set_property", + "body": [ + "set_property ${1:property_name} ${2:value}" + ], + "description": "set property" + }, + "create_clock": { + "prefix": "create_clock", + "body": [ + "create_clock ${1:signal_name} ${2:clock_name} ${3:frequency} ${4:uncertainty}" + ] + }, + "set_initial_state": { + "prefix": "set_initial_state", + "body": [ + "set_initial_5state ${1:initial_state}" + ] + }, + "connect_port": { + "prefix": "connect_port", + "body": [ + "connect_port ${1:source_port} ${2:sink_port}" + ] + } } diff --git a/src/function/index.ts b/src/function/index.ts index 06eb280..c1ca646 100644 --- a/src/function/index.ts +++ b/src/function/index.ts @@ -60,6 +60,7 @@ function registerLsp(context: vscode.ExtensionContext) { const vlogSelector: vscode.DocumentSelector = {scheme: 'file', language: 'verilog'}; const svlogSelector: vscode.DocumentSelector = {scheme: 'file', language: 'systemverilog'}; const vhdlSelector: vscode.DocumentSelector = {scheme: 'file', language: 'vhdl'}; + const tclSelector: vscode.DocumentSelector = {scheme: 'file', language: 'tcl'}; // formatter vscode.languages.registerDocumentFormattingEditProvider(vlogSelector, lspFormatter.hdlFormatterProvider); @@ -79,10 +80,14 @@ function registerLsp(context: vscode.ExtensionContext) { vscode.languages.registerCompletionItemProvider(vlogSelector, lspCompletion.vlogCompletionProvider); vscode.languages.registerDocumentSemanticTokensProvider(vlogSelector, lspDocSemantic.vlogDocSenmanticProvider, lspDocSemantic.vlogLegend); + // tcl lsp + vscode.languages.registerCompletionItemProvider(tclSelector, lspCompletion.tclCompletionProvider); + lspLinter.vlogLinter.initialise(); lspCore.hdlSymbolStorage.initialise(); // vhdl lsp + } diff --git a/src/function/lsp/completion/index.ts b/src/function/lsp/completion/index.ts index 5a16895..f6ccdb7 100644 --- a/src/function/lsp/completion/index.ts +++ b/src/function/lsp/completion/index.ts @@ -1,8 +1,10 @@ import { vlogCompletionProvider, vlogIncludeCompletionProvider, vlogMacroCompletionProvider, vlogPositionPortProvider } from './vlog'; +import { tclCompletionProvider } from './tcl'; export { vlogCompletionProvider, vlogIncludeCompletionProvider, vlogMacroCompletionProvider, - vlogPositionPortProvider + vlogPositionPortProvider, + tclCompletionProvider }; \ No newline at end of file diff --git a/src/function/lsp/completion/tcl.ts b/src/function/lsp/completion/tcl.ts new file mode 100644 index 0000000..3447fec --- /dev/null +++ b/src/function/lsp/completion/tcl.ts @@ -0,0 +1,42 @@ +import * as vscode from 'vscode'; + +import { tclKeyword } from '../util/keyword'; +import { MainOutput } from '../../../global'; + + +class TCLCompletionProvider implements vscode.CompletionItemProvider { + keywordsCompletionItems: vscode.CompletionItem[] | undefined; + constructor() { + this.keywordsCompletionItems = this.provideKeywords(); + MainOutput.report('lsp for tcl is ready'); + } + public provideCompletionItems(document: vscode.TextDocument, position: vscode.Position, token: vscode.CancellationToken, context: vscode.CompletionContext): vscode.ProviderResult> { + try { + const items = this.provideKeywords(); + return items; + } catch (err) { + console.log(err); + } + } + + private provideKeywords(): vscode.CompletionItem[] { + if (this.keywordsCompletionItems === undefined) { + const keywords: vscode.CompletionItem[] = []; + for (const tcl of tclKeyword.keys()) { + const item = new vscode.CompletionItem(tcl); + item.kind = vscode.CompletionItemKind.Keyword; + keywords.push(item); + } + this.keywordsCompletionItems = keywords; + MainOutput.report('tcl lsp is ready'); + } + + return this.keywordsCompletionItems; + } +} + +const tclCompletionProvider = new TCLCompletionProvider(); + +export { + tclCompletionProvider +}; \ No newline at end of file diff --git a/src/function/lsp/linter/vivado.ts b/src/function/lsp/linter/vivado.ts new file mode 100644 index 0000000..e69de29 diff --git a/src/function/lsp/util/keyword.ts b/src/function/lsp/util/keyword.ts index 3a26bd2..5d5546e 100644 --- a/src/function/lsp/util/keyword.ts +++ b/src/function/lsp/util/keyword.ts @@ -123,9 +123,40 @@ const systemverilogKeyword = new Keywords([ ); +const tclKeyword = new Keywords([ + 'create_clock', + 'set_clock_uncertainty', + 'create_reset', + 'set_initial_state', + 'create_sync', + 'create_source_sync', + 'create_launch_bar', + 'connect_port', + 'set_signal_type', + 'set_edge_detect', + 'set_delay', + 'create_generated_clock', + 'create_programmable_logic', + 'create_lookup_table', + 'create_shift_register', + 'create_counter', + 'create_multiplier', + 'create_divider', + 'create_comparator', + 'create_register', + 'create_flop', + 'connect_power_pin', + 'connect_ground_pin', + 'set_property' +], +[], +[] +); + export { vlogKeyword, vhdlKeyword, - systemverilogKeyword + systemverilogKeyword, + tclKeyword }; \ No newline at end of file