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完成 xilinx 原语适配

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锦恢 2024-11-14 16:19:06 +08:00
parent c3a3ed6d6e
commit 13990c830b
29 changed files with 526 additions and 223 deletions
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3
l10n/bundle.l10n.de.json
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@ -27,5 +27,6 @@
"info.level.test": "Dies ist ein einfaches Beispiel", "info.level.test": "Dies ist ein einfaches Beispiel",
"info.progress.build-ip-module-tree": "构建 IP 模块树", "info.progress.build-ip-module-tree": "构建 IP 模块树",
"info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核", "info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核",
"info.progress.initialize-configure": "初始化项目配置" "info.progress.initialize-configure": "初始化项目配置",
"info.treeview.item.tooltip": "can't find the module of this instance"
} }

3
l10n/bundle.l10n.en.json
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@ -27,5 +27,6 @@
"info.level.test": "This is a simple example", "info.level.test": "This is a simple example",
"info.progress.build-ip-module-tree": "构建 IP 模块树", "info.progress.build-ip-module-tree": "构建 IP 模块树",
"info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核", "info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核",
"info.progress.initialize-configure": "初始化项目配置" "info.progress.initialize-configure": "初始化项目配置",
"info.treeview.item.tooltip": "can't find the module of this instance"
} }

3
l10n/bundle.l10n.ja.json
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@ -27,5 +27,6 @@
"info.level.test": "これは簡単な例です", "info.level.test": "これは簡単な例です",
"info.progress.build-ip-module-tree": "构建 IP 模块树", "info.progress.build-ip-module-tree": "构建 IP 模块树",
"info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核", "info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核",
"info.progress.initialize-configure": "初始化项目配置" "info.progress.initialize-configure": "初始化项目配置",
"info.treeview.item.tooltip": "can't find the module of this instance"
} }

3
l10n/bundle.l10n.zh-cn.json
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@ -27,5 +27,6 @@
"info.level.test": "这是一个简单的样例", "info.level.test": "这是一个简单的样例",
"info.progress.build-ip-module-tree": "构建 IP 模块树", "info.progress.build-ip-module-tree": "构建 IP 模块树",
"info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核", "info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核",
"info.progress.initialize-configure": "初始化项目配置" "info.progress.initialize-configure": "初始化项目配置",
"info.treeview.item.tooltip": "无法找到当前实例的模块"
} }

3
l10n/bundle.l10n.zh-tw.json
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@ -27,5 +27,6 @@
"info.level.test": "這是一個簡單的樣例", "info.level.test": "這是一個簡單的樣例",
"info.progress.build-ip-module-tree": "构建 IP 模块树", "info.progress.build-ip-module-tree": "构建 IP 模块树",
"info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核", "info.treeview.ip-no-active.message": "当前 IP 还未激活，请通过 Xilinx 工具链将 XCI 文件生成完整的 IP 核",
"info.progress.initialize-configure": "初始化项目配置" "info.progress.initialize-configure": "初始化项目配置",
"info.treeview.item.tooltip": "can't find the module of this instance"
} }

98
package.json
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@ -43,133 +43,134 @@
"digital-ide.welcome.show": { "digital-ide.welcome.show": {
"type": "boolean", "type": "boolean",
"default": true, "default": true,
"description": "show the welcome text in Digital-IDE" "description": "%digital-ide.welcome.show.title%"
}, },
"digital-ide.dont-show-again.propose.issue": { "digital-ide.dont-show-again.propose.issue": {
"type": "boolean", "type": "boolean",
"default": false, "default": false,
"description": "show the welcome text in Digital-IDE" "description": "%digital-ide.dont-show-again.propose.issue.title%"
}, },
"digital-ide.lib.custom.path": { "digital-ide.lib.custom.path": {
"type": "string", "type": "string",
"default": "", "default": "",
"description": "path of the dictionary of \"custom\" in library" "description": "%digital-ide.lib.custom.path.title%"
}, },
"digital-ide.prj.file.structure.notice": { "digital-ide.prj.file.structure.notice": {
"type": "boolean", "type": "boolean",
"default": true, "default": true,
"description": "notice when change file structure" "description": "%digital-ide.prj.file.structure.notice.title%"
}, },
"digital-ide.prj.vivado.install.path": { "digital-ide.prj.vivado.install.path": {
"type": "string", "type": "string",
"default": "", "default": "C:/Xilinx/Vivado/2018.3/bin",
"description": "Set the xilinx install path. Ignore this setting if you add relative path to environment variable PATH \n e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin \n Default path is C:/Xilinx/Vivado/2018.3/bin" "description": "%digital-ide.prj.vivado.install.path.title%"
}, },
"digital-ide.prj.modelsim.install.path": { "digital-ide.prj.modelsim.install.path": {
"type": "string", "type": "string",
"default": "", "default": "C:/modeltech64_10.4/win64",
"description": "set the modelsim install path. Ignore this setting if you add relative path to environment variable PATH \n Default path is C:/modeltech64_10.4/win64" "description": "%digital-ide.prj.modelsim.install.path.title%"
}, },
"digital-ide.prj.xilinx.IP.repo.path": { "digital-ide.prj.xilinx.IP.repo.path": {
"type": "string", "type": "string",
"default": "", "default": "",
"description": "User-designed IP libraries from xilinx After configuring this property, the plugin will automatically add the path to the IP repo of vivado." "description": "%digital-ide.prj.xilinx.IP.repo.path.title%"
}, },
"digital-ide.prj.xilinx.BD.repo.path": { "digital-ide.prj.xilinx.BD.repo.path": {
"type": "string", "type": "string",
"default": "", "default": "",
"description": "User-defined placement path for xilinx block design files" "description": "%digital-ide.prj.xilinx.BD.repo.path.title%"
}, },
"digital-ide.prj.xsdk.install.path": { "digital-ide.prj.xsdk.install.path": {
"type": "string", "type": "string",
"default": "" "default": "",
"description": "%digital-ide.prj.xsdk.install.path.title%"
}, },
"digital-ide.function.doc.webview.backgroundImage": { "digital-ide.function.doc.webview.backgroundImage": {
"type": "string", "type": "string",
"default": "", "default": "",
"description": "url of the background image" "description": "%digital-ide.function.doc.webview.backgroundImage.title%"
}, },
"digital-ide.function.doc.pdf.scale": { "digital-ide.function.doc.pdf.scale": {
"type": "number", "type": "number",
"default": 1, "default": 1,
"description": "scale of the exported pdf" "description": "%digital-ide.function.doc.pdf.scale.title%"
}, },
"digital-ide.function.doc.pdf.printBackground": { "digital-ide.function.doc.pdf.printBackground": {
"type": "boolean", "type": "boolean",
"default": true, "default": true,
"description": "whether print background" "description": "%digital-ide.function.doc.pdf.printBackground.title%"
}, },
"digital-ide.function.doc.pdf.landscape": { "digital-ide.function.doc.pdf.landscape": {
"type": "boolean", "type": "boolean",
"default": false, "default": false,
"description": "whether export pdf as a landscape style" "description": "%digital-ide.function.doc.pdf.landscape.title%"
}, },
"digital-ide.function.doc.pdf.format": { "digital-ide.function.doc.pdf.format": {
"type": "string", "type": "string",
"default": "A4", "default": "A4",
"description": "format of pdf size" "description": "%digital-ide.function.doc.pdf.format.title%"
}, },
"digital-ide.function.doc.pdf.displayHeaderFooter": { "digital-ide.function.doc.pdf.displayHeaderFooter": {
"type": "boolean", "type": "boolean",
"default": false, "default": false,
"description": "display header and footer in the exported pdf" "description": "%digital-ide.function.doc.pdf.displayHeaderFooter.title%"
}, },
"digital-ide.function.doc.pdf.browserPath": { "digital-ide.function.doc.pdf.browserPath": {
"type": "string", "type": "string",
"default": "C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe", "default": "C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
"description": "the absolute path of edge or chrome, we need browser to render pdf" "description": "%digital-ide.function.doc.pdf.browserPath.title%"
}, },
"digital-ide.function.doc.pdf.margin.top": { "digital-ide.function.doc.pdf.margin.top": {
"type": "number", "type": "number",
"default": 0.5, "default": 0.5,
"description": "top margin of exported pdf, unit cm" "description": "%digital-ide.function.doc.pdf.margin.top.title%"
}, },
"digital-ide.function.doc.pdf.margin.right": { "digital-ide.function.doc.pdf.margin.right": {
"type": "number", "type": "number",
"default": 0.5, "default": 0.5,
"description": "top margin of exported pdf, unit cm" "description": "%digital-ide.function.doc.pdf.margin.right.title%"
}, },
"digital-ide.function.doc.pdf.margin.bottom": { "digital-ide.function.doc.pdf.margin.bottom": {
"type": "number", "type": "number",
"default": 0.5, "default": 0.5,
"description": "top margin of exported pdf, unit cm" "description": "%digital-ide.function.doc.pdf.margin.bottom.title%"
}, },
"digital-ide.function.doc.pdf.margin.left": { "digital-ide.function.doc.pdf.margin.left": {
"type": "number", "type": "number",
"default": 0.5, "default": 0.5,
"description": "top margin of exported pdf, unit cm" "description": "%digital-ide.function.doc.pdf.margin.left.title%"
}, },
"digital-ide.function.doc.pdf.headerTemplate": { "digital-ide.function.doc.pdf.headerTemplate": {
"type": "string", "type": "string",
"default": "<div style=\"font-size: 9px; margin-left: 1cm;\"> <span class='title'></span></div> <div style=\"font-size: 9px; margin-left: auto; margin-right: 1cm; \"> <span class='date'></span></div>", "default": "<div style=\"font-size: 9px; margin-left: 1cm;\"> <span class='title'></span></div> <div style=\"font-size: 9px; margin-left: auto; margin-right: 1cm; \"> <span class='date'></span></div>",
"description": "html template of header, if displayHeaderFooter is set to false, this setting will be ignored" "description": "%digital-ide.function.doc.pdf.headerTemplate.title%"
}, },
"digital-ide.function.doc.pdf.footerTemplate": { "digital-ide.function.doc.pdf.footerTemplate": {
"type": "string", "type": "string",
"default": "<div style=\"font-size: 9px; margin-left: 1cm;\"> <span class='title'></span></div> <div style=\"font-size: 9px; margin-left: auto; margin-right: 1cm; \"> <span class='date'></span></div>", "default": "<div style=\"font-size: 9px; margin-left: 1cm;\"> <span class='title'></span></div> <div style=\"font-size: 9px; margin-left: auto; margin-right: 1cm; \"> <span class='date'></span></div>",
"description": "html template of footer, if displayHeaderFooter is set to false, this setting will be ignored" "description": "%digital-ide.function.doc.pdf.footerTemplate.title%"
}, },
"digital-ide.function.simulate.icarus.installPath": { "digital-ide.function.simulate.icarus.installPath": {
"type": "string", "type": "string",
"description": "Path of install path of iverilog components, if set to \"\", then iverilog and vvp in environment will be used for simulation. Otherwise, ones that in the install path will be used." "description": "%digital-ide.function.simulate.icarus.installPath.title%"
}, },
"digital-ide.function.simulate.simulationHome": { "digital-ide.function.simulate.simulationHome": {
"type": "string", "type": "string",
"description": "Path of simulation folder, .vvp and other file during simulation will be generated here" "description": "%digital-ide.function.simulate.simulationHome.title%"
}, },
"digital-ide.function.simulate.gtkwavePath": { "digital-ide.function.simulate.gtkwavePath": {
"type": "string", "type": "string",
"default": "gtkwave", "default": "gtkwave",
"description": "Absolute path of launch path of gtkwave software" "description": "%digital-ide.function.simulate.gtkwavePath.title%"
}, },
"digital-ide.function.simulate.xilinxLibPath": { "digital-ide.function.simulate.xilinxLibPath": {
"type": "string", "type": "string",
"description": "Path of Xilinx library for simulation" "description": "%digital-ide.function.simulate.xilinxLibPath.title%"
}, },
"digital-ide.function.simulate.runInTerminal": { "digital-ide.function.simulate.runInTerminal": {
"type": "boolean", "type": "boolean",
"default": false, "default": false,
"description": "run the simulation command in terminal instead of output" "description": "%digital-ide.function.simulate.runInTerminal.title%"
}, },
"digital-ide.function.lsp.formatter.vlog.default.style": { "digital-ide.function.lsp.formatter.vlog.default.style": {
"type": "string", "type": "string",
@ -179,15 +180,15 @@
"gnu" "gnu"
], ],
"default": "kr", "default": "kr",
"description": "Select the verilog and systemverilog formatter style." "description": "%digital-ide.function.lsp.formatter.vlog.default.style.title%"
}, },
"digital-ide.function.lsp.formatter.vlog.default.args": { "digital-ide.function.lsp.formatter.vlog.default.args": {
"type": "string", "type": "string",
"default": "", "default": "",
"description": "Add verilog formatter arguments here (like istyle)." "description": "%digital-ide.function.lsp.formatter.vlog.default.args.title%"
}, },
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case": { "digital-ide.function.lsp.formatter.vhdl.default.keyword-case": {
"description": "Keyword case", "description": "%digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title%",
"type": "string", "type": "string",
"default": "LowerCase", "default": "LowerCase",
"enum": [ "enum": [
@ -196,12 +197,12 @@
] ]
}, },
"digital-ide.function.lsp.formatter.vhdl.default.align-comments": { "digital-ide.function.lsp.formatter.vhdl.default.align-comments": {
"description": "Align comments", "description": "%digital-ide.function.lsp.formatter.vhdl.default.align-comments.title%",
"type": "boolean", "type": "boolean",
"default": false "default": false
}, },
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case": { "digital-ide.function.lsp.formatter.vhdl.default.type-name-case": {
"description": "Type name case", "description": "%digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title%",
"type": "string", "type": "string",
"default": "LowerCase", "default": "LowerCase",
"enum": [ "enum": [
@ -210,17 +211,17 @@
] ]
}, },
"digital-ide.function.lsp.formatter.vhdl.default.indentation": { "digital-ide.function.lsp.formatter.vhdl.default.indentation": {
"description": "Indentation", "description": "%digital-ide.function.lsp.formatter.vhdl.default.indentation.title%",
"type": "number", "type": "number",
"default": 4 "default": 4
}, },
"digital-ide.function.lsp.completion.vlog.autoAddInclude": { "digital-ide.function.lsp.completion.vlog.auto-add-include": {
"description": "`include \"xxx.v\" will be added to the top of the file automatically", "description": "%digital-ide.function.lsp.completion.vlog.auto-add-include.title%",
"type": "boolean", "type": "boolean",
"default": true "default": true
}, },
"digital-ide.function.lsp.completion.vlog.completeWholeInstante": { "digital-ide.function.lsp.completion.vlog.auto-add-output-declaration": {
"description": "complete everything invoking a module needs including paramters and ports", "description": "%digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title%",
"type": "boolean", "type": "boolean",
"default": true "default": true
}, },
@ -237,7 +238,7 @@
"default" "default"
], ],
"default": "default", "default": "default",
"description": "choose diagnostor to do linter in editing verilog" "description": "%digital-ide.function.lsp.linter.vlog.diagnostor.title%"
}, },
"digital-ide.function.lsp.linter.svlog.diagnostor": { "digital-ide.function.lsp.linter.svlog.diagnostor": {
"type": "string", "type": "string",
@ -252,7 +253,7 @@
"default" "default"
], ],
"default": "default", "default": "default",
"description": "choose diagnostor to do linter in editing verilog" "description": "%digital-ide.function.lsp.linter.svlog.diagnostor.title%"
}, },
"digital-ide.function.lsp.linter.vhdl.diagnostor": { "digital-ide.function.lsp.linter.vhdl.diagnostor": {
"type": "string", "type": "string",
@ -267,7 +268,7 @@
"default" "default"
], ],
"default": "default", "default": "default",
"description": "choose diagnostor to do linter in editing vhdl" "description": "%digital-ide.function.lsp.linter.vhdl.diagnostor.title%"
}, },
"digital-ide.function.lsp.linter.systemverilog.diagnostor": { "digital-ide.function.lsp.linter.systemverilog.diagnostor": {
"type": "string", "type": "string",
@ -282,15 +283,15 @@
"default" "default"
], ],
"default": "default", "default": "default",
"description": "choose diagnostor to do linter in editing systemverilog" "description": "%digital-ide.function.lsp.linter.systemverilog.diagnostor.title%"
}, },
"digital-ide.function.instantiation.addComment": { "digital-ide.function.instantiation.addComment": {
"description": "add comment like // ports, // input, // output when doing instantiation, including completion for module invoking", "description": "%digital-ide.function.instantiation.addComment.title%",
"type": "boolean", "type": "boolean",
"default": true "default": true
}, },
"digital-ide.function.instantiation.autoNetOutputDeclaration": { "digital-ide.function.instantiation.autoNetOutputDeclaration": {
"description": "auto declare output type nets in the scope when instantiation happens.", "description": "%digital-ide.function.instantiation.autoNetOutputDeclaration.title%",
"type": "boolean", "type": "boolean",
"default": true "default": true
}, },
@ -299,7 +300,12 @@
"default": [ "default": [
"\n" "\n"
], ],
"description": "Trigger characters for onTypeFormatting" "description": "%fpga-support.onTypeFormattingTriggerCharacters.title%"
},
"digital-ide.function.lsp.file-parse-maxsize": {
"type": "integer",
"default": 1,
"description": "%digital-ide.function.lsp.file-parse-maxsize.title%"
} }
} }
}, },

45
package.nls.de.json
View File

@ -48,5 +48,48 @@
"digital-ide.lsp.systemverilog.linter.pick.title": "SystemVerilog-Diagnose auswählen", "digital-ide.lsp.systemverilog.linter.pick.title": "SystemVerilog-Diagnose auswählen",
"digital-ide.tool.export-filelist.title": "Dateiliste exportieren", "digital-ide.tool.export-filelist.title": "Dateiliste exportieren",
"digital-ide.treeview": "Digital IDE: Modulbaum", "digital-ide.treeview": "Digital IDE: Modulbaum",
"digital-ide.digital-lsp.download.title": "Digital-Sprachserver herunterladen" "digital-ide.digital-lsp.download.title": "Digital-Sprachserver herunterladen",
"digital-ide.welcome.show.title": "show the welcome text in Digital-IDE",
"digital-ide.dont-show-again.propose.issue.title": "show the welcome text in Digital-IDE",
"digital-ide.lib.custom.path.title": "path of the dictionary of \"custom\" in library",
"digital-ide.prj.file.structure.notice.title": "notice when change file structure",
"digital-ide.prj.vivado.install.path.title": "Set the xilinx install path. Ignore this setting if you add relative path to environment variable PATH \n e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin \n Default path is C:/Xilinx/Vivado/2018.3/bin",
"digital-ide.prj.modelsim.install.path.title": "set the modelsim install path. Ignore this setting if you add relative path to environment variable PATH \n Default path is C:/modeltech64_10.4/win64",
"digital-ide.prj.xilinx.IP.repo.path.title": "User-designed IP libraries from xilinx After configuring this property, the plugin will automatically add the path to the IP repo of vivado.",
"digital-ide.prj.xilinx.BD.repo.path.title": "User-defined placement path for xilinx block design files",
"digital-ide.prj.xsdk.install.path.title": "",
"digital-ide.function.doc.webview.backgroundImage.title": "url of the background image",
"digital-ide.function.doc.pdf.scale.title": "scale of the exported pdf",
"digital-ide.function.doc.pdf.printBackground.title": "whether print background",
"digital-ide.function.doc.pdf.landscape.title": "whether export pdf as a landscape style",
"digital-ide.function.doc.pdf.format.title": "format of pdf size",
"digital-ide.function.doc.pdf.displayHeaderFooter.title": "display header and footer in the exported pdf",
"digital-ide.function.doc.pdf.browserPath.title": "the absolute path of edge or chrome, we need browser to render pdf",
"digital-ide.function.doc.pdf.margin.top.title": "top margin of exported pdf, unit cm",
"digital-ide.function.doc.pdf.margin.right.title": "top margin of exported pdf, unit cm",
"digital-ide.function.doc.pdf.margin.bottom.title": "top margin of exported pdf, unit cm",
"digital-ide.function.doc.pdf.margin.left.title": "top margin of exported pdf, unit cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "html template of header, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.doc.pdf.footerTemplate.title": "html template of footer, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.simulate.icarus.installPath.title": "Path of install path of iverilog components, if set to \"\", then iverilog and vvp in environment will be used for simulation. Otherwise, ones that in the install path will be used.",
"digital-ide.function.simulate.simulationHome.title": "Path of simulation folder, .vvp and other file during simulation will be generated here",
"digital-ide.function.simulate.gtkwavePath.title": "Absolute path of launch path of gtkwave software",
"digital-ide.function.simulate.xilinxLibPath.title": "Path of Xilinx library for simulation",
"digital-ide.function.simulate.runInTerminal.title": "run the simulation command in terminal instead of output",
"digital-ide.function.lsp.formatter.vlog.default.style.title": "Select the verilog and systemverilog formatter style.",
"digital-ide.function.lsp.formatter.vlog.default.args.title": "Add verilog formatter arguments here (like istyle).",
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "Keyword case",
"digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "Align comments",
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "Type name case",
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "`include \"xxx.v\" will be added to the top of the file automatically",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "complete everything invoking a module needs including paramters and ports",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "choose diagnostor to do linter in editing vhdl",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "choose diagnostor to do linter in editing systemverilog",
"digital-ide.function.instantiation.addComment.title": "add comment like // ports, // input, // output when doing instantiation, including completion for module invoking",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "auto declare output type nets in the scope when instantiation happens.",
"fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
} }

45
package.nls.ja.json
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@ -48,5 +48,48 @@
"digital-ide.lsp.systemverilog.linter.pick.title": "SystemVerilog の診断を選択", "digital-ide.lsp.systemverilog.linter.pick.title": "SystemVerilog の診断を選択",
"digital-ide.tool.export-filelist.title": "ファイルリストをエクスポート", "digital-ide.tool.export-filelist.title": "ファイルリストをエクスポート",
"digital-ide.treeview": "Digital IDE: モジュールツリー", "digital-ide.treeview": "Digital IDE: モジュールツリー",
"digital-ide.digital-lsp.download.title": "Digital 言語サーバーをダウンロード" "digital-ide.digital-lsp.download.title": "Digital LSP 言語サーバーをダウンロード",
"digital-ide.welcome.show.title": "Digital-IDE でウェルカムテキストを表示",
"digital-ide.dont-show-again.propose.issue.title": "Digital-IDE でウェルカムテキストを表示",
"digital-ide.lib.custom.path.title": "ユーザー定義の lib ディレクトリのパス",
"digital-ide.prj.file.structure.notice.title": "ローカルファイルが削除されたときに通知を表示するかどうか",
"digital-ide.prj.vivado.install.path.title": "Xilinx Vivado のインストールパスを設定します。例：D:/APP/vivado_18_3/Vivado/2018.3/bin。デフォルトのパスは C:/Xilinx/Vivado/2018.3/bin\n環境変数 PATH に相対パスを追加した場合、この設定を無視してください",
"digital-ide.prj.modelsim.install.path.title": "Modelsim のインストールパスを設定します。デフォルトのパスは C:/modeltech64_10.4/win64\n環境変数 PATH に相対パスを追加した場合、この設定を無視してください",
"digital-ide.prj.xilinx.IP.repo.path.title": "ユーザー設計の Xilinx IP ライブラリのパス。このプロパティを設定すると、プラグインは自動的にパスを Vivado の IP ライブラリに追加します。",
"digital-ide.prj.xilinx.BD.repo.path.title": "ユーザー定義の Xilinx BD ファイルの配置パス",
"digital-ide.prj.xsdk.install.path.title": "",
"digital-ide.function.doc.webview.backgroundImage.title": "背景画像の URL",
"digital-ide.function.doc.pdf.scale.title": "エクスポートされた PDF のスケール",
"digital-ide.function.doc.pdf.printBackground.title": "背景を印刷するかどうか",
"digital-ide.function.doc.pdf.landscape.title": "PDF を横向きスタイルでエクスポートするかどうか",
"digital-ide.function.doc.pdf.format.title": "PDF のサイズフォーマット",
"digital-ide.function.doc.pdf.displayHeaderFooter.title": "エクスポートされた PDF にヘッダーとフッターを表示する",
"digital-ide.function.doc.pdf.browserPath.title": "Edge または Chrome の絶対パス、PDF をレンダリングするためにブラウザが必要です。デフォルトのパスは C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
"digital-ide.function.doc.pdf.margin.top.title": "エクスポートされた PDF の上余白、単位 cm",
"digital-ide.function.doc.pdf.margin.right.title": "エクスポートされた PDF の右余白、単位 cm",
"digital-ide.function.doc.pdf.margin.bottom.title": "エクスポートされた PDF の下余白、単位 cm",
"digital-ide.function.doc.pdf.margin.left.title": "エクスポートされた PDF の左余白、単位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "ヘッダーの HTML テンプレート、displayHeaderFooter が false に設定されている場合、この設定は無視されます",
"digital-ide.function.doc.pdf.footerTemplate.title": "フッターの HTML テンプレート、displayHeaderFooter が false に設定されている場合、この設定は無視されます",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog コンポーネントのインストールパス、空に設定されている場合、環境の iverilog と vvp がシミュレーションに使用されます。それ以外の場合、インストールパスのコンポーネントが使用されます。",
"digital-ide.function.simulate.simulationHome.title": "シミュレーションフォルダのパス、シミュレーション中の .vvp およびその他のファイルがここに生成されます",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave ソフトウェアの起動パスの絶対パス",
"digital-ide.function.simulate.xilinxLibPath.title": "シミュレーション用の Xilinx ライブラリのパス",
"digital-ide.function.simulate.runInTerminal.title": "出力ではなくターミナルでシミュレーションコマンドを実行する",
"digital-ide.function.lsp.formatter.vlog.default.style.title": "Verilog および SystemVerilog フォーマッタスタイルを選択します。",
"digital-ide.function.lsp.formatter.vlog.default.args.title": "ここに Verilog フォーマッタ引数（例：istyle）を追加します。",
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "キーワードの大文字小文字",
"digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "コメントの整列",
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "型名の大文字小文字",
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "インデント",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "モジュールの自動補完をトリガーするとき、トップの include マクロにインスタンス化されたモジュールがあるファイルが含まれていない場合、ファイルの先頭に `include \"xxx.v\" を自動的に追加します",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "モジュールの自動補完をトリガーするとき、インスタンス化されたモジュールの上に output タイプの信号の宣言を自動的に生成します",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "Verilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "SystemVerilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "VHDL 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "SystemVerilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.instantiation.addComment.title": "インスタンス化時に // ポート, // 入力, // 出力 のようなコメントを追加し、モジュール呼び出しの補完を含みます",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "インスタンス化が発生したときにスコープ内で出力タイプのネットを自動的に宣言します。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting のトリガー文字",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
} }

45
package.nls.json
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@ -48,5 +48,48 @@
"digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog", "digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog",
"digital-ide.tool.export-filelist.title": "export filelist", "digital-ide.tool.export-filelist.title": "export filelist",
"digital-ide.treeview": "Digital IDE: TreeView", "digital-ide.treeview": "Digital IDE: TreeView",
"digital-ide.digital-lsp.download.title": "Download Digital LSP" "digital-ide.digital-lsp.download.title": "Download Digital LSP Language Server",
"digital-ide.welcome.show.title": "Show welcome text in Digital-IDE",
"digital-ide.dont-show-again.propose.issue.title": "Show welcome text in Digital-IDE",
"digital-ide.lib.custom.path.title": "Path of the user-defined lib directory",
"digital-ide.prj.file.structure.notice.title": "Show a notice when a local file is deleted",
"digital-ide.prj.vivado.install.path.title": "Set the Xilinx Vivado installation path. For example: D:/APP/vivado_18_3/Vivado/2018.3/bin. The default path is C:/Xilinx/Vivado/2018.3/bin\nIgnore this setting if you add a relative path to the environment variable PATH",
"digital-ide.prj.modelsim.install.path.title": "Set the Modelsim installation path. The default path is C:/modeltech64_10.4/win64\nIgnore this setting if you add a relative path to the environment variable PATH",
"digital-ide.prj.xilinx.IP.repo.path.title": "Path of the user-designed Xilinx IP library. After configuring this property, the plugin will automatically add the path to the Vivado IP library.",
"digital-ide.prj.xilinx.BD.repo.path.title": "User-defined placement path for Xilinx BD files",
"digital-ide.prj.xsdk.install.path.title": "",
"digital-ide.function.doc.webview.backgroundImage.title": "URL of the background image",
"digital-ide.function.doc.pdf.scale.title": "Scale of the exported PDF",
"digital-ide.function.doc.pdf.printBackground.title": "Whether to print the background",
"digital-ide.function.doc.pdf.landscape.title": "Whether to export the PDF in landscape style",
"digital-ide.function.doc.pdf.format.title": "Format of the PDF size",
"digital-ide.function.doc.pdf.displayHeaderFooter.title": "Display header and footer in the exported PDF",
"digital-ide.function.doc.pdf.browserPath.title": "Absolute path of Edge or Chrome, we need a browser to render the PDF. The default path is C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
"digital-ide.function.doc.pdf.margin.top.title": "Top margin of the exported PDF, unit cm",
"digital-ide.function.doc.pdf.margin.right.title": "Right margin of the exported PDF, unit cm",
"digital-ide.function.doc.pdf.margin.bottom.title": "Bottom margin of the exported PDF, unit cm",
"digital-ide.function.doc.pdf.margin.left.title": "Left margin of the exported PDF, unit cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "HTML template of the header, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.doc.pdf.footerTemplate.title": "HTML template of the footer, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.simulate.icarus.installPath.title": "Installation path of Icarus Verilog components, if set to empty, the iverilog and vvp in the environment will be used for simulation. Otherwise, the components in the installation path will be used.",
"digital-ide.function.simulate.simulationHome.title": "Path of the simulation folder, .vvp and other files during simulation will be generated here",
"digital-ide.function.simulate.gtkwavePath.title": "Absolute path of the launch path of the gtkwave software",
"digital-ide.function.simulate.xilinxLibPath.title": "Path of the Xilinx library for simulation",
"digital-ide.function.simulate.runInTerminal.title": "Run the simulation command in the terminal instead of the output",
"digital-ide.function.lsp.formatter.vlog.default.style.title": "Select the Verilog and SystemVerilog formatter style.",
"digital-ide.function.lsp.formatter.vlog.default.args.title": "Add Verilog formatter arguments here (like istyle).",
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "Keyword case",
"digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "Align comments",
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "Type name case",
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "When triggering module auto-completion, if the top include macro does not include the file where the instantiated module is located, automatically add `include \"xxx.v\" at the top of the file",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "When triggering module auto-completion, automatically generate the declaration of output type signals above the instantiated module",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "Choose the diagnostor to do linter in editing Verilog",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "Choose the diagnostor to do linter in editing VHDL",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
"digital-ide.function.instantiation.addComment.title": "Add comments like // ports, // input, // output when doing instantiation, including completion for module invoking",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "Automatically declare output type nets in the scope when instantiation happens.",
"fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
} }

47
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@ -37,7 +37,7 @@
"digital-ide.netlist.title": "netlist", "digital-ide.netlist.title": "netlist",
"digital-ide.fsm.title": "有限状态机", "digital-ide.fsm.title": "有限状态机",
"digital-ide.lsp.tool.insertTextToUri.title": "插入文本uri", "digital-ide.lsp.tool.insertTextToUri.title": "插入文本uri",
"digital-ide.lsp.tool.transformOldPropertyFile.title": "转换配置文件从先前版本新版本", "digital-ide.lsp.tool.transformOldPropertyFile.title": "转换配置文件从先前版本到新版本",
"digital-ide.vhdl2vlog.title": "vhdl代码翻译为verilog代码", "digital-ide.vhdl2vlog.title": "vhdl代码翻译为verilog代码",
"digital-ide.fsm.show.title": "显示当前文件的FSM图", "digital-ide.fsm.show.title": "显示当前文件的FSM图",
"digital-ide.netlist.show.title": "显示当前文件的netlist", "digital-ide.netlist.show.title": "显示当前文件的netlist",
@ -48,5 +48,48 @@
"digital-ide.lsp.systemverilog.linter.pick.title": "选择 SystemVerilog 的诊断", "digital-ide.lsp.systemverilog.linter.pick.title": "选择 SystemVerilog 的诊断",
"digital-ide.tool.export-filelist.title": "导出 filelist", "digital-ide.tool.export-filelist.title": "导出 filelist",
"digital-ide.treeview": "Digital IDE: 模块树", "digital-ide.treeview": "Digital IDE: 模块树",
"digital-ide.digital-lsp.download.title": "下载 Digital 语言服务器" "digital-ide.digital-lsp.download.title": "下载 Digital LSP 语言服务器",
"digital-ide.welcome.show.title": "在 Digital-IDE 中显示欢迎文本",
"digital-ide.dont-show-again.propose.issue.title": "在 Digital-IDE 中显示欢迎文本",
"digital-ide.lib.custom.path.title": "用户自定义 lib 目录的路径",
"digital-ide.prj.file.structure.notice.title": "是否在本地文件被删除时显示提示",
"digital-ide.prj.vivado.install.path.title": "设置 Xilinx Vivado 安装路径。例如：D:/APP/vivado_18_3/Vivado/2018.3/bin 。默认路径是 C:/Xilinx/Vivado/2018.3/bin\n如果将相对路径添加到环境变量 PATH 中，请忽略此设置",
"digital-ide.prj.modelsim.install.path.title": "设置 Modelsim 安装路径。默认路径是 C:/modeltech64_10.4/win64\n如果将相对路径添加到环境变量 PATH 中，请忽略此设置",
"digital-ide.prj.xilinx.IP.repo.path.title": "用户设计的 Xilinx IP 库路径。配置此属性后，插件将自动将路径添加到 Vivado 的 IP 库中。",
"digital-ide.prj.xilinx.BD.repo.path.title": "用户定义的 Xilinx BD 文件放置路径",
"digital-ide.prj.xsdk.install.path.title": "",
"digital-ide.function.doc.webview.backgroundImage.title": "背景图片的 URL",
"digital-ide.function.doc.pdf.scale.title": "导出的 PDF 缩放比例",
"digital-ide.function.doc.pdf.printBackground.title": "是否打印背景",
"digital-ide.function.doc.pdf.landscape.title": "是否以横向样式导出 PDF",
"digital-ide.function.doc.pdf.format.title": "PDF 尺寸格式",
"digital-ide.function.doc.pdf.displayHeaderFooter.title": "在导出的 PDF 中显示页眉和页脚",
"digital-ide.function.doc.pdf.browserPath.title": "Edge 或 Chrome 的绝对路径，我们需要浏览器来渲染 PDF。默认路径为 C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
"digital-ide.function.doc.pdf.margin.top.title": "导出的 PDF 的上边距，单位 cm",
"digital-ide.function.doc.pdf.margin.right.title": "导出的 PDF 的右边距，单位 cm",
"digital-ide.function.doc.pdf.margin.bottom.title": "导出的 PDF 的下边距，单位 cm",
"digital-ide.function.doc.pdf.margin.left.title": "导出的 PDF 的左边距，单位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "页眉的 HTML 模板，如果 displayHeaderFooter 设置为 false，则此设置将被忽略",
"digital-ide.function.doc.pdf.footerTemplate.title": "页脚的 HTML 模板，如果 displayHeaderFooter 设置为 false，则此设置将被忽略",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog 组件的安装路径，如果设置为空，则使用环境中的 iverilog 和 vvp 进行仿真。否则，将使用安装路径中的组件。",
"digital-ide.function.simulate.simulationHome.title": "仿真文件夹路径，仿真期间的 .vvp 和其他文件将生成在此处",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave 软件的启动路径的绝对路径",
"digital-ide.function.simulate.xilinxLibPath.title": "仿真用 Xilinx 库的路径",
"digital-ide.function.simulate.runInTerminal.title": "在终端中运行仿真命令，而不是在输出中运行",
"digital-ide.function.lsp.formatter.vlog.default.style.title": "选择 Verilog 和 SystemVerilog 格式化器样式。",
"digital-ide.function.lsp.formatter.vlog.default.args.title": "在此处添加 Verilog 格式化器参数（如 istyle）。",
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "关键字大小写",
"digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "对齐注释",
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "类型名称大小写",
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "缩进",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "触发模块的自动补全时，如果顶部 include 宏中没有包含被例化模块所在的文件，则自动在文件顶部添加 `include \"xxx.v\"",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "触发模块的自动补全时，在例化模块上方自动生成 output 类型信号的申明",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "选择编辑 Verilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "选择编辑 SystemVerilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "选择编辑 VHDL 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "选择编辑 SystemVerilog 时的诊断器进行语法检查",
"digital-ide.function.instantiation.addComment.title": "在进行实例化时添加注释，如 // 端口, // 输入, // 输出，包括模块调用的完成",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "在实例化发生时自动在作用域中声明输出类型的网络。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting 的触发字符",
"digital-ide.function.lsp.file-parse-maxsize.title": "最大解析的文件阈值，大小超出这个值的文件不会被解析。单位为 MB，必须是整数。默认为 1MB"
} }

45
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@ -48,5 +48,48 @@
"digital-ide.lsp.systemverilog.linter.pick.title": "選擇 SystemVerilog 的診斷", "digital-ide.lsp.systemverilog.linter.pick.title": "選擇 SystemVerilog 的診斷",
"digital-ide.tool.export-filelist.title": "導出 filelist", "digital-ide.tool.export-filelist.title": "導出 filelist",
"digital-ide.treeview": "Digital IDE: 模塊樹", "digital-ide.treeview": "Digital IDE: 模塊樹",
"digital-ide.digital-lsp.download.title": "下載 Digital 語言服務器" "digital-ide.digital-lsp.download.title": "下載 Digital LSP 語言伺服器",
"digital-ide.welcome.show.title": "在 Digital-IDE 中顯示歡迎文字",
"digital-ide.dont-show-again.propose.issue.title": "在 Digital-IDE 中顯示歡迎文字",
"digital-ide.lib.custom.path.title": "用戶自訂 lib 目錄的路徑",
"digital-ide.prj.file.structure.notice.title": "是否在本地文件被刪除時顯示提示",
"digital-ide.prj.vivado.install.path.title": "設置 Xilinx Vivado 安裝路徑。例如：D:/APP/vivado_18_3/Vivado/2018.3/bin 。預設路徑是 C:/Xilinx/Vivado/2018.3/bin\n如果將相對路徑添加到環境變數 PATH 中，請忽略此設置",
"digital-ide.prj.modelsim.install.path.title": "設置 Modelsim 安裝路徑。預設路徑是 C:/modeltech64_10.4/win64\n如果將相對路徑添加到環境變數 PATH 中，請忽略此設置",
"digital-ide.prj.xilinx.IP.repo.path.title": "用戶設計的 Xilinx IP 庫路徑。配置此屬性後，插件將自動將路徑添加到 Vivado 的 IP 庫中。",
"digital-ide.prj.xilinx.BD.repo.path.title": "用戶定義的 Xilinx BD 文件放置路徑",
"digital-ide.prj.xsdk.install.path.title": "",
"digital-ide.function.doc.webview.backgroundImage.title": "背景圖片的 URL",
"digital-ide.function.doc.pdf.scale.title": "導出的 PDF 縮放比例",
"digital-ide.function.doc.pdf.printBackground.title": "是否打印背景",
"digital-ide.function.doc.pdf.landscape.title": "是否以橫向樣式導出 PDF",
"digital-ide.function.doc.pdf.format.title": "PDF 尺寸格式",
"digital-ide.function.doc.pdf.displayHeaderFooter.title": "在導出的 PDF 中顯示頁眉和頁腳",
"digital-ide.function.doc.pdf.browserPath.title": "Edge 或 Chrome 的絕對路徑，我們需要瀏覽器來渲染 PDF。預設路徑為 C:/Program Files (x86)/Microsoft/Edge/Application/msedge.exe",
"digital-ide.function.doc.pdf.margin.top.title": "導出的 PDF 的上邊距，單位 cm",
"digital-ide.function.doc.pdf.margin.right.title": "導出的 PDF 的右邊距，單位 cm",
"digital-ide.function.doc.pdf.margin.bottom.title": "導出的 PDF 的下邊距，單位 cm",
"digital-ide.function.doc.pdf.margin.left.title": "導出的 PDF 的左邊距，單位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "頁眉的 HTML 模板，如果 displayHeaderFooter 設置為 false，則此設置將被忽略",
"digital-ide.function.doc.pdf.footerTemplate.title": "頁腳的 HTML 模板，如果 displayHeaderFooter 設置為 false，則此設置將被忽略",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog 組件的安裝路徑，如果設置為空，則使用環境中的 iverilog 和 vvp 進行仿真。否則，將使用安裝路徑中的組件。",
"digital-ide.function.simulate.simulationHome.title": "仿真文件夾路徑，仿真期間的 .vvp 和其他文件將生成在此處",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave 軟件的啟動路徑的絕對路徑",
"digital-ide.function.simulate.xilinxLibPath.title": "仿真用 Xilinx 庫的路徑",
"digital-ide.function.simulate.runInTerminal.title": "在終端中運行仿真命令，而不是在輸出中運行",
"digital-ide.function.lsp.formatter.vlog.default.style.title": "選擇 Verilog 和 SystemVerilog 格式化器樣式。",
"digital-ide.function.lsp.formatter.vlog.default.args.title": "在此處添加 Verilog 格式化器參數（如 istyle）。",
"digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "關鍵字大小寫",
"digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "對齊註釋",
"digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "類型名稱大小寫",
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "縮進",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "觸發模塊的自動補全時，如果頂部 include 宏中沒有包含被例化模塊所在的文件，則自動在文件頂部添加 `include \"xxx.v\"",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "觸發模塊的自動補全時，在例化模塊上方自動生成 output 類型信號的申明",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "選擇編輯 Verilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "選擇編輯 SystemVerilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "選擇編輯 VHDL 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "選擇編輯 SystemVerilog 時的診斷器進行語法檢查",
"digital-ide.function.instantiation.addComment.title": "在進行實例化時添加註釋，如 // 端口, // 輸入, // 輸出，包括模塊調用的完成",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "在實例化發生時自動在作用域中聲明輸出類型的網絡。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting 的觸發字符",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
} }

BIN
resources/dide-lsp/static/xilinx/primitive.bin Normal file
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Binary file not shown.

36
script/command/make_title_token.py
View File

@ -11,6 +11,8 @@ LANG_PACKGE_FILES = {
'en': './package.nls.json', 'en': './package.nls.json',
'zh-cn': './package.nls.zh-cn.json', 'zh-cn': './package.nls.zh-cn.json',
'zh-tw': './package.nls.zh-tw.json', 'zh-tw': './package.nls.zh-tw.json',
'de': './package.nls.de.json',
'ja': './package.nls.ja.json'
} }
def generate_title_token(command_name: str) -> str: def generate_title_token(command_name: str) -> str:
@ -20,27 +22,43 @@ def generate_title_token(command_name: str) -> str:
title_token_name = [prj_name] + main_names + ['title'] title_token_name = [prj_name] + main_names + ['title']
return '.'.join(title_token_name) return '.'.join(title_token_name)
def merge_tokens(lang_package_path: str, tokens: List[str]): def merge_tokens(lang_package_path: str, tokens: List[str], token_values: List[str]):
config = read_json(lang_package_path) config = read_json(lang_package_path)
for token in tokens: for token, value in zip(tokens, token_values):
if token not in config: if token not in config:
config[token] = "" config[token] = value
write_json(lang_package_path, config) write_json(lang_package_path, config)
if __name__ == '__main__': if __name__ == '__main__':
# adjust main package # adjust main package
config = read_json(PACKAGE_FILE) config = read_json(PACKAGE_FILE)
commands = config['contributes']['commands']
token_names = [] token_names = []
token_values = []
for c_item in commands: # 获取 properties 中的 title
if 'command' in c_item: for property_name in config['contributes']['configuration']['properties']:
token_name = generate_title_token(c_item['command']) # property_name: digital-ide.welcome.show
property_body = config['contributes']['configuration']['properties'][property_name]
print(property_body)
token_name = generate_title_token(property_name)
token_names.append(token_name)
if 'description' in property_body and not property_body['description'].startswith('%'):
token_values.append(property_body['description'])
else:
token_values.append("")
property_body['description'] = '%' + token_name + '%'
# 获取 command 中的 title
for item in config['contributes']['commands']:
if 'command' in item:
token_name = generate_title_token(item['command'])
token_names.append(token_name) token_names.append(token_name)
c_item['title'] = '%' + token_name + '%' token_values.append("")
item['title'] = '%' + token_name + '%'
write_json(PACKAGE_FILE, config) write_json(PACKAGE_FILE, config)
# cover in lang package # cover in lang package
for name, lang_path in LANG_PACKGE_FILES.items(): for name, lang_path in LANG_PACKGE_FILES.items():
merge_tokens(lang_path, token_names) merge_tokens(lang_path, token_names, token_values)

8
snippets/sdc.json
View File

@ -1,10 +1,6 @@
{ {
"ILA_CORE": { "ILA_CORE": {
<<<<<<< HEAD
"prefix": "ila",
=======
"prefix": "create_ILA_CORE", "prefix": "create_ILA_CORE",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
"body": [ "body": [
"set_property C_CLK_INPUT_FREQ_HZ ${1:100000000} [get_debug_cores dbg_hub]", "set_property C_CLK_INPUT_FREQ_HZ ${1:100000000} [get_debug_cores dbg_hub]",
"set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]", "set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]",
@ -13,11 +9,7 @@
] ]
}, },
"Debug_CORE": { "Debug_CORE": {
<<<<<<< HEAD
"prefix": "debug",
=======
"prefix": "create_Debug_CORE", "prefix": "create_Debug_CORE",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
"body": [ "body": [
"create_debug_core u_ila_${1:0} ila", "create_debug_core u_ila_${1:0} ila",
"set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_$1]", "set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_$1]",

68
snippets/svlog.json
View File

@ -198,11 +198,7 @@
"reg [${1:32}:0] cnt$2 = 0;", "reg [${1:32}:0] cnt$2 = 0;",
"reg ${3:impulse};", "reg ${3:impulse};",
"parameter SET_TIME = $1'd$4;", "parameter SET_TIME = $1'd$4;",
<<<<<<< HEAD
"always@(posedge clcok) begin",
=======
"always@(posedge clk) begin", "always@(posedge clk) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if (cnt$2 == SET_TIME) begin", " if (cnt$2 == SET_TIME) begin",
" cnt$2 <= $1'd0;", " cnt$2 <= $1'd0;",
" $3 <= 1'd1;", " $3 <= 1'd1;",
@ -220,11 +216,7 @@
"body": [ "body": [
"reg [${1:3}:0] cnt$2 = 0;", "reg [${1:3}:0] cnt$2 = 0;",
"reg clk_div$2;", "reg clk_div$2;",
<<<<<<< HEAD
"always@(posedge ${3:clcok}) begin",
=======
"always@(posedge ${3:clk}) begin", "always@(posedge ${3:clk}) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if (cnt$2 == ${4:3}) begin", " if (cnt$2 == ${4:3}) begin",
" cnt$2 <= $1'd0;", " cnt$2 <= $1'd0;",
" clk_div$2 <= ~clk_div$2;", " clk_div$2 <= ~clk_div$2;",
@ -245,15 +237,9 @@
"wire gate$2_pose = gate$2 & ~gate$2_buf;", "wire gate$2_pose = gate$2 & ~gate$2_buf;",
"wire gate$2_nege = ~gate$2 & gate$2_buf;", "wire gate$2_nege = ~gate$2 & gate$2_buf;",
<<<<<<< HEAD
"always@(posedge clcok) begin",
" gate$2 <= ${1:signal};",
" gate$2_buf <= gate$2;",
=======
"always@(posedge clk) begin", "always@(posedge clk) begin",
" gate$2 <= ${1:signal};", " gate$2 <= ${1:signal};",
" gate$2_buf <= gate$2;", " gate$2_buf <= gate$2;",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
"end" "end"
] ]
}, },
@ -277,13 +263,8 @@
"body": [ "body": [
"reg rst_n_s1, rst_n_s2;", "reg rst_n_s1, rst_n_s2;",
"wire rst_n", "wire rst_n",
<<<<<<< HEAD
"always @ (posedge clcok or negedge rstn) begin",
" if (!rstn) begin",
=======
"always @ (posedge clk or negedge sys_rst_n) begin", "always @ (posedge clk or negedge sys_rst_n) begin",
" if (sys_rst_n) begin", " if (sys_rst_n) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" rst_n_s2 <= 1'b0;", " rst_n_s2 <= 1'b0;",
" rst_n_s1 <= 1'b0;", " rst_n_s1 <= 1'b0;",
" end", " end",
@ -293,11 +274,7 @@
"end", "end",
"assign rst_n = rst_n_s2;" "assign rst_n = rst_n_s2;"
], ],
<<<<<<< HEAD
"description" : "Asynchronous rstn synchronous release (intel device)"
=======
"description" : "Asynchronous sys_rst_n synchronous release (intel device)" "description" : "Asynchronous sys_rst_n synchronous release (intel device)"
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
}, },
"reset": { "reset": {
@ -305,13 +282,8 @@
"body": [ "body": [
"reg rst_s1, rst_s2;", "reg rst_s1, rst_s2;",
"wire rst", "wire rst",
<<<<<<< HEAD
"always @ (posedge clcok or posedge reset) begin",
" if (reset) begin",
=======
"always @ (posedge clk or posedge sys_rst) begin", "always @ (posedge clk or posedge sys_rst) begin",
" if (sys_rst) begin", " if (sys_rst) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" rst_s2 <= 1'b0;", " rst_s2 <= 1'b0;",
" rst_s1 <= 1'b0;", " rst_s1 <= 1'b0;",
" end", " end",
@ -321,19 +293,11 @@
"end", "end",
"assign rst = rst_s2;" "assign rst = rst_s2;"
], ],
<<<<<<< HEAD
"description" : "Asynchronous reset synchronous release (xilinx device)"
},
"initial sim": {
"prefix": "dump",
=======
"description" : "Asynchronous sys_rst synchronous release (xilinx device)" "description" : "Asynchronous sys_rst synchronous release (xilinx device)"
}, },
"initial sim": { "initial sim": {
"prefix": "inits", "prefix": "inits",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
"body": [ "body": [
"initial begin", "initial begin",
" \\$dumpfile(\"wave.vcd\");", " \\$dumpfile(\"wave.vcd\");",
@ -405,29 +369,17 @@
"alwaysposclk": { "alwaysposclk": {
"prefix": "alclk", "prefix": "alclk",
"body": [ "body": [
<<<<<<< HEAD
"always @(posedge clcok) begin",
" $1;",
"end"
],
"description": "always @(posedge clcok) directly"
=======
"always @(posedge clk) begin", "always @(posedge clk) begin",
" $1;", " $1;",
"end" "end"
], ],
"description": "always @(posedge clk) directly" "description": "always @(posedge clk) directly"
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
}, },
"alwayssyncrst": { "alwayssyncrst": {
"prefix": "alsync", "prefix": "alsync",
"body": [ "body": [
<<<<<<< HEAD
"always @(posedge clcok) begin",
=======
"always @(posedge clk) begin", "always @(posedge clk) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if(rst) begin", " if(rst) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
@ -442,11 +394,7 @@
"alwaysasyncrst": { "alwaysasyncrst": {
"prefix": "alasync", "prefix": "alasync",
"body": [ "body": [
<<<<<<< HEAD
"always @(posedge clcok or posedge rst) begin",
=======
"always @(posedge clk or posedge rst) begin", "always @(posedge clk or posedge rst) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if(rst) begin", " if(rst) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
@ -461,11 +409,7 @@
"alwayssyncrstn": { "alwayssyncrstn": {
"prefix": "alsyncn", "prefix": "alsyncn",
"body": [ "body": [
<<<<<<< HEAD
"always @(posedge clcok) begin",
=======
"always @(posedge clk) begin", "always @(posedge clk) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if(!rst_n) begin", " if(!rst_n) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
@ -480,11 +424,7 @@
"alwaysasyncrstn": { "alwaysasyncrstn": {
"prefix": "alasyncn", "prefix": "alasyncn",
"body": [ "body": [
<<<<<<< HEAD
"always @(posedge clcok or negedge rst_n) begin",
=======
"always @(posedge clk or negedge rst_n) begin", "always @(posedge clk or negedge rst_n) begin",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" if(!rst_n) begin", " if(!rst_n) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
@ -524,11 +464,7 @@
" parameter INPUT_WIDTH = ${2:12},", " parameter INPUT_WIDTH = ${2:12},",
" parameter OUTPUT_WIDTH = $2", " parameter OUTPUT_WIDTH = $2",
") (", ") (",
<<<<<<< HEAD
" input clcok,",
=======
" input clk,", " input clk,",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" input RST,", " input RST,",
" input [INPUT_WIDTH - 1 : 0] ${3:data_i},", " input [INPUT_WIDTH - 1 : 0] ${3:data_i},",
" output [OUTPUT_WIDTH - 1 : 0] ${4:data_o}", " output [OUTPUT_WIDTH - 1 : 0] ${4:data_o}",
@ -543,11 +479,7 @@
"prefix": "mod", "prefix": "mod",
"body": [ "body": [
"module ${1:moduleName} (", "module ${1:moduleName} (",
<<<<<<< HEAD
" input clcok,",
=======
" input clk,", " input clk,",
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
" input rst,", " input rst,",
" $2", " $2",
");", ");",

30
src/extension.ts
View File

@ -11,37 +11,41 @@ import * as lspClient from './function/lsp-client';
import { refreshArchTree } from './function/treeView'; import { refreshArchTree } from './function/treeView';
async function registerCommand(context: vscode.ExtensionContext, version: string) { async function registerCommand(context: vscode.ExtensionContext, packageJson: any) {
func.registerFunctionCommands(context); func.registerFunctionCommands(context);
func.registerLsp(context, version); func.registerLsp(context, packageJson.version);
func.registerToolCommands(context); func.registerToolCommands(context);
func.registerFSM(context); func.registerFSM(context);
func.registerNetlist(context); func.registerNetlist(context);
func.registerWaveViewer(context); func.registerWaveViewer(context);
} }
function getVersion(context: vscode.ExtensionContext): string { function readPackageJson(context: vscode.ExtensionContext): any | undefined {
let extensionPath = context.extensionPath; const extensionPath = context.extensionPath;
let packagePath = extensionPath + '/package.json'; const packagePath = extensionPath + '/package.json';
if (!fs.existsSync(packagePath)) { if (!fs.existsSync(packagePath)) {
return '0.4.0'; vscode.window.showErrorMessage("Digital IDE 安装目录已经被污染，请重新安装！");
return undefined;
} }
let packageMeta = fs.readFileSync(packagePath, { encoding: 'utf-8' }); const packageMeta = fs.readFileSync(packagePath, { encoding: 'utf-8' });
let packageJson = JSON.parse(packageMeta); return JSON.parse(packageMeta);
return packageJson.version;
} }
async function launch(context: vscode.ExtensionContext) { async function launch(context: vscode.ExtensionContext) {
const { t } = vscode.l10n; const { t } = vscode.l10n;
console.log(t('info.welcome.title')); console.log(t('info.welcome.title'));
console.log(t('info.welcome.join-qq-group') + ' https://qm.qq.com/q/1M655h3GsA'); console.log(t('info.welcome.join-qq-group') + ' https://qm.qq.com/q/1M655h3GsA');
const versionString = getVersion(context); const packageJson = readPackageJson(context);
if (packageJson === undefined) {
return;
}
await vscode.window.withProgress({ await vscode.window.withProgress({
location: vscode.ProgressLocation.Window, location: vscode.ProgressLocation.Window,
title: t('info.progress.register-command') title: t('info.progress.register-command')
}, async () => { }, async () => {
await registerCommand(context, versionString); await registerCommand(context, packageJson);
}); });
await vscode.window.withProgress({ await vscode.window.withProgress({
@ -59,7 +63,7 @@ async function launch(context: vscode.ExtensionContext) {
location: vscode.ProgressLocation.Window, location: vscode.ProgressLocation.Window,
title: "启动 Digital LSP 语言服务器" title: "启动 Digital LSP 语言服务器"
}, async () => { }, async () => {
await lspClient.activate(context, versionString); await lspClient.activate(context, packageJson);
}); });
await vscode.window.withProgress({ await vscode.window.withProgress({
@ -79,7 +83,7 @@ async function launch(context: vscode.ExtensionContext) {
}); });
MainOutput.report('Digital-IDE 已经启动，当前版本：' + versionString, ReportType.Launch); MainOutput.report('Digital-IDE 已经启动，当前版本：' + packageJson.version, ReportType.Launch);
console.log(hdlParam); console.log(hdlParam);
// show welcome information (if first install) // show welcome information (if first install)

1
src/function/dide-viewer/api.ts
View File

@ -60,6 +60,7 @@ export async function saveView(data: any, uri: vscode.Uri, panel: vscode.Webview
const originPayload = mergePayloadCache(originVcdViewFile, payload); const originPayload = mergePayloadCache(originVcdViewFile, payload);
const savePath = path.isAbsolute(originVcdViewFile) ? originVcdViewFile : path.join(rootPath, originVcdViewFile); const savePath = path.isAbsolute(originVcdViewFile) ? originVcdViewFile : path.join(rootPath, originVcdViewFile);
const buffer = BSON.serialize(originPayload); const buffer = BSON.serialize(originPayload);
fs.writeFileSync(savePath, buffer); fs.writeFileSync(savePath, buffer);
} catch (error) { } catch (error) {

10
src/function/dide-viewer/index.ts
View File

@ -226,7 +226,15 @@ function getViewLaunchFiles(context: vscode.ExtensionContext, uri: vscode.Uri, p
if (recoverJson.originVcdFile) { if (recoverJson.originVcdFile) {
const vcdPath = recoverJson.originVcdFile; const vcdPath = recoverJson.originVcdFile;
if (!fs.existsSync(vcdPath)) { if (!fs.existsSync(vcdPath)) {
return new Error(t('error.vcd-viewer.unexist-direct-vcd-file') + ':' + vcdPath); // 如果不存在，去相同目录下寻找同名 vcd
const sameFolderVcdPath = entryPath.slice(0, -5) + '.vcd';
if (fs.existsSync(sameFolderVcdPath)) {
const vcd = panel.webview.asWebviewUri(vscode.Uri.file(sameFolderVcdPath)).toString();
const view = panel.webview.asWebviewUri(uri).toString();
return { vcd, view, wasm, vcdjs, worker, root };
} else {
return new Error(t('error.vcd-viewer.unexist-direct-vcd-file') + ':' + vcdPath);
}
} }
const vcd = panel.webview.asWebviewUri(vscode.Uri.file(recoverJson.originVcdFile)).toString(); const vcd = panel.webview.asWebviewUri(vscode.Uri.file(recoverJson.originVcdFile)).toString();
const view = panel.webview.asWebviewUri(uri).toString(); const view = panel.webview.asWebviewUri(uri).toString();

47
src/function/lsp-client/config.ts Normal file
View File

@ -0,0 +1,47 @@
import * as vscode from 'vscode';
import { LanguageClient } from 'vscode-languageclient/node';
import { UpdateConfigurationType } from '../../global/lsp';
interface ConfigItem {
name: string,
value: CommonValue
}
type CommonValue = string | boolean | number;
export function registerConfigurationUpdater(client: LanguageClient, packageJson: any) {
const lspConfigures: ConfigItem[] = [];
const properties = packageJson?.contributes?.configuration?.properties;
const dideConfig = vscode.workspace.getConfiguration('digital-ide');
for (const propertyName of Object.keys(properties) || []) {
if (propertyName.includes('function.lsp')) {
const section = propertyName.slice(12);
let value = dideConfig.get<CommonValue>(section, '');
lspConfigures.push({ name: propertyName, value });
}
}
// 初始化，配置参数全部同步到后端
client.sendRequest(UpdateConfigurationType, {
configs: lspConfigures,
configType: 'lsp'
});
vscode.workspace.onDidChangeConfiguration(async event => {
const changeConfigs: ConfigItem[] = [];
const dideConfig = vscode.workspace.getConfiguration('');
for (const config of lspConfigures) {
if (event.affectsConfiguration(config.name)) {
const lastestValue = dideConfig.get<CommonValue>(config.name, '');
changeConfigs.push({ name: config.name, value: lastestValue });
}
}
if (changeConfigs.length > 0) {
await client.sendRequest(UpdateConfigurationType, {
configs: changeConfigs,
configType: 'lsp'
});
}
});
}

11
src/function/lsp-client/index.ts
View File

@ -15,6 +15,7 @@ import { IProgress, LspClient, opeParam } from '../../global';
import axios, { AxiosResponse } from "axios"; import axios, { AxiosResponse } from "axios";
import { chooseBestDownloadSource, getGiteeDownloadLink, getGithubDownloadLink, getPlatformPlatformSignature } from "./cdn"; import { chooseBestDownloadSource, getGiteeDownloadLink, getGithubDownloadLink, getPlatformPlatformSignature } from "./cdn";
import { hdlDir, hdlPath } from "../../hdlFs"; import { hdlDir, hdlPath } from "../../hdlFs";
import { registerConfigurationUpdater } from "./config";
function getLspServerExecutionName() { function getLspServerExecutionName() {
const osname = platform(); const osname = platform();
@ -141,7 +142,8 @@ export async function downloadLsp(context: vscode.ExtensionContext, version: str
return false; return false;
} }
export async function activate(context: vscode.ExtensionContext, version: string) { export async function activate(context: vscode.ExtensionContext, packageJson: any) {
const version = packageJson.version;
await checkAndDownload(context, version); await checkAndDownload(context, version);
const lspServerName = getLspServerExecutionName(); const lspServerName = getLspServerExecutionName();
@ -174,8 +176,6 @@ export async function activate(context: vscode.ExtensionContext, version: string
let extensionPath = hdlPath.toSlash(context.extensionPath); let extensionPath = hdlPath.toSlash(context.extensionPath);
vscode.window.showInformationMessage("toolchain: " + opeParam.prjInfo.toolChain);
let clientOptions: LanguageClientOptions = { let clientOptions: LanguageClientOptions = {
documentSelector: [ documentSelector: [
{ {
@ -212,8 +212,13 @@ export async function activate(context: vscode.ExtensionContext, version: string
LspClient.DigitalIDE = client; LspClient.DigitalIDE = client;
await client.start(); await client.start();
registerConfigurationUpdater(client, packageJson);
} }
export function deactivate(): Thenable<void> | undefined { export function deactivate(): Thenable<void> | undefined {
if (!LspClient.DigitalIDE) { if (!LspClient.DigitalIDE) {
return undefined; return undefined;

12
src/function/lsp/completion/vhdl.ts
View File

@ -80,8 +80,8 @@ import { hdlPath } from '../../../hdlFs';
// const suggestModules: vscode.CompletionItem[] = []; // const suggestModules: vscode.CompletionItem[] = [];
// const lspVhdlConfig = vscode.workspace.getConfiguration('digital-ide.function.lsp.completion.vhdl'); // const lspVhdlConfig = vscode.workspace.getConfiguration('digital-ide.function.lsp.completion.vhdl');
// const autoAddInclude: boolean = lspVhdlConfig.get('autoAddInclude', true); // const auto-add-include: boolean = lspVhdlConfig.get('auto-add-include', true);
// const completeWholeInstante: boolean = lspVhdlConfig.get('completeWholeInstante', true); // const auto-add-output-declaration: boolean = lspVhdlConfig.get('auto-add-output-declaration', true);
// const includePaths = new Set<AbsPath>(); // const includePaths = new Set<AbsPath>();
// let lastIncludeLine = 0; // let lastIncludeLine = 0;
@ -94,9 +94,9 @@ import { hdlPath } from '../../../hdlFs';
// const insertRange = new vscode.Range(insertPosition, insertPosition); // const insertRange = new vscode.Range(insertPosition, insertPosition);
// const fileFolder = hdlPath.resolve(filePath, '..'); // const fileFolder = hdlPath.resolve(filePath, '..');
// // used only when completeWholeInstante is true // // used only when auto-add-output-declaration is true
// let completePrefix = ''; // let completePrefix = '';
// if (completeWholeInstante) { // if (auto-add-output-declaration) {
// const wordRange = document.getWordRangeAtPosition(position); // const wordRange = document.getWordRangeAtPosition(position);
// const countStart = wordRange ? wordRange.start.character : position.character; // const countStart = wordRange ? wordRange.start.character : position.character;
// const spaceNumber = Math.floor(countStart / 4) * 4; // const spaceNumber = Math.floor(countStart / 4) * 4;
@ -110,7 +110,7 @@ import { hdlPath } from '../../../hdlFs';
// // const clItem = new vscode.CompletionItem(module.name, vscode.CompletionItemKind.Class); // // const clItem = new vscode.CompletionItem(module.name, vscode.CompletionItemKind.Class);
// // // feature 1 : auto add include path if there's no corresponding include path // // // feature 1 : auto add include path if there's no corresponding include path
// // if (autoAddInclude && !includePaths.has(module.path)) { // // if (auto-add-include && !includePaths.has(module.path)) {
// // const relPath: RelPath = hdlPath.relative(fileFolder, module.path); // // const relPath: RelPath = hdlPath.relative(fileFolder, module.path);
// // const includeString = '`include "' + relPath + '"\n'; // // const includeString = '`include "' + relPath + '"\n';
// // const textEdit = new vscode.TextEdit(insertRange, includeString); // // const textEdit = new vscode.TextEdit(insertRange, includeString);
@ -118,7 +118,7 @@ import { hdlPath } from '../../../hdlFs';
// // } // // }
// // // feature 2 : auto complete instance // // // feature 2 : auto complete instance
// // if (completeWholeInstante) { // // if (auto-add-output-declaration) {
// // const snippetString = instanceVhdlCode(module, '', true); // // const snippetString = instanceVhdlCode(module, '', true);
// // clItem.insertText = new vscode.SnippetString(snippetString); // // clItem.insertText = new vscode.SnippetString(snippetString);
// // } // // }

12
src/function/lsp/completion/vlog.ts
View File

@ -289,8 +289,8 @@ import { instanceVlogCode } from '../../sim/instance';
// const suggestModules: vscode.CompletionItem[] = []; // const suggestModules: vscode.CompletionItem[] = [];
// const lspVlogConfig = vscode.workspace.getConfiguration('digital-ide.function.lsp.completion.vlog'); // const lspVlogConfig = vscode.workspace.getConfiguration('digital-ide.function.lsp.completion.vlog');
// const autoAddInclude: boolean = lspVlogConfig.get('autoAddInclude', true); // const auto-add-include: boolean = lspVlogConfig.get('auto-add-include', true);
// const completeWholeInstante: boolean = lspVlogConfig.get('completeWholeInstante', true); // const auto-add-output-declaration: boolean = lspVlogConfig.get('auto-add-output-declaration', true);
// const includePaths = new Set<AbsPath>(); // const includePaths = new Set<AbsPath>();
// let lastIncludeLine = 0; // let lastIncludeLine = 0;
@ -303,9 +303,9 @@ import { instanceVlogCode } from '../../sim/instance';
// const insertRange = new vscode.Range(insertPosition, insertPosition); // const insertRange = new vscode.Range(insertPosition, insertPosition);
// const fileFolder = hdlPath.resolve(filePath, '..'); // const fileFolder = hdlPath.resolve(filePath, '..');
// // used only when completeWholeInstante is true // // used only when auto-add-output-declaration is true
// let completePrefix = ''; // let completePrefix = '';
// if (completeWholeInstante) { // if (auto-add-output-declaration) {
// const wordRange = document.getWordRangeAtPosition(position); // const wordRange = document.getWordRangeAtPosition(position);
// const countStart = wordRange ? wordRange.start.character : position.character; // const countStart = wordRange ? wordRange.start.character : position.character;
// const spaceNumber = Math.floor(countStart / 4) * 4; // const spaceNumber = Math.floor(countStart / 4) * 4;
@ -319,7 +319,7 @@ import { instanceVlogCode } from '../../sim/instance';
// const clItem = new vscode.CompletionItem(module.name, vscode.CompletionItemKind.Class); // const clItem = new vscode.CompletionItem(module.name, vscode.CompletionItemKind.Class);
// // feature 1 : auto add include path if there's no corresponding include path // // feature 1 : auto add include path if there's no corresponding include path
// if (autoAddInclude && !includePaths.has(module.path)) { // if (auto-add-include && !includePaths.has(module.path)) {
// const relPath: RelPath = hdlPath.relative(fileFolder, module.path); // const relPath: RelPath = hdlPath.relative(fileFolder, module.path);
// const includeString = '`include "' + relPath + '"\n'; // const includeString = '`include "' + relPath + '"\n';
// const textEdit = new vscode.TextEdit(insertRange, includeString); // const textEdit = new vscode.TextEdit(insertRange, includeString);
@ -327,7 +327,7 @@ import { instanceVlogCode } from '../../sim/instance';
// } // }
// // feature 2 : auto complete instance // // feature 2 : auto complete instance
// if (completeWholeInstante) { // if (auto-add-output-declaration) {
// const snippetString = instanceVlogCode(module, '', true); // const snippetString = instanceVlogCode(module, '', true);
// clItem.insertText = new vscode.SnippetString(snippetString); // clItem.insertText = new vscode.SnippetString(snippetString);
// } // }

29
src/function/lsp/util/index.ts
View File

@ -225,22 +225,22 @@ function matchInstance(singleWord: string, module: HdlModule): AllowNull<HdlInst
} }
function filterInstanceByPosition(position: vscode.Position, symbols: RawSymbol[], module: HdlModule): AllowNull<HdlInstance> { // function filterInstanceByPosition(position: vscode.Position, symbols: RawSymbol[], module: HdlModule): AllowNull<HdlInstance> {
if (!symbols) { // if (!symbols) {
return null; // return null;
} // }
for (const symbol of symbols) { // for (const symbol of symbols) {
const inst = module.getInstance(symbol.name); // const inst = module.getInstance(symbol.name);
if (positionAfterEqual(position, symbol.range.start) && // if (positionAfterEqual(position, symbol.range.start) &&
positionAfterEqual(symbol.range.end, position) && // positionAfterEqual(symbol.range.end, position) &&
inst) { // inst) {
return inst; // return inst;
} // }
} // }
return null; // return null;
} // }
async function getInstPortByPosition(inst: HdlInstance, position: vscode.Position, singleWord: string): Promise<AllowNull<HdlModulePort>> { async function getInstPortByPosition(inst: HdlInstance, position: vscode.Position, singleWord: string): Promise<AllowNull<HdlModulePort>> {
@ -468,7 +468,6 @@ export {
transformRange, transformRange,
locateVlogSymbol, locateVlogSymbol,
locateVhdlSymbol, locateVhdlSymbol,
filterInstanceByPosition,
isPositionInput, isPositionInput,
isInComment, isInComment,
matchInclude, matchInclude,

7
src/function/tool.ts
View File

@ -25,6 +25,7 @@ const PPY_REPLACE: Record<string, string> = {
PRJ_NAME: 'prjName', PRJ_NAME: 'prjName',
ARCH: 'arch', ARCH: 'arch',
SOC: 'soc', SOC: 'soc',
SOC_MODE: 'soc',
enableShowlog: 'enableShowLog', enableShowlog: 'enableShowLog',
Device: 'device' Device: 'device'
}; };
@ -66,6 +67,12 @@ async function transformOldPpy() {
delete oldPpyContent[oldName]; delete oldPpyContent[oldName];
} }
// 老版本的是 SOC_MODE.soc，新版本需要变成 soc.core
if (oldPpyContent.soc && oldPpyContent.soc.soc !== undefined) {
oldPpyContent.soc.core = oldPpyContent.soc.soc;
delete oldPpyContent.soc['soc'];
}
hdlFile.writeJSON(propertyJsonPath, oldPpyContent); hdlFile.writeJSON(propertyJsonPath, oldPpyContent);
} else { } else {

2
src/function/treeView/index.ts
View File

@ -31,7 +31,7 @@ async function openFileAtPosition(uri: vscode.Uri, range?: Range) {
function openFileByUri(path: string, range: Range, element: ModuleDataItem) { function openFileByUri(path: string, range: Range, element: ModuleDataItem) {
const { t } = vscode.l10n; const { t } = vscode.l10n;
if (range === undefined) { if (range === undefined) {
vscode.window.showErrorMessage(`${path} not support jump yet`); // vscode.window.showErrorMessage(`${path} not support jump yet`);
return; return;
} }

6
src/function/treeView/tree.ts
View File

@ -109,6 +109,7 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
public getTreeItem(element: ModuleDataItem): vscode.TreeItem | Thenable<vscode.TreeItem> { public getTreeItem(element: ModuleDataItem): vscode.TreeItem | Thenable<vscode.TreeItem> {
const { t } = vscode.l10n;
let itemName = element.name; let itemName = element.name;
if (itemModes.has(element.icon)) { if (itemModes.has(element.icon)) {
itemName = `${element.type}(${itemName})`; itemName = `${element.type}(${itemName})`;
@ -135,7 +136,7 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
// set tooltip // set tooltip
treeItem.tooltip = element.path; treeItem.tooltip = element.path;
if (!treeItem.tooltip) { if (!treeItem.tooltip) {
treeItem.tooltip = "can't find the module of this instance"; treeItem.tooltip = t('info.treeview.item.tooltip');
} }
// set iconPath // set iconPath
@ -243,7 +244,6 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
if (targetModule) { if (targetModule) {
for (const instance of targetModule.getAllInstances()) { for (const instance of targetModule.getAllInstances()) {
// 所有的例化模块都定向到它的定义文件上 // 所有的例化模块都定向到它的定义文件上
const item: ModuleDataItem = { const item: ModuleDataItem = {
icon: 'file', icon: 'file',
type: instance.name, type: instance.name,
@ -287,6 +287,8 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
if (item.doFastFileType === 'ip') { if (item.doFastFileType === 'ip') {
return 'ip'; return 'ip';
} else if (item.doFastFileType === 'primitives') {
return 'celllib';
} }
if (hdlPath.exist(item.path)) { if (hdlPath.exist(item.path)) {

24
src/global/lsp.ts
View File

@ -13,6 +13,8 @@ export const LspClient: IDigitalIDELspClient = {
VhdlClient: undefined VhdlClient: undefined
}; };
/** /**
* @description 构造请求参数 * @description 构造请求参数
* RequestType<P, R, E, RO> * RequestType<P, R, E, RO>
@ -21,10 +23,11 @@ export const LspClient: IDigitalIDELspClient = {
* E: 请求的错误类型。 * E: 请求的错误类型。
* RO: 请求的可选参数类型。 * RO: 请求的可选参数类型。
*/ */
export const CustomRequestType = new RequestType<void, number, void>('custom/request'); export const CustomRequestType = new RequestType<void, number, void>('custom/request');
export const CustomParamRequestType = new RequestType<ICommonParam, number, void>('custom/paramRequest'); export const CustomParamRequestType = new RequestType<ICommonParam, number, void>('custom/paramRequest');
export const DoFastRequestType = new RequestType<IDoFastParam, Fast, void>('api/fast'); export const DoFastRequestType = new RequestType<IDoFastParam, Fast, void>('api/fast');
export const UpdateFastRequestType = new RequestType<IDoFastParam, Fast, void>('api/update-fast'); export const UpdateConfigurationType = new RequestType<IUpdateConfigurationParam, void, void>('api/update-fast');
export const DoPrimitivesJudgeType = new RequestType<IDoPrimitivesJudgeParam, boolean, void>('api/do-primitives-judge');
export interface ITextDocumentItem { export interface ITextDocumentItem {
uri: vscode.Uri, uri: vscode.Uri,
@ -37,6 +40,19 @@ export interface ICommonParam {
param: string param: string
} }
export interface IUpdateConfigurationParam {
configs: {
name: string,
value: string | boolean | number
}[],
configType: string
}
export interface IDoPrimitivesJudgeParam {
name: string
}
export type DoFastFileType = 'common' | 'ip' | 'primitives'; export type DoFastFileType = 'common' | 'ip' | 'primitives';
export type DoFastToolChainType = 'xilinx' | 'efinity' | 'intel'; export type DoFastToolChainType = 'xilinx' | 'efinity' | 'intel';

60
src/hdlParser/core.ts
View File

@ -7,9 +7,10 @@ import { MainOutput, ReportType } from '../global/outputChannel';
import * as common from './common'; import * as common from './common';
import { hdlFile, hdlPath } from '../hdlFs'; import { hdlFile, hdlPath } from '../hdlFs';
import { HdlSymbol } from './util'; import { defaultMacro, defaultRange, doPrimitivesJudgeApi, HdlSymbol } from './util';
import { DoFastFileType } from '../global/lsp'; import { DoFastFileType } from '../global/lsp';
class HdlParam { class HdlParam {
private readonly topModules : Set<HdlModule> = new Set<HdlModule>(); private readonly topModules : Set<HdlModule> = new Set<HdlModule>();
private readonly srcTopModules : Set<HdlModule> = new Set<HdlModule>(); private readonly srcTopModules : Set<HdlModule> = new Set<HdlModule>();
@ -481,6 +482,17 @@ class HdlInstance {
if (this.isSameSource()) { if (this.isSameSource()) {
this.module?.addLocalReferedInstance(this); this.module?.addLocalReferedInstance(this);
} }
} else {
doPrimitivesJudgeApi(instModName).then(isPrimitive => {
if (isPrimitive) {
// 构造 fake hdlfile
if (opeParam.prjInfo.toolChain === 'xilinx') {
const fakeModule = new HdlModule(
XilinxPrimitivesHdlFile, instModName, defaultRange, [], [], []);
this.module = fakeModule;
}
}
});
} }
} }
@ -526,7 +538,8 @@ class HdlModule {
range: common.Range; range: common.Range;
params: common.HdlModuleParam[]; params: common.HdlModuleParam[];
ports: common.HdlModulePort[]; ports: common.HdlModulePort[];
private rawInstances: common.RawHdlInstance[] | undefined; public rawInstances: common.RawHdlInstance[] | undefined;
// TODO: 此处无法采用 instance name 作为主键，是因为 verilog 允许 instance name 同名出现
private nameToInstances: Map<string, HdlInstance>; private nameToInstances: Map<string, HdlInstance>;
private unhandleInstances: Set<HdlInstance>; private unhandleInstances: Set<HdlInstance>;
private globalRefers: Set<HdlInstance>; private globalRefers: Set<HdlInstance>;
@ -575,8 +588,12 @@ class HdlModule {
return this.file.languageId; return this.file.languageId;
} }
public getInstance(name: string): HdlInstance | undefined { public makeInstanceKey(instanceName: string, moduleName: string): string {
return this.nameToInstances.get(name); return instanceName + '-' + moduleName;
}
public getInstance(name: string, moduleName: string): HdlInstance | undefined {
return this.nameToInstances.get(this.makeInstanceKey(name, moduleName));
} }
public getAllInstances(): HdlInstance[] { public getAllInstances(): HdlInstance[] {
@ -609,7 +626,8 @@ class HdlModule {
this.addUnhandleInstance(hdlInstance); this.addUnhandleInstance(hdlInstance);
} }
if (this.nameToInstances) { if (this.nameToInstances) {
this.nameToInstances.set(rawHdlInstance.name, hdlInstance); const key = this.makeInstanceKey(rawHdlInstance.name, rawHdlInstance.type);
this.nameToInstances.set(key, hdlInstance);
} }
return hdlInstance; return hdlInstance;
} else if (this.languageId === HdlLangID.Vhdl) { } else if (this.languageId === HdlLangID.Vhdl) {
@ -623,7 +641,8 @@ class HdlModule {
this); this);
hdlInstance.module = this; hdlInstance.module = this;
if (this.nameToInstances) { if (this.nameToInstances) {
this.nameToInstances.set(rawHdlInstance.name, hdlInstance); const key = this.makeInstanceKey(rawHdlInstance.name, rawHdlInstance.type);
this.nameToInstances.set(key, hdlInstance);
} }
return hdlInstance; return hdlInstance;
} else { } else {
@ -644,8 +663,9 @@ class HdlModule {
public makeNameToInstances() { public makeNameToInstances() {
if (this.rawInstances !== undefined) { if (this.rawInstances !== undefined) {
this.nameToInstances.clear(); this.nameToInstances.clear();
for (const inst of this.rawInstances) { for (const inst of this.rawInstances) {
this.createHdlInstance(inst); const instance = this.createHdlInstance(inst);
} }
// this.rawInstances = undefined; // this.rawInstances = undefined;
} else { } else {
@ -654,8 +674,8 @@ class HdlModule {
} }
} }
public deleteInstanceByName(name: string) { public deleteInstanceByName(instanceName: string, moduleName: string) {
const inst = this.getInstance(name); const inst = this.getInstance(instanceName, moduleName);
this.deleteInstance(inst); this.deleteInstance(inst);
} }
@ -664,7 +684,8 @@ class HdlModule {
this.deleteUnhandleInstance(inst); this.deleteUnhandleInstance(inst);
hdlParam.deleteUnhandleInstance(inst); hdlParam.deleteUnhandleInstance(inst);
if (this.nameToInstances) { if (this.nameToInstances) {
this.nameToInstances.delete(inst.name); const key = this.makeInstanceKey(inst.name, inst.type);
this.nameToInstances.delete(key);
} }
// delete reference from instance's instMod // delete reference from instance's instMod
const instMod = inst.module; const instMod = inst.module;
@ -819,25 +840,27 @@ class HdlModule {
this.params = newModule.params; this.params = newModule.params;
this.range = newModule.range; this.range = newModule.range;
// compare and make change to instance // compare and make change to instance
const uncheckedInstanceNames = new Set<string>(); const uncheckedInstanceNames = new Map<string, HdlInstance>();
for (const inst of this.getAllInstances()) { for (const inst of this.getAllInstances()) {
uncheckedInstanceNames.add(inst.name); const key = this.makeInstanceKey(inst.name, inst.type);
uncheckedInstanceNames.set(key, inst);
} }
for (const newInst of newModule.instances) { for (const newInst of newModule.instances) {
if (uncheckedInstanceNames.has(newInst.name)) { const newInstKey = this.makeInstanceKey(newInst.name, newInst.type);
if (uncheckedInstanceNames.has(newInstKey)) {
// match exist instance, compare and update // match exist instance, compare and update
const originalInstance = this.getInstance(newInst.name); const originalInstance = this.getInstance(newInst.name, newInst.type);
originalInstance?.update(newInst); originalInstance?.update(newInst);
uncheckedInstanceNames.delete(newInst.name); uncheckedInstanceNames.delete(newInstKey);
} else { } else {
// unknown instance, create it // unknown instance, create it
this.createHdlInstance(newInst); this.createHdlInstance(newInst);
} }
} }
// delete Instance that not visited // delete Instance that not visited
for (const instName of uncheckedInstanceNames) { for (const inst of uncheckedInstanceNames.values()) {
this.deleteInstanceByName(instName); this.deleteInstanceByName(inst.name, inst.type);
} }
} }
}; };
@ -945,6 +968,9 @@ class HdlFile {
} }
} }
export const XilinxPrimitivesHdlFile = new HdlFile('xilinx-primitives', HdlLangID.Verilog, defaultMacro, [], 'primitives');
export { export {
hdlParam, hdlParam,

38
src/hdlParser/util.ts
View File

@ -1,12 +1,11 @@
import * as vscode from 'vscode'; import * as vscode from 'vscode';
import { hdlFile } from '../hdlFs'; import { hdlFile } from '../hdlFs';
import { HdlLangID } from '../global/enum';
import { AbsPath, LspClient, opeParam } from '../global'; import { AbsPath, LspClient, opeParam } from '../global';
import { DoFastRequestType, ITextDocumentItem, CustomParamRequestType, UpdateFastRequestType, DoFastFileType, DoFastToolChainType } from '../global/lsp'; import { DoFastRequestType, DoFastFileType, DoFastToolChainType, DoPrimitivesJudgeType } from '../global/lsp';
import { Fast, RawHdlModule } from './common'; import { Fast, Macro, Range } from './common';
async function doFastApi(path: string, fileType: DoFastFileType): Promise<Fast | undefined> { export async function doFastApi(path: string, fileType: DoFastFileType): Promise<Fast | undefined> {
try { try {
const client = LspClient.DigitalIDE; const client = LspClient.DigitalIDE;
const langID = hdlFile.getLanguageId(path); const langID = hdlFile.getLanguageId(path);
@ -23,8 +22,23 @@ async function doFastApi(path: string, fileType: DoFastFileType): Promise<Fast |
} }
} }
export async function doPrimitivesJudgeApi(primitiveName: string): Promise<boolean> {
try {
const client = LspClient.DigitalIDE;
if (client) {
const response = await client.sendRequest(DoPrimitivesJudgeType, { name: primitiveName });
return response;
}
} catch (error) {
console.error("error happen when run judgePrimitivesApi, " + error);
console.error("error query primitive name: " + primitiveName);
return false;
}
return false;
}
namespace HdlSymbol {
export namespace HdlSymbol {
/** /**
* @description 计算出模块级的信息 * @description 计算出模块级的信息
* @param path 文件绝对路径 * @param path 文件绝对路径
@ -35,8 +49,14 @@ namespace HdlSymbol {
} }
} }
export const defaultRange: Range = {
start: { line: 0, character: 0 },
export { end: { line: 0, character: 0 }
HdlSymbol, };
export const defaultMacro: Macro = {
errors: [],
includes: [],
defines: [],
invalid: []
}; };