From 170dcfb3b6ee54b28ec3feda248f6b7f0866b18e Mon Sep 17 00:00:00 2001
From: Kirigaya <1193466151@qq.com>
Date: Tue, 12 Dec 2023 08:21:48 +0800
Subject: [PATCH] fix bug#24 | fix bug#25 | fix bug#12

---
 src/function/lsp/hover/vlog.ts   |  9 +++++++--
 src/function/lsp/util/feature.ts | 16 +++++-----------
 src/function/lsp/util/index.ts   |  1 -
 syntaxes/verilog.tmLanguage.json |  6 ++----
 4 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/function/lsp/hover/vlog.ts b/src/function/lsp/hover/vlog.ts
index 51dd730..5e840a6 100644
--- a/src/function/lsp/hover/vlog.ts
+++ b/src/function/lsp/hover/vlog.ts
@@ -5,7 +5,7 @@ import { hdlParam } from '../../../hdlParser';
 import { All } from '../../../../resources/hdlParser';
 import { vlogKeyword } from '../util/keyword';
 import * as util from '../util';
-import { MainOutput, ReportType } from '../../../global';
+import { LspOutput, MainOutput, ReportType } from '../../../global';
 import { HdlLangID } from '../../../global/enum';
 import { hdlSymbolStorage } from '../core';
 
@@ -148,7 +148,9 @@ class VlogHoverProvider implements vscode.HoverProvider {
         
         // match params
         const paramResult = util.matchParams(targetWord, currentModule);
+
         if (paramResult) {
+            LspOutput.report('<vlog hover> get param info ' + paramResult?.name, ReportType.Info);
             const paramComment = await util.searchCommentAround(filePath, paramResult.range);
             const paramDesc = util.makeParamDesc(paramResult);
             content.appendCodeblock(paramDesc, HdlLangID.Verilog);
@@ -160,9 +162,12 @@ class VlogHoverProvider implements vscode.HoverProvider {
 
         // match ports        
         const portResult = util.matchPorts(targetWord, currentModule);
-        if (portResult) {            
+
+        if (portResult) {
+            LspOutput.report('<vlog hover> get port info ' + portResult?.name, ReportType.Info);
             const portComment = await util.searchCommentAround(filePath, portResult.range);
             const portDesc = util.makePortDesc(portResult);
+            
             content.appendCodeblock(portDesc, HdlLangID.Verilog);            
             if (portComment) {
                 content.appendCodeblock(portComment, HdlLangID.Verilog);
diff --git a/src/function/lsp/util/feature.ts b/src/function/lsp/util/feature.ts
index 1332aba..8fd5eb1 100644
--- a/src/function/lsp/util/feature.ts
+++ b/src/function/lsp/util/feature.ts
@@ -131,8 +131,9 @@ async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, no
 
     let content = '';
     let is_b_comment = false;
-    let line = range.start.line;
+    let line = range.start.line + 1;
     const firstLine = range.start.line - 1;
+    console.log('enter getFullSymbolInfo');
     
     while (line) {
         line --;
@@ -160,20 +161,13 @@ async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, no
         }
 
         // 判断该行是否存在行注释
-        let l_comment_index = content.indexOf(l_comment_symbol);
+        let l_comment_index = content.indexOf(l_comment_symbol);    
         
         if (l_comment_index >= 0) {
             let before_l_comment = content.slice(0, l_comment_index);
-            // before_l_comment = del_comments(before_l_comment, b_comment_end_index);            
             if (before_l_comment.match(nonblank)) {
-                // 如果去除块注释之后还有字符则认为该注释不属于所要的
-                if (line === firstLine) {
-                    // let b_comment_last_index = content.lastIndexOf('*/');
-                    // b_comment_last_index = (b_comment_last_index == -1) ? 0 : (b_comment_last_index + 2);
-                    // comments.push(content.slice(b_comment_last_index, l_comment_index) + '\n');
-                    comments.push(content.slice(l_comment_index, content.length) + '\n');
-                    continue;
-                }
+                // TODO : check again if bug takes place 
+                comments.push(content.slice(l_comment_index, content.length) + '\n');
                 break; 
             }
 
diff --git a/src/function/lsp/util/index.ts b/src/function/lsp/util/index.ts
index 5a27b97..84e3634 100644
--- a/src/function/lsp/util/index.ts
+++ b/src/function/lsp/util/index.ts
@@ -329,7 +329,6 @@ function matchParams(singleWord: string, module: HdlModule): AllowNull<HdlModule
 
 
 function makePortDesc(port: HdlModulePort): string {
-
     const portDescArray = [];
     portDescArray.push(port.type);    
     if (port.netType) {
diff --git a/syntaxes/verilog.tmLanguage.json b/syntaxes/verilog.tmLanguage.json
index 617faa2..1fadc70 100644
--- a/syntaxes/verilog.tmLanguage.json
+++ b/syntaxes/verilog.tmLanguage.json
@@ -170,7 +170,7 @@
         "keywords": {
             "patterns": [
                 {
-                    "match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|output|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
+                    "match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
                     "name": "keyword.other.verilog"
                 },
                 {
@@ -239,9 +239,7 @@
                         {
                             "include": "#strings"
                         },
-                        {
-                            "include": "#instantiation_patterns"
-                        },
+ 
                         {
                             "include": "#operators"
                         },