From 190eb358ed69af66acd9d38279747f3ccebe13d8 Mon Sep 17 00:00:00 2001 From: Kirigaya <1193466151@qq.com> Date: Fri, 14 Jul 2023 20:16:48 +0800 Subject: [PATCH] #add translator --- package.json | 47 +++++++++++++++++++++++-- resources/translator/index.js | 64 ++++++++++++++++++++++++----------- src/test/user/src/hello.v | 16 +++++++++ src/test/user/src/hello.vhd | 14 ++++++++ 4 files changed, 119 insertions(+), 22 deletions(-) create mode 100644 src/test/user/src/hello.v create mode 100644 src/test/user/src/hello.vhd diff --git a/package.json b/package.json index 2631970..0f291e8 100644 --- a/package.json +++ b/package.json @@ -419,7 +419,11 @@ { "command": "digital-ide.vhdl2vlog", "title": "%digital-ide.vhdl2vlog.title%", - "category": "Digital-IDE" + "category": "Digital-IDE", + "icon": { + "light": "images/svg/light/translate.svg", + "dark": "images/svg/dark/translate.svg" + } } ], "menus": { @@ -477,8 +481,45 @@ "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "digital-ide.hdlDoc.showWebview", "group": "navigation@4" - } - ] + }, + { + "when": "resourceLangId == vhdl", + "command": "digital-ide.vhdl2vlog", + "group": "navigation@5" + } + ], + "editor/context": [ + { + "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", + "command": "digital-ide.pl.setSrcTop", + "group": "navigation@1" + }, + { + "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", + "command": "digital-ide.pl.setSimTop", + "group": "navigation@2" + }, + { + "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", + "command": "digital-ide.tool.instance", + "group": "navigation@3" + }, + { + "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", + "command": "digital-ide.tool.testbench", + "group": "navigation@4" + }, + { + "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", + "command": "digital-ide.tool.icarus.simulateFile", + "group": "navigation@5" + }, + { + "when": "resourceLangId == vhdl", + "command": "digital-ide.vhdl2vlog", + "group": "navigation@8" + } + ] }, "viewsContainers": { "activitybar": [ diff --git a/resources/translator/index.js b/resources/translator/index.js index 02f8896..643c368 100644 --- a/resources/translator/index.js +++ b/resources/translator/index.js @@ -1,7 +1,21 @@ /* eslint-disable @typescript-eslint/naming-convention */ const fs = require('fs'); const vscode = require('vscode'); +const fspath = require('path'); const vhd2vl = require("./vhd2vlog"); +const formatter = require('../formatter'); + +/** + * + * @param {string} path + * @return {string} + */ +function getFileName(path) { + const fileName = fspath.basename(path); + const names = fileName.split('.'); + names.pop(); + return names.join('.'); +} /** * @@ -10,30 +24,42 @@ const vhd2vl = require("./vhd2vlog"); */ async function vhdl2vlog(uri) { const path = uri.fsPath.replace(/\\/g, '/'); + const fileName = getFileName(path); + const Module = await vhd2vl(); - const content = fs.readFileSync(path, "utf-8"); + let content = fs.readFileSync(path, "utf-8"); const status = Module.ccall('vhdlParse', '', ['string'], [content]); if (!status) { content = Module.ccall('getVlog', 'string', ['string'], []); - vscode.window.showSaveDialog({ - filters: { - verilog: ["v", "V", "vh", "vl"], // 文件类型过滤 - }, - }).then(fileInfos => { - let path_full = fileInfos === null || fileInfos === void 0 ? void 0 : fileInfos.path; - if (path_full !== undefined) { - if (path_full[0] === '/' && require('os').platform() === 'win32') { - path_full = path_full.substring(1); - } - fs.writeFileSync(path_full, content, "utf-8"); - vscode.window.showInformationMessage("translate successfully"); - const options = { - preview: false, - viewColumn: vscode.ViewColumn.Two - }; - vscode.window.showTextDocument(vscode.Uri.file(path_full), options); + // format + content = await formatter.hdlFormatterProvider.vlogFormatter.format_from_code(content); + + const folderPath = fspath.dirname(path); + const defaultSaveUri = new vscode.Uri('file', '', folderPath + '/' + fileName + '.v', '', ''); + console.log(defaultSaveUri); + const vscodeDialogConfig = { + title: 'save the verilog code', + defaultUri: defaultSaveUri, + verilog: ["v", "V", "vh", "vl"] + }; + const fileInfos = await vscode.window.showSaveDialog(vscodeDialogConfig); + + if (fileInfos && fileInfos.path) { + let savePath = fileInfos.path; + console.log(savePath); + + if (savePath[0] === '/' && require('os').platform() === 'win32') { + savePath = savePath.substring(1); } - }); + fs.writeFileSync(savePath, content, "utf-8"); + vscode.window.showInformationMessage("translate successfully"); + const options = { + preview: false, + viewColumn: vscode.ViewColumn.Two + }; + vscode.window.showTextDocument(vscode.Uri.file(savePath), options); + } + } else { const error = Module.ccall('getErr', 'string', ['string'], []); vscode.window.showErrorMessage(error); diff --git a/src/test/user/src/hello.v b/src/test/user/src/hello.v new file mode 100644 index 0000000..c96ec27 --- /dev/null +++ b/src/test/user/src/hello.v @@ -0,0 +1,16 @@ +// VHDL code for a 2-to-1 multiplexer + +module mux2to1( + input wire a, + input wire b, + input wire sel, + output wire outp + ); + + + + + + assign outp = sel == 1'b0 ? a : b; + +endmodule diff --git a/src/test/user/src/hello.vhd b/src/test/user/src/hello.vhd new file mode 100644 index 0000000..f40f549 --- /dev/null +++ b/src/test/user/src/hello.vhd @@ -0,0 +1,14 @@ +-- VHDL code for a 2-to-1 multiplexer +library IEEE; +use IEEE.std_logic_1164.all; + +entity mux2to1 is + port(a, b : in std_logic; + sel : in std_logic; + outp : out std_logic); +end mux2to1; + +architecture behavioral of mux2to1 is +begin + outp <= a when sel = '0' else b; +end behavioral; \ No newline at end of file