diff --git a/.gitignore b/.gitignore index ffccfbd..995ed11 100644 --- a/.gitignore +++ b/.gitignore @@ -16,4 +16,4 @@ resources/hdlParser/parser.js resources/hdlParser/parser.wasm resources/dide-viewer/view/* resources/dide-lsp/server/* -resources/dide-lsp/static/* \ No newline at end of file +resources/dide-lsp/static/* diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_float_types.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_float_types.vhdl new file mode 100644 index 0000000..073cab4 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_float_types.vhdl @@ -0,0 +1,61 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Fixed Point and Floating Point types package +-- +-- Library : This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- +-- Purpose : Definitions for use in fixed point and floating point +-- arithmetic packages +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package fixed_float_types is + + -- Types used for generics of fixed_generic_pkg + + type fixed_round_style_type is (fixed_round, fixed_truncate); + + type fixed_overflow_style_type is (fixed_saturate, fixed_wrap); + + -- Type used for generics of float_generic_pkg + + -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD, + -- and FE_TOWARDZERO floating point rounding macros. + + type round_type is (round_nearest, -- Default, nearest LSB '0' + round_inf, -- Round toward positive infinity + round_neginf, -- Round toward negative infinity + round_zero); -- Round toward zero (truncate) + +end package fixed_float_types; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg-body.vhdl new file mode 100644 index 0000000..84e4f20 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg-body.vhdl @@ -0,0 +1,6368 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Fixed-point package (Generic package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary fixed point arithmetic +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library IEEE; +use IEEE.MATH_REAL.all; + +package body fixed_generic_pkg is + -- Author David Bishop (dbishop@vhdl.org) + -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton + -- null array constants + constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0'); + constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0'); + constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); + + -- This differed constant will tell you if the package body is synthesizable + -- or implemented as real numbers, set to "true" if synthesizable. + constant fixedsynth_or_real : BOOLEAN := true; + + -- Special version of "minimum" to do some boundary checking without errors + function mins (l, r : INTEGER) + return INTEGER is + begin -- function mins + if (L = INTEGER'low or R = INTEGER'low) then + return 0; -- error condition, silent + end if; + return minimum (L, R); + end function mins; + + -- Special version of "minimum" to do some boundary checking with errors + function mine (l, r : INTEGER) + return INTEGER is + begin -- function mine + if (L = INTEGER'low or R = INTEGER'low) then + report fixed_generic_pkg'instance_name + & " Unbounded number passed, was a literal used?" + severity error; + return 0; + end if; + return minimum (L, R); + end function mine; + + -- The following functions are used only internally. Every function + -- calls "cleanvec" either directly or indirectly. + -- purpose: Fixes "downto" problem and resolves meta states + function cleanvec ( + arg : UNRESOLVED_sfixed) -- input + return UNRESOLVED_sfixed + is + constant left_index : INTEGER := maximum(arg'left, arg'right); + constant right_index : INTEGER := mins(arg'left, arg'right); + variable result : UNRESOLVED_sfixed (arg'range); + begin -- function cleanvec + assert not (arg'ascending and (arg'low /= INTEGER'low)) + report fixed_generic_pkg'instance_name + & " Vector passed using a ""to"" range, expected is ""downto""" + severity error; + return arg; + end function cleanvec; + + -- purpose: Fixes "downto" problem and resolves meta states + function cleanvec ( + arg : UNRESOLVED_ufixed) -- input + return UNRESOLVED_ufixed + is + constant left_index : INTEGER := maximum(arg'left, arg'right); + constant right_index : INTEGER := mins(arg'left, arg'right); + variable result : UNRESOLVED_ufixed (arg'range); + begin -- function cleanvec + assert not (arg'ascending and (arg'low /= INTEGER'low)) + report fixed_generic_pkg'instance_name + & " Vector passed using a ""to"" range, expected is ""downto""" + severity error; + return arg; + end function cleanvec; + + -- Type convert a "unsigned" into a "ufixed", used internally + function to_fixed ( + arg : UNRESOLVED_UNSIGNED; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (left_index downto right_index); + begin -- function to_fixed + result := UNRESOLVED_ufixed(arg); + return result; + end function to_fixed; + + -- Type convert a "signed" into an "sfixed", used internally + function to_fixed ( + arg : UNRESOLVED_SIGNED; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (left_index downto right_index); + begin -- function to_fixed + result := UNRESOLVED_sfixed(arg); + return result; + end function to_fixed; + + -- Type convert a "ufixed" into an "unsigned", used internally + function to_uns ( + arg : UNRESOLVED_ufixed) -- fp vector + return UNRESOLVED_UNSIGNED + is + subtype t is UNRESOLVED_UNSIGNED(arg'high - arg'low downto 0); + variable slv : t; + begin -- function to_uns + slv := t(arg); + return slv; + end function to_uns; + + -- Type convert an "sfixed" into a "signed", used internally + function to_s ( + arg : UNRESOLVED_sfixed) -- fp vector + return UNRESOLVED_SIGNED + is + subtype t is UNRESOLVED_SIGNED(arg'high - arg'low downto 0); + variable slv : t; + begin -- function to_s + slv := t(arg); + return slv; + end function to_s; + + -- adds 1 to the LSB of the number + procedure round_up (arg : in UNRESOLVED_ufixed; + result : out UNRESOLVED_ufixed; + overflowx : out BOOLEAN) is + variable arguns, resuns : UNRESOLVED_UNSIGNED (arg'high-arg'low+1 downto 0) + := (others => '0'); + begin -- round_up + arguns (arguns'high-1 downto 0) := to_uns (arg); + resuns := arguns + 1; + result := to_fixed(resuns(arg'high-arg'low + downto 0), arg'high, arg'low); + overflowx := (resuns(resuns'high) = '1'); + end procedure round_up; + + -- adds 1 to the LSB of the number + procedure round_up (arg : in UNRESOLVED_sfixed; + result : out UNRESOLVED_sfixed; + overflowx : out BOOLEAN) is + variable args, ress : UNRESOLVED_SIGNED (arg'high-arg'low+1 downto 0); + begin -- round_up + args (args'high-1 downto 0) := to_s (arg); + args(args'high) := arg(arg'high); -- sign extend + ress := args + 1; + result := to_fixed(ress (ress'high-1 + downto 0), arg'high, arg'low); + overflowx := ((arg(arg'high) /= ress(ress'high-1)) + and (or (STD_ULOGIC_VECTOR(ress)) /= '0')); + end procedure round_up; + + -- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up + -- when the remainder is > 0.5. If the remainder IS 0.5 then if the + -- bottom bit is a "1" it is rounded, otherwise it remains the same. + function round_fixed (arg : UNRESOLVED_ufixed; + remainder : UNRESOLVED_ufixed; + overflow_style : fixed_overflow_style_type := fixed_overflow_style) + return UNRESOLVED_ufixed + is + variable rounds : BOOLEAN; + variable round_overflow : BOOLEAN; + variable result : UNRESOLVED_ufixed (arg'range); + begin + rounds := false; + if (remainder'length > 1) then + if (remainder (remainder'high) = '1') then + rounds := (arg(arg'low) = '1') + or (or (to_sulv(remainder(remainder'high-1 downto + remainder'low))) = '1'); + end if; + else + rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); + end if; + if rounds then + round_up(arg => arg, + result => result, + overflowx => round_overflow); + else + result := arg; + end if; + if (overflow_style = fixed_saturate) and round_overflow then + result := saturate (result'high, result'low); + end if; + return result; + end function round_fixed; + + -- Rounding case statement + function round_fixed (arg : UNRESOLVED_sfixed; + remainder : UNRESOLVED_sfixed; + overflow_style : fixed_overflow_style_type := fixed_overflow_style) + return UNRESOLVED_sfixed + is + variable rounds : BOOLEAN; + variable round_overflow : BOOLEAN; + variable result : UNRESOLVED_sfixed (arg'range); + begin + rounds := false; + if (remainder'length > 1) then + if (remainder (remainder'high) = '1') then + rounds := (arg(arg'low) = '1') + or (or (to_sulv(remainder(remainder'high-1 downto + remainder'low))) = '1'); + end if; + else + rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); + end if; + if rounds then + round_up(arg => arg, + result => result, + overflowx => round_overflow); + else + result := arg; + end if; + if round_overflow then + if (overflow_style = fixed_saturate) then + if arg(arg'high) = '0' then + result := saturate (result'high, result'low); + else + result := not saturate (result'high, result'low); + end if; + -- Sign bit not fixed when wrapping + end if; + end if; + return result; + end function round_fixed; + + -- converts an sfixed into a ufixed. The output is the same length as the + -- input, because abs("1000") = "1000" = 8. + function to_ufixed ( + arg : UNRESOLVED_sfixed) + return UNRESOLVED_ufixed + is + constant left_index : INTEGER := arg'high; + constant right_index : INTEGER := mine(arg'low, arg'low); + variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index); + variable result : UNRESOLVED_ufixed(left_index downto right_index); + begin + if arg'length < 1 then + return NAUF; + end if; + xarg := abs(arg); + result := UNRESOLVED_ufixed (xarg (left_index downto right_index)); + return result; + end function to_ufixed; + +----------------------------------------------------------------------------- +-- Visible functions +----------------------------------------------------------------------------- + + -- Conversion functions. These are needed for synthesis where typically + -- the only input and output type is a std_logic_vector. + function to_sulv ( + arg : UNRESOLVED_ufixed) -- fixed point vector + return STD_ULOGIC_VECTOR + is + variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); + begin + if arg'length < 1 then + return NSLV; + end if; + result := STD_ULOGIC_VECTOR (arg); + return result; + end function to_sulv; + + function to_sulv ( + arg : UNRESOLVED_sfixed) -- fixed point vector + return STD_ULOGIC_VECTOR + is + variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); + begin + if arg'length < 1 then + return NSLV; + end if; + result := STD_ULOGIC_VECTOR (arg); + return result; + end function to_sulv; + + function to_slv ( + arg : UNRESOLVED_ufixed) -- fixed point vector + return STD_LOGIC_VECTOR is + begin + return to_sulv(arg); + end function to_slv; + + function to_slv ( + arg : UNRESOLVED_sfixed) -- fixed point vector + return STD_LOGIC_VECTOR is + begin + return to_sulv(arg); + end function to_slv; + + function to_ufixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return unresolved_ufixed + is + variable result : UNRESOLVED_ufixed (left_index downto right_index); + begin + if (arg'length < 1 or right_index > left_index) then + return NAUF; + end if; + if (arg'length /= result'length) then + report fixed_generic_pkg'instance_name & "TO_UFIXED(SLV) " + & "Vector lengths do not match. Input length is " + & INTEGER'image(arg'length) & " and output will be " + & INTEGER'image(result'length) & " wide." + severity error; + return NAUF; + else + result := to_fixed (arg => UNRESOLVED_UNSIGNED(arg), + left_index => left_index, + right_index => right_index); + return result; + end if; + end function to_ufixed; + + function to_sfixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return unresolved_sfixed + is + variable result : UNRESOLVED_sfixed (left_index downto right_index); + begin + if (arg'length < 1 or right_index > left_index) then + return NASF; + end if; + if (arg'length /= result'length) then + report fixed_generic_pkg'instance_name & "TO_SFIXED(SLV) " + & "Vector lengths do not match. Input length is " + & INTEGER'image(arg'length) & " and output will be " + & INTEGER'image(result'length) & " wide." + severity error; + return NASF; + else + result := to_fixed (arg => UNRESOLVED_SIGNED(arg), + left_index => left_index, + right_index => right_index); + return result; + end if; + end function to_sfixed; + + -- Two's complement number, Grows the vector by 1 bit. + -- because "abs (1000.000) = 01000.000" or abs(-16) = 16. + function "abs" ( + arg : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed + is + constant left_index : INTEGER := arg'high; + constant right_index : INTEGER := mine(arg'low, arg'low); + variable ressns : UNRESOLVED_SIGNED (arg'length downto 0); + variable result : UNRESOLVED_sfixed (left_index+1 downto right_index); + begin + if (arg'length < 1 or result'length < 1) then + return NASF; + end if; + ressns (arg'length-1 downto 0) := to_s (cleanvec (arg)); + ressns (arg'length) := ressns (arg'length-1); -- expand sign bit + result := to_fixed (abs(ressns), left_index+1, right_index); + return result; + end function "abs"; + + -- also grows the vector by 1 bit. + function "-" ( + arg : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed + is + constant left_index : INTEGER := arg'high+1; + constant right_index : INTEGER := mine(arg'low, arg'low); + variable ressns : UNRESOLVED_SIGNED (arg'length downto 0); + variable result : UNRESOLVED_sfixed (left_index downto right_index); + begin + if (arg'length < 1 or result'length < 1) then + return NASF; + end if; + ressns (arg'length-1 downto 0) := to_s (cleanvec(arg)); + ressns (arg'length) := ressns (arg'length-1); -- expand sign bit + result := to_fixed (-ressns, left_index, right_index); + return result; + end function "-"; + + -- Addition + function "+" ( + l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) = + return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d)) + is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mine(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable result : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + begin + if (l'length < 1 or r'length < 1 or result'length < 1) then + return NAUF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + result_slv := lslv + rslv; + result := to_fixed(result_slv, left_index, right_index); + return result; + end function "+"; + + function "+" ( + l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) = + return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d)) + is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mine(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable result : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0); + variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0); + begin + if (l'length < 1 or r'length < 1 or result'length < 1) then + return NASF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + result_slv := lslv + rslv; + result := to_fixed(result_slv, left_index, right_index); + return result; + end function "+"; + + -- Subtraction + function "-" ( + l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) = + return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d)) + is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mine(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable result : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + begin + if (l'length < 1 or r'length < 1 or result'length < 1) then + return NAUF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + result_slv := lslv - rslv; + result := to_fixed(result_slv, left_index, right_index); + return result; + end function "-"; + + function "-" ( + l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) = + return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d)) + is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mine(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable result : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0); + variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0); + begin + if (l'length < 1 or r'length < 1 or result'length < 1) then + return NASF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + result_slv := lslv - rslv; + result := to_fixed(result_slv, left_index, right_index); + return result; + end function "-"; + + function "*" ( + l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) = + return UNRESOLVED_ufixed -- ufixed(a+c+1 downto b+d) + is + variable lslv : UNRESOLVED_UNSIGNED (l'length-1 downto 0); + variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (r'length+l'length-1 downto 0); + variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto + mine(l'low, l'low) + mine(r'low, r'low)); + begin + if (l'length < 1 or r'length < 1 or + result'length /= result_slv'length) then + return NAUF; + end if; + lslv := to_uns (cleanvec(l)); + rslv := to_uns (cleanvec(r)); + result_slv := lslv * rslv; + result := to_fixed (result_slv, result'high, result'low); + return result; + end function "*"; + + function "*" ( + l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) = + return UNRESOLVED_sfixed -- sfixed(a+c+1 downto b+d) + is + variable lslv : UNRESOLVED_SIGNED (l'length-1 downto 0); + variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0); + variable result_slv : UNRESOLVED_SIGNED (r'length+l'length-1 downto 0); + variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto + mine(l'low, l'low) + mine(r'low, r'low)); + begin + if (l'length < 1 or r'length < 1 or + result'length /= result_slv'length) then + return NASF; + end if; + lslv := to_s (cleanvec(l)); + rslv := to_s (cleanvec(r)); + result_slv := lslv * rslv; + result := to_fixed (result_slv, result'high, result'low); + return result; + end function "*"; + + function "/" ( + l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) = + return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1) + begin + return divide (l, r); + end function "/"; + + function "/" ( + l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) = + return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c) + begin + return divide (l, r); + end function "/"; + + -- This version of divide gives the user more control + -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) + function divide ( + l, r : UNRESOLVED_ufixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto + mine (l'low, l'low) - r'high -1); + variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits); + variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1); + variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1 or + mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then + return NAUF; + end if; + lresize := resize (arg => l, + left_index => lresize'high, + right_index => lresize'low, + overflow_style => fixed_wrap, -- vector only grows + round_style => fixed_truncate); + lslv := to_uns (cleanvec (lresize)); + rslv := to_uns (cleanvec (r)); + if (rslv = 0) then + report fixed_generic_pkg'instance_name + & "DIVIDE(ufixed) Division by zero" severity error; + result := saturate (result'high, result'low); -- saturate + else + result_slv := lslv / rslv; + dresult := to_fixed (result_slv, dresult'high, dresult'low); + result := resize (arg => dresult, + left_index => result'high, + right_index => result'low, + overflow_style => fixed_wrap, -- overflow impossible + round_style => round_style); + end if; + return result; + end function divide; + + -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) + function divide ( + l, r : UNRESOLVED_sfixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto + mine (l'low, l'low) - r'high); + variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits); + variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1); + variable lslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0); + variable result_slv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1 or + mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then + return NASF; + end if; + lresize := resize (arg => l, + left_index => lresize'high, + right_index => lresize'low, + overflow_style => fixed_wrap, -- vector only grows + round_style => fixed_truncate); + lslv := to_s (cleanvec (lresize)); + rslv := to_s (cleanvec (r)); + if (rslv = 0) then + report fixed_generic_pkg'instance_name + & "DIVIDE(sfixed) Division by zero" severity error; + result := saturate (result'high, result'low); + else + result_slv := lslv / rslv; + dresult := to_fixed (result_slv, dresult'high, dresult'low); + result := resize (arg => dresult, + left_index => result'high, + right_index => result'low, + overflow_style => fixed_wrap, -- overflow impossible + round_style => round_style); + end if; + return result; + end function divide; + + -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) + function reciprocal ( + arg : UNRESOLVED_ufixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed + is + constant one : UNRESOLVED_ufixed (0 downto 0) := "1"; + begin + return divide (l => one, + r => arg, + round_style => round_style, + guard_bits => guard_bits); + end function reciprocal; + + -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) + function reciprocal ( + arg : UNRESOLVED_sfixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed + is + constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit. + variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high); + begin + if (arg'length < 1 or resultx'length < 1) then + return NASF; + else + resultx := divide (l => one, + r => arg, + round_style => round_style, + guard_bits => guard_bits); + return resultx (resultx'high-1 downto resultx'low); -- remove extra bit + end if; + end function reciprocal; + + -- ufixed (a downto b) rem ufixed (c downto d) + -- = ufixed (min(a,c) downto min(b,d)) + function "rem" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return remainder (l, r); + end function "rem"; + + -- remainder + -- sfixed (a downto b) rem sfixed (c downto d) + -- = sfixed (min(a,c) downto min(b,d)) + function "rem" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return remainder (l, r); + end function "rem"; + + -- ufixed (a downto b) rem ufixed (c downto d) + -- = ufixed (min(a,c) downto min(b,d)) + function remainder ( + l, r : UNRESOLVED_ufixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto + mine(l'low, r'low)); + variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto + mins(r'low, r'low)-guard_bits); + variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits); + variable dresult : UNRESOLVED_ufixed (rresize'range); + variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + variable rslv : UNRESOLVED_UNSIGNED (rresize'length-1 downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (rslv'range); + begin + if (l'length < 1 or r'length < 1 or + mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then + return NAUF; + end if; + lresize := resize (arg => l, + left_index => lresize'high, + right_index => lresize'low, + overflow_style => fixed_wrap, -- vector only grows + round_style => fixed_truncate); + lslv := to_uns (lresize); + rresize := resize (arg => r, + left_index => rresize'high, + right_index => rresize'low, + overflow_style => fixed_wrap, -- vector only grows + round_style => fixed_truncate); + rslv := to_uns (rresize); + if (rslv = 0) then + report fixed_generic_pkg'instance_name + & "remainder(ufixed) Division by zero" severity error; + result := saturate (result'high, result'low); -- saturate + else + if (r'low <= l'high) then + result_slv := lslv rem rslv; + dresult := to_fixed (result_slv, dresult'high, dresult'low); + result := resize (arg => dresult, + left_index => result'high, + right_index => result'low, + overflow_style => fixed_wrap, -- can't overflow + round_style => round_style); + end if; + if l'low < r'low then + result(mins(r'low-1, l'high) downto l'low) := + cleanvec(l(mins(r'low-1, l'high) downto l'low)); + end if; + end if; + return result; + end function remainder; + + -- remainder + -- sfixed (a downto b) rem sfixed (c downto d) + -- = sfixed (min(a,c) downto min(b,d)) + function remainder ( + l, r : UNRESOLVED_sfixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed + is + variable l_abs : UNRESOLVED_ufixed (l'range); + variable r_abs : UNRESOLVED_ufixed (r'range); + variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto + mine(r'low, l'low)); + variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto + mins(r'low, l'low)); + begin + if (l'length < 1 or r'length < 1 or + mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then + return NASF; + end if; + l_abs := to_ufixed (l); + r_abs := to_ufixed (r); + result := UNRESOLVED_sfixed (remainder ( + l => l_abs, + r => r_abs, + round_style => round_style)); + neg_result := -result; + if l(l'high) = '1' then + result := neg_result(result'range); + end if; + return result; + end function remainder; + + -- modulo + -- ufixed (a downto b) mod ufixed (c downto d) + -- = ufixed (min(a,c) downto min(b, d)) + function "mod" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return modulo (l, r); + end function "mod"; + + -- sfixed (a downto b) mod sfixed (c downto d) + -- = sfixed (c downto min(b, d)) + function "mod" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return modulo(l, r); + end function "mod"; + + -- modulo + -- ufixed (a downto b) mod ufixed (c downto d) + -- = ufixed (min(a,c) downto min(b, d)) + function modulo ( + l, r : UNRESOLVED_ufixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed is + begin + return remainder(l => l, + r => r, + round_style => round_style, + guard_bits => guard_bits); + end function modulo; + + -- sfixed (a downto b) mod sfixed (c downto d) + -- = sfixed (c downto min(b, d)) + function modulo ( + l, r : UNRESOLVED_sfixed; -- fixed point input + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed + is + variable l_abs : UNRESOLVED_ufixed (l'range); + variable r_abs : UNRESOLVED_ufixed (r'range); + variable result : UNRESOLVED_sfixed (r'high downto + mine(r'low, l'low)); + variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto + mins(r'low, l'low)); + variable dresult_not_zero : BOOLEAN; + begin + if (l'length < 1 or r'length < 1 or + mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then + return NASF; + end if; + l_abs := to_ufixed (l); + r_abs := to_ufixed (r); + dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs, + r => r_abs, + round_style => round_style)); + if (to_s(dresult) = 0) then + dresult_not_zero := false; + else + dresult_not_zero := true; + end if; + if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0' + and dresult_not_zero then + result := resize (arg => r - dresult, + left_index => result'high, + right_index => result'low, + overflow_style => overflow_style, + round_style => round_style); + elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then + result := resize (arg => -dresult, + left_index => result'high, + right_index => result'low, + overflow_style => overflow_style, + round_style => round_style); + elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1' + and dresult_not_zero then + result := resize (arg => dresult + r, + left_index => result'high, + right_index => result'low, + overflow_style => overflow_style, + round_style => round_style); + else + result := resize (arg => dresult, + left_index => result'high, + right_index => result'low, + overflow_style => overflow_style, + round_style => round_style); + end if; + return result; + end function modulo; + + -- Procedure for those who need an "accumulator" function + procedure add_carry ( + L, R : in UNRESOLVED_ufixed; + c_in : in STD_ULOGIC; + result : out UNRESOLVED_ufixed; + c_out : out STD_ULOGIC) is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index + downto 0); + variable cx : UNRESOLVED_UNSIGNED (0 downto 0); -- Carry in + begin + if (l'length < 1 or r'length < 1) then + result := NAUF; + c_out := '0'; + else + cx (0) := c_in; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + result_slv := lslv + rslv + cx; + c_out := result_slv(left_index); + result := to_fixed(result_slv (left_index-right_index-1 downto 0), + left_index-1, right_index); + end if; + end procedure add_carry; + + procedure add_carry ( + L, R : in UNRESOLVED_sfixed; + c_in : in STD_ULOGIC; + result : out UNRESOLVED_sfixed; + c_out : out STD_ULOGIC) is + constant left_index : INTEGER := maximum(l'high, r'high)+1; + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index + downto 0); + variable result_slv : UNRESOLVED_SIGNED (left_index-right_index + downto 0); + variable cx : UNRESOLVED_SIGNED (1 downto 0); -- Carry in + begin + if (l'length < 1 or r'length < 1) then + result := NASF; + c_out := '0'; + else + cx (1) := '0'; + cx (0) := c_in; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + result_slv := lslv + rslv + cx; + c_out := result_slv(left_index); + result := to_fixed(result_slv (left_index-right_index-1 downto 0), + left_index-1, right_index); + end if; + end procedure add_carry; + + -- Scales the result by a power of 2. Width of input = width of output with + -- the decimal point moved. + function scalb (y : UNRESOLVED_ufixed; N : INTEGER) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N); + begin + if y'length < 1 then + return NAUF; + else + result := y; + return result; + end if; + end function scalb; + + function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) + return UNRESOLVED_ufixed is + begin + return scalb (y => y, + N => to_integer(N)); + end function scalb; + + function scalb (y : UNRESOLVED_sfixed; N : INTEGER) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N); + begin + if y'length < 1 then + return NASF; + else + result := y; + return result; + end if; + end function scalb; + + function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) + return UNRESOLVED_sfixed is + begin + return scalb (y => y, + N => to_integer(N)); + end function scalb; + + function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is + begin + if to_X01(arg(arg'high)) = '1' then + return true; + else + return false; + end if; + end function Is_Negative; + + function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) + return INTEGER is + begin + for_loop : for i in arg'reverse_range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'high+1; -- return out of bounds 'high + end function find_rightmost; + + function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) + return INTEGER is + begin + for_loop : for i in arg'range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'low-1; -- return out of bounds 'low + end function find_leftmost; + + function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) + return INTEGER is + begin + for_loop : for i in arg'reverse_range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'high+1; -- return out of bounds 'high + end function find_rightmost; + + function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) + return INTEGER is + begin + for_loop : for i in arg'range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'low-1; -- return out of bounds 'low + end function find_leftmost; + + function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + argslv := argslv sll COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sll"; + + function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + argslv := argslv srl COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "srl"; + + function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + argslv := argslv rol COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "rol"; + + function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + argslv := argslv ror COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "ror"; + + function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + -- Arithmetic shift on an unsigned is a logical shift + argslv := argslv sll COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sla"; + + function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed + is + variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_ufixed (arg'range); + begin + argslv := to_uns (arg); + -- Arithmetic shift on an unsigned is a logical shift + argslv := argslv srl COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sra"; + + function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + argslv := argslv sll COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sll"; + + function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + argslv := argslv srl COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "srl"; + + function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + argslv := argslv rol COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "rol"; + + function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + argslv := argslv ror COUNT; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "ror"; + + function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + if COUNT > 0 then + -- Arithmetic shift left on a 2's complement number is a logic shift + argslv := argslv sll COUNT; + else + argslv := argslv sra -COUNT; + end if; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sla"; + + function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed + is + variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0); + variable result : UNRESOLVED_sfixed (arg'range); + begin + argslv := to_s (arg); + if COUNT > 0 then + argslv := argslv sra COUNT; + else + -- Arithmetic shift left on a 2's complement number is a logic shift + argslv := argslv sll -COUNT; + end if; + result := to_fixed (argslv, result'high, result'low); + return result; + end function "sra"; + + -- Because some people want the older functions. + function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) + return UNRESOLVED_ufixed is + begin + if (ARG'length < 1) then + return NAUF; + end if; + return ARG sla COUNT; + end function SHIFT_LEFT; + + function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) + return UNRESOLVED_ufixed is + begin + if (ARG'length < 1) then + return NAUF; + end if; + return ARG sra COUNT; + end function SHIFT_RIGHT; + + function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) + return UNRESOLVED_sfixed is + begin + if (ARG'length < 1) then + return NASF; + end if; + return ARG sla COUNT; + end function SHIFT_LEFT; + + function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) + return UNRESOLVED_sfixed is + begin + if (ARG'length < 1) then + return NASF; + end if; + return ARG sra COUNT; + end function SHIFT_RIGHT; + + ---------------------------------------------------------------------------- + -- logical functions + ---------------------------------------------------------------------------- + function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + RESULT := not to_sulv(L); + return to_ufixed(RESULT, L'high, L'low); + end function "not"; + + function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) and to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """and"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "and"; + + function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) or to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """or"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "or"; + + function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nand to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """nand"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "nand"; + + function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """nor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "nor"; + + function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """xor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "xor"; + + function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xnor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """xnor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_ufixed(RESULT, L'high, L'low); + end function "xnor"; + + function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + RESULT := not to_sulv(L); + return to_sfixed(RESULT, L'high, L'low); + end function "not"; + + function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) and to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """and"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "and"; + + function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) or to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """or"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "or"; + + function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nand to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """nand"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "nand"; + + function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """nor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "nor"; + + function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """xor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "xor"; + + function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xnor to_sulv(R); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """xnor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_sfixed(RESULT, L'high, L'low); + end function "xnor"; + + -- Vector and std_ulogic functions, same as functions in numeric_std + function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L and R(i); + end loop; + return result; + end function "and"; + + function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) and R; + end loop; + return result; + end function "and"; + + function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L or R(i); + end loop; + return result; + end function "or"; + + function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) or R; + end loop; + return result; + end function "or"; + + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L nand R(i); + end loop; + return result; + end function "nand"; + + function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) nand R; + end loop; + return result; + end function "nand"; + + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L nor R(i); + end loop; + return result; + end function "nor"; + + function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) nor R; + end loop; + return result; + end function "nor"; + + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L xor R(i); + end loop; + return result; + end function "xor"; + + function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) xor R; + end loop; + return result; + end function "xor"; + + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (R'range); + begin + for i in result'range loop + result(i) := L xnor R(i); + end loop; + return result; + end function "xnor"; + + function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (L'range); + begin + for i in result'range loop + result(i) := L(i) xnor R; + end loop; + return result; + end function "xnor"; + + function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L and R(i); + end loop; + return result; + end function "and"; + + function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) and R; + end loop; + return result; + end function "and"; + + function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L or R(i); + end loop; + return result; + end function "or"; + + function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) or R; + end loop; + return result; + end function "or"; + + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L nand R(i); + end loop; + return result; + end function "nand"; + + function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) nand R; + end loop; + return result; + end function "nand"; + + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L nor R(i); + end loop; + return result; + end function "nor"; + + function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) nor R; + end loop; + return result; + end function "nor"; + + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L xor R(i); + end loop; + return result; + end function "xor"; + + function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) xor R; + end loop; + return result; + end function "xor"; + + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (R'range); + begin + for i in result'range loop + result(i) := L xnor R(i); + end loop; + return result; + end function "xnor"; + + function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (L'range); + begin + for i in result'range loop + result(i) := L(i) xnor R; + end loop; + return result; + end function "xnor"; + + -- Reduction operators + function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return and to_sulv(l); + end function "and"; + + function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return nand to_sulv(l); + end function "nand"; + + function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return or to_sulv(l); + end function "or"; + + function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return nor to_sulv(l); + end function "nor"; + + function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return xor to_sulv(l); + end function "xor"; + + function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is + begin + return xnor to_sulv(l); + end function "xnor"; + + function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return and to_sulv(l); + end function "and"; + + function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return nand to_sulv(l); + end function "nand"; + + function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return or to_sulv(l); + end function "or"; + + function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return nor to_sulv(l); + end function "nor"; + + function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return xor to_sulv(l); + end function "xor"; + + function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is + begin + return xnor to_sulv(l); + end function "xnor"; + -- End reduction operators + + function "?=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?= rslv; + end if; + end function "?="; + + function "?/=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?/= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?/="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?/= rslv; + end if; + end function "?/="; + + function "?>" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?> + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?>"": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?> rslv; + end if; + end function "?>"; + + function "?>=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?>= + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?>="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?>= rslv; + end if; + end function "?>="; + + function "?<" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?< + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?<"": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?< rslv; + end if; + end function "?<"; + + function "?<=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin -- ?<= + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?<="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv ?<= rslv; + end if; + end function "?<="; + + function "?=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?= rslv; + end if; + end function "?="; + + function "?/=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?/= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?/="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?/= rslv; + end if; + end function "?/="; + + function "?>" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?> + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?>"": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?> rslv; + end if; + end function "?>"; + + function "?>=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?>= + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?>="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?>= rslv; + end if; + end function "?>="; + + function "?<" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?< + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?<"": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?< rslv; + end if; + end function "?<"; + + function "?<=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin -- ?<= + if ((l'length < 1) or (r'length < 1)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """?<="": null detected, returning X" + severity warning; + return 'X'; + else + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv ?<= rslv; + end if; + end function "?<="; + + -- Match function, similar to "std_match" from numeric_std + function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is + begin + if (L'high = R'high and L'low = R'low) then + return std_match(to_sulv(L), to_sulv(R)); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" + severity warning; + return false; + end if; + end function std_match; + + function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is + begin + if (L'high = R'high and L'low = R'low) then + return std_match(to_sulv(L), to_sulv(R)); + else + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" + severity warning; + return false; + end if; + end function std_match; + + -- compare functions + function "=" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv = rslv; + end function "="; + + function "=" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv = rslv; + end function "="; + + function "/=" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """/="": null argument detected, returning TRUE" + severity warning; + return true; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv /= rslv; + end function "/="; + + function "/=" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """/="": null argument detected, returning TRUE" + severity warning; + return true; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv /= rslv; + end function "/="; + + function ">" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>"": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv > rslv; + end function ">"; + + function ">" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>"": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv > rslv; + end function ">"; + + function "<" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<"": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv < rslv; + end function "<"; + + function "<" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<"": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv < rslv; + end function "<"; + + function ">=" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv >= rslv; + end function ">="; + + function ">=" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """>="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv >= rslv; + end function ">="; + + function "<=" ( + l, r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_uns (lresize); + rslv := to_uns (rresize); + return lslv <= rslv; + end function "<="; + + function "<=" ( + l, r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN + is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0); + begin + if (l'length < 1 or r'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<="": null argument detected, returning FALSE" + severity warning; + return false; + elsif (Is_X(l) or Is_X(r)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & """<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + lslv := to_s (lresize); + rslv := to_s (rresize); + return lslv <= rslv; + end function "<="; + + -- overloads of the default maximum and minimum functions + function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + begin + if (l'length < 1 or r'length < 1) then + return NAUF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + return to_fixed(maximum(to_uns(lresize), to_uns(rresize)), + left_index, right_index); + end function maximum; + + function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + begin + if (l'length < 1 or r'length < 1) then + return NASF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + return to_fixed(maximum(to_s(lresize), to_s(rresize)), + left_index, right_index); + end function maximum; + + function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index); + begin + if (l'length < 1 or r'length < 1) then + return NAUF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + return to_fixed(minimum(to_uns(lresize), to_uns(rresize)), + left_index, right_index); + end function minimum; + + function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is + constant left_index : INTEGER := maximum(l'high, r'high); + constant right_index : INTEGER := mins(l'low, r'low); + variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index); + begin + if (l'length < 1 or r'length < 1) then + return NASF; + end if; + lresize := resize (l, left_index, right_index); + rresize := resize (r, left_index, right_index); + return to_fixed(minimum(to_s(lresize), to_s(rresize)), + left_index, right_index); + end function minimum; + + function to_ufixed ( + arg : NATURAL; -- integer + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mins (right_index, right_index); -- catch literals + variable result : UNRESOLVED_ufixed (left_index downto fw); + variable sresult : UNRESOLVED_ufixed (left_index downto 0) := + (others => '0'); -- integer portion + variable argx : NATURAL; -- internal version of arg + begin + if (result'length < 1) then + return NAUF; + end if; + if arg /= 0 then + argx := arg; + for I in 0 to sresult'left loop + if (argx mod 2) = 0 then + sresult(I) := '0'; + else + sresult(I) := '1'; + end if; + argx := argx/2; + end loop; + if argx /= 0 then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_UFIXED(NATURAL): vector truncated" + severity warning; + if overflow_style = fixed_saturate then + return saturate (left_index, right_index); + end if; + end if; + result := resize (arg => sresult, + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + else + result := (others => '0'); + end if; + return result; + end function to_ufixed; + + function to_sfixed ( + arg : INTEGER; -- integer + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mins (right_index, right_index); -- catch literals + variable result : UNRESOLVED_sfixed (left_index downto fw); + variable sresult : UNRESOLVED_sfixed (left_index downto 0) := + (others => '0'); -- integer portion + variable argx : INTEGER; -- internal version of arg + variable sign : STD_ULOGIC; -- sign of input + begin + if (result'length < 1) then -- null range + return NASF; + end if; + if arg /= 0 then + if (arg < 0) then + sign := '1'; + argx := -(arg + 1); + else + sign := '0'; + argx := arg; + end if; + for I in 0 to sresult'left loop + if (argx mod 2) = 0 then + sresult(I) := sign; + else + sresult(I) := not sign; + end if; + argx := argx/2; + end loop; + if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_SFIXED(INTEGER): vector truncated" + severity warning; + if overflow_style = fixed_saturate then -- saturate + if arg < 0 then + result := not saturate (result'high, result'low); -- underflow + else + result := saturate (result'high, result'low); -- overflow + end if; + return result; + end if; + end if; + result := resize (arg => sresult, + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + else + result := (others => '0'); + end if; + return result; + end function to_sfixed; + + function to_ufixed ( + arg : REAL; -- real + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mins (right_index, right_index); -- catch literals + variable result : UNRESOLVED_ufixed (left_index downto fw) := + (others => '0'); + variable Xresult : UNRESOLVED_ufixed (left_index downto + fw-guard_bits) := + (others => '0'); + variable presult : REAL; + begin + -- If negative or null range, return. + if (left_index < fw) then + return NAUF; + end if; + if (arg < 0.0) then + report fixed_generic_pkg'instance_name + & "TO_UFIXED: Negative argument passed " + & REAL'image(arg) severity error; + return result; + end if; + presult := arg; + if presult >= (2.0**(left_index+1)) then + assert NO_WARNING report fixed_generic_pkg'instance_name + & "TO_UFIXED(REAL): vector truncated" + severity warning; + if overflow_style = fixed_wrap then + presult := presult mod (2.0**(left_index+1)); -- wrap + else + return saturate (result'high, result'low); + end if; + end if; + for i in Xresult'range loop + if presult >= 2.0**i then + Xresult(i) := '1'; + presult := presult - 2.0**i; + else + Xresult(i) := '0'; + end if; + end loop; + if guard_bits > 0 and round_style = fixed_round then + result := round_fixed (arg => Xresult (left_index + downto right_index), + remainder => Xresult (right_index-1 downto + right_index-guard_bits), + overflow_style => overflow_style); + else + result := Xresult (result'range); + end if; + return result; + end function to_ufixed; + + function to_sfixed ( + arg : REAL; -- real + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mins (right_index, right_index); -- catch literals + variable result : UNRESOLVED_sfixed (left_index downto fw) := + (others => '0'); + variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) := + (others => '0'); + variable presult : REAL; + begin + if (left_index < fw) then -- null range + return NASF; + end if; + if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then + assert NO_WARNING report fixed_generic_pkg'instance_name + & "TO_SFIXED(REAL): vector truncated" + severity warning; + if overflow_style = fixed_saturate then + if arg < 0.0 then -- saturate + result := not saturate (result'high, result'low); -- underflow + else + result := saturate (result'high, result'low); -- overflow + end if; + return result; + else + presult := abs(arg) mod (2.0**(left_index+1)); -- wrap + end if; + else + presult := abs(arg); + end if; + for i in Xresult'range loop + if presult >= 2.0**i then + Xresult(i) := '1'; + presult := presult - 2.0**i; + else + Xresult(i) := '0'; + end if; + end loop; + if arg < 0.0 then + Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low); + end if; + if guard_bits > 0 and round_style = fixed_round then + result := round_fixed (arg => Xresult (left_index + downto right_index), + remainder => Xresult (right_index-1 downto + right_index-guard_bits), + overflow_style => overflow_style); + else + result := Xresult (result'range); + end if; + return result; + end function to_sfixed; + + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED; -- unsigned + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; + variable result : UNRESOLVED_ufixed (left_index downto right_index); + begin + if arg'length < 1 or (left_index < right_index) then + return NAUF; + end if; + result := resize (arg => UNRESOLVED_ufixed (XARG), + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + return result; + end function to_ufixed; + + -- converted version + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED) -- unsigned + return UNRESOLVED_ufixed + is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; + begin + if arg'length < 1 then + return NAUF; + end if; + return UNRESOLVED_ufixed(xarg); + end function to_ufixed; + + function to_sfixed ( + arg : UNRESOLVED_SIGNED; -- signed + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; + variable result : UNRESOLVED_sfixed (left_index downto right_index); + begin + if arg'length < 1 or (left_index < right_index) then + return NASF; + end if; + result := resize (arg => UNRESOLVED_sfixed (XARG), + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + return result; + end function to_sfixed; + + -- converted version + function to_sfixed ( + arg : UNRESOLVED_SIGNED) -- signed + return UNRESOLVED_sfixed + is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; + begin + if arg'length < 1 then + return NASF; + end if; + return UNRESOLVED_sfixed(xarg); + end function to_sfixed; + + function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is + variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low); + begin + if arg'length < 1 then + return NASF; + end if; + result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg)); + result (arg'high+1) := '0'; + return result; + end function to_sfixed; + + -- Because of the fairly complicated sizing rules in the fixed point + -- packages these functions are provided to compute the result ranges + -- Example: + -- signal uf1 : ufixed (3 downto -3); + -- signal uf2 : ufixed (4 downto -2); + -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto + -- ufixed_low (3, -3, '*', 4, -2)); + -- uf1multuf2 <= uf1 * uf2; + -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), + -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed) + function ufixed_high (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER is + begin + case operation is + when '+'| '-' => return maximum (left_index, left_index2) + 1; + when '*' => return left_index + left_index2 + 1; + when '/' => return left_index - right_index2; + when '1' => return -right_index; -- reciprocal + when 'R'|'r' => return mins (left_index, left_index2); -- "rem" + when 'M'|'m' => return mins (left_index, left_index2); -- "mod" + when others => return left_index; -- For abs and default + end case; + end function ufixed_high; + + function ufixed_low (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER is + begin + case operation is + when '+'| '-' => return mins (right_index, right_index2); + when '*' => return right_index + right_index2; + when '/' => return right_index - left_index2 - 1; + when '1' => return -left_index - 1; -- reciprocal + when 'R'|'r' => return mins (right_index, right_index2); -- "rem" + when 'M'|'m' => return mins (right_index, right_index2); -- "mod" + when others => return right_index; -- for abs and default + end case; + end function ufixed_low; + + function sfixed_high (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER is + begin + case operation is + when '+'| '-' => return maximum (left_index, left_index2) + 1; + when '*' => return left_index + left_index2 + 1; + when '/' => return left_index - right_index2 + 1; + when '1' => return -right_index + 1; -- reciprocal + when 'R'|'r' => return mins (left_index, left_index2); -- "rem" + when 'M'|'m' => return left_index2; -- "mod" + when 'A'|'a' => return left_index + 1; -- "abs" + when 'N'|'n' => return left_index + 1; -- -sfixed + when others => return left_index; + end case; + end function sfixed_high; + + function sfixed_low (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER is + begin + case operation is + when '+'| '-' => return mins (right_index, right_index2); + when '*' => return right_index + right_index2; + when '/' => return right_index - left_index2; + when '1' => return -left_index; -- reciprocal + when 'R'|'r' => return mins (right_index, right_index2); -- "rem" + when 'M'|'m' => return mins (right_index, right_index2); -- "mod" + when others => return right_index; -- default for abs, neg and default + end case; + end function sfixed_low; + + -- Same as above, but using the "size_res" input only for their ranges: + -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto + -- ufixed_low (uf1, '*', uf2)); + -- uf1multuf2 <= uf1 * uf2; + function ufixed_high (size_res : UNRESOLVED_ufixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_ufixed) + return INTEGER is + begin + return ufixed_high (left_index => size_res'high, + right_index => size_res'low, + operation => operation, + left_index2 => size_res2'high, + right_index2 => size_res2'low); + end function ufixed_high; + + function ufixed_low (size_res : UNRESOLVED_ufixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_ufixed) + return INTEGER is + begin + return ufixed_low (left_index => size_res'high, + right_index => size_res'low, + operation => operation, + left_index2 => size_res2'high, + right_index2 => size_res2'low); + end function ufixed_low; + + function sfixed_high (size_res : UNRESOLVED_sfixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_sfixed) + return INTEGER is + begin + return sfixed_high (left_index => size_res'high, + right_index => size_res'low, + operation => operation, + left_index2 => size_res2'high, + right_index2 => size_res2'low); + end function sfixed_high; + + function sfixed_low (size_res : UNRESOLVED_sfixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_sfixed) + return INTEGER is + begin + return sfixed_low (left_index => size_res'high, + right_index => size_res'low, + operation => operation, + left_index2 => size_res2'high, + right_index2 => size_res2'low); + end function sfixed_low; + + -- purpose: returns a saturated number + function saturate ( + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed + is + constant sat : UNRESOLVED_ufixed (left_index downto right_index) := + (others => '1'); + begin + return sat; + end function saturate; + + -- purpose: returns a saturated number + function saturate ( + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed + is + variable sat : UNRESOLVED_sfixed (left_index downto right_index) := + (others => '1'); + begin + -- saturate positive, to saturate negative, just do "not saturate()" + sat (left_index) := '0'; + return sat; + end function saturate; + + function saturate ( + size_res : UNRESOLVED_ufixed) -- only the size of this is used + return UNRESOLVED_ufixed is + begin + return saturate (size_res'high, size_res'low); + end function saturate; + + function saturate ( + size_res : UNRESOLVED_sfixed) -- only the size of this is used + return UNRESOLVED_sfixed is + begin + return saturate (size_res'high, size_res'low); + end function saturate; + + -- As a concession to those who use a graphical DSP environment, + -- these functions take parameters in those tools format and create + -- fixed point numbers. These functions are designed to convert from + -- a std_logic_vector to the VHDL fixed point format using the conventions + -- of these packages. In a pure VHDL environment you should use the + -- "to_ufixed" and "to_sfixed" routines. + -- Unsigned fixed point + function to_UFix ( + arg : STD_ULOGIC_VECTOR; + width : NATURAL; -- width of vector + fraction : NATURAL) -- width of fraction + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction); + begin + if (arg'length /= result'length) then + report fixed_generic_pkg'instance_name + & "TO_UFIX (STD_ULOGIC_VECTOR) " + & "Vector lengths do not match. Input length is " + & INTEGER'image(arg'length) & " and output will be " + & INTEGER'image(result'length) & " wide." + severity error; + return NAUF; + else + result := to_ufixed (arg, result'high, result'low); + return result; + end if; + end function to_UFix; + + -- signed fixed point + function to_SFix ( + arg : STD_ULOGIC_VECTOR; + width : NATURAL; -- width of vector + fraction : NATURAL) -- width of fraction + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction); + begin + if (arg'length /= result'length) then + report fixed_generic_pkg'instance_name + & "TO_SFIX (STD_ULOGIC_VECTOR) " + & "Vector lengths do not match. Input length is " + & INTEGER'image(arg'length) & " and output will be " + & INTEGER'image(result'length) & " wide." + severity error; + return NASF; + else + result := to_sfixed (arg, result'high, result'low); + return result; + end if; + end function to_SFix; + + -- finding the bounds of a number. These functions can be used like this: + -- signal xxx : ufixed (7 downto -3); + -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" + -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) + -- downto UFix_low(11, 3, "+", 11, 3)); + -- Where "11" is the width of xxx (xxx'length), + -- and 3 is the lower bound (abs (xxx'low)) + -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" + function ufix_high ( + width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER is + begin + return ufixed_high (left_index => width - 1 - fraction, + right_index => -fraction, + operation => operation, + left_index2 => width2 - 1 - fraction2, + right_index2 => -fraction2); + end function ufix_high; + + function ufix_low ( + width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER is + begin + return ufixed_low (left_index => width - 1 - fraction, + right_index => -fraction, + operation => operation, + left_index2 => width2 - 1 - fraction2, + right_index2 => -fraction2); + end function ufix_low; + + function sfix_high ( + width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER is + begin + return sfixed_high (left_index => width - fraction, + right_index => -fraction, + operation => operation, + left_index2 => width2 - fraction2, + right_index2 => -fraction2); + end function sfix_high; + + function sfix_low ( + width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER is + begin + return sfixed_low (left_index => width - fraction, + right_index => -fraction, + operation => operation, + left_index2 => width2 - fraction2, + right_index2 => -fraction2); + end function sfix_low; + + function to_unsigned ( + arg : UNRESOLVED_ufixed; -- ufixed point input + constant size : NATURAL; -- length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_UNSIGNED is + begin + return to_uns(resize (arg => arg, + left_index => size-1, + right_index => 0, + round_style => round_style, + overflow_style => overflow_style)); + end function to_unsigned; + + function to_unsigned ( + arg : UNRESOLVED_ufixed; -- ufixed point input + size_res : UNRESOLVED_UNSIGNED; -- length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_UNSIGNED is + begin + return to_unsigned (arg => arg, + size => size_res'length, + round_style => round_style, + overflow_style => overflow_style); + end function to_unsigned; + + function to_signed ( + arg : UNRESOLVED_sfixed; -- sfixed point input + constant size : NATURAL; -- length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_SIGNED is + begin + return to_s(resize (arg => arg, + left_index => size-1, + right_index => 0, + round_style => round_style, + overflow_style => overflow_style)); + end function to_signed; + + function to_signed ( + arg : UNRESOLVED_sfixed; -- sfixed point input + size_res : UNRESOLVED_SIGNED; -- used for length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_SIGNED is + begin + return to_signed (arg => arg, + size => size_res'length, + round_style => round_style, + overflow_style => overflow_style); + end function to_signed; + + function to_real ( + arg : UNRESOLVED_ufixed) -- ufixed point input + return REAL + is + constant left_index : INTEGER := arg'high; + constant right_index : INTEGER := arg'low; + variable result : REAL; -- result + variable arg_int : UNRESOLVED_ufixed (left_index downto right_index); + begin + if (arg'length < 1) then + return 0.0; + end if; + arg_int := to_x01(cleanvec(arg)); + if (Is_X(arg_int)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_REAL (ufixed): metavalue detected, returning 0.0" + severity warning; + return 0.0; + end if; + result := 0.0; + for i in arg_int'range loop + if (arg_int(i) = '1') then + result := result + (2.0**i); + end if; + end loop; + return result; + end function to_real; + + function to_real ( + arg : UNRESOLVED_sfixed) -- ufixed point input + return REAL + is + constant left_index : INTEGER := arg'high; + constant right_index : INTEGER := arg'low; + variable result : REAL; -- result + variable arg_int : UNRESOLVED_sfixed (left_index downto right_index); + -- unsigned version of argument + variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index); + -- absolute of argument + begin + if (arg'length < 1) then + return 0.0; + end if; + arg_int := to_x01(cleanvec(arg)); + if (Is_X(arg_int)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_REAL (sfixed): metavalue detected, returning 0.0" + severity warning; + return 0.0; + end if; + arg_uns := to_ufixed (arg_int); + result := to_real (arg_uns); + if (arg_int(arg_int'high) = '1') then + result := -result; + end if; + return result; + end function to_real; + + function to_integer ( + arg : UNRESOLVED_ufixed; -- fixed point input + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return NATURAL + is + constant left_index : INTEGER := arg'high; + variable arg_uns : UNRESOLVED_UNSIGNED (left_index+1 downto 0) + := (others => '0'); + begin + if (arg'length < 1) then + return 0; + end if; + if (Is_X (arg)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_INTEGER (ufixed): metavalue detected, returning 0" + severity warning; + return 0; + end if; + if (left_index < -1) then + return 0; + end if; + arg_uns := to_uns(resize (arg => arg, + left_index => arg_uns'high, + right_index => 0, + round_style => round_style, + overflow_style => overflow_style)); + return to_integer (arg_uns); + end function to_integer; + + function to_integer ( + arg : UNRESOLVED_sfixed; -- fixed point input + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return INTEGER + is + constant left_index : INTEGER := arg'high; + constant right_index : INTEGER := arg'low; + variable arg_s : UNRESOLVED_SIGNED (left_index+1 downto 0); + begin + if (arg'length < 1) then + return 0; + end if; + if (Is_X (arg)) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_INTEGER (sfixed): metavalue detected, returning 0" + severity warning; + return 0; + end if; + if (left_index < -1) then + return 0; + end if; + arg_s := to_s(resize (arg => arg, + left_index => arg_s'high, + right_index => 0, + round_style => round_style, + overflow_style => overflow_style)); + return to_integer (arg_s); + end function to_integer; + + function to_01 ( + s : UNRESOLVED_ufixed; -- ufixed point input + constant XMAP : STD_ULOGIC := '0') -- Map x to + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (s'range); -- result + begin + if (s'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_01(ufixed): null detected, returning NULL" + severity warning; + return NAUF; + end if; + return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low); + end function to_01; + + function to_01 ( + s : UNRESOLVED_sfixed; -- sfixed point input + constant XMAP : STD_ULOGIC := '0') -- Map x to + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (s'range); + begin + if (s'length < 1) then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "TO_01(sfixed): null detected, returning NULL" + severity warning; + return NASF; + end if; + return to_fixed (to_01(to_s(s), XMAP), s'high, s'low); + end function to_01; + + function Is_X ( + arg : UNRESOLVED_ufixed) + return BOOLEAN + is + variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv + begin + argslv := to_sulv(arg); + return Is_X (argslv); + end function Is_X; + + function Is_X ( + arg : UNRESOLVED_sfixed) + return BOOLEAN + is + variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv + begin + argslv := to_sulv(arg); + return Is_X (argslv); + end function Is_X; + + function To_X01 ( + arg : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low); + end function To_X01; + + function to_X01 ( + arg : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low); + end function To_X01; + + function To_X01Z ( + arg : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low); + end function To_X01Z; + + function to_X01Z ( + arg : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low); + end function To_X01Z; + + function To_UX01 ( + arg : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low); + end function To_UX01; + + function to_UX01 ( + arg : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low); + end function To_UX01; + + function resize ( + arg : UNRESOLVED_ufixed; -- input + constant left_index : INTEGER; -- integer portion + constant right_index : INTEGER; -- size of fraction + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant arghigh : INTEGER := maximum (arg'high, arg'low); + constant arglow : INTEGER := mine (arg'high, arg'low); + variable invec : UNRESOLVED_ufixed (arghigh downto arglow); + variable result : UNRESOLVED_ufixed(left_index downto right_index) := + (others => '0'); + variable needs_rounding : BOOLEAN := false; + begin -- resize + if (arg'length < 1) or (result'length < 1) then + return NAUF; + elsif (invec'length < 1) then + return result; -- string literal value + else + invec := cleanvec(arg); + if (right_index > arghigh) then -- return top zeros + needs_rounding := (round_style = fixed_round) and + (right_index = arghigh+1); + elsif (left_index < arglow) then -- return overflow + if (overflow_style = fixed_saturate) and + (or(to_sulv(invec)) = '1') then + result := saturate (result'high, result'low); -- saturate + end if; + elsif (arghigh > left_index) then + -- wrap or saturate? + if (overflow_style = fixed_saturate and + or (to_sulv(invec(arghigh downto left_index+1))) = '1') + then + result := saturate (result'high, result'low); -- saturate + else + if (arglow >= right_index) then + result (left_index downto arglow) := + invec(left_index downto arglow); + else + result (left_index downto right_index) := + invec (left_index downto right_index); + needs_rounding := (round_style = fixed_round); -- round + end if; + end if; + else -- arghigh <= integer width + if (arglow >= right_index) then + result (arghigh downto arglow) := invec; + else + result (arghigh downto right_index) := + invec (arghigh downto right_index); + needs_rounding := (round_style = fixed_round); -- round + end if; + end if; + -- Round result + if needs_rounding then + result := round_fixed (arg => result, + remainder => invec (right_index-1 + downto arglow), + overflow_style => overflow_style); + end if; + return result; + end if; + end function resize; + + function resize ( + arg : UNRESOLVED_sfixed; -- input + constant left_index : INTEGER; -- integer portion + constant right_index : INTEGER; -- size of fraction + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant arghigh : INTEGER := maximum (arg'high, arg'low); + constant arglow : INTEGER := mine (arg'high, arg'low); + variable invec : UNRESOLVED_sfixed (arghigh downto arglow); + variable result : UNRESOLVED_sfixed(left_index downto right_index) := + (others => '0'); + variable reduced : STD_ULOGIC; + variable needs_rounding : BOOLEAN := false; -- rounding + begin -- resize + if (arg'length < 1) or (result'length < 1) then + return NASF; + elsif (invec'length < 1) then + return result; -- string literal value + else + invec := cleanvec(arg); + if (right_index > arghigh) then -- return top zeros + if (arg'low /= INTEGER'low) then -- check for a literal + result := (others => arg(arghigh)); -- sign extend + end if; + needs_rounding := (round_style = fixed_round) and + (right_index = arghigh+1); + elsif (left_index < arglow) then -- return overflow + if (overflow_style = fixed_saturate) then + reduced := or (to_sulv(invec)); + if (reduced = '1') then + if (invec(arghigh) = '0') then + -- saturate POSITIVE + result := saturate (result'high, result'low); + else + -- saturate negative + result := not saturate (result'high, result'low); + end if; + -- else return 0 (input was 0) + end if; + -- else return 0 (wrap) + end if; + elsif (arghigh > left_index) then + if (invec(arghigh) = '0') then + reduced := or (to_sulv(invec(arghigh-1 downto + left_index))); + if overflow_style = fixed_saturate and reduced = '1' then + -- saturate positive + result := saturate (result'high, result'low); + else + if (right_index > arglow) then + result := invec (left_index downto right_index); + needs_rounding := (round_style = fixed_round); + else + result (left_index downto arglow) := + invec (left_index downto arglow); + end if; + end if; + else + reduced := and (to_sulv(invec(arghigh-1 downto + left_index))); + if overflow_style = fixed_saturate and reduced = '0' then + result := not saturate (result'high, result'low); + else + if (right_index > arglow) then + result := invec (left_index downto right_index); + needs_rounding := (round_style = fixed_round); + else + result (left_index downto arglow) := + invec (left_index downto arglow); + end if; + end if; + end if; + else -- arghigh <= integer width + if (arglow >= right_index) then + result (arghigh downto arglow) := invec; + else + result (arghigh downto right_index) := + invec (arghigh downto right_index); + needs_rounding := (round_style = fixed_round); -- round + end if; + if (left_index > arghigh) then -- sign extend + result(left_index downto arghigh+1) := (others => invec(arghigh)); + end if; + end if; + -- Round result + if (needs_rounding) then + result := round_fixed (arg => result, + remainder => invec (right_index-1 + downto arglow), + overflow_style => overflow_style); + end if; + return result; + end if; + end function resize; + + -- size_res functions + -- These functions compute the size from a passed variable named "size_res" + -- The only part of this variable used it it's size, it is never passed + -- to a lower level routine. + function to_ufixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + size_res : UNRESOLVED_ufixed) -- for size only + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_ufixed (size_res'left downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NAUF; + else + result := to_ufixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low); + return result; + end if; + end function to_ufixed; + + function to_sfixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + size_res : UNRESOLVED_sfixed) -- for size only + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_sfixed (size_res'left downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NASF; + else + result := to_sfixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low); + return result; + end if; + end function to_sfixed; + + function to_ufixed ( + arg : NATURAL; -- integer + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_ufixed (size_res'left downto fw); + begin + if (result'length < 1) then + return NAUF; + else + result := to_ufixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_ufixed; + + function to_sfixed ( + arg : INTEGER; -- integer + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_sfixed (size_res'left downto fw); + begin + if (result'length < 1) then + return NASF; + else + result := to_sfixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_sfixed; + + function to_ufixed ( + arg : REAL; -- real + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_ufixed (size_res'left downto fw); + begin + if (result'length < 1) then + return NAUF; + else + result := to_ufixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + guard_bits => guard_bits, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_ufixed; + + function to_sfixed ( + arg : REAL; -- real + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_sfixed (size_res'left downto fw); + begin + if (result'length < 1) then + return NASF; + else + result := to_sfixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + guard_bits => guard_bits, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_sfixed; + + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED; -- unsigned + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_ufixed (size_res'left downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NAUF; + else + result := to_ufixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_ufixed; + + function to_sfixed ( + arg : UNRESOLVED_SIGNED; -- signed + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_sfixed (size_res'left downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NASF; + else + result := to_sfixed (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function to_sfixed; + + function resize ( + arg : UNRESOLVED_ufixed; -- input + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_ufixed (size_res'high downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NAUF; + else + result := resize (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function resize; + + function resize ( + arg : UNRESOLVED_sfixed; -- input + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed + is + constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals + variable result : UNRESOLVED_sfixed (size_res'high downto fw); + begin + if (result'length < 1 or arg'length < 1) then + return NASF; + else + result := resize (arg => arg, + left_index => size_res'high, + right_index => size_res'low, + round_style => round_style, + overflow_style => overflow_style); + return result; + end if; + end function resize; + + -- Overloaded math functions for real + function "+" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l + to_ufixed (r, l'high, l'low)); + end function "+"; + + function "+" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) + r); + end function "+"; + + function "+" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l + to_sfixed (r, l'high, l'low)); + end function "+"; + + function "+" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) + r); + end function "+"; + + function "-" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l - to_ufixed (r, l'high, l'low)); + end function "-"; + + function "-" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) - r); + end function "-"; + + function "-" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l - to_sfixed (r, l'high, l'low)); + end function "-"; + + function "-" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) - r); + end function "-"; + + function "*" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l * to_ufixed (r, l'high, l'low)); + end function "*"; + + function "*" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) * r); + end function "*"; + + function "*" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l * to_sfixed (r, l'high, l'low)); + end function "*"; + + function "*" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) * r); + end function "*"; + + function "/" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l / to_ufixed (r, l'high, l'low)); + end function "/"; + + function "/" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) / r); + end function "/"; + + function "/" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l / to_sfixed (r, l'high, l'low)); + end function "/"; + + function "/" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) / r); + end function "/"; + + function "rem" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l rem to_ufixed (r, l'high, l'low)); + end function "rem"; + + function "rem" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) rem r); + end function "rem"; + + function "rem" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l rem to_sfixed (r, l'high, l'low)); + end function "rem"; + + function "rem" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) rem r); + end function "rem"; + + function "mod" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : REAL) + return UNRESOLVED_ufixed is + begin + return (l mod to_ufixed (r, l'high, l'low)); + end function "mod"; + + function "mod" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, r'low) mod r); + end function "mod"; + + function "mod" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : REAL) + return UNRESOLVED_sfixed is + begin + return (l mod to_sfixed (r, l'high, l'low)); + end function "mod"; + + function "mod" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, r'low) mod r); + end function "mod"; + + -- Overloaded math functions for integers + function "+" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l + to_ufixed (r, l'high, 0)); + end function "+"; + + function "+" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) + r); + end function "+"; + + function "+" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l + to_sfixed (r, l'high, 0)); + end function "+"; + + function "+" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) + r); + end function "+"; + + -- Overloaded functions + function "-" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l - to_ufixed (r, l'high, 0)); + end function "-"; + + function "-" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) - r); + end function "-"; + + function "-" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l - to_sfixed (r, l'high, 0)); + end function "-"; + + function "-" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) - r); + end function "-"; + + -- Overloaded functions + function "*" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l * to_ufixed (r, l'high, 0)); + end function "*"; + + function "*" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) * r); + end function "*"; + + function "*" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l * to_sfixed (r, l'high, 0)); + end function "*"; + + function "*" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) * r); + end function "*"; + + -- Overloaded functions + function "/" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l / to_ufixed (r, l'high, 0)); + end function "/"; + + function "/" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) / r); + end function "/"; + + function "/" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l / to_sfixed (r, l'high, 0)); + end function "/"; + + function "/" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) / r); + end function "/"; + + function "rem" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l rem to_ufixed (r, l'high, 0)); + end function "rem"; + + function "rem" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) rem r); + end function "rem"; + + function "rem" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l rem to_sfixed (r, l'high, 0)); + end function "rem"; + + function "rem" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) rem r); + end function "rem"; + + function "mod" ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return (l mod to_ufixed (r, l'high, 0)); + end function "mod"; + + function "mod" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return (to_ufixed (l, r'high, 0) mod r); + end function "mod"; + + function "mod" ( + l : UNRESOLVED_sfixed; -- fixed point input + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return (l mod to_sfixed (r, l'high, 0)); + end function "mod"; + + function "mod" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return UNRESOLVED_sfixed is + begin + return (to_sfixed (l, r'high, 0) mod r); + end function "mod"; + + -- overloaded ufixed compare functions with integer + function "=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l = to_ufixed (r, l'high, l'low)); + end function "="; + + function "/=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l /= to_ufixed (r, l'high, l'low)); + end function "/="; + + function ">=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l >= to_ufixed (r, l'high, l'low)); + end function ">="; + + function "<=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l <= to_ufixed (r, l'high, l'low)); + end function "<="; + + function ">" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l > to_ufixed (r, l'high, l'low)); + end function ">"; + + function "<" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return BOOLEAN is + begin + return (l < to_ufixed (r, l'high, l'low)); + end function "<"; + + function "?=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?= to_ufixed (r, l'high, l'low)); + end function "?="; + + function "?/=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?/= to_ufixed (r, l'high, l'low)); + end function "?/="; + + function "?>=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?>= to_ufixed (r, l'high, l'low)); + end function "?>="; + + function "?<=" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?<= to_ufixed (r, l'high, l'low)); + end function "?<="; + + function "?>" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?> to_ufixed (r, l'high, l'low)); + end function "?>"; + + function "?<" ( + l : UNRESOLVED_ufixed; + r : NATURAL) -- fixed point input + return STD_ULOGIC is + begin + return (l ?< to_ufixed (r, l'high, l'low)); + end function "?<"; + + function maximum ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return maximum (l, to_ufixed (r, l'high, l'low)); + end function maximum; + + function minimum ( + l : UNRESOLVED_ufixed; -- fixed point input + r : NATURAL) + return UNRESOLVED_ufixed is + begin + return minimum (l, to_ufixed (r, l'high, l'low)); + end function minimum; + + -- NATURAL to ufixed + function "=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) = r); + end function "="; + + function "/=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) /= r); + end function "/="; + + function ">=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) >= r); + end function ">="; + + function "<=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) <= r); + end function "<="; + + function ">" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) > r); + end function ">"; + + function "<" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) < r); + end function "<"; + + function "?=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?= r); + end function "?="; + + function "?/=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?/= r); + end function "?/="; + + function "?>=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?>= r); + end function "?>="; + + function "?<=" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?<= r); + end function "?<="; + + function "?>" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?> r); + end function "?>"; + + function "?<" ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?< r); + end function "?<"; + + function maximum ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return maximum (to_ufixed (l, r'high, r'low), r); + end function maximum; + + function minimum ( + l : NATURAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return minimum (to_ufixed (l, r'high, r'low), r); + end function minimum; + + -- overloaded ufixed compare functions with real + function "=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l = to_ufixed (r, l'high, l'low)); + end function "="; + + function "/=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l /= to_ufixed (r, l'high, l'low)); + end function "/="; + + function ">=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l >= to_ufixed (r, l'high, l'low)); + end function ">="; + + function "<=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l <= to_ufixed (r, l'high, l'low)); + end function "<="; + + function ">" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l > to_ufixed (r, l'high, l'low)); + end function ">"; + + function "<" ( + l : UNRESOLVED_ufixed; + r : REAL) + return BOOLEAN is + begin + return (l < to_ufixed (r, l'high, l'low)); + end function "<"; + + function "?=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?= to_ufixed (r, l'high, l'low)); + end function "?="; + + function "?/=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?/= to_ufixed (r, l'high, l'low)); + end function "?/="; + + function "?>=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?>= to_ufixed (r, l'high, l'low)); + end function "?>="; + + function "?<=" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?<= to_ufixed (r, l'high, l'low)); + end function "?<="; + + function "?>" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?> to_ufixed (r, l'high, l'low)); + end function "?>"; + + function "?<" ( + l : UNRESOLVED_ufixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?< to_ufixed (r, l'high, l'low)); + end function "?<"; + + function maximum ( + l : UNRESOLVED_ufixed; + r : REAL) + return UNRESOLVED_ufixed is + begin + return maximum (l, to_ufixed (r, l'high, l'low)); + end function maximum; + + function minimum ( + l : UNRESOLVED_ufixed; + r : REAL) + return UNRESOLVED_ufixed is + begin + return minimum (l, to_ufixed (r, l'high, l'low)); + end function minimum; + + -- real and ufixed + function "=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) = r); + end function "="; + + function "/=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) /= r); + end function "/="; + + function ">=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) >= r); + end function ">="; + + function "<=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) <= r); + end function "<="; + + function ">" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) > r); + end function ">"; + + function "<" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return BOOLEAN is + begin + return (to_ufixed (l, r'high, r'low) < r); + end function "<"; + + function "?=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?= r); + end function "?="; + + function "?/=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?/= r); + end function "?/="; + + function "?>=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?>= r); + end function "?>="; + + function "?<=" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?<= r); + end function "?<="; + + function "?>" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?> r); + end function "?>"; + + function "?<" ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_ufixed (l, r'high, r'low) ?< r); + end function "?<"; + + function maximum ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return maximum (to_ufixed (l, r'high, r'low), r); + end function maximum; + + function minimum ( + l : REAL; + r : UNRESOLVED_ufixed) -- fixed point input + return UNRESOLVED_ufixed is + begin + return minimum (to_ufixed (l, r'high, r'low), r); + end function minimum; + + -- overloaded sfixed compare functions with integer + function "=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l = to_sfixed (r, l'high, l'low)); + end function "="; + + function "/=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l /= to_sfixed (r, l'high, l'low)); + end function "/="; + + function ">=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l >= to_sfixed (r, l'high, l'low)); + end function ">="; + + function "<=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l <= to_sfixed (r, l'high, l'low)); + end function "<="; + + function ">" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l > to_sfixed (r, l'high, l'low)); + end function ">"; + + function "<" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return BOOLEAN is + begin + return (l < to_sfixed (r, l'high, l'low)); + end function "<"; + + function "?=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?= to_sfixed (r, l'high, l'low)); + end function "?="; + + function "?/=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?/= to_sfixed (r, l'high, l'low)); + end function "?/="; + + function "?>=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?>= to_sfixed (r, l'high, l'low)); + end function "?>="; + + function "?<=" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?<= to_sfixed (r, l'high, l'low)); + end function "?<="; + + function "?>" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?> to_sfixed (r, l'high, l'low)); + end function "?>"; + + function "?<" ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return STD_ULOGIC is + begin + return (l ?< to_sfixed (r, l'high, l'low)); + end function "?<"; + + function maximum ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return maximum (l, to_sfixed (r, l'high, l'low)); + end function maximum; + + function minimum ( + l : UNRESOLVED_sfixed; + r : INTEGER) + return UNRESOLVED_sfixed is + begin + return minimum (l, to_sfixed (r, l'high, l'low)); + end function minimum; + + -- integer and sfixed + function "=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) = r); + end function "="; + + function "/=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) /= r); + end function "/="; + + function ">=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) >= r); + end function ">="; + + function "<=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) <= r); + end function "<="; + + function ">" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) > r); + end function ">"; + + function "<" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) < r); + end function "<"; + + function "?=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?= r); + end function "?="; + + function "?/=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?/= r); + end function "?/="; + + function "?>=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?>= r); + end function "?>="; + + function "?<=" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?<= r); + end function "?<="; + + function "?>" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?> r); + end function "?>"; + + function "?<" ( + l : INTEGER; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?< r); + end function "?<"; + + function maximum ( + l : INTEGER; + r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return maximum (to_sfixed (l, r'high, r'low), r); + end function maximum; + + function minimum ( + l : INTEGER; + r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return minimum (to_sfixed (l, r'high, r'low), r); + end function minimum; + + -- overloaded sfixed compare functions with real + function "=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l = to_sfixed (r, l'high, l'low)); + end function "="; + + function "/=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l /= to_sfixed (r, l'high, l'low)); + end function "/="; + + function ">=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l >= to_sfixed (r, l'high, l'low)); + end function ">="; + + function "<=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l <= to_sfixed (r, l'high, l'low)); + end function "<="; + + function ">" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l > to_sfixed (r, l'high, l'low)); + end function ">"; + + function "<" ( + l : UNRESOLVED_sfixed; + r : REAL) + return BOOLEAN is + begin + return (l < to_sfixed (r, l'high, l'low)); + end function "<"; + + function "?=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?= to_sfixed (r, l'high, l'low)); + end function "?="; + + function "?/=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?/= to_sfixed (r, l'high, l'low)); + end function "?/="; + + function "?>=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?>= to_sfixed (r, l'high, l'low)); + end function "?>="; + + function "?<=" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?<= to_sfixed (r, l'high, l'low)); + end function "?<="; + + function "?>" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?> to_sfixed (r, l'high, l'low)); + end function "?>"; + + function "?<" ( + l : UNRESOLVED_sfixed; + r : REAL) + return STD_ULOGIC is + begin + return (l ?< to_sfixed (r, l'high, l'low)); + end function "?<"; + + function maximum ( + l : UNRESOLVED_sfixed; + r : REAL) + return UNRESOLVED_sfixed is + begin + return maximum (l, to_sfixed (r, l'high, l'low)); + end function maximum; + + function minimum ( + l : UNRESOLVED_sfixed; + r : REAL) + return UNRESOLVED_sfixed is + begin + return minimum (l, to_sfixed (r, l'high, l'low)); + end function minimum; + + -- REAL and sfixed + function "=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) = r); + end function "="; + + function "/=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) /= r); + end function "/="; + + function ">=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) >= r); + end function ">="; + + function "<=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) <= r); + end function "<="; + + function ">" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) > r); + end function ">"; + + function "<" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return BOOLEAN is + begin + return (to_sfixed (l, r'high, r'low) < r); + end function "<"; + + function "?=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?= r); + end function "?="; + + function "?/=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?/= r); + end function "?/="; + + function "?>=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?>= r); + end function "?>="; + + function "?<=" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?<= r); + end function "?<="; + + function "?>" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?> r); + end function "?>"; + + function "?<" ( + l : REAL; + r : UNRESOLVED_sfixed) -- fixed point input + return STD_ULOGIC is + begin + return (to_sfixed (l, r'high, r'low) ?< r); + end function "?<"; + + function maximum ( + l : REAL; + r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return maximum (to_sfixed (l, r'high, r'low), r); + end function maximum; + + function minimum ( + l : REAL; + r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return minimum (to_sfixed (l, r'high, r'low), r); + end function minimum; + + -- copied from std_logic_textio + type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); + type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; + type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; + type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; + + constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; + constant char_to_MVL9 : MVL9_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); + constant char_to_MVL9plus : MVL9plus_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); + constant NBSP : CHARACTER := CHARACTER'val(160); -- space character + constant NUS : STRING(2 to 1) := (others => ' '); + + -- purpose: Skips white space + procedure skip_whitespace ( + L : inout LINE) is + variable readOk : BOOLEAN; + variable c : CHARACTER; + begin + while L /= null and L.all'length /= 0 loop + if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then + read (l, c, readOk); + else + exit; + end if; + end loop; + end procedure skip_whitespace; + + -- purpose: writes fixed point into a line + procedure write ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + variable s : STRING(1 to value'length +1) := (others => ' '); + variable sindx : INTEGER; + begin -- function write Example: 0011.1100 + sindx := 1; + for i in value'high downto value'low loop + if i = -1 then + s(sindx) := '.'; + sindx := sindx + 1; + end if; + s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); + sindx := sindx + 1; + end loop; + write(l, s, justified, field); + end procedure write; + + -- purpose: writes fixed point into a line + procedure write ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + variable s : STRING(1 to value'length +1); + variable sindx : INTEGER; + begin -- function write Example: 0011.1100 + sindx := 1; + for i in value'high downto value'low loop + if i = -1 then + s(sindx) := '.'; + sindx := sindx + 1; + end if; + s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); + sindx := sindx + 1; + end loop; + write(l, s, justified, field); + end procedure write; + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_ufixed) is + -- Possible data: 00000.0000000 + -- 000000000000 + variable c : CHARACTER; + variable readOk : BOOLEAN; + variable i : INTEGER; -- index variable + variable mv : ufixed (VALUE'range); + variable lastu : BOOLEAN := false; -- last character was an "_" + variable founddot : BOOLEAN := false; -- found a "." + begin -- READ + VALUE := (VALUE'range => 'U'); + Skip_whitespace (L); + if VALUE'length > 0 then -- non Null input string + read (l, c, readOk); + i := value'high; + while i >= VALUE'low loop + if readOk = false then -- Bail out if there was a bad read + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "End of string encountered" + severity error; + return; + elsif c = '_' then + if i = value'high then + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "String begins with an ""_""" severity error; + return; + elsif lastu then + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + elsif c = '.' then -- binary point + if founddot then + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "Two binary points found in input string" severity error; + return; + elsif i /= -1 then -- Seperator in the wrong spot + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "Decimal point does not match number format " + severity error; + return; + end if; + founddot := true; + lastu := false; + elsif c = ' ' or c = NBSP or c = HT then -- reading done. + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "Short read, Space encounted in input string" + severity error; + return; + elsif char_to_MVL9plus(c) = error then + report fixed_generic_pkg'instance_name & "READ(ufixed) " + & "Character '" & + c & "' read, expected STD_ULOGIC literal." + severity error; + return; + else + mv(i) := char_to_MVL9(c); + i := i - 1; + if i < mv'low then + VALUE := mv; + return; + end if; + lastu := false; + end if; + read(L, c, readOk); + end loop; + end if; + end procedure READ; + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN) is + -- Possible data: 00000.0000000 + -- 000000000000 + variable c : CHARACTER; + variable readOk : BOOLEAN; + variable mv : ufixed (VALUE'range); + variable i : INTEGER; -- index variable + variable lastu : BOOLEAN := false; -- last character was an "_" + variable founddot : BOOLEAN := false; -- found a "." + begin -- READ + VALUE := (VALUE'range => 'U'); + Skip_whitespace (L); + if VALUE'length > 0 then + read (l, c, readOk); + i := value'high; + GOOD := false; + while i >= VALUE'low loop + if not readOk then -- Bail out if there was a bad read + return; + elsif c = '_' then + if i = value'high then -- Begins with an "_" + return; + elsif lastu then -- "__" detected + return; + else + lastu := true; + end if; + elsif c = '.' then -- binary point + if founddot then + return; + elsif i /= -1 then -- Seperator in the wrong spot + return; + end if; + founddot := true; + lastu := false; + elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read + return; + else + mv(i) := char_to_MVL9(c); + i := i - 1; + if i < mv'low then -- reading done + GOOD := true; + VALUE := mv; + return; + end if; + lastu := false; + end if; + read(L, c, readOk); + end loop; + else + GOOD := true; -- read into a null array + end if; + end procedure READ; + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_sfixed) is + variable c : CHARACTER; + variable readOk : BOOLEAN; + variable i : INTEGER; -- index variable + variable mv : sfixed (VALUE'range); + variable lastu : BOOLEAN := false; -- last character was an "_" + variable founddot : BOOLEAN := false; -- found a "." + begin -- READ + VALUE := (VALUE'range => 'U'); + Skip_whitespace (L); + if VALUE'length > 0 then -- non Null input string + read (l, c, readOk); + i := value'high; + while i >= VALUE'low loop + if readOk = false then -- Bail out if there was a bad read + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "End of string encountered" + severity error; + return; + elsif c = '_' then + if i = value'high then + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "String begins with an ""_""" severity error; + return; + elsif lastu then + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + elsif c = '.' then -- binary point + if founddot then + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "Two binary points found in input string" severity error; + return; + elsif i /= -1 then -- Seperator in the wrong spot + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "Decimal point does not match number format " + severity error; + return; + end if; + founddot := true; + lastu := false; + elsif c = ' ' or c = NBSP or c = HT then -- reading done. + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "Short read, Space encounted in input string" + severity error; + return; + elsif char_to_MVL9plus(c) = error then + report fixed_generic_pkg'instance_name & "READ(sfixed) " + & "Character '" & + c & "' read, expected STD_ULOGIC literal." + severity error; + return; + else + mv(i) := char_to_MVL9(c); + i := i - 1; + if i < mv'low then + VALUE := mv; + return; + end if; + lastu := false; + end if; + read(L, c, readOk); + end loop; + end if; + end procedure READ; + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN) is + variable value_ufixed : UNRESOLVED_ufixed (VALUE'range); + begin -- READ + READ (L => L, VALUE => value_ufixed, GOOD => GOOD); + VALUE := UNRESOLVED_sfixed (value_ufixed); + end procedure READ; + + -- octal read and write + procedure owrite ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + begin -- Example 03.30 + write (L => L, + VALUE => to_ostring (VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure owrite; + + procedure owrite ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + begin -- Example 03.30 + write (L => L, + VALUE => to_ostring (VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure owrite; + + -- Note that for Octal and Hex read, you can not start with a ".", + -- the read is for numbers formatted "A.BC". These routines go to + -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3). + procedure Char2TriBits (C : CHARACTER; + RESULT : out STD_ULOGIC_VECTOR(2 downto 0); + GOOD : out BOOLEAN; + ISSUE_ERROR : in BOOLEAN) is + begin + case c is + when '0' => result := o"0"; good := true; + when '1' => result := o"1"; good := true; + when '2' => result := o"2"; good := true; + when '3' => result := o"3"; good := true; + when '4' => result := o"4"; good := true; + when '5' => result := o"5"; good := true; + when '6' => result := o"6"; good := true; + when '7' => result := o"7"; good := true; + when 'Z' => result := "ZZZ"; good := true; + when 'X' => result := "XXX"; good := true; + when others => + assert not ISSUE_ERROR + report fixed_generic_pkg'instance_name + & "OREAD Error: Read a '" & c & + "', expected an Octal character (0-7)." + severity error; + result := "UUU"; + good := false; + end case; + end procedure Char2TriBits; + + -- purpose: Routines common to the OREAD routines + procedure OREAD_common ( + L : inout LINE; + slv : out STD_ULOGIC_VECTOR; + igood : out BOOLEAN; + idex : out INTEGER; + constant bpoint : in INTEGER; -- binary point + constant message : in BOOLEAN; + constant smath : in BOOLEAN) is + + -- purpose: error message routine + procedure errmes ( + constant mess : in STRING) is -- error message + begin + if message then + if smath then + report fixed_generic_pkg'instance_name + & "OREAD(sfixed) " + & mess + severity error; + else + report fixed_generic_pkg'instance_name + & "OREAD(ufixed) " + & mess + severity error; + end if; + end if; + end procedure errmes; + variable xgood : BOOLEAN; + variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits + variable c : CHARACTER; + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + variable founddot : BOOLEAN := false; -- found a dot. + begin + Skip_whitespace (L); + if slv'length > 0 then + i := slv'high; + read (l, c, xgood); + while i > 0 loop + if xgood = false then + errmes ("Error: end of string encountered"); + exit; + elsif c = '_' then + if i = slv'length then + errmes ("Error: String begins with an ""_"""); + xgood := false; + exit; + elsif lastu then + errmes ("Error: Two underscores detected in input string ""__"""); + xgood := false; + exit; + else + lastu := true; + end if; + elsif (c = '.') then + if (i + 1 /= bpoint) then + errmes ("encountered ""."" at wrong index"); + xgood := false; + exit; + elsif i = slv'length then + errmes ("encounted a ""."" at the beginning of the line"); + xgood := false; + exit; + elsif founddot then + errmes ("Two ""."" encounted in input string"); + xgood := false; + exit; + end if; + founddot := true; + lastu := false; + else + Char2triBits(c, nybble, xgood, message); + if not xgood then + exit; + end if; + slv (i downto i-2) := nybble; + i := i - 3; + lastu := false; + end if; + if i > 0 then + read (L, c, xgood); + end if; + end loop; + idex := i; + igood := xgood; + else + igood := true; -- read into a null array + idex := -1; + end if; + end procedure OREAD_common; + + -- Note that for Octal and Hex read, you can not start with a ".", + -- the read is for numbers formatted "A.BC". These routines go to + -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3). + procedure OREAD (L : inout LINE; + VALUE : out UNRESOLVED_ufixed) is + constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_ufixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + OREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => true, + smath => false); + if igood then -- We did not get another error + if not ((i = -1) and -- We read everything, and high bits 0 + (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then + report fixed_generic_pkg'instance_name + & "OREAD(ufixed): Vector truncated." + severity error; + else + if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "OREAD(ufixed): Vector truncated" + severity warning; + end if; + valuex := to_ufixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + end if; + end if; + end procedure OREAD; + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN) is + constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_ufixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + OREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => false, + smath => false); + if (igood and -- We did not get another error + (i = -1) and -- We read everything, and high bits 0 + (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then + valuex := to_ufixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + good := true; + else + good := false; + end if; + end procedure OREAD; + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed) is + constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_sfixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + OREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => true, + smath => true); + if igood then -- We did not get another error + if not ((i = -1) and -- We read everything + ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits + or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or + (slv(VALUE'high-lbv) = '1' and + and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then + report fixed_generic_pkg'instance_name + & "OREAD(sfixed): Vector truncated." + severity error; + else + if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "OREAD(sfixed): Vector truncated" + severity warning; + end if; + valuex := to_sfixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + end if; + end if; + end procedure OREAD; + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN) is + constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_sfixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + OREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => false, + smath => true); + if (igood -- We did not get another error + and (i = -1) -- We read everything + and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits + or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or + (slv(VALUE'high-lbv) = '1' and + and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then + valuex := to_sfixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + good := true; + else + good := false; + end if; + end procedure OREAD; + + -- hex read and write + procedure hwrite ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + begin -- Example 03.30 + write (L => L, + VALUE => to_hstring (VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure hwrite; + + -- purpose: writes fixed point into a line + procedure hwrite ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + begin -- Example 03.30 + write (L => L, + VALUE => to_hstring (VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure hwrite; + + -- Hex Read and Write procedures for STD_ULOGIC_VECTOR. + -- Modified from the original to be more forgiving. + + procedure Char2QuadBits (C : CHARACTER; + RESULT : out STD_ULOGIC_VECTOR(3 downto 0); + GOOD : out BOOLEAN; + ISSUE_ERROR : in BOOLEAN) is + begin + case c is + when '0' => result := x"0"; good := true; + when '1' => result := x"1"; good := true; + when '2' => result := x"2"; good := true; + when '3' => result := x"3"; good := true; + when '4' => result := x"4"; good := true; + when '5' => result := x"5"; good := true; + when '6' => result := x"6"; good := true; + when '7' => result := x"7"; good := true; + when '8' => result := x"8"; good := true; + when '9' => result := x"9"; good := true; + when 'A' | 'a' => result := x"A"; good := true; + when 'B' | 'b' => result := x"B"; good := true; + when 'C' | 'c' => result := x"C"; good := true; + when 'D' | 'd' => result := x"D"; good := true; + when 'E' | 'e' => result := x"E"; good := true; + when 'F' | 'f' => result := x"F"; good := true; + when 'Z' => result := "ZZZZ"; good := true; + when 'X' => result := "XXXX"; good := true; + when others => + assert not ISSUE_ERROR + report fixed_generic_pkg'instance_name + & "HREAD Error: Read a '" & c & + "', expected a Hex character (0-F)." + severity error; + result := "UUUU"; + good := false; + end case; + end procedure Char2QuadBits; + + -- purpose: Routines common to the HREAD routines + procedure HREAD_common ( + L : inout LINE; + slv : out STD_ULOGIC_VECTOR; + igood : out BOOLEAN; + idex : out INTEGER; + constant bpoint : in INTEGER; -- binary point + constant message : in BOOLEAN; + constant smath : in BOOLEAN) is + + -- purpose: error message routine + procedure errmes ( + constant mess : in STRING) is -- error message + begin + if message then + if smath then + report fixed_generic_pkg'instance_name + & "HREAD(sfixed) " + & mess + severity error; + else + report fixed_generic_pkg'instance_name + & "HREAD(ufixed) " + & mess + severity error; + end if; + end if; + end procedure errmes; + variable xgood : BOOLEAN; + variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits + variable c : CHARACTER; + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + variable founddot : BOOLEAN := false; -- found a dot. + begin + Skip_whitespace (L); + if slv'length > 0 then + i := slv'high; + read (l, c, xgood); + while i > 0 loop + if xgood = false then + errmes ("Error: end of string encountered"); + exit; + elsif c = '_' then + if i = slv'length then + errmes ("Error: String begins with an ""_"""); + xgood := false; + exit; + elsif lastu then + errmes ("Error: Two underscores detected in input string ""__"""); + xgood := false; + exit; + else + lastu := true; + end if; + elsif (c = '.') then + if (i + 1 /= bpoint) then + errmes ("encountered ""."" at wrong index"); + xgood := false; + exit; + elsif i = slv'length then + errmes ("encounted a ""."" at the beginning of the line"); + xgood := false; + exit; + elsif founddot then + errmes ("Two ""."" encounted in input string"); + xgood := false; + exit; + end if; + founddot := true; + lastu := false; + else + Char2QuadBits(c, nybble, xgood, message); + if not xgood then + exit; + end if; + slv (i downto i-3) := nybble; + i := i - 4; + lastu := false; + end if; + if i > 0 then + read (L, c, xgood); + end if; + end loop; + idex := i; + igood := xgood; + else + idex := -1; + igood := true; -- read null string + end if; + end procedure HREAD_common; + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed) is + constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_ufixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + HREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => false, + smath => false); + if igood then + if not ((i = -1) and -- We read everything, and high bits 0 + (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then + report fixed_generic_pkg'instance_name + & "HREAD(ufixed): Vector truncated." + severity error; + else + if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "HREAD(ufixed): Vector truncated" + severity warning; + end if; + valuex := to_ufixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + end if; + end if; + end procedure HREAD; + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN) is + constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_ufixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + HREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => false, + smath => false); + if (igood and -- We did not get another error + (i = -1) and -- We read everything, and high bits 0 + (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then + valuex := to_ufixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + good := true; + else + good := false; + end if; + end procedure HREAD; + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed) is + constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_sfixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + HREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => true, + smath => true); + if igood then -- We did not get another error + if not ((i = -1) -- We read everything + and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits + or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or + (slv(VALUE'high-lbv) = '1' and + and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then + report fixed_generic_pkg'instance_name + & "HREAD(sfixed): Vector truncated." + severity error; + else + if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then + assert NO_WARNING + report fixed_generic_pkg'instance_name + & "HREAD(sfixed): Vector truncated" + severity warning; + end if; + valuex := to_sfixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + end if; + end if; + end procedure HREAD; + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN) is + constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; + constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4; + variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits + variable valuex : UNRESOLVED_sfixed (hbv downto lbv); + variable igood : BOOLEAN; + variable i : INTEGER; + begin + VALUE := (VALUE'range => 'U'); + HREAD_common ( L => L, + slv => slv, + igood => igood, + idex => i, + bpoint => -lbv, + message => false, + smath => true); + if (igood and -- We did not get another error + (i = -1) and -- We read everything + ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits + or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or + (slv(VALUE'high-lbv) = '1' and + and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then + valuex := to_sfixed (slv, hbv, lbv); + VALUE := valuex (VALUE'range); + good := true; + else + good := false; + end if; + end procedure HREAD; + + -- To_string functions. Useful in "report" statements. + -- Example: report "result was " & to_string(result); + function to_string (value : UNRESOLVED_ufixed) return STRING is + variable s : STRING(1 to value'length +1) := (others => ' '); + variable subval : UNRESOLVED_ufixed (value'high downto -1); + variable sindx : INTEGER; + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + if value(value'high) = 'Z' then + return to_string (resize (sfixed(value), 0, value'low)); + else + return to_string (resize (value, 0, value'low)); + end if; + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_string(subval); + else + return to_string (resize (value, value'high, -1)); + end if; + else + sindx := 1; + for i in value'high downto value'low loop + if i = -1 then + s(sindx) := '.'; + sindx := sindx + 1; + end if; + s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); + sindx := sindx + 1; + end loop; + return s; + end if; + end if; + end function to_string; + + function to_string (value : UNRESOLVED_sfixed) return STRING is + variable s : STRING(1 to value'length + 1) := (others => ' '); + variable subval : UNRESOLVED_sfixed (value'high downto -1); + variable sindx : INTEGER; + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + return to_string (resize (value, 0, value'low)); + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_string(subval); + else + return to_string (resize (value, value'high, -1)); + end if; + else + sindx := 1; + for i in value'high downto value'low loop + if i = -1 then + s(sindx) := '.'; + sindx := sindx + 1; + end if; + s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); + sindx := sindx + 1; + end loop; + return s; + end if; + end if; + end function to_string; + + function to_ostring (value : UNRESOLVED_ufixed) return STRING is + constant lne : INTEGER := (-VALUE'low+2)/3; + variable subval : UNRESOLVED_ufixed (value'high downto -3); + variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1); + variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0); + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + if value(value'high) = 'Z' then + return to_ostring (resize (sfixed(value), 2, value'low)); + else + return to_ostring (resize (value, 2, value'low)); + end if; + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_ostring(subval); + else + return to_ostring (resize (value, value'high, -3)); + end if; + else + slv := to_sulv (value); + if Is_X (value (value'low)) then + lpad := (others => value (value'low)); + else + lpad := (others => '0'); + end if; + return to_ostring(slv(slv'high downto slv'high-VALUE'high)) + & "." + & to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad); + end if; + end if; + end function to_ostring; + + function to_hstring (value : UNRESOLVED_ufixed) return STRING is + constant lne : INTEGER := (-VALUE'low+3)/4; + variable subval : UNRESOLVED_ufixed (value'high downto -4); + variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1); + variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0); + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + if value(value'high) = 'Z' then + return to_hstring (resize (sfixed(value), 3, value'low)); + else + return to_hstring (resize (value, 3, value'low)); + end if; + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_hstring(subval); + else + return to_hstring (resize (value, value'high, -4)); + end if; + else + slv := to_sulv (value); + if Is_X (value (value'low)) then + lpad := (others => value(value'low)); + else + lpad := (others => '0'); + end if; + return to_hstring(slv(slv'high downto slv'high-VALUE'high)) + & "." + & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad); + end if; + end if; + end function to_hstring; + + function to_ostring (value : UNRESOLVED_sfixed) return STRING is + constant ne : INTEGER := ((value'high+1)+2)/3; + variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1); + constant lne : INTEGER := (-VALUE'low+2)/3; + variable subval : UNRESOLVED_sfixed (value'high downto -3); + variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1); + variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0); + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + return to_ostring (resize (value, 2, value'low)); + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_ostring(subval); + else + return to_ostring (resize (value, value'high, -3)); + end if; + else + pad := (others => value(value'high)); + slv := to_sulv (value); + if Is_X (value (value'low)) then + lpad := (others => value(value'low)); + else + lpad := (others => '0'); + end if; + return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high)) + & "." + & to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad); + end if; + end if; + end function to_ostring; + + function to_hstring (value : UNRESOLVED_sfixed) return STRING is + constant ne : INTEGER := ((value'high+1)+3)/4; + variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1); + constant lne : INTEGER := (-VALUE'low+3)/4; + variable subval : UNRESOLVED_sfixed (value'high downto -4); + variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1); + variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0); + begin + if value'length < 1 then + return NUS; + else + if value'high < 0 then + return to_hstring (resize (value, 3, value'low)); + elsif value'low >= 0 then + if Is_X (value(value'low)) then + subval := (others => value(value'low)); + subval (value'range) := value; + return to_hstring(subval); + else + return to_hstring (resize (value, value'high, -4)); + end if; + else + slv := to_sulv (value); + pad := (others => value(value'high)); + if Is_X (value (value'low)) then + lpad := (others => value(value'low)); + else + lpad := (others => '0'); + end if; + return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high)) + & "." + & to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad); + end if; + end if; + end function to_hstring; + + -- From string functions allow you to convert a string into a fixed + -- point number. Example: + -- signal uf1 : ufixed (3 downto -3); + -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 + -- The "." is optional in this syntax, however it exist and is + -- in the wrong location an error is produced. Overflow will + -- result in saturation. + function from_string ( + bstring : STRING; -- binary string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(bstring); + read (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_string: Bad string "& bstring severity error; + return result; + end function from_string; + + -- Octal and hex conversions work as follows: + -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) + -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) + function from_ostring ( + ostring : STRING; -- Octal string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(ostring); + oread (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_ostring: Bad string "& ostring severity error; + return result; + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(hstring); + hread (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_hstring: Bad string "& hstring severity error; + return result; + end function from_hstring; + + function from_string ( + bstring : STRING; -- binary string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(bstring); + read (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_string: Bad string "& bstring severity error; + return result; + end function from_string; + + function from_ostring ( + ostring : STRING; -- Octal string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(ostring); + oread (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_ostring: Bad string "& ostring severity error; + return result; + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (left_index downto right_index); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(hstring); + hread (L, result, good); + deallocate (L); + assert (good) + report fixed_generic_pkg'instance_name + & "from_hstring: Bad string "& hstring severity error; + return result; + end function from_hstring; + + -- Same as above, "size_res" is used for it's range only. + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return from_string (bstring, size_res'high, size_res'low); + end function from_string; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return from_ostring (ostring, size_res'high, size_res'low); + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed is + begin + return from_hstring(hstring, size_res'high, size_res'low); + end function from_hstring; + + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return from_string (bstring, size_res'high, size_res'low); + end function from_string; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return from_ostring (ostring, size_res'high, size_res'low); + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed is + begin + return from_hstring (hstring, size_res'high, size_res'low); + end function from_hstring; + + -- Direct conversion functions. Example: + -- signal uf1 : ufixed (3 downto -3); + -- uf1 <= from_string ("0110.100"); -- 6.5 + -- In this case the "." is not optional, and the size of + -- the output must match exactly. + -- purpose: Calculate the string boundaries + procedure calculate_string_boundry ( + arg : in STRING; -- input string + left_index : out INTEGER; -- left + right_index : out INTEGER) is -- right + -- examples "10001.111" would return +4, -3 + -- "07X.44" would return +2, -2 (then the octal routine would multiply) + -- "A_B_._C" would return +1, -1 (then the hex routine would multiply) + alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range + variable l, r : INTEGER; -- internal indexes + variable founddot : BOOLEAN := false; + begin + if arg'length > 0 then + l := xarg'high - 1; + r := 0; + for i in xarg'range loop + if xarg(i) = '_' then + if r = 0 then + l := l - 1; + else + r := r + 1; + end if; + elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then + report fixed_generic_pkg'instance_name + & "Found a space in the input STRING " & xarg + severity error; + elsif xarg(i) = '.' then + if founddot then + report fixed_generic_pkg'instance_name + & "Found two binary points in input string " & xarg + severity error; + else + l := l - i; + r := -i + 1; + founddot := true; + end if; + end if; + end loop; + left_index := l; + right_index := r; + else + left_index := 0; + right_index := 0; + end if; + end procedure calculate_string_boundry; + + -- Direct conversion functions. Example: + -- signal uf1 : ufixed (3 downto -3); + -- uf1 <= from_string ("0110.100"); -- 6.5 + -- In this case the "." is not optional, and the size of + -- the output must match exactly. + function from_string ( + bstring : STRING) -- binary string + return UNRESOLVED_ufixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (bstring, left_index, right_index); + return from_string (bstring, left_index, right_index); + end function from_string; + + -- Direct octal and hex conversion functions. In this case + -- the string lengths must match. Example: + -- signal sf1 := sfixed (5 downto -3); + -- sf1 <= from_ostring ("71.4") -- -6.5 + function from_ostring ( + ostring : STRING) -- Octal string + return UNRESOLVED_ufixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (ostring, left_index, right_index); + return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3); + end function from_ostring; + + function from_hstring ( + hstring : STRING) -- hex string + return UNRESOLVED_ufixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (hstring, left_index, right_index); + return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4); + end function from_hstring; + + function from_string ( + bstring : STRING) -- binary string + return UNRESOLVED_sfixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (bstring, left_index, right_index); + return from_string (bstring, left_index, right_index); + end function from_string; + + function from_ostring ( + ostring : STRING) -- Octal string + return UNRESOLVED_sfixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (ostring, left_index, right_index); + return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3); + end function from_ostring; + + function from_hstring ( + hstring : STRING) -- hex string + return UNRESOLVED_sfixed + is + variable left_index, right_index : INTEGER; + begin + calculate_string_boundry (hstring, left_index, right_index); + return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4); + end function from_hstring; + +end package body fixed_generic_pkg; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg.vhdl new file mode 100644 index 0000000..36a2aed --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_generic_pkg.vhdl @@ -0,0 +1,1439 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Fixed-point package (Generic package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary fixed point +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +use STD.TEXTIO.all; +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.fixed_float_types.all; + +package fixed_generic_pkg is + generic ( + -- Rounding routine to use in fixed point, fixed_round or fixed_truncate + fixed_round_style : fixed_round_style_type := fixed_round; + -- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap + fixed_overflow_style : fixed_overflow_style_type := fixed_saturate; + -- Extra bits used in divide routines + fixed_guard_bits : NATURAL := 3; + -- If TRUE, then turn off warnings on "X" propagation + no_warning : BOOLEAN := false + ); + + -- Author David Bishop (dbishop@vhdl.org) + constant CopyRightNotice : STRING := + "Copyright 2008 by IEEE. All rights reserved."; + + -- base Unsigned fixed point type, downto direction assumed + type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC; + -- base Signed fixed point type, downto direction assumed + type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC; + + alias U_ufixed is UNRESOLVED_ufixed; + alias U_sfixed is UNRESOLVED_sfixed; + + subtype ufixed is (resolved) UNRESOLVED_ufixed; + subtype sfixed is (resolved) UNRESOLVED_sfixed; + + --=========================================================================== + -- Arithmetic Operators: + --=========================================================================== + + -- Absolute value, 2's complement + -- abs sfixed(a downto b) = sfixed(a+1 downto b) + function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Negation, 2's complement + -- - sfixed(a downto b) = sfixed(a+1 downto b) + function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed; + + -- Addition + -- ufixed(a downto b) + ufixed(c downto d) + -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) + function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed(a downto b) + sfixed(c downto d) + -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) + function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Subtraction + -- ufixed(a downto b) - ufixed(c downto d) + -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) + function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed(a downto b) - sfixed(c downto d) + -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) + function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Multiplication + -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d) + function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d) + function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Division + -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) + function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) + function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Remainder + -- ufixed (a downto b) rem ufixed (c downto d) + -- = ufixed (minimum(a,c) downto minimum(b,d)) + function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed (a downto b) rem sfixed (c downto d) + -- = sfixed (minimum(a,c) downto minimum(b,d)) + function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Modulo + -- ufixed (a downto b) mod ufixed (c downto d) + -- = ufixed (minimum(a,c) downto minimum(b, d)) + function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed (a downto b) mod sfixed (c downto d) + -- = sfixed (c downto minimum(b, d)) + function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + ---------------------------------------------------------------------------- + -- In these routines the "real" or "natural" (integer) + -- are converted into a fixed point number and then the operation is + -- performed. It is assumed that the array will be large enough. + -- If the input is "real" then the real number is converted into a fixed of + -- the same size as the fixed point input. If the number is an "integer" + -- then it is converted into fixed with the range (l'high downto 0). + ---------------------------------------------------------------------------- + + -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b) + function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d) + function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) + function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) + function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b) + function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d) + function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) + function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) + function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b) + function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d) + function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) + function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) + function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) + function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) + function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1) + function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1) + function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b) + function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d) + function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0)) + function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0)) + function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b) + function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + + -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d) + function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0)) + function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; + + -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0)) + function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + + -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b) + function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d) + function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) + function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) + function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b) + function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d) + function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) + function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) + function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b) + function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d) + function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b) + function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d) + function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a) + function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c) + function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a) + function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c) + function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b) + function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d) + function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0)) + function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0)) + function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b) + function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + + -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d) + function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0)) + function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; + + -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0)) + function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- This version of divide gives the user more control + -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) + function divide ( + l, r : UNRESOLVED_ufixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + -- This version of divide gives the user more control + -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) + function divide ( + l, r : UNRESOLVED_sfixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + -- These functions return 1/X + -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) + function reciprocal ( + arg : UNRESOLVED_ufixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) + function reciprocal ( + arg : UNRESOLVED_sfixed; -- fixed point input + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + -- REM function + -- ufixed (a downto b) rem ufixed (c downto d) + -- = ufixed (minimum(a,c) downto minimum(b,d)) + function remainder ( + l, r : UNRESOLVED_ufixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + -- sfixed (a downto b) rem sfixed (c downto d) + -- = sfixed (minimum(a,c) downto minimum(b,d)) + function remainder ( + l, r : UNRESOLVED_sfixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + -- mod function + -- ufixed (a downto b) mod ufixed (c downto d) + -- = ufixed (minimum(a,c) downto minimum(b, d)) + function modulo ( + l, r : UNRESOLVED_ufixed; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + -- sfixed (a downto b) mod sfixed (c downto d) + -- = sfixed (c downto minimum(b, d)) + function modulo ( + l, r : UNRESOLVED_sfixed; + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + -- Procedure for those who need an "accumulator" function. + -- add_carry (ufixed(a downto b), ufixed (c downto d)) + -- = ufixed (maximum(a,c) downto minimum(b,d)) + procedure add_carry ( + L, R : in UNRESOLVED_ufixed; + c_in : in STD_ULOGIC; + result : out UNRESOLVED_ufixed; + c_out : out STD_ULOGIC); + + -- add_carry (sfixed(a downto b), sfixed (c downto d)) + -- = sfixed (maximum(a,c) downto minimum(b,d)) + procedure add_carry ( + L, R : in UNRESOLVED_sfixed; + c_in : in STD_ULOGIC; + result : out UNRESOLVED_sfixed; + c_out : out STD_ULOGIC); + + -- Scales the result by a power of 2. Width of input = width of output with + -- the binary point moved. + function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed; + function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed; + function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed; + function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed; + + function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN; + + --=========================================================================== + -- Comparison Operators + --=========================================================================== + + function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; + + function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; + + function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN; + function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN; + + -- Overloads the default "maximum" and "minimum" function + + function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + ---------------------------------------------------------------------------- + -- In these compare functions a natural is converted into a + -- fixed point number of the bounds "maximum(l'high,0) downto 0" + ---------------------------------------------------------------------------- + + function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; + + function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; + + function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; + + function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + + function maximum (l : UNRESOLVED_ufixed; r : NATURAL) + return UNRESOLVED_ufixed; + function minimum (l : UNRESOLVED_ufixed; r : NATURAL) + return UNRESOLVED_ufixed; + function maximum (l : NATURAL; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function minimum (l : NATURAL; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + ---------------------------------------------------------------------------- + -- In these compare functions a real is converted into a + -- fixed point number of the bounds "l'high+1 downto l'low" + ---------------------------------------------------------------------------- + + function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; + + function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; + + function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; + + function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; + + function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; + function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + ---------------------------------------------------------------------------- + -- In these compare functions an integer is converted into a + -- fixed point number of the bounds "maximum(l'high,1) downto 0" + ---------------------------------------------------------------------------- + + function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; + + function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; + + function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; + + function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; + + function maximum (l : UNRESOLVED_sfixed; r : INTEGER) + return UNRESOLVED_sfixed; + function maximum (l : INTEGER; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function minimum (l : UNRESOLVED_sfixed; r : INTEGER) + return UNRESOLVED_sfixed; + function minimum (l : INTEGER; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + ---------------------------------------------------------------------------- + -- In these compare functions a real is converted into a + -- fixed point number of the bounds "l'high+1 downto l'low" + ---------------------------------------------------------------------------- + + function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; + + function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; + + function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; + + function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; + + function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; + function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + --=========================================================================== + -- Shift and Rotate Functions. + -- Note that sra and sla are not the same as the BIT_VECTOR version + --=========================================================================== + + function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) + return UNRESOLVED_ufixed; + function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) + return UNRESOLVED_sfixed; + function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) + return UNRESOLVED_ufixed; + function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) + return UNRESOLVED_ufixed; + function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) + return UNRESOLVED_sfixed; + function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) + return UNRESOLVED_sfixed; + + ---------------------------------------------------------------------------- + -- logical functions + ---------------------------------------------------------------------------- + + function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- Vector and std_ulogic functions, same as functions in numeric_std + function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) + return UNRESOLVED_ufixed; + function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) + return UNRESOLVED_sfixed; + + -- Reduction operators, same as numeric_std functions + function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; + function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; + + -- returns arg'low-1 if not found + function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) + return INTEGER; + function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) + return INTEGER; + + -- returns arg'high+1 if not found + function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) + return INTEGER; + function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) + return INTEGER; + + --=========================================================================== + -- RESIZE Functions + --=========================================================================== + -- resizes the number (larger or smaller) + -- The returned result will be ufixed (left_index downto right_index) + -- If "round_style" is fixed_round, then the result will be rounded. + -- If the MSB of the remainder is a "1" AND the LSB of the unrounded result + -- is a '1' or the lower bits of the remainder include a '1' then the result + -- will be increased by the smallest representable number for that type. + -- "overflow_style" can be fixed_saturate or fixed_wrap. + -- In saturate mode, if the number overflows then the largest possible + -- representable number is returned. If wrap mode, then the upper bits + -- of the number are truncated. + + function resize ( + arg : UNRESOLVED_ufixed; -- input + constant left_index : INTEGER; -- integer portion + constant right_index : INTEGER; -- size of fraction + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + -- "size_res" functions create the size of the output from the indices + -- of the "size_res" input. The actual value of "size_res" is not used. + function resize ( + arg : UNRESOLVED_ufixed; -- input + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + -- Note that in "wrap" mode the sign bit is not replicated. Thus the + -- resize of a negative number can have a positive result in wrap mode. + function resize ( + arg : UNRESOLVED_sfixed; -- input + constant left_index : INTEGER; -- integer portion + constant right_index : INTEGER; -- size of fraction + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + function resize ( + arg : UNRESOLVED_sfixed; -- input + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + --=========================================================================== + -- Conversion Functions + --=========================================================================== + + -- integer (natural) to unsigned fixed point. + -- arguments are the upper and lower bounds of the number, thus + -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3); + function to_ufixed ( + arg : NATURAL; -- integer + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + function to_ufixed ( + arg : NATURAL; -- integer + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + -- real to unsigned fixed point + function to_ufixed ( + arg : REAL; -- real + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + function to_ufixed ( + arg : REAL; -- real + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_ufixed; + + -- unsigned to unsigned fixed point + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED; -- unsigned + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED; -- unsigned + size_res : UNRESOLVED_ufixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_ufixed; + + -- Performs a conversion. ufixed (arg'range) is returned + function to_ufixed ( + arg : UNRESOLVED_UNSIGNED) -- unsigned + return UNRESOLVED_ufixed; + + -- unsigned fixed point to unsigned + function to_unsigned ( + arg : UNRESOLVED_ufixed; -- fixed point input + constant size : NATURAL; -- length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_UNSIGNED; + + -- unsigned fixed point to unsigned + function to_unsigned ( + arg : UNRESOLVED_ufixed; -- fixed point input + size_res : UNRESOLVED_UNSIGNED; -- used for length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_UNSIGNED; + + -- unsigned fixed point to real + function to_real ( + arg : UNRESOLVED_ufixed) -- fixed point input + return REAL; + + -- unsigned fixed point to integer + function to_integer ( + arg : UNRESOLVED_ufixed; -- fixed point input + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return NATURAL; + + -- Integer to UNRESOLVED_sfixed + function to_sfixed ( + arg : INTEGER; -- integer + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + function to_sfixed ( + arg : INTEGER; -- integer + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + -- Real to sfixed + function to_sfixed ( + arg : REAL; -- real + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + function to_sfixed ( + arg : REAL; -- real + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style; + constant guard_bits : NATURAL := fixed_guard_bits) + return UNRESOLVED_sfixed; + + -- signed to sfixed + function to_sfixed ( + arg : UNRESOLVED_SIGNED; -- signed + constant left_index : INTEGER; -- left index (high index) + constant right_index : INTEGER := 0; -- right index + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + function to_sfixed ( + arg : UNRESOLVED_SIGNED; -- signed + size_res : UNRESOLVED_sfixed; -- for size only + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_sfixed; + + -- signed to sfixed (output assumed to be size of signed input) + function to_sfixed ( + arg : UNRESOLVED_SIGNED) -- signed + return UNRESOLVED_sfixed; + + -- Conversion from ufixed to sfixed + function to_sfixed ( + arg : UNRESOLVED_ufixed) + return UNRESOLVED_sfixed; + + -- signed fixed point to signed + function to_signed ( + arg : UNRESOLVED_sfixed; -- fixed point input + constant size : NATURAL; -- length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_SIGNED; + + -- signed fixed point to signed + function to_signed ( + arg : UNRESOLVED_sfixed; -- fixed point input + size_res : UNRESOLVED_SIGNED; -- used for length of output + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return UNRESOLVED_SIGNED; + + -- signed fixed point to real + function to_real ( + arg : UNRESOLVED_sfixed) -- fixed point input + return REAL; + + -- signed fixed point to integer + function to_integer ( + arg : UNRESOLVED_sfixed; -- fixed point input + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; + constant round_style : fixed_round_style_type := fixed_round_style) + return INTEGER; + + -- Because of the fairly complicated sizing rules in the fixed point + -- packages these functions are provided to compute the result ranges + -- Example: + -- signal uf1 : ufixed (3 downto -3); + -- signal uf2 : ufixed (4 downto -2); + -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto + -- ufixed_low (3, -3, '*', 4, -2)); + -- uf1multuf2 <= uf1 * uf2; + -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), + -- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -) + function ufixed_high (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER; + + function ufixed_low (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER; + + function sfixed_high (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER; + + function sfixed_low (left_index, right_index : INTEGER; + operation : CHARACTER := 'X'; + left_index2, right_index2 : INTEGER := 0) + return INTEGER; + + -- Same as above, but using the "size_res" input only for their ranges: + -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto + -- ufixed_low (uf1, '*', uf2)); + -- uf1multuf2 <= uf1 * uf2; + -- + function ufixed_high (size_res : UNRESOLVED_ufixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_ufixed) + return INTEGER; + + function ufixed_low (size_res : UNRESOLVED_ufixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_ufixed) + return INTEGER; + + function sfixed_high (size_res : UNRESOLVED_sfixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_sfixed) + return INTEGER; + + function sfixed_low (size_res : UNRESOLVED_sfixed; + operation : CHARACTER := 'X'; + size_res2 : UNRESOLVED_sfixed) + return INTEGER; + + -- purpose: returns a saturated number + function saturate ( + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed; + + -- purpose: returns a saturated number + function saturate ( + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed; + + function saturate ( + size_res : UNRESOLVED_ufixed) -- only the size of this is used + return UNRESOLVED_ufixed; + + function saturate ( + size_res : UNRESOLVED_sfixed) -- only the size of this is used + return UNRESOLVED_sfixed; + + --=========================================================================== + -- Translation Functions + --=========================================================================== + + -- maps meta-logical values + function to_01 ( + s : UNRESOLVED_ufixed; -- fixed point input + constant XMAP : STD_ULOGIC := '0') -- Map x to + return UNRESOLVED_ufixed; + + -- maps meta-logical values + function to_01 ( + s : UNRESOLVED_sfixed; -- fixed point input + constant XMAP : STD_ULOGIC := '0') -- Map x to + return UNRESOLVED_sfixed; + + function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN; + function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN; + function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; + function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; + + -- straight vector conversion routines, needed for synthesis. + -- These functions are here so that a std_logic_vector can be + -- converted to and from sfixed and ufixed. Note that you can + -- not convert these vectors because of their negative index. + + function to_slv ( + arg : UNRESOLVED_ufixed) -- fixed point vector + return STD_LOGIC_VECTOR; + alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed + return STD_LOGIC_VECTOR]; + alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed + return STD_LOGIC_VECTOR]; + + function to_slv ( + arg : UNRESOLVED_sfixed) -- fixed point vector + return STD_LOGIC_VECTOR; + alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed + return STD_LOGIC_VECTOR]; + alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed + return STD_LOGIC_VECTOR]; + + function to_sulv ( + arg : UNRESOLVED_ufixed) -- fixed point vector + return STD_ULOGIC_VECTOR; + alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed + return STD_ULOGIC_VECTOR]; + alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed + return STD_ULOGIC_VECTOR]; + + function to_sulv ( + arg : UNRESOLVED_sfixed) -- fixed point vector + return STD_ULOGIC_VECTOR; + alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed + return STD_ULOGIC_VECTOR]; + alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed + return STD_ULOGIC_VECTOR]; + + function to_ufixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed; + + function to_ufixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + size_res : UNRESOLVED_ufixed) -- for size only + return UNRESOLVED_ufixed; + + function to_sfixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed; + + function to_sfixed ( + arg : STD_ULOGIC_VECTOR; -- shifted vector + size_res : UNRESOLVED_sfixed) -- for size only + return UNRESOLVED_sfixed; + + -- As a concession to those who use a graphical DSP environment, + -- these functions take parameters in those tools format and create + -- fixed point numbers. These functions are designed to convert from + -- a std_logic_vector to the VHDL fixed point format using the conventions + -- of these packages. In a pure VHDL environment you should use the + -- "to_ufixed" and "to_sfixed" routines. + + -- unsigned fixed point + function to_UFix ( + arg : STD_ULOGIC_VECTOR; + width : NATURAL; -- width of vector + fraction : NATURAL) -- width of fraction + return UNRESOLVED_ufixed; + + -- signed fixed point + function to_SFix ( + arg : STD_ULOGIC_VECTOR; + width : NATURAL; -- width of vector + fraction : NATURAL) -- width of fraction + return UNRESOLVED_sfixed; + + -- finding the bounds of a number. These functions can be used like this: + -- signal xxx : ufixed (7 downto -3); + -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" + -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) + -- downto UFix_low(11, 3, "+", 11, 3)); + -- Where "11" is the width of xxx (xxx'length), + -- and 3 is the lower bound (abs (xxx'low)) + -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" + + function UFix_high (width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER; + + function UFix_low (width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER; + + -- Same as above but for signed fixed point. Note that the width + -- of a signed fixed point number ignores the sign bit, thus + -- width = sxxx'length-1 + + function SFix_high (width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER; + + function SFix_low (width, fraction : NATURAL; + operation : CHARACTER := 'X'; + width2, fraction2 : NATURAL := 0) + return INTEGER; + + --=========================================================================== + -- string and textio Functions + --=========================================================================== + + -- purpose: writes fixed point into a line + procedure WRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + -- purpose: writes fixed point into a line + procedure WRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_ufixed); + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN); + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_sfixed); + + procedure READ(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN); + + alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; + alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; + alias bread is READ [LINE, UNRESOLVED_ufixed]; + alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; + alias bread is READ [LINE, UNRESOLVED_sfixed]; + alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; + alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; + alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; + alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; + alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed]; + alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; + alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed]; + + -- octal read and write + procedure OWRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + procedure OWRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed); + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN); + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed); + + procedure OREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN); + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed]; + alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; + alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; + + -- hex read and write + procedure HWRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_ufixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + -- purpose: writes fixed point into a line + procedure HWRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_sfixed; -- fixed point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0); + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed); + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_ufixed; + GOOD : out BOOLEAN); + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed); + + procedure HREAD(L : inout LINE; + VALUE : out UNRESOLVED_sfixed; + GOOD : out BOOLEAN); + alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed]; + alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; + alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; + + -- returns a string, useful for: + -- assert (x = y) report "error found " & to_string(x) severity error; + function to_string (value : UNRESOLVED_ufixed) return STRING; + + alias to_bstring is to_string [UNRESOLVED_ufixed return STRING]; + alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING]; + + function to_ostring (value : UNRESOLVED_ufixed) return STRING; + alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING]; + + function to_hstring (value : UNRESOLVED_ufixed) return STRING; + alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING]; + + function to_string (value : UNRESOLVED_sfixed) return STRING; + alias to_bstring is to_string [UNRESOLVED_sfixed return STRING]; + alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING]; + + function to_ostring (value : UNRESOLVED_sfixed) return STRING; + alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING]; + + function to_hstring (value : UNRESOLVED_sfixed) return STRING; + alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING]; + + -- From string functions allow you to convert a string into a fixed + -- point number. Example: + -- signal uf1 : ufixed (3 downto -3); + -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 + -- The "." is optional in this syntax, however it exist and is + -- in the wrong location an error is produced. Overflow will + -- result in saturation. + + function from_string ( + bstring : STRING; -- binary string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed; + alias from_bstring is from_string [STRING, INTEGER, INTEGER + return UNRESOLVED_ufixed]; + alias from_binary_string is from_string [STRING, INTEGER, INTEGER + return UNRESOLVED_ufixed]; + + -- Octal and hex conversions work as follows: + -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) + -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) + + function from_ostring ( + ostring : STRING; -- Octal string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed; + alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER + return UNRESOLVED_ufixed]; + + function from_hstring ( + hstring : STRING; -- hex string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_ufixed; + alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER + return UNRESOLVED_ufixed]; + + function from_string ( + bstring : STRING; -- binary string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed; + alias from_bstring is from_string [STRING, INTEGER, INTEGER + return UNRESOLVED_sfixed]; + alias from_binary_string is from_string [STRING, INTEGER, INTEGER + return UNRESOLVED_sfixed]; + + function from_ostring ( + ostring : STRING; -- Octal string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed; + alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER + return UNRESOLVED_sfixed]; + + function from_hstring ( + hstring : STRING; -- hex string + constant left_index : INTEGER; + constant right_index : INTEGER) + return UNRESOLVED_sfixed; + alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER + return UNRESOLVED_sfixed]; + + -- Same as above, "size_res" is used for it's range only. + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + alias from_bstring is from_string [STRING, UNRESOLVED_ufixed + return UNRESOLVED_ufixed]; + alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed + return UNRESOLVED_ufixed]; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed + return UNRESOLVED_ufixed]; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_ufixed) + return UNRESOLVED_ufixed; + alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed + return UNRESOLVED_ufixed]; + + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + alias from_bstring is from_string [STRING, UNRESOLVED_sfixed + return UNRESOLVED_sfixed]; + alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed + return UNRESOLVED_sfixed]; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed + return UNRESOLVED_sfixed]; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_sfixed) + return UNRESOLVED_sfixed; + alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed + return UNRESOLVED_sfixed]; + + -- Direct conversion functions. Example: + -- signal uf1 : ufixed (3 downto -3); + -- uf1 <= from_string ("0110.100"); -- 6.5 + -- In this case the "." is not optional, and the size of + -- the output must match exactly. + + function from_string ( + bstring : STRING) -- binary string + return UNRESOLVED_ufixed; + alias from_bstring is from_string [STRING return UNRESOLVED_ufixed]; + alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed]; + + -- Direct octal and hex conversion functions. In this case + -- the string lengths must match. Example: + -- signal sf1 := sfixed (5 downto -3); + -- sf1 <= from_ostring ("71.4") -- -6.5 + + function from_ostring ( + ostring : STRING) -- Octal string + return UNRESOLVED_ufixed; + alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed]; + + function from_hstring ( + hstring : STRING) -- hex string + return UNRESOLVED_ufixed; + alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed]; + + function from_string ( + bstring : STRING) -- binary string + return UNRESOLVED_sfixed; + alias from_bstring is from_string [STRING return UNRESOLVED_sfixed]; + alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed]; + + function from_ostring ( + ostring : STRING) -- Octal string + return UNRESOLVED_sfixed; + alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed]; + + function from_hstring ( + hstring : STRING) -- hex string + return UNRESOLVED_sfixed; + alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed]; + +end package fixed_generic_pkg; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_pkg.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_pkg.vhdl new file mode 100644 index 0000000..1e2ef1a --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_pkg.vhdl @@ -0,0 +1,51 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Fixed-point package (Instantiated package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary fixed point +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library IEEE; + +package fixed_pkg is new IEEE.fixed_generic_pkg + generic map ( + fixed_round_style => IEEE.fixed_float_types.fixed_round, + fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate, + fixed_guard_bits => 3, + no_warning => false + ); diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg-body.vhdl new file mode 100644 index 0000000..f02f926 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg-body.vhdl @@ -0,0 +1,5715 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Floating-point package (Generic package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary floating point +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package body float_generic_pkg is + + -- Author David Bishop (dbishop@vhdl.org) + ----------------------------------------------------------------------------- + -- type declarations + ----------------------------------------------------------------------------- + + -- This deferred constant will tell you if the package body is synthesizable + -- or implemented as real numbers, set to "true" if synthesizable. + constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant + + -- types of boundary conditions + type boundary_type is (normal, infinity, zero, denormal); + + -- null range array constant + constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); + constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); + + -- Special version of "minimum" to do some boundary checking + function mine (L, R : INTEGER) + return INTEGER is + begin -- function minimum + if (L = INTEGER'low or R = INTEGER'low) then + report float_generic_pkg'instance_name + & " Unbounded number passed, was a literal used?" + severity error; + return 0; + end if; + return minimum (L, R); + end function mine; + + -- Generates the base number for the exponent normalization offset. + function gen_expon_base ( + constant exponent_width : NATURAL) + return SIGNED + is + variable result : SIGNED (exponent_width-1 downto 0); + begin + result := (others => '1'); + result (exponent_width-1) := '0'; + return result; + end function gen_expon_base; + + -- Integer version of the "log2" command (contributed by Peter Ashenden) + function log2 (A : NATURAL) return NATURAL is + variable quotient : NATURAL; + variable result : NATURAL := 0; + begin + quotient := A / 2; + while quotient > 0 loop + quotient := quotient / 2; + result := result + 1; + end loop; + return result; + end function log2; + + -- Function similar to the ILOGB function in MATH_REAL + function log2 (A : REAL) return INTEGER is + variable Y : REAL; + variable N : INTEGER := 0; + begin + if (A = 1.0 or A = 0.0) then + return 0; + end if; + Y := A; + if(A > 1.0) then + while Y >= 2.0 loop + Y := Y / 2.0; + N := N + 1; + end loop; + return N; + end if; + -- O < Y < 1 + while Y < 1.0 loop + Y := Y * 2.0; + N := N - 1; + end loop; + return N; + end function log2; + + -- purpose: Test the boundary conditions of a Real number + procedure test_boundary ( + arg : in REAL; -- Input, converted to real + constant fraction_width : in NATURAL; -- length of FP output fraction + constant exponent_width : in NATURAL; -- length of FP exponent + constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP + variable btype : out boundary_type; + variable log2i : out INTEGER + ) is + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + constant exp_min : SIGNED (12 downto 0) := + -(resize(expon_base, 13)) + 1; -- Minimum normal exponent + constant exp_ext_min : SIGNED (12 downto 0) := + exp_min - fraction_width; -- Minimum for denormal exponent + variable log2arg : INTEGER; -- log2 of argument + begin -- function test_boundary + -- Check to see if the exponent is big enough + -- Note that the argument is always an absolute value at this point. + log2arg := log2(arg); + if arg = 0.0 then + btype := zero; + elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) + btype := normal; + else + if log2arg < to_integer(exp_min) then + if denormalize then + if log2arg < to_integer(exp_ext_min) then + btype := zero; + else + btype := denormal; + end if; + else + if log2arg < to_integer(exp_min)-1 then + btype := zero; + else + btype := normal; -- Can still represent this number + end if; + end if; + elsif exponent_width < 11 then + if log2arg > to_integer(expon_base)+1 then + btype := infinity; + else + btype := normal; + end if; + else + btype := normal; + end if; + end if; + log2i := log2arg; + end procedure test_boundary; + + -- purpose: Rounds depending on the state of the "round_style" + -- Logic taken from + -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" + -- by David Goldberg (1991) + function check_round ( + fract_in : STD_ULOGIC; -- input fraction + sign : STD_ULOGIC; -- sign bit + remainder : UNSIGNED; -- remainder to round from + sticky : STD_ULOGIC := '0'; -- Sticky bit + constant round_style : round_type) -- rounding type + return BOOLEAN + is + variable result : BOOLEAN; + variable or_reduced : STD_ULOGIC; + begin -- function check_round + result := false; + if (remainder'length > 0) then -- if remainder in a null array + or_reduced := or (remainder & sticky); + rounding_case : case round_style is + when round_nearest => -- Round Nearest, default mode + if remainder(remainder'high) = '1' then -- round + if (remainder'length > 1) then + if ((or (remainder(remainder'high-1 + downto remainder'low)) = '1' + or sticky = '1') + or fract_in = '1') then + -- Make the bottom bit zero if possible if we are at 1/2 + result := true; + end if; + else + result := (fract_in = '1' or sticky = '1'); + end if; + end if; + when round_inf => -- round up if positive, else truncate. + if or_reduced = '1' and sign = '0' then + result := true; + end if; + when round_neginf => -- round down if negative, else truncate. + if or_reduced = '1' and sign = '1' then + result := true; + end if; + when round_zero => -- round toward 0 Truncate + null; + end case rounding_case; + end if; + return result; + end function check_round; + + -- purpose: Rounds depending on the state of the "round_style" + -- unsigned version + procedure fp_round ( + fract_in : in UNSIGNED; -- input fraction + expon_in : in SIGNED; -- input exponent + fract_out : out UNSIGNED; -- output fraction + expon_out : out SIGNED) is -- output exponent + begin -- procedure fp_round + if and (fract_in) = '1' then -- Fraction is all "1" + expon_out := expon_in + 1; + fract_out := to_unsigned(0, fract_out'high+1); + else + expon_out := expon_in; + fract_out := fract_in + 1; + end if; + end procedure fp_round; + + -- This version of break_number doesn't call "classfp" + procedure break_number ( -- internal version + arg : in UNRESOLVED_float; + fptyp : in valid_fpstate; + denormalize : in BOOLEAN := true; + fract : out UNSIGNED; + expon : out SIGNED) is + constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction + constant exponent_width : NATURAL := arg'high; -- length of FP output exponent + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable exp : SIGNED (expon'range); + begin + fract (fraction_width-1 downto 0) := + UNSIGNED (to_slv(arg(-1 downto -fraction_width))); + breakcase : case fptyp is + when pos_zero | neg_zero => + fract (fraction_width) := '0'; + exp := -expon_base; + when pos_denormal | neg_denormal => + if denormalize then + exp := -expon_base; + fract (fraction_width) := '0'; + else + exp := -expon_base - 1; + fract (fraction_width) := '1'; + end if; + when pos_normal | neg_normal | pos_inf | neg_inf => + fract (fraction_width) := '1'; + exp := SIGNED(arg(exponent_width-1 downto 0)); + exp (exponent_width-1) := not exp(exponent_width-1); + when others => + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "BREAK_NUMBER: " & + "Meta state detected in fp_break_number process" + severity warning; + -- complete the case, if a NAN goes in, a NAN comes out. + exp := (others => '1'); + fract (fraction_width) := '1'; + end case breakcase; + expon := exp; + end procedure break_number; + + -- purpose: floating point to UNSIGNED + -- Used by to_integer, to_unsigned, and to_signed functions + procedure float_to_unsigned ( + arg : in UNRESOLVED_float; -- floating point input + variable sign : out STD_ULOGIC; -- sign of output + variable frac : out UNSIGNED; -- unsigned biased output + constant denormalize : in BOOLEAN; -- turn on denormalization + constant bias : in NATURAL; -- bias for fixed point + constant round_style : in round_type) is -- rounding method + constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction + constant exponent_width : INTEGER := arg'high; -- length of FP output exponent + variable fract : UNSIGNED (frac'range); -- internal version of frac + variable isign : STD_ULOGIC; -- internal version of sign + variable exp : INTEGER; -- Exponent + variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp + -- Base to divide fraction by + variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted + variable shift : INTEGER; + variable remainder : UNSIGNED (2 downto 0); + variable round : STD_ULOGIC; -- round BIT + begin + isign := to_x01(arg(arg'high)); + -- exponent /= '0', normal floating point + expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); + expon(exponent_width-1) := not expon(exponent_width-1); + exp := to_integer (expon); + -- Figure out the fraction + fract := (others => '0'); -- fill with zero + fract (fract'high) := '1'; -- Add the "1.0". + shift := (fract'high-1) - exp; + if fraction_width > fract'high then -- Can only use size-2 bits + fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto + -fract'high))); + else -- can use all bits + fract (fract'high-1 downto fract'high-fraction_width) := + UNSIGNED (to_slv (arg(-1 downto -fraction_width))); + end if; + frac_shift := fract & "000"; + if shift < 0 then -- Overflow + fract := (others => '1'); + else + frac_shift := shift_right (frac_shift, shift); + fract := frac_shift (frac_shift'high downto 3); + remainder := frac_shift (2 downto 0); + -- round (round_zero will bypass this and truncate) + case round_style is + when round_nearest => + round := remainder(2) and + (fract (0) or (or (remainder (1 downto 0)))); + when round_inf => + round := remainder(2) and not isign; + when round_neginf => + round := remainder(2) and isign; + when others => + round := '0'; + end case; + if round = '1' then + fract := fract + 1; + end if; + end if; + frac := fract; + sign := isign; + end procedure float_to_unsigned; + + -- purpose: returns a part of a vector, this function is here because + -- or (fractr (to_integer(shiftx) downto 0)); + -- can't be synthesized in some synthesis tools. + function smallfract ( + arg : UNSIGNED; + shift : NATURAL) + return STD_ULOGIC + is + variable orx : STD_ULOGIC; + begin + orx := arg(shift); + for i in arg'range loop + if i < shift then + orx := arg(i) or orx; + end if; + end loop; + return orx; + end function smallfract; + --------------------------------------------------------------------------- + -- Visible functions + --------------------------------------------------------------------------- + + -- purpose: converts the negative index to a positive one + -- negative indices are illegal in 1164 and 1076.3 + function to_sulv ( + arg : UNRESOLVED_float) -- fp vector + return STD_ULOGIC_VECTOR + is + variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); + begin -- function to_std_ulogic_vector + if arg'length < 1 then + return NSLV; + end if; + result := STD_ULOGIC_VECTOR (arg); + return result; + end function to_sulv; + + -- Converts an fp into an SULV + function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is + begin + return to_sulv (arg); + end function to_slv; + + -- purpose: normalizes a floating point number + -- This version assumes an "unsigned" input with + function normalize ( + fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized + expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 + sign : STD_ULOGIC; -- sign BIT + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent + constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float + is + variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction + variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction + variable exp : SIGNED (exponent_width+1 downto 0); -- exponent + variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent + variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result + variable shiftr : INTEGER; -- shift amount + variable stickyx : STD_ULOGIC; -- version of sticky + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable round, zerores, infres : BOOLEAN; + begin -- function normalize + zerores := false; + infres := false; + round := false; + shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" + - fraction_width - nguard; -- subtract the length we want + exp := resize (expon, exp'length) + shiftr; + if (or (fract) = '0') then -- Zero + zerores := true; + elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) + or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then + if (exp >= -resize(expon_base, exp'length)-fraction_width-1) + and denormalize then + exp := -resize(expon_base, exp'length)-1; + shiftr := -to_integer (expon + expon_base); -- new shift + else -- return zero + zerores := true; + end if; + elsif (exp > expon_base-1) then -- infinity + infres := true; + end if; + if zerores then + result := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif infres then + result := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + sfract := fract srl shiftr; -- shift + if shiftr > 0 then +-- stickyx := sticky or (or (fract (shiftr-1 downto 0))); + stickyx := sticky or smallfract (fract, shiftr-1); + else + stickyx := sticky; + end if; + if nguard > 0 then + round := check_round ( + fract_in => sfract (nguard), + sign => sign, + remainder => sfract(nguard-1 downto 0), + sticky => stickyx, + round_style => round_style); + end if; + if round then + fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), + expon_in => exp(rexp'range), + fract_out => rfract, + expon_out => rexp); + else + rfract := sfract (fraction_width-1+nguard downto nguard); + rexp := exp(rexp'range); + end if; + -- result + rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); + rexpon (exponent_width-1) := not rexpon(exponent_width-1); + result (rexpon'range) := UNRESOLVED_float(rexpon); + result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); + end if; + result (exponent_width) := sign; -- sign BIT + return result; + end function normalize; + + -- purpose: normalizes a floating point number + -- This version assumes a "ufixed" input + function normalize ( + fract : UNRESOLVED_ufixed; -- unsigned fixed point + expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent + constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable arguns : UNSIGNED (fract'high + fraction_width + nguard + downto 0) := (others => '0'); + begin -- function normalize + arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := + UNSIGNED (to_slv (fract)); + result := normalize (fract => arguns, + expon => expon, + sign => sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => nguard); + return result; + end function normalize; + + -- purpose: normalizes a floating point number + -- This version assumes a "ufixed" input with a "size_res" input + function normalize ( + fract : UNRESOLVED_ufixed; -- unsigned fixed point + expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + size_res : UNRESOLVED_float; -- used for sizing only + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -size_res'low; + constant exponent_width : NATURAL := size_res'high; + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable arguns : UNSIGNED (fract'high + fraction_width + nguard + downto 0) := (others => '0'); + begin -- function normalize + arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := + UNSIGNED (to_slv (fract)); + result := normalize (fract => arguns, + expon => expon, + sign => sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => nguard); + return result; + end function normalize; + + -- Regular "normalize" function with a "size_res" input. + function normalize ( + fract : UNRESOLVED_UNSIGNED; -- unsigned + expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + size_res : UNRESOLVED_float; -- used for sizing only + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float is + begin + return normalize (fract => fract, + expon => expon, + sign => sign, + sticky => sticky, + fraction_width => -size_res'low, + exponent_width => size_res'high, + round_style => round_style, + denormalize => denormalize, + nguard => nguard); + end function normalize; + + -- Returns the class which X falls into + function Classfp ( + x : UNRESOLVED_float; -- floating point input + check_error : BOOLEAN := float_check_error) -- check for errors + return valid_fpstate + is + constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction + constant exponent_width : INTEGER := x'high; -- length of FP output exponent + variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- classfp + if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 + or x'left < x'right) then + report FLOAT_GENERIC_PKG'instance_name + & "CLASSFP: " & + "Floating point number detected with a bad range" + severity error; + return isx; + end if; + -- Check for "X". + arg := to_01 (x, 'X'); + if (arg(0) = 'X') then + return isx; -- If there is an X in the number + -- Special cases, check for illegal number + elsif check_error and + (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) + = '1') then -- Exponent is all "1". + if or (to_slv (arg (-1 downto -fraction_width))) + /= '0' then -- Fraction must be all "0" or this is not a number. + if (arg(-1) = '1') then -- From "W. Khan - IEEE standard + return nan; -- 754 binary FP Signaling nan (Not a number) + else + return quiet_nan; + end if; + -- Check for infinity + elsif arg(exponent_width) = '0' then + return pos_inf; -- Positive infinity + else + return neg_inf; -- Negative infinity + end if; + -- check for "0" + elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) + = '0' then -- Exponent is all "0" + if or (to_slv (arg (-1 downto -fraction_width))) + = '0' then -- Fraction is all "0" + if arg(exponent_width) = '0' then + return pos_zero; -- Zero + else + return neg_zero; + end if; + else + if arg(exponent_width) = '0' then + return pos_denormal; -- Denormal number (ieee extended fp) + else + return neg_denormal; + end if; + end if; + else + if arg(exponent_width) = '0' then + return pos_normal; -- Normal FP number + else + return neg_normal; + end if; + end if; + end function Classfp; + + procedure break_number ( + arg : in UNRESOLVED_float; + denormalize : in BOOLEAN := float_denormalize; + check_error : in BOOLEAN := float_check_error; + fract : out UNRESOLVED_UNSIGNED; + expon : out UNRESOLVED_SIGNED; + sign : out STD_ULOGIC) is + constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction + variable fptyp : valid_fpstate; + begin + fptyp := Classfp (arg, check_error); + sign := to_x01(arg(arg'high)); + break_number ( + arg => arg, + fptyp => fptyp, + denormalize => denormalize, + fract => fract, + expon => expon); + end procedure break_number; + + procedure break_number ( + arg : in UNRESOLVED_float; + denormalize : in BOOLEAN := float_denormalize; + check_error : in BOOLEAN := float_check_error; + fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width + expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 + sign : out STD_ULOGIC) is + constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction + variable fptyp : valid_fpstate; + variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction + begin + fptyp := Classfp (arg, check_error); + sign := to_x01(arg(arg'high)); + break_number ( + arg => arg, + fptyp => fptyp, + denormalize => denormalize, + fract => ufract, + expon => expon); + fract (0 downto -fraction_width) := ufixed (ufract); + end procedure break_number; + + -- Arithmetic functions + function "abs" ( + arg : UNRESOLVED_float) -- floating point input + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (arg'range); -- result + begin + if (arg'length > 0) then + result := to_01 (arg, 'X'); + result (arg'high) := '0'; -- set the sign bit to positive + return result; + else + return NAFP; + end if; + end function "abs"; + + -- IEEE 754 "negative" function + function "-" ( + arg : UNRESOLVED_float) -- floating point input + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (arg'range); -- result + begin + if (arg'length > 0) then + result := to_01 (arg, 'X'); + result (arg'high) := not result (arg'high); -- invert sign bit + return result; + else + return NAFP; + end if; + end function "-"; + + -- Addition, adds two floating point numbers + function add ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + constant addguard : NATURAL := guard; -- add one guard bit + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions + variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables + variable urfract, ulfract : UNSIGNED (fraction_width downto 0); + variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); + variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents + variable rexpon : SIGNED (exponent_width downto 0); -- result exponent + variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions + variable sign : STD_ULOGIC; -- sign of the output + variable leftright : BOOLEAN; -- left or right used + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + variable sticky : STD_ULOGIC; -- Holds precision for rounding + begin -- addition + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + if (lfptype = isx or rfptype = isx) then + fpresult := (others => 'X'); + elsif (lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan) + -- Return quiet NAN, IEEE754-1985-7.1,1 + or (lfptype = pos_inf and rfptype = neg_inf) + or (lfptype = neg_inf and rfptype = pos_inf) then + -- Return quiet NAN, IEEE754-1985-7.1,2 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf + fpresult := neg_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 + fpresult := neg_zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => ulfract, + expon => exponl); + fractl := (others => '0'); + fractl (fraction_width+addguard downto addguard) := ulfract; + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => urfract, + expon => exponr); + fractr := (others => '0'); + fractr (fraction_width+addguard downto addguard) := urfract; + shiftx := (exponl(exponent_width-1) & exponl) - exponr; + if shiftx < -fractl'high then + rexpon := exponr(exponent_width-1) & exponr; + fractc := fractr; + fracts := (others => '0'); -- add zero + leftright := false; + sticky := or (fractl); + elsif shiftx < 0 then + shiftx := - shiftx; + fracts := shift_right (fractl, to_integer(shiftx)); + fractc := fractr; + rexpon := exponr(exponent_width-1) & exponr; + leftright := false; +-- sticky := or (fractl (to_integer(shiftx) downto 0)); + sticky := smallfract (fractl, to_integer(shiftx)); + elsif shiftx = 0 then + rexpon := exponl(exponent_width-1) & exponl; + sticky := '0'; + if fractr > fractl then + fractc := fractr; + fracts := fractl; + leftright := false; + else + fractc := fractl; + fracts := fractr; + leftright := true; + end if; + elsif shiftx > fractr'high then + rexpon := exponl(exponent_width-1) & exponl; + fracts := (others => '0'); -- add zero + fractc := fractl; + leftright := true; + sticky := or (fractr); + elsif shiftx > 0 then + fracts := shift_right (fractr, to_integer(shiftx)); + fractc := fractl; + rexpon := exponl(exponent_width-1) & exponl; + leftright := true; +-- sticky := or (fractr (to_integer(shiftx) downto 0)); + sticky := smallfract (fractr, to_integer(shiftx)); + end if; + -- add + fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB + if l(l'high) = r(r'high) then + ufract := fractc + fracts; + sign := l(l'high); + else -- signs are different + ufract := fractc - fracts; -- always positive result + if leftright then -- Figure out which sign to use + sign := l(l'high); + else + sign := r(r'high); + end if; + end if; + if or (ufract) = '0' then + sign := '0'; -- IEEE 854, 6.3, paragraph 2. + end if; + -- normalize + fpresult := normalize (fract => ufract, + expon => rexpon, + sign => sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => addguard); + end if; + return fpresult; + end function add; + + -- Subtraction, Calls "add". + function subtract ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + variable negr : UNRESOLVED_float (r'range); -- negative version of r + begin + negr := -r; -- r := -r + return add (l => l, + r => negr, + round_style => round_style, + guard => guard, + check_error => check_error, + denormalize => denormalize); + end function subtract; + + -- Floating point multiply + function multiply ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + constant multguard : NATURAL := guard; -- guard bits + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions + variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction + variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction + variable shifty : INTEGER; -- denormal shift + variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents + variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent + variable fp_sign : STD_ULOGIC; -- sign of result + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + variable sticky : STD_ULOGIC; -- Holds precision for rounding + begin -- multiply + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + if (lfptype = isx or rfptype = isx) then + fpresult := (others => 'X'); + elsif ((lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan)) then + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (((lfptype = pos_inf or lfptype = neg_inf) and + (rfptype = pos_zero or rfptype = neg_zero)) or + ((rfptype = pos_inf or rfptype = neg_inf) and + (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf + -- Return quiet NAN, IEEE754-1985-7.1,3 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (lfptype = pos_inf or rfptype = pos_inf + or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + -- figure out the sign + fp_sign := l(l'high) xor r(r'high); -- figure out the sign + fpresult (exponent_width) := fp_sign; + else + fp_sign := l(l'high) xor r(r'high); -- figure out the sign + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => fractl, + expon => exponl); + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => fractr, + expon => exponr); + if (rfptype = pos_denormal or rfptype = neg_denormal) then + shifty := fraction_width - find_leftmost(fractr, '1'); + fractr := shift_left (fractr, shifty); + elsif (lfptype = pos_denormal or lfptype = neg_denormal) then + shifty := fraction_width - find_leftmost(fractl, '1'); + fractl := shift_left (fractl, shifty); + else + shifty := 0; + -- Note that a denormal number * a denormal number is always zero. + end if; + -- multiply + -- add the exponents + rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; + rfract := fractl * fractr; -- Multiply the fraction + sfract := rfract (rfract'high downto + rfract'high - (fraction_width+1+multguard)); + sticky := or (rfract (rfract'high-(fraction_width+1+multguard) + downto 0)); + -- normalize + fpresult := normalize (fract => sfract, + expon => rexpon, + sign => fp_sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => multguard); + end if; + return fpresult; + end function multiply; + + function short_divide ( + lx, rx : UNSIGNED) + return UNSIGNED + is + -- This is a special divider for the floating point routines. + -- For a true unsigned divider, "stages" needs to = lx'high + constant stages : INTEGER := lx'high - rx'high; -- number of stages + variable partial : UNSIGNED (lx'range); + variable q : UNSIGNED (stages downto 0); + variable partial_argl : SIGNED (rx'high + 2 downto 0); + variable partial_arg : SIGNED (rx'high + 2 downto 0); + begin + partial := lx; + for i in stages downto 0 loop + partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), + partial_argl'length); + partial_arg := partial_argl - SIGNED ("0" & rx); + if (partial_arg (partial_arg'high) = '1') then -- negative + q(i) := '0'; + else + q(i) := '1'; + partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := + UNSIGNED (partial_arg(rx'range)); + end if; + end loop; + -- to make the output look like that of the unsigned IEEE divide. + return resize (q, lx'length); + end function short_divide; + + -- 1/X function. Needed for algorithm development. + function reciprocal ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction + constant exponent_width : NATURAL := arg'high; -- length of FP output exponent + constant divguard : NATURAL := guard; -- guard bits + function onedivy ( + arg : UNSIGNED) + return UNSIGNED + is + variable q : UNSIGNED((2*arg'high)+1 downto 0); + variable one : UNSIGNED (q'range); + begin + one := (others => '0'); + one(one'high) := '1'; + q := short_divide (one, arg); -- Unsigned divide + return resize (q, arg'length+1); + end function onedivy; + variable fptype : valid_fpstate; + variable expon : SIGNED (exponent_width-1 downto 0); -- exponents + variable denorm_offset : NATURAL range 0 to 2; + variable fract : UNSIGNED (fraction_width downto 0); + variable fractg : UNSIGNED (fraction_width+divguard downto 0); + variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- reciprocal + fptype := classfp(arg, check_error); + classcase : case fptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf | neg_inf => -- 1/inf, return 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + when neg_zero | pos_zero => -- 1/0 + report FLOAT_GENERIC_PKG'instance_name + & "RECIPROCAL: Floating Point divide by zero" + severity error; + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + when others => + if (fptype = pos_denormal or fptype = neg_denormal) + and ((arg (-1) or arg(-2)) /= '1') then + -- 1/denormal = infinity, with the exception of 2**-expon_base + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + fpresult (exponent_width) := to_x01 (arg (exponent_width)); + else + break_number ( + arg => arg, + fptyp => fptype, + denormalize => denormalize, + fract => fract, + expon => expon); + fractg := (others => '0'); + if (fptype = pos_denormal or fptype = neg_denormal) then + -- The reciprocal of a denormal number is typically zero, + -- except for two special cases which are trapped here. + if (to_x01(arg (-1)) = '1') then + fractg (fractg'high downto divguard+1) := + fract (fract'high-1 downto 0); -- Shift to not denormal + denorm_offset := 1; -- add 1 to exponent compensate + else -- arg(-2) = '1' + fractg (fractg'high downto divguard+2) := + fract (fract'high-2 downto 0); -- Shift to not denormal + denorm_offset := 2; -- add 2 to exponent compensate + end if; + else + fractg (fractg'high downto divguard) := fract; + denorm_offset := 0; + end if; + expon := - expon - 3 + denorm_offset; + sfract := onedivy (fractg); + -- normalize + fpresult := normalize (fract => sfract, + expon => expon, + sign => arg(exponent_width), + sticky => '1', + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => divguard); + end if; + end case classcase; + return fpresult; + end function reciprocal; + + -- floating point division + function divide ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + constant divguard : NATURAL := guard; -- division guard bits + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable ulfract, urfract : UNSIGNED (fraction_width downto 0); + variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left + variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right + variable rfract : UNSIGNED (fractl'range); -- result fraction + variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction + variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents + variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent + variable fp_sign, sticky : STD_ULOGIC; -- sign of result + variable shifty, shiftx : INTEGER; -- denormal number shift + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- divide + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + classcase : case rfptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf | neg_inf => + if lfptype = pos_inf or lfptype = neg_inf -- inf / inf + or lfptype = quiet_nan or lfptype = nan then + -- Return quiet NAN, IEEE754-1985-7.1,4 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + else -- x / inf = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (fpresult'high) := fp_sign; -- sign + end if; + when pos_zero | neg_zero => + if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 + or lfptype = quiet_nan or lfptype = nan then + -- Return quiet NAN, IEEE754-1985-7.1,4 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + report float_generic_pkg'instance_name + & "DIVIDE: Floating Point divide by zero" + severity error; + -- Infinity, define in 754-1985-7.2 + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (fpresult'high) := fp_sign; -- sign + end if; + when others => + classcase2 : case lfptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf | neg_inf => -- inf / x = inf + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult(exponent_width) := fp_sign; + when pos_zero | neg_zero => -- 0 / X = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult(exponent_width) := fp_sign; + when others => + fp_sign := l(l'high) xor r(r'high); -- sign + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => ulfract, + expon => exponl); + -- right side + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => urfract, + expon => exponr); + -- Compute the exponent + rexpon := resize (exponl, rexpon'length) - exponr - 2; + if (rfptype = pos_denormal or rfptype = neg_denormal) then + -- Do the shifting here not after. That way we have a smaller + -- shifter, and need a smaller divider, because the top + -- bit in the divisor will always be a "1". + shifty := fraction_width - find_leftmost(urfract, '1'); + urfract := shift_left (urfract, shifty); + rexpon := rexpon + shifty; + end if; + fractr := (others => '0'); + fractr (fraction_width+divguard downto divguard) := urfract; + if (lfptype = pos_denormal or lfptype = neg_denormal) then + shiftx := fraction_width - find_leftmost(ulfract, '1'); + ulfract := shift_left (ulfract, shiftx); + rexpon := rexpon - shiftx; + end if; + fractl := (others => '0'); + fractl (fractl'high downto fractl'high-fraction_width) := ulfract; + -- divide + rfract := short_divide (fractl, fractr); -- unsigned divide + sfract := rfract (sfract'range); -- lower bits + sticky := '1'; + -- normalize + fpresult := normalize (fract => sfract, + expon => rexpon, + sign => fp_sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => divguard); + end case classcase2; + end case classcase; + return fpresult; + end function divide; + + -- division by a power of 2 + function dividebyp2 ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable ulfract, urfract : UNSIGNED (fraction_width downto 0); + variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents + variable rexpon : SIGNED(exponent_width downto 0); -- result exponent + variable fp_sign : STD_ULOGIC; -- sign of result + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- divisionbyp2 + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + classcase : case rfptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf | neg_inf => + if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf + -- Return quiet NAN, IEEE754-1985-7.1,4 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + else -- x / inf = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (fpresult'high) := fp_sign; -- sign + end if; + when pos_zero | neg_zero => + if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 + -- Return quiet NAN, IEEE754-1985-7.1,4 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + report FLOAT_GENERIC_PKG'instance_name + & "DIVIDEBYP2: Floating Point divide by zero" + severity error; + -- Infinity, define in 754-1985-7.2 + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (fpresult'high) := fp_sign; -- sign + end if; + when others => + classcase2 : case lfptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf | neg_inf => -- inf / x = inf + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (exponent_width) := fp_sign; -- sign + when pos_zero | neg_zero => -- 0 / X = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + fp_sign := l(l'high) xor r(r'high); -- sign + fpresult (exponent_width) := fp_sign; -- sign + when others => + fp_sign := l(l'high) xor r(r'high); -- sign + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => ulfract, + expon => exponl); + -- right side + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => urfract, + expon => exponr); + assert (or (urfract (fraction_width-1 downto 0)) = '0') + report FLOAT_GENERIC_PKG'instance_name + & "DIVIDEBYP2: " + & "Dividebyp2 called with a non power of two divisor" + severity error; + rexpon := (exponl(exponl'high)&exponl) + - (exponr(exponr'high)&exponr) - 1; + -- normalize + fpresult := normalize (fract => ulfract, + expon => rexpon, + sign => fp_sign, + sticky => '1', + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => 0); + end case classcase2; + end case classcase; + return fpresult; + end function dividebyp2; + + -- Multiply accumulate result = l*r + c + function mac ( + l, r, c : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := + -mine (mine(l'low, r'low), c'low); -- length of FP output fraction + constant exponent_width : NATURAL := + maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent + variable lfptype, rfptype, cfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions + variable fractx : UNSIGNED (fraction_width+guard downto 0); + variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); + variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction + variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction + variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents + variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent + variable shifty : INTEGER; -- denormal shift + variable shiftx : SIGNED (rexpon'range); -- shift fractions + variable fp_sign : STD_ULOGIC; -- sign of result + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); + variable leftright : BOOLEAN; -- left or right used + variable sticky : STD_ULOGIC; -- Holds precision for rounding + begin -- multiply + if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + cfptype := classfp (c, check_error); + end if; + if (lfptype = isx or rfptype = isx or cfptype = isx) then + fpresult := (others => 'X'); + elsif (lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan or + cfptype = nan or cfptype = quiet_nan) then + -- Return quiet NAN, IEEE754-1985-7.1,1 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (((lfptype = pos_inf or lfptype = neg_inf) and + (rfptype = pos_zero or rfptype = neg_zero)) or + ((rfptype = pos_inf or rfptype = neg_inf) and + (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf + -- Return quiet NAN, IEEE754-1985-7.1,3 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (lfptype = pos_inf or rfptype = pos_inf + or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf + or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf + fpresult := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + -- figure out the sign + fpresult (exponent_width) := l(l'high) xor r(r'high); + else + fp_sign := l(l'high) xor r(r'high); -- figure out the sign + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + cresize := resize (arg => to_x01(c), + exponent_width => exponent_width, + fraction_width => -cresize'low, + denormalize_in => denormalize, + denormalize => denormalize); + cfptype := classfp (cresize, false); -- errors already checked + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => fractl, + expon => exponl); + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => fractr, + expon => exponr); + break_number ( + arg => cresize, + fptyp => cfptype, + denormalize => denormalize, + fract => fractx, + expon => exponc); + if (rfptype = pos_denormal or rfptype = neg_denormal) then + shifty := fraction_width - find_leftmost(fractr, '1'); + fractr := shift_left (fractr, shifty); + elsif (lfptype = pos_denormal or lfptype = neg_denormal) then + shifty := fraction_width - find_leftmost(fractl, '1'); + fractl := shift_left (fractl, shifty); + else + shifty := 0; + -- Note that a denormal number * a denormal number is always zero. + end if; + -- multiply + rfract := fractl * fractr; -- Multiply the fraction + -- add the exponents + rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; + shiftx := rexpon - exponc; + if shiftx < -fractl'high then + rexpon2 := resize (exponc, rexpon2'length); + fractc := "0" & fractx; + fracts := (others => '0'); + sticky := or (rfract); + elsif shiftx < 0 then + shiftx := - shiftx; + fracts := shift_right (rfract (rfract'high downto rfract'high + - fracts'length+1), + to_integer(shiftx)); + fractc := "0" & fractx; + rexpon2 := resize (exponc, rexpon2'length); + leftright := false; + sticky := or (rfract (to_integer(shiftx)+rfract'high + - fracts'length downto 0)); + elsif shiftx = 0 then + rexpon2 := resize (exponc, rexpon2'length); + sticky := or (rfract (rfract'high - fractc'length downto 0)); + if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx + then + fractc := "0" & fractx; + fracts := rfract (rfract'high downto rfract'high + - fracts'length+1); + leftright := false; + else + fractc := rfract (rfract'high downto rfract'high + - fractc'length+1); + fracts := "0" & fractx; + leftright := true; + end if; + elsif shiftx > fractx'high then + rexpon2 := rexpon; + fracts := (others => '0'); + fractc := rfract (rfract'high downto rfract'high - fractc'length+1); + leftright := true; + sticky := or (fractx & rfract (rfract'high - fractc'length + downto 0)); + else -- fractx'high > shiftx > 0 + rexpon2 := rexpon; + fracts := "0" & shift_right (fractx, to_integer (shiftx)); + fractc := rfract (rfract'high downto rfract'high - fractc'length+1); + leftright := true; + sticky := or (fractx (to_integer (shiftx) downto 0) + & rfract (rfract'high - fractc'length downto 0)); + end if; + fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB + if fp_sign = to_X01(c(c'high)) then + ufract := fractc + fracts; + fp_sign := fp_sign; + else -- signs are different + ufract := fractc - fracts; -- always positive result + if leftright then -- Figure out which sign to use + fp_sign := fp_sign; + else + fp_sign := c(c'high); + end if; + end if; + -- normalize + fpresult := normalize (fract => ufract, + expon => rexpon2, + sign => fp_sign, + sticky => sticky, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => guard); + end if; + return fpresult; + end function mac; + + -- "rem" function + function remainder ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + constant divguard : NATURAL := guard; -- division guard bits + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable ulfract, urfract : UNSIGNED (fraction_width downto 0); + variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right + variable rfract : UNSIGNED (fractr'range); -- result fraction + variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction + variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents + variable rexpon : SIGNED (exponent_width downto 0); -- result exponent + variable fp_sign : STD_ULOGIC; -- sign of result + variable shifty : INTEGER; -- denormal number shift + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- remainder + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + if (lfptype = isx or rfptype = isx) then + fpresult := (others => 'X'); + elsif (lfptype = nan or lfptype = quiet_nan) + or (rfptype = nan or rfptype = quiet_nan) + -- Return quiet NAN, IEEE754-1985-7.1,1 + or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x + -- Return quiet NAN, IEEE754-1985-7.1,5 + or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 + -- Return quiet NAN, IEEE754-1985-7.1,5 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (abs(l) < abs(r)) then + fpresult := l; + else + fp_sign := to_X01(l(l'high)); -- sign + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + lfptype := classfp (lresize, false); -- errors already checked + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rfptype := classfp (rresize, false); -- errors already checked + fractl := (others => '0'); + break_number ( + arg => lresize, + fptyp => lfptype, + denormalize => denormalize, + fract => ulfract, + expon => exponl); + fractl (fraction_width+divguard downto divguard) := ulfract; + -- right side + fractr := (others => '0'); + break_number ( + arg => rresize, + fptyp => rfptype, + denormalize => denormalize, + fract => urfract, + expon => exponr); + fractr (fraction_width+divguard downto divguard) := urfract; + rexpon := (exponr(exponr'high)&exponr); + shifty := to_integer(exponl - rexpon); + if (shifty > 0) then + fractr := shift_right (fractr, shifty); + rexpon := rexpon + shifty; + end if; + if (fractr /= 0) then + -- rem + rfract := fractl rem fractr; -- unsigned rem + sfract := rfract (sfract'range); -- lower bits + -- normalize + fpresult := normalize (fract => sfract, + expon => rexpon, + sign => fp_sign, + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => divguard); + else + -- If we shift "fractr" so far that it becomes zero, return zero. + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + end if; + end if; + return fpresult; + end function remainder; + + -- "mod" function + function modulo ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); + variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- remainder + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + lfptype := isx; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + if (lfptype = isx or rfptype = isx) then + fpresult := (others => 'X'); + elsif (lfptype = nan or lfptype = quiet_nan) + or (rfptype = nan or rfptype = quiet_nan) + -- Return quiet NAN, IEEE754-1985-7.1,1 + or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x + -- Return quiet NAN, IEEE754-1985-7.1,5 + or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 + -- Return quiet NAN, IEEE754-1985-7.1,5 + fpresult := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 + fpresult := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + remres := remainder (l => abs(l), + r => abs(r), + round_style => round_style, + guard => guard, + check_error => false, + denormalize => denormalize); + -- MOD is the same as REM, but you do something different with + -- negative values + if (is_negative (l)) then + remres := - remres; + end if; + if (is_negative (l) = is_negative (r) or remres = 0) then + fpresult := remres; + else + fpresult := add (l => remres, + r => r, + round_style => round_style, + guard => guard, + check_error => false, + denormalize => denormalize); + end if; + end if; + return fpresult; + end function modulo; + + -- Square root of a floating point number. Done using Newton's Iteration. + function sqrt ( + arg : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; + constant guard : NATURAL := float_guard_bits; + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_float + is + constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction + constant exponent_width : NATURAL := arg'high; -- length of FP output exponent + variable sign : STD_ULOGIC; + variable fpresult : float (arg'range); + variable fptype : valid_fpstate; + variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents + variable expon : SIGNED(exponent_width downto 0); -- exponents + variable ufact : ufixed (0 downto arg'low); + variable fact : ufixed (2 downto -fraction_width); -- fraction + variable resb : ufixed (fact'high+1 downto fact'low); + begin -- square root + fptype := Classfp (arg, check_error); + classcase : case fptype is + when isx => + fpresult := (others => 'X'); + when nan | quiet_nan | + -- Return quiet NAN, IEEE754-1985-7.1,1 + neg_normal | neg_denormal | neg_inf => -- sqrt (neg) + -- Return quiet NAN, IEEE754-1985-7.1.6 + fpresult := qnanfp (fraction_width => fraction_width-guard, + exponent_width => exponent_width); + when pos_inf => -- Sqrt (inf), return infinity + fpresult := pos_inffp (fraction_width => fraction_width-guard, + exponent_width => exponent_width); + when pos_zero => -- return 0 + fpresult := zerofp (fraction_width => fraction_width-guard, + exponent_width => exponent_width); + when neg_zero => -- IEEE754-1985-6.3 return -0 + fpresult := neg_zerofp (fraction_width => fraction_width-guard, + exponent_width => exponent_width); + when others => + break_number (arg => arg, + denormalize => denormalize, + check_error => false, + fract => ufact, + expon => iexpon, + sign => sign); + expon := resize (iexpon+1, expon'length); -- get exponent + fact := resize (ufact, fact'high, fact'low); + if (expon(0) = '1') then + fact := fact sla 1; -- * 2.0 + end if; + expon := shift_right (expon, 1); -- exponent/2 + -- Newton's iteration - root := (1 + arg) / 2 + resb := (fact + 1) sra 1; + for j in 0 to fraction_width/4 loop + -- root := (root + (arg/root))/2 + resb := resize (arg => (resb + (fact/resb)) sra 1, + left_index => resb'high, + right_index => resb'low, + round_style => fixed_truncate, + overflow_style => fixed_wrap); + end loop; + fpresult := normalize (fract => resb, + expon => expon-1, + sign => '0', + exponent_width => arg'high, + fraction_width => -arg'low, + round_style => round_style, + denormalize => denormalize, + nguard => guard); + end case classcase; + return fpresult; + end function sqrt; + + function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is + -- Technically -0 should return "false", but I'm leaving that case out. + begin + return (to_x01(arg(arg'high)) = '1'); + end function Is_Negative; + + -- compare functions + -- =, /=, >=, <=, <, > + + function eq ( -- equal = + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + variable lfptype, rfptype : valid_fpstate; + variable is_equal, is_unordered : BOOLEAN; + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- equal + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return false; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + end if; + if (lfptype = neg_zero or lfptype = pos_zero) and + (rfptype = neg_zero or rfptype = pos_zero) then + is_equal := true; + else + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + is_equal := (to_slv(lresize) = to_slv(rresize)); + end if; + if (check_error) then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return is_equal and not is_unordered; + end function eq; + + function lt ( -- less than < + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable expl, expr : UNSIGNED (exponent_width-1 downto 0); + variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); + variable is_less_than, is_unordered : BOOLEAN; + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + is_less_than := false; + else + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits + expl := UNSIGNED(lresize(exponent_width-1 downto 0)); + expr := UNSIGNED(rresize(exponent_width-1 downto 0)); + if expl = expr then + fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); + fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); + if to_x01(l(l'high)) = '0' then -- positive number + is_less_than := (fractl < fractr); + else + is_less_than := (fractl > fractr); -- negative + end if; + else + if to_x01(l(l'high)) = '0' then -- positive number + is_less_than := (expl < expr); + else + is_less_than := (expl > expr); -- negative + end if; + end if; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + if (lfptype = neg_zero and rfptype = pos_zero) then + is_less_than := false; -- -0 < 0 returns false. + else + is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); + end if; + end if; + end if; + if check_error then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return is_less_than and not is_unordered; + end function lt; + + function gt ( -- greater than > + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable expl, expr : UNSIGNED (exponent_width-1 downto 0); + variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); + variable is_greater_than : BOOLEAN; + variable is_unordered : BOOLEAN; + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- greater_than + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + is_greater_than := false; + else + lresize := resize (arg => to_x01(l), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + rresize := resize (arg => to_x01(r), + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => denormalize, + denormalize => denormalize); + if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits + expl := UNSIGNED(lresize(exponent_width-1 downto 0)); + expr := UNSIGNED(rresize(exponent_width-1 downto 0)); + if expl = expr then + fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); + fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); + if to_x01(l(l'high)) = '0' then -- positive number + is_greater_than := fractl > fractr; + else + is_greater_than := fractl < fractr; -- negative + end if; + else + if to_x01(l(l'high)) = '0' then -- positive number + is_greater_than := expl > expr; + else + is_greater_than := expl < expr; -- negative + end if; + end if; + else + lfptype := classfp (l, check_error); + rfptype := classfp (r, check_error); + if (lfptype = pos_zero and rfptype = neg_zero) then + is_greater_than := false; -- 0 > -0 returns false. + else + is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); + end if; + end if; + end if; + if check_error then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return is_greater_than and not is_unordered; + end function gt; + + -- purpose: /= function + function ne ( -- not equal /= + l, r : UNRESOLVED_float; + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + variable is_equal, is_unordered : BOOLEAN; + begin + is_equal := eq (l => l, + r => r, + check_error => false, + denormalize => denormalize); + if check_error then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return not (is_equal and not is_unordered); + end function ne; + + function le ( -- less than or equal to <= + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + variable is_greater_than, is_unordered : BOOLEAN; + begin + is_greater_than := gt (l => l, + r => r, + check_error => false, + denormalize => denormalize); + if check_error then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return not is_greater_than and not is_unordered; + end function le; + + function ge ( -- greater than or equal to >= + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN + is + variable is_less_than, is_unordered : BOOLEAN; + begin + is_less_than := lt (l => l, + r => r, + check_error => false, + denormalize => denormalize); + if check_error then + is_unordered := Unordered (x => l, + y => r); + else + is_unordered := false; + end if; + return not is_less_than and not is_unordered; + end function ge; + + function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable is_equal, is_unordered : STD_ULOGIC; + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- ?= + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + lfptype := classfp (l, float_check_error); + rfptype := classfp (r, float_check_error); + end if; + if (lfptype = neg_zero or lfptype = pos_zero) and + (rfptype = neg_zero or rfptype = pos_zero) then + is_equal := '1'; + else + lresize := resize (arg => l, + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => float_denormalize, + denormalize => float_denormalize); + rresize := resize (arg => r, + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => float_denormalize, + denormalize => float_denormalize); + is_equal := to_sulv(lresize) ?= to_sulv(rresize); + end if; + if (float_check_error) then + if (lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan) then + is_unordered := '1'; + else + is_unordered := '0'; + end if; + else + is_unordered := '0'; + end if; + return is_equal and not is_unordered; + end function "?="; + + function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lfptype, rfptype : valid_fpstate; + variable is_equal, is_unordered : STD_ULOGIC; + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- ?/= + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + lfptype := classfp (l, float_check_error); + rfptype := classfp (r, float_check_error); + end if; + if (lfptype = neg_zero or lfptype = pos_zero) and + (rfptype = neg_zero or rfptype = pos_zero) then + is_equal := '1'; + else + lresize := resize (arg => l, + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => float_denormalize, + denormalize => float_denormalize); + rresize := resize (arg => r, + exponent_width => exponent_width, + fraction_width => fraction_width, + denormalize_in => float_denormalize, + denormalize => float_denormalize); + is_equal := to_sulv(lresize) ?= to_sulv(rresize); + end if; + if (float_check_error) then + if (lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan) then + is_unordered := '1'; + else + is_unordered := '0'; + end if; + else + is_unordered := '0'; + end if; + return not (is_equal and not is_unordered); + end function "?/="; + + function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); + variable founddash : BOOLEAN := false; + begin + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + founddash := true; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + founddash := true; + end if; + end loop; + if founddash then + report float_generic_pkg'instance_name + & " ""?>"": '-' found in compare string" + severity error; + return 'X'; + elsif is_x(l) or is_x(r) then + return 'X'; + elsif l > r then + return '1'; + else + return '0'; + end if; + end if; + end function "?>"; + + function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); + variable founddash : BOOLEAN := false; + begin + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + founddash := true; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + founddash := true; + end if; + end loop; + if founddash then + report float_generic_pkg'instance_name + & " ""?>="": '-' found in compare string" + severity error; + return 'X'; + elsif is_x(l) or is_x(r) then + return 'X'; + elsif l >= r then + return '1'; + else + return '0'; + end if; + end if; + end function "?>="; + + function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); + variable founddash : BOOLEAN := false; + begin + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + founddash := true; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + founddash := true; + end if; + end loop; + if founddash then + report float_generic_pkg'instance_name + & " ""?<"": '-' found in compare string" + severity error; + return 'X'; + elsif is_x(l) or is_x(r) then + return 'X'; + elsif l < r then + return '1'; + else + return '0'; + end if; + end if; + end function "?<"; + + function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is + constant fraction_width : NATURAL := -mine(l'low, r'low); + variable founddash : BOOLEAN := false; + begin + if (fraction_width = 0 or l'length < 7 or r'length < 7) then + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + founddash := true; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + founddash := true; + end if; + end loop; + if founddash then + report float_generic_pkg'instance_name + & " ""?<="": '-' found in compare string" + severity error; + return 'X'; + elsif is_x(l) or is_x(r) then + return 'X'; + elsif l <= r then + return '1'; + else + return '0'; + end if; + end if; + end function "?<="; + + function std_match (L, R : UNRESOLVED_float) return BOOLEAN is + begin + if (L'high = R'high and L'low = R'low) then + return std_match(to_sulv(L), to_sulv(R)); + else + report float_generic_pkg'instance_name + & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" + severity warning; + return false; + end if; + end function std_match; + + function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is + begin + for_loop : for i in arg'reverse_range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'high+1; -- return out of bounds 'high + end function find_rightmost; + + function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is + begin + for_loop : for i in arg'range loop + if arg(i) ?= y then + return i; + end if; + end loop; + return arg'low-1; -- return out of bounds 'low + end function find_leftmost; + + -- These override the defaults for the compare operators. + function "=" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return eq(l, r); + end function "="; + + function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return ne(l, r); + end function "/="; + + function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return ge(l, r); + end function ">="; + + function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return le(l, r); + end function "<="; + + function ">" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return gt(l, r); + end function ">"; + + function "<" (l, r : UNRESOLVED_float) return BOOLEAN is + begin + return lt(l, r); + end function "<"; + + -- purpose: maximum of two numbers (overrides default) + function maximum ( + L, R : UNRESOLVED_float) + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin + if ((L'length < 1) or (R'length < 1)) then return NAFP; + end if; + lresize := resize (l, exponent_width, fraction_width); + rresize := resize (r, exponent_width, fraction_width); + if lresize > rresize then return lresize; + else return rresize; + end if; + end function maximum; + + function minimum ( + L, R : UNRESOLVED_float) + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction + constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent + variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); + begin + if ((L'length < 1) or (R'length < 1)) then return NAFP; + end if; + lresize := resize (l, exponent_width, fraction_width); + rresize := resize (r, exponent_width, fraction_width); + if lresize > rresize then return rresize; + else return lresize; + end if; + end function minimum; + + ----------------------------------------------------------------------------- + -- conversion functions + ----------------------------------------------------------------------------- + + -- Converts a floating point number of one format into another format + function resize ( + arg : UNRESOLVED_float; -- Floating point input + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction + constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + -- result value + variable fptype : valid_fpstate; + variable expon_in : SIGNED (in_exponent_width-1 downto 0); + variable fract_in : UNSIGNED (in_fraction_width downto 0); + variable round : BOOLEAN; + variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract + variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract + variable passguard : NATURAL; + begin + fptype := classfp(arg, check_error); + if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in + and (in_exponent_width < exponent_width + or in_fraction_width < fraction_width)) + or in_exponent_width > exponent_width + or in_fraction_width > fraction_width then + -- size reduction + classcase : case fptype is + when isx => + result := (others => 'X'); + when nan | quiet_nan => + result := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_inf => + result := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + when neg_inf => + result := neg_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + when pos_zero | neg_zero => + result := zerofp (fraction_width => fraction_width, -- hate -0 + exponent_width => exponent_width); + when others => + break_number ( + arg => arg, + fptyp => fptype, + denormalize => denormalize_in, + fract => fract_in, + expon => expon_in); + if fraction_width > in_fraction_width and denormalize_in then + -- You only get here if you have a denormal input + fract_out := (others => '0'); -- pad with zeros + fract_out (fraction_width downto + fraction_width - in_fraction_width) := fract_in; + result := normalize ( + fract => fract_out, + expon => expon_in, + sign => arg(arg'high), + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => 0); + else + result := normalize ( + fract => fract_in, + expon => expon_in, + sign => arg(arg'high), + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => in_fraction_width - fraction_width); + end if; + end case classcase; + else -- size increase or the same size + if exponent_width > in_exponent_width then + expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); + if fptype = pos_zero or fptype = neg_zero then + result (exponent_width-1 downto 0) := (others => '0'); + elsif expon_in = -1 then -- inf or nan (shorts out check_error) + result (exponent_width-1 downto 0) := (others => '1'); + else + -- invert top BIT + expon_in(expon_in'high) := not expon_in(expon_in'high); + expon_out := resize (expon_in, expon_out'length); -- signed expand + -- Flip it back. + expon_out(expon_out'high) := not expon_out(expon_out'high); + result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); + end if; + result (exponent_width) := arg (in_exponent_width); -- sign + else -- exponent_width = in_exponent_width + result (exponent_width downto 0) := arg (in_exponent_width downto 0); + end if; + if fraction_width > in_fraction_width then + result (-1 downto -fraction_width) := (others => '0'); -- zeros + result (-1 downto -in_fraction_width) := + arg (-1 downto -in_fraction_width); + else -- fraction_width = in_fraciton_width + result (-1 downto -fraction_width) := + arg (-1 downto -in_fraction_width); + end if; + end if; + return result; + end function resize; + + function resize ( + arg : UNRESOLVED_float; -- floating point input + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := resize (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style, + check_error => check_error, + denormalize_in => denormalize_in, + denormalize => denormalize); + return result; + end if; + end function resize; + + function to_float32 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float32 is + begin + return resize (arg => arg, + exponent_width => float32'high, + fraction_width => -float32'low, + round_style => round_style, + check_error => check_error, + denormalize_in => denormalize_in, + denormalize => denormalize); + end function to_float32; + + function to_float64 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float64 is + begin + return resize (arg => arg, + exponent_width => float64'high, + fraction_width => -float64'low, + round_style => round_style, + check_error => check_error, + denormalize_in => denormalize_in, + denormalize => denormalize); + end function to_float64; + + function to_float128 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float128 is + begin + return resize (arg => arg, + exponent_width => float128'high, + fraction_width => -float128'low, + round_style => round_style, + check_error => check_error, + denormalize_in => denormalize_in, + denormalize => denormalize); + end function to_float128; + + -- to_float (Real) + -- typically not Synthesizable unless the input is a constant. + function to_float ( + arg : REAL; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable arg_real : REAL; -- Real version of argument + variable validfp : boundary_type; -- Check for valid results + variable exp : INTEGER; -- Integer version of exponent + variable expon : UNSIGNED (exponent_width - 1 downto 0); + -- Unsigned version of exp. + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable fract : UNSIGNED (fraction_width-1 downto 0); + variable frac : REAL; -- Real version of fraction + constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding + variable round : BOOLEAN; -- to round or not to round + begin + result := (others => '0'); + arg_real := arg; + if arg_real < 0.0 then + result (exponent_width) := '1'; + arg_real := - arg_real; -- Make it positive. + else + result (exponent_width) := '0'; + end if; + test_boundary (arg => arg_real, + fraction_width => fraction_width, + exponent_width => exponent_width, + denormalize => denormalize, + btype => validfp, + log2i => exp); + if validfp = zero then + return result; -- Result initialized to "0". + elsif validfp = infinity then + result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" + -- return infinity. + return result; + else + if validfp = denormal then -- Exponent will default to "0". + expon := (others => '0'); + frac := arg_real * (2.0 ** (to_integer(expon_base)-1)); + else -- Number less than 1. "normal" number + expon := UNSIGNED (to_signed (exp-1, exponent_width)); + expon(exponent_width-1) := not expon(exponent_width-1); + frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1. + end if; + for i in 0 to fract'high loop + if frac >= 2.0 ** (-1 - i) then + fract (fract'high - i) := '1'; + frac := frac - 2.0 ** (-1 - i); + else + fract (fract'high - i) := '0'; + end if; + end loop; + round := false; + case round_style is + when round_nearest => + if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then + round := true; + end if; + when round_inf => + if frac /= 0.0 and result(exponent_width) = '0' then + round := true; + end if; + when round_neginf => + if frac /= 0.0 and result(exponent_width) = '1' then + round := true; + end if; + when others => + null; -- don't round + end case; + if (round) then + if and(fract) = '1' then -- fraction is all "1" + expon := expon + 1; + fract := (others => '0'); + else + fract := fract + 1; + end if; + end if; + result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); + result (-1 downto -fraction_width) := UNRESOLVED_float(fract); + return result; + end if; + end function to_float; + + -- to_float (Integer) + function to_float ( + arg : INTEGER; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable arg_int : NATURAL; -- Natural version of argument + variable expon : SIGNED (exponent_width-1 downto 0); + variable exptmp : SIGNED (exponent_width-1 downto 0); + -- Unsigned version of exp. + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); + variable fracttmp : UNSIGNED (fraction_width-1 downto 0); + variable round : BOOLEAN; + variable shift : NATURAL; + variable shiftr : NATURAL; + variable roundfrac : NATURAL; -- used in rounding + begin + if arg < 0 then + result (exponent_width) := '1'; + arg_int := -arg; -- Make it positive. + else + result (exponent_width) := '0'; + arg_int := arg; + end if; + if arg_int = 0 then + result := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + -- If the number is larger than we can represent in this number system + -- we need to return infinity. + shift := log2(arg_int); + if shift > to_integer(expon_base) then + -- worry about infinity + if result (exponent_width) = '0' then + result := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + -- return negative infinity. + result := neg_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + end if; + else -- Normal number (can't be denormal) + -- Compute Exponent + expon := to_signed (shift-1, expon'length); -- positive fraction. + -- Compute Fraction + arg_int := arg_int - 2**shift; -- Subtract off the 1.0 + shiftr := shift; + for I in fract'high downto maximum (fract'high - shift + 1, 0) loop + shiftr := shiftr - 1; + if (arg_int >= 2**shiftr) then + arg_int := arg_int - 2**shiftr; + fract(I) := '1'; + else + fract(I) := '0'; + end if; + end loop; + -- Rounding routine + round := false; + if arg_int > 0 then + roundfrac := 2**(shiftr-1); + case round_style is + when round_nearest => + if arg_int > roundfrac or + ((arg_int = roundfrac) and fract(0) = '1') then + round := true; + end if; + when round_inf => + if arg_int /= 0 and result (exponent_width) = '0' then + round := true; + end if; + when round_neginf => + if arg_int /= 0 and result (exponent_width) = '1' then + round := true; + end if; + when others => + null; + end case; + end if; + if round then + fp_round(fract_in => fract, + expon_in => expon, + fract_out => fracttmp, + expon_out => exptmp); + fract := fracttmp; + expon := exptmp; + end if; + -- Put the number together and return + expon(exponent_width-1) := not expon(exponent_width-1); + result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); + result (-1 downto -fraction_width) := UNRESOLVED_float(fract); + end if; + end if; + return result; + end function to_float; + + -- to_float (unsigned) + function to_float ( + arg : UNSIGNED; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; + variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg + begin + if arg'length < 1 then + return NAFP; + end if; + sarg (XARG'range) := SIGNED (XARG); + sarg (sarg'high) := '0'; + result := to_float (arg => sarg, + exponent_width => exponent_width, + fraction_width => fraction_width, + round_style => round_style); + return result; + end function to_float; + + -- to_float (signed) + function to_float ( + arg : SIGNED; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; + variable arg_int : UNSIGNED(xarg'range); -- Real version of argument + variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input + variable rexp : SIGNED (exponent_width - 1 downto 0); + variable exp : SIGNED (exponent_width - 1 downto 0); + -- signed version of exp. + variable expon : UNSIGNED (exponent_width - 1 downto 0); + -- Unsigned version of exp. + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable round : BOOLEAN; + variable fract : UNSIGNED (fraction_width-1 downto 0); + variable rfract : UNSIGNED (fraction_width-1 downto 0); + variable sign : STD_ULOGIC; -- sign bit + begin + if arg'length < 1 then + return NAFP; + end if; + if Is_X (xarg) then + result := (others => 'X'); + elsif (xarg = 0) then + result := zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else -- Normal number (can't be denormal) + sign := to_X01(xarg (xarg'high)); + arg_int := UNSIGNED(abs (to_01(xarg))); + -- Compute Exponent + argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 + if argb2 > UNSIGNED(expon_base) then + result := pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + result (exponent_width) := sign; + else + exp := SIGNED(resize(argb2, exp'length)); + arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); + if (arg_int'high > fraction_width) then + fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); + round := check_round ( + fract_in => fract (0), + sign => sign, + remainder => arg_int((arg_int'high-fraction_width-1) + downto 0), + round_style => round_style); + if round then + fp_round(fract_in => fract, + expon_in => exp, + fract_out => rfract, + expon_out => rexp); + else + rfract := fract; + rexp := exp; + end if; + else + rexp := exp; + rfract := (others => '0'); + rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := + arg_int (arg_int'high-1 downto 0); + end if; + result (exponent_width) := sign; + expon := UNSIGNED (rexp-1); + expon(exponent_width-1) := not expon(exponent_width-1); + result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); + result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); + end if; + end if; + return result; + end function to_float; + + -- std_logic_vector to float + function to_float ( + arg : STD_ULOGIC_VECTOR; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction + return UNRESOLVED_float + is + variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); + begin + if arg'length < 1 then + return NAFP; + end if; + fpvar := UNRESOLVED_float(arg); + return fpvar; + end function to_float; + + -- purpose: converts a ufixed to a floating point + function to_float ( + arg : UNRESOLVED_ufixed; -- unsigned fixed point input + constant exponent_width : NATURAL := float_exponent_width; -- width of exponent + constant fraction_width : NATURAL := float_fraction_width; -- width of fraction + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions + return UNRESOLVED_float + is + variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + begin -- function to_float + if (arg'length < 1) then + return NAFP; + end if; + sarg (arg'range) := sfixed (arg); + sarg (sarg'high) := '0'; + result := to_float (arg => sarg, + exponent_width => exponent_width, + fraction_width => fraction_width, + round_style => round_style, + denormalize => denormalize); + return result; + end function to_float; + + function to_float ( + arg : UNRESOLVED_sfixed; -- signed fixed point + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- rounding option + return UNRESOLVED_float + is + constant integer_width : INTEGER := arg'high; + constant in_fraction_width : INTEGER := arg'low; + variable xresult : sfixed (integer_width downto in_fraction_width); + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 + downto 0); -- signed version of argument + variable argx : SIGNED (integer_width - in_fraction_width downto 0); + variable exp, exptmp : SIGNED (exponent_width downto 0); + variable expon : UNSIGNED (exponent_width - 1 downto 0); + -- Unsigned version of exp. + constant expon_base : SIGNED (exponent_width-1 downto 0) := + gen_expon_base(exponent_width); -- exponent offset + variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := + (others => '0'); + variable round : BOOLEAN := false; + begin + if (arg'length < 1) then + return NAFP; + end if; + xresult := to_01(arg, 'X'); + argx := SIGNED(to_slv(xresult)); + if (Is_X (arg)) then + result := (others => 'X'); + elsif (argx = 0) then + result := (others => '0'); + else + result := (others => '0'); -- zero out the result + if argx(argx'left) = '1' then -- toss the sign bit + result (exponent_width) := '1'; -- Negative number + argx := -argx; -- Make it positive. + else + result (exponent_width) := '0'; + end if; + arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); + -- Compute Exponent + exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 + if exp + in_fraction_width > expon_base then -- return infinity + result (-1 downto -fraction_width) := (others => '0'); + result (exponent_width -1 downto 0) := (others => '1'); + return result; + elsif (denormalize and + (exp + in_fraction_width <= -resize(expon_base, exp'length))) then + exp := -resize(expon_base, exp'length); + -- shift by a constant + arg_int := shift_left (arg_int, + (arg_int'high + to_integer(expon_base) + + in_fraction_width - 1)); + if (arg_int'high > fraction_width) then + fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); + round := check_round ( + fract_in => arg_int(arg_int'high-fraction_width), + sign => result(result'high), + remainder => arg_int((arg_int'high-fraction_width-1) + downto 0), + round_style => round_style); + if (round) then + fp_round (fract_in => arg_int (arg_int'high-1 downto + (arg_int'high-fraction_width)), + expon_in => exp, + fract_out => fract, + expon_out => exptmp); + exp := exptmp; + end if; + else + fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := + arg_int (arg_int'high-1 downto 0); + end if; + else + arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); + exp := exp + in_fraction_width; + if (arg_int'high > fraction_width) then + fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); + round := check_round ( + fract_in => fract(0), + sign => result(result'high), + remainder => arg_int((arg_int'high-fraction_width-1) + downto 0), + round_style => round_style); + if (round) then + fp_round (fract_in => fract, + expon_in => exp, + fract_out => fracttmp, + expon_out => exptmp); + fract := fracttmp; + exp := exptmp; + end if; + else + fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := + arg_int (arg_int'high-1 downto 0); + end if; + end if; + expon := UNSIGNED (resize(exp-1, exponent_width)); + expon(exponent_width-1) := not expon(exponent_width-1); + result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); + result (-1 downto -fraction_width) := UNRESOLVED_float(fract); + end if; + return result; + end function to_float; + + -- size_res functions + -- Integer to float + function to_float ( + arg : INTEGER; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style); + return result; + end if; + end function to_float; + + -- real to float + function to_float ( + arg : REAL; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style, + denormalize => denormalize); + return result; + end if; + end function to_float; + + -- unsigned to float + function to_float ( + arg : UNRESOLVED_UNSIGNED; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style); + return result; + end if; + end function to_float; + + -- signed to float + function to_float ( + arg : UNRESOLVED_SIGNED; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style); + return result; + end if; + end function to_float; + + -- std_ulogic_vector to float + function to_float ( + arg : STD_ULOGIC_VECTOR; + size_res : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low); + return result; + end if; + end function to_float; + + -- unsigned fixed point to float + function to_float ( + arg : UNRESOLVED_ufixed; -- unsigned fixed point input + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style, + denormalize => denormalize); + return result; + end if; + end function to_float; + + -- signed fixed point to float + function to_float ( + arg : UNRESOLVED_sfixed; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- rounding option + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_float (arg => arg, + exponent_width => size_res'high, + fraction_width => -size_res'low, + round_style => round_style, + denormalize => denormalize); + return result; + end if; + end function to_float; + + -- to_integer (float) + function to_integer ( + arg : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return INTEGER + is + variable validfp : valid_fpstate; -- Valid FP state + variable frac : UNSIGNED (-arg'low downto 0); -- Fraction + variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction + variable expon : SIGNED (arg'high-1 downto 0); + variable isign : STD_ULOGIC; -- internal version of sign + variable round : STD_ULOGIC; -- is rounding needed? + variable result : INTEGER; + variable base : INTEGER; -- Integer exponent + begin + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal => + result := 0; -- return 0 + when pos_inf => + result := INTEGER'high; + when neg_inf => + result := INTEGER'low; + when others => + break_number ( + arg => arg, + fptyp => validfp, + denormalize => false, + fract => frac, + expon => expon); + fract (fract'high) := '0'; -- Add extra bit for 0.6 case + fract (fract'high-1 downto 0) := frac; + isign := to_x01 (arg (arg'high)); + base := to_integer (expon) + 1; + if base < -1 then + result := 0; + elsif base >= frac'high then + result := to_integer (fract) * 2**(base - frac'high); + else -- We need to round + if base = -1 then -- trap for 0.6 case. + result := 0; + else + result := to_integer (fract (frac'high downto frac'high-base)); + end if; + -- rounding routine + case round_style is + when round_nearest => + if frac'high - base > 1 then + round := fract (frac'high - base - 1) and + (fract (frac'high - base) + or (or (fract (frac'high - base - 2 downto 0)))); + else + round := fract (frac'high - base - 1) and + fract (frac'high - base); + end if; + when round_inf => + round := fract(frac'high - base - 1) and not isign; + when round_neginf => + round := fract(frac'high - base - 1) and isign; + when others => + round := '0'; + end case; + if round = '1' then + result := result + 1; + end if; + end if; + if isign = '1' then + result := - result; + end if; + end case classcase; + return result; + end function to_integer; + + -- to_unsigned (float) + function to_unsigned ( + arg : UNRESOLVED_float; -- floating point input + constant size : NATURAL; -- length of output + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_UNSIGNED + is + variable validfp : valid_fpstate; -- Valid FP state + variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction + variable sign : STD_ULOGIC; -- not used + begin + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | nan | quiet_nan => + frac := (others => 'X'); + when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal => + frac := (others => '0'); -- return 0 + when pos_inf => + frac := (others => '1'); + when others => + float_to_unsigned ( + arg => arg, + frac => frac, + sign => sign, + denormalize => false, + bias => 0, + round_style => round_style); + end case classcase; + return (frac); + end function to_unsigned; + + -- to_signed (float) + function to_signed ( + arg : UNRESOLVED_float; -- floating point input + constant size : NATURAL; -- length of output + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_SIGNED + is + variable sign : STD_ULOGIC; -- true if negative + variable validfp : valid_fpstate; -- Valid FP state + variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction + variable result : UNRESOLVED_SIGNED (size-1 downto 0); + begin + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | nan | quiet_nan => + result := (others => 'X'); + when pos_zero | neg_zero | pos_denormal | neg_denormal => + result := (others => '0'); -- return 0 + when pos_inf => + result := (others => '1'); + result (result'high) := '0'; + when neg_inf => + result := (others => '0'); + result (result'high) := '1'; + when others => + float_to_unsigned ( + arg => arg, + sign => sign, + frac => frac, + denormalize => false, + bias => 0, + round_style => round_style); + result (size-1) := '0'; + result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); + if sign = '1' then + -- Because the most negative signed number is 1 less than the most + -- positive signed number, we need this code. + if frac(frac'high) = '1' then -- return most negative number + result := (others => '0'); + result (result'high) := '1'; + else + result := -result; + end if; + else + if frac(frac'high) = '1' then -- return most positive number + result := (others => '1'); + result (result'high) := '0'; + end if; + end if; + end case classcase; + return result; + end function to_signed; + + -- purpose: Converts a float to ufixed + function to_ufixed ( + arg : UNRESOLVED_float; -- fp input + constant left_index : INTEGER; -- integer part + constant right_index : INTEGER; -- fraction part + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_ufixed + is + constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction + constant exponent_width : INTEGER := arg'high; -- length of FP output exponent + constant size : INTEGER := left_index - right_index + 4; -- unsigned size + variable expon_base : INTEGER; -- exponent offset + variable validfp : valid_fpstate; -- Valid FP state + variable exp : INTEGER; -- Exponent + variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent + -- Base to divide fraction by + variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction + variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted + variable shift : INTEGER; + variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); + variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result + begin -- function to_ufixed + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | nan | quiet_nan => + frac := (others => 'X'); + when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal => + frac := (others => '0'); -- return 0 + when pos_inf => + frac := (others => '1'); -- always saturate + when others => + expon_base := 2**(exponent_width-1) -1; -- exponent offset + -- Figure out the fraction + if (validfp = pos_denormal) and denormalize then + exp := -expon_base +1; + frac (frac'high) := '0'; -- Remove the "1.0". + else + -- exponent /= '0', normal floating point + expon := UNSIGNED(arg (exponent_width-1 downto 0)); + expon(exponent_width-1) := not expon(exponent_width-1); + exp := to_integer (SIGNED(expon)) +1; + frac (frac'high) := '1'; -- Add the "1.0". + end if; + shift := (frac'high - 3 + right_index) - exp; + if fraction_width > frac'high then -- Can only use size-2 bits + frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto + -frac'high))); + else -- can use all bits + frac (frac'high-1 downto frac'high-fraction_width) := + UNSIGNED (to_slv (arg(-1 downto -fraction_width))); + end if; + frac_shift := frac srl shift; + if shift < 0 then -- Overflow + frac := (others => '1'); + else + frac := frac_shift; + end if; + end case classcase; + result_big := to_ufixed ( + arg => STD_ULOGIC_VECTOR(frac), + left_index => left_index, + right_index => (right_index-3)); + result := resize (arg => result_big, + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + return result; + end function to_ufixed; + + -- purpose: Converts a float to sfixed + function to_sfixed ( + arg : UNRESOLVED_float; -- fp input + constant left_index : INTEGER; -- integer part + constant right_index : INTEGER; -- fraction part + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_sfixed + is + constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction + constant exponent_width : INTEGER := arg'high; -- length of FP output exponent + constant size : INTEGER := left_index - right_index + 4; -- unsigned size + variable expon_base : INTEGER; -- exponent offset + variable validfp : valid_fpstate; -- Valid FP state + variable exp : INTEGER; -- Exponent + variable sign : BOOLEAN; -- true if negative + variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent + -- Base to divide fraction by + variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction + variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted + variable shift : INTEGER; + variable rsigned : SIGNED (size-1 downto 0); -- signed version of result + variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); + variable result : UNRESOLVED_sfixed (left_index downto right_index) + := (others => '0'); -- result + begin -- function to_sfixed + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | nan | quiet_nan => + result := (others => 'X'); + when pos_zero | neg_zero => + result := (others => '0'); -- return 0 + when neg_inf => + result (left_index) := '1'; -- return smallest negative number + when pos_inf => + result := (others => '1'); -- return largest number + result (left_index) := '0'; + when others => + expon_base := 2**(exponent_width-1) -1; -- exponent offset + if arg(exponent_width) = '0' then + sign := false; + else + sign := true; + end if; + -- Figure out the fraction + if (validfp = pos_denormal or validfp = neg_denormal) + and denormalize then + exp := -expon_base +1; + frac (frac'high) := '0'; -- Add the "1.0". + else + -- exponent /= '0', normal floating point + expon := UNSIGNED(arg (exponent_width-1 downto 0)); + expon(exponent_width-1) := not expon(exponent_width-1); + exp := to_integer (SIGNED(expon)) +1; + frac (frac'high) := '1'; -- Add the "1.0". + end if; + shift := (frac'high - 3 + right_index) - exp; + if fraction_width > frac'high then -- Can only use size-2 bits + frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto + -frac'high))); + else -- can use all bits + frac (frac'high-1 downto frac'high-fraction_width) := + UNSIGNED (to_slv (arg(-1 downto -fraction_width))); + end if; + frac_shift := frac srl shift; + if shift < 0 then -- Overflow + frac := (others => '1'); + else + frac := frac_shift; + end if; + if not sign then + rsigned := SIGNED("0" & frac); + else + rsigned := -(SIGNED("0" & frac)); + end if; + result_big := to_sfixed ( + arg => STD_LOGIC_VECTOR(rsigned), + left_index => left_index, + right_index => (right_index-3)); + result := resize (arg => result_big, + left_index => left_index, + right_index => right_index, + round_style => round_style, + overflow_style => overflow_style); + end case classcase; + return result; + end function to_sfixed; + + -- size_res versions + -- float to unsigned + function to_unsigned ( + arg : UNRESOLVED_float; -- floating point input + size_res : UNRESOLVED_UNSIGNED; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_UNSIGNED + is + variable result : UNRESOLVED_UNSIGNED (size_res'range); + begin + if (SIZE_RES'length = 0) then + return result; + else + result := to_unsigned ( + arg => arg, + size => size_res'length, + round_style => round_style, + check_error => check_error); + return result; + end if; + end function to_unsigned; + + -- float to signed + function to_signed ( + arg : UNRESOLVED_float; -- floating point input + size_res : UNRESOLVED_SIGNED; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_SIGNED + is + variable result : UNRESOLVED_SIGNED (size_res'range); + begin + if (SIZE_RES'length = 0) then + return result; + else + result := to_signed ( + arg => arg, + size => size_res'length, + round_style => round_style, + check_error => check_error); + return result; + end if; + end function to_signed; + + -- purpose: Converts a float to unsigned fixed point + function to_ufixed ( + arg : UNRESOLVED_float; -- fp input + size_res : UNRESOLVED_ufixed; + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_ufixed + is + variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_ufixed ( + arg => arg, + left_index => size_res'high, + right_index => size_res'low, + overflow_style => overflow_style, + round_style => round_style, + check_error => check_error, + denormalize => denormalize); + return result; + end if; + end function to_ufixed; + + -- float to signed fixed point + function to_sfixed ( + arg : UNRESOLVED_float; -- fp input + size_res : UNRESOLVED_sfixed; + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_sfixed + is + variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); + begin + if (result'length < 1) then + return result; + else + result := to_sfixed ( + arg => arg, + left_index => size_res'high, + right_index => size_res'low, + overflow_style => overflow_style, + round_style => round_style, + check_error => check_error, + denormalize => denormalize); + return result; + end if; + end function to_sfixed; + + -- to_real (float) + -- typically not Synthesizable unless the input is a constant. + function to_real ( + arg : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return REAL + is + constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction + constant exponent_width : INTEGER := arg'high; -- length of FP output exponent + variable sign : REAL; -- Sign, + or - 1 + variable exp : INTEGER; -- Exponent + variable expon_base : INTEGER; -- exponent offset + variable frac : REAL := 0.0; -- Fraction + variable validfp : valid_fpstate; -- Valid FP state + variable expon : UNSIGNED (exponent_width - 1 downto 0) + := (others => '1'); -- Vectorized exponent + begin + validfp := classfp (arg, check_error); + classcase : case validfp is + when isx | pos_zero | neg_zero | nan | quiet_nan => + return 0.0; + when neg_inf => + return REAL'low; -- Negative infinity. + when pos_inf => + return REAL'high; -- Positive infinity + when others => + expon_base := 2**(exponent_width-1) -1; + if to_X01(arg(exponent_width)) = '0' then + sign := 1.0; + else + sign := -1.0; + end if; + -- Figure out the fraction + for i in 0 to fraction_width-1 loop + if to_X01(arg (-1 - i)) = '1' then + frac := frac + (2.0 **(-1 - i)); + end if; + end loop; -- i + if validfp = pos_normal or validfp = neg_normal or not denormalize then + -- exponent /= '0', normal floating point + expon := UNSIGNED(arg (exponent_width-1 downto 0)); + expon(exponent_width-1) := not expon(exponent_width-1); + exp := to_integer (SIGNED(expon)) +1; + sign := sign * (2.0 ** exp) * (1.0 + frac); + else -- exponent = '0', IEEE extended floating point + exp := 1 - expon_base; + sign := sign * (2.0 ** exp) * frac; + end if; + return sign; + end case classcase; + end function to_real; + + -- For Verilog compatability + function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is + variable result : float64; -- 64 bit floating point + begin + result := to_float (arg => arg, + exponent_width => float64'high, + fraction_width => -float64'low); + return to_sulv (result); + end function realtobits; + + function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is + variable arg64 : float64; -- arg converted to float + begin + arg64 := to_float (arg => arg, + exponent_width => float64'high, + fraction_width => -float64'low); + return to_real (arg64); + end function bitstoreal; + + -- purpose: Removes meta-logical values from FP string + function to_01 ( + arg : UNRESOLVED_float; -- floating point input + XMAP : STD_LOGIC := '0') + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (arg'range); + begin -- function to_01 + if (arg'length < 1) then + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "TO_01: null detected, returning NULL" + severity warning; + return NAFP; + end if; + result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); + return result; + end function to_01; + + function Is_X + (arg : UNRESOLVED_float) + return BOOLEAN is + begin + return Is_X (to_slv(arg)); + end function Is_X; + + function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is + variable result : UNRESOLVED_float (arg'range); + begin + if (arg'length < 1) then + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "TO_X01: null detected, returning NULL" + severity warning; + return NAFP; + else + result := UNRESOLVED_float (to_X01(to_slv(arg))); + return result; + end if; + end function to_X01; + + function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is + variable result : UNRESOLVED_float (arg'range); + begin + if (arg'length < 1) then + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "TO_X01Z: null detected, returning NULL" + severity warning; + return NAFP; + else + result := UNRESOLVED_float (to_X01Z(to_slv(arg))); + return result; + end if; + end function to_X01Z; + + function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is + variable result : UNRESOLVED_float (arg'range); + begin + if (arg'length < 1) then + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "TO_UX01: null detected, returning NULL" + severity warning; + return NAFP; + else + result := UNRESOLVED_float (to_UX01(to_slv(arg))); + return result; + end if; + end function to_UX01; + + -- These allows the base math functions to use the default values + -- of their parameters. Thus they do full IEEE floating point. + function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return add (l, r); + end function "+"; + + function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return subtract (l, r); + end function "-"; + + function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return multiply (l, r); + end function "*"; + + function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return divide (l, r); + end function "/"; + + function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return remainder (l, r); + end function "rem"; + + function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is + begin + return modulo (l, r); + end function "mod"; + + -- overloaded versions + function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return add (l, r_float); + end function "+"; + + function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return add (l_float, r); + end function "+"; + + function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return add (l, r_float); + end function "+"; + + function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return add (l_float, r); + end function "+"; + + function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return subtract (l, r_float); + end function "-"; + + function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return subtract (l_float, r); + end function "-"; + + function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return subtract (l, r_float); + end function "-"; + + function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return subtract (l_float, r); + end function "-"; + + function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return multiply (l, r_float); + end function "*"; + + function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return multiply (l_float, r); + end function "*"; + + function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return multiply (l, r_float); + end function "*"; + + function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return multiply (l_float, r); + end function "*"; + + function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return divide (l, r_float); + end function "/"; + + function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return divide (l_float, r); + end function "/"; + + function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return divide (l, r_float); + end function "/"; + + function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return divide (l_float, r); + end function "/"; + + function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return remainder (l, r_float); + end function "rem"; + + function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return remainder (l_float, r); + end function "rem"; + + function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return remainder (l, r_float); + end function "rem"; + + function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return remainder (l_float, r); + end function "rem"; + + function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return modulo (l, r_float); + end function "mod"; + + function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return modulo (l_float, r); + end function "mod"; + + function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return modulo (l, r_float); + end function "mod"; + + function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return modulo (l_float, r); + end function "mod"; + + function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return eq (l, r_float); + end function "="; + + function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return ne (l, r_float); + end function "/="; + + function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return ge (l, r_float); + end function ">="; + + function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return le (l, r_float); + end function "<="; + + function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return gt (l, r_float); + end function ">"; + + function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return lt (l, r_float); + end function "<"; + + function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return eq (l_float, r); + end function "="; + + function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return ne (l_float, r); + end function "/="; + + function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return ge (l_float, r); + end function ">="; + + function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return le (l_float, r); + end function "<="; + + function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return gt (l_float, r); + end function ">"; + + function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return lt (l_float, r); + end function "<"; + + function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return eq (l, r_float); + end function "="; + + function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return ne (l, r_float); + end function "/="; + + function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return ge (l, r_float); + end function ">="; + + function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return le (l, r_float); + end function "<="; + + function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return gt (l, r_float); + end function ">"; + + function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return lt (l, r_float); + end function "<"; + + function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return eq (l_float, r); + end function "="; + + function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return ne (l_float, r); + end function "/="; + + function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return ge (l_float, r); + end function ">="; + + function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return le (l_float, r); + end function "<="; + + function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return gt (l_float, r); + end function ">"; + + function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float(l, r'high, -r'low); + return lt (l_float, r); + end function "<"; + + -- ?= overloads + function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?= r_float; + end function "?="; + + function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?/= r_float; + end function "?/="; + + function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?> r_float; + end function "?>"; + + function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?>= r_float; + end function "?>="; + + function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?< r_float; + end function "?<"; + + function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?<= r_float; + end function "?<="; + + -- real and float + function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?= r; + end function "?="; + + function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?/= r; + end function "?/="; + + function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?> r; + end function "?>"; + + function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?>= r; + end function "?>="; + + function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?< r; + end function "?<"; + + function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?<= r; + end function "?<="; + + -- ?= overloads + function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?= r_float; + end function "?="; + + function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?/= r_float; + end function "?/="; + + function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?> r_float; + end function "?>"; + + function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?>= r_float; + end function "?>="; + + function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?< r_float; + end function "?<"; + + function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return l ?<= r_float; + end function "?<="; + + -- integer and float + function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?= r; + end function "?="; + + function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?/= r; + end function "?/="; + + function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?> r; + end function "?>"; + + function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?>= r; + end function "?>="; + + function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?< r; + end function "?<"; + + function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return l_float ?<= r; + end function "?<="; + + -- minimum and maximum overloads + function minimum (l : UNRESOLVED_float; r : REAL) + return UNRESOLVED_float + is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return minimum (l, r_float); + end function minimum; + + function maximum (l : UNRESOLVED_float; r : REAL) + return UNRESOLVED_float + is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return maximum (l, r_float); + end function maximum; + + function minimum (l : REAL; r : UNRESOLVED_float) + return UNRESOLVED_float + is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return minimum (l_float, r); + end function minimum; + + function maximum (l : REAL; r : UNRESOLVED_float) + return UNRESOLVED_float + is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return maximum (l_float, r); + end function maximum; + + function minimum (l : UNRESOLVED_float; r : INTEGER) + return UNRESOLVED_float + is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return minimum (l, r_float); + end function minimum; + + function maximum (l : UNRESOLVED_float; r : INTEGER) + return UNRESOLVED_float + is + variable r_float : UNRESOLVED_float (l'range); + begin + r_float := to_float (r, l'high, -l'low); + return maximum (l, r_float); + end function maximum; + + function minimum (l : INTEGER; r : UNRESOLVED_float) + return UNRESOLVED_float + is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return minimum (l_float, r); + end function minimum; + + function maximum (l : INTEGER; r : UNRESOLVED_float) + return UNRESOLVED_float + is + variable l_float : UNRESOLVED_float (r'range); + begin + l_float := to_float (l, r'high, -r'low); + return maximum (l_float, r); + end function maximum; + + ---------------------------------------------------------------------------- + -- logical functions + ---------------------------------------------------------------------------- + function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + RESULT := not to_sulv(L); + return to_float (RESULT, L'high, -L'low); + end function "not"; + + function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) and to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """and"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "and"; + + function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) or to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """or"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "or"; + + function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nand to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """nand"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "nand"; + + function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) nor to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """nor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "nor"; + + function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xor to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """xor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "xor"; + + function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is + variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto + begin + if (L'high = R'high and L'low = R'low) then + RESULT := to_sulv(L) xnor to_sulv(R); + else + assert NO_WARNING + report float_generic_pkg'instance_name + & """xnor"": Range error L'RANGE /= R'RANGE" + severity warning; + RESULT := (others => 'X'); + end if; + return to_float (RESULT, L'high, -L'low); + end function "xnor"; + + -- Vector and std_ulogic functions, same as functions in numeric_std + function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L and to_sulv(R)); + return result; + end function "and"; + + function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) and R); + return result; + end function "and"; + + function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L or to_sulv(R)); + return result; + end function "or"; + + function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) or R); + return result; + end function "or"; + + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L nand to_sulv(R)); + return result; + end function "nand"; + + function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) nand R); + return result; + end function "nand"; + + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L nor to_sulv(R)); + return result; + end function "nor"; + + function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) nor R); + return result; + end function "nor"; + + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L xor to_sulv(R)); + return result; + end function "xor"; + + function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) xor R); + return result; + end function "xor"; + + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (R'range); + begin + result := UNRESOLVED_float (L xnor to_sulv(R)); + return result; + end function "xnor"; + + function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (L'range); + begin + result := UNRESOLVED_float (to_sulv(L) xnor R); + return result; + end function "xnor"; + + -- Reduction operators, same as numeric_std functions + + function "and" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return and to_sulv(l); + end function "and"; + + function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return nand to_sulv(l); + end function "nand"; + + function "or" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return or to_sulv(l); + end function "or"; + + function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return nor to_sulv(l); + end function "nor"; + + function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return xor to_sulv(l); + end function "xor"; + + function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is + begin + return xnor to_sulv(l); + end function "xnor"; + + ----------------------------------------------------------------------------- + -- Recommended Functions from the IEEE 754 Appendix + ----------------------------------------------------------------------------- + -- returns x with the sign of y. + function Copysign ( + x, y : UNRESOLVED_float) -- floating point input + return UNRESOLVED_float is + begin + return y(y'high) & x (x'high-1 downto x'low); + end function Copysign; + + -- Returns y * 2**n for integral values of N without computing 2**n + function Scalb ( + y : UNRESOLVED_float; -- floating point input + N : INTEGER; -- exponent to add + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction + constant exponent_width : NATURAL := y'high; -- length of FP output exponent + variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument + variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp + variable exp : SIGNED (exponent_width downto 0); + variable ufract : UNSIGNED (fraction_width downto 0); + constant expon_base : SIGNED (exponent_width-1 downto 0) + := gen_expon_base(exponent_width); -- exponent offset + variable fptype : valid_fpstate; + begin + -- This can be done by simply adding N to the exponent. + arg := to_01 (y, 'X'); + fptype := classfp(arg, check_error); + classcase : case fptype is + when isx => + result := (others => 'X'); + when nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + result := qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + when others => + break_number ( + arg => arg, + fptyp => fptype, + denormalize => denormalize, + fract => ufract, + expon => expon); + exp := resize (expon, exp'length) + N; + result := normalize ( + fract => ufract, + expon => exp, + sign => to_x01 (arg (arg'high)), + fraction_width => fraction_width, + exponent_width => exponent_width, + round_style => round_style, + denormalize => denormalize, + nguard => 0); + end case classcase; + return result; + end function Scalb; + + -- Returns y * 2**n for integral values of N without computing 2**n + function Scalb ( + y : UNRESOLVED_float; -- floating point input + N : UNRESOLVED_SIGNED; -- exponent to add + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float + is + variable n_int : INTEGER; + begin + n_int := to_integer(N); + return Scalb (y => y, + N => n_int, + round_style => round_style, + check_error => check_error, + denormalize => denormalize); + end function Scalb; + + -- returns the unbiased exponent of x + function Logb ( + x : UNRESOLVED_float) -- floating point input + return INTEGER + is + constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction + constant exponent_width : NATURAL := x'high; -- length of FP output exponent + variable result : INTEGER; -- result + variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument + variable expon : SIGNED (exponent_width - 1 downto 0); + variable fract : UNSIGNED (fraction_width downto 0); + constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent + -- offset +1 + variable fptype : valid_fpstate; + begin + -- Just return the exponent. + arg := to_01 (x, 'X'); + fptype := classfp(arg); + classcase : case fptype is + when isx | nan | quiet_nan => + -- Return quiet NAN, IEEE754-1985-7.1,1 + result := 0; + when pos_denormal | neg_denormal => + fract (fraction_width) := '0'; + fract (fraction_width-1 downto 0) := + UNSIGNED (to_slv(arg(-1 downto -fraction_width))); + result := find_leftmost (fract, '1') -- Find the first "1" + - fraction_width; -- subtract the length we want + result := -expon_base + 1 + result; + when others => + expon := SIGNED(arg (exponent_width - 1 downto 0)); + expon(exponent_width-1) := not expon(exponent_width-1); + expon := expon + 1; + result := to_integer (expon); + end case classcase; + return result; + end function Logb; + + -- returns the unbiased exponent of x + function Logb ( + x : UNRESOLVED_float) -- floating point input + return UNRESOLVED_SIGNED + is + constant exponent_width : NATURAL := x'high; -- length of FP output exponent + variable result : SIGNED (exponent_width - 1 downto 0); -- result + begin + -- Just return the exponent. + result := to_signed (Logb (x), exponent_width); + return result; + end function Logb; + + -- returns the next representable neighbor of x in the direction toward y + function Nextafter ( + x, y : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_float + is + constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction + constant exponent_width : NATURAL := x'high; -- length of FP output exponent + function "=" ( + l, r : UNRESOLVED_float) -- inputs + return BOOLEAN is + begin -- function "=" + return eq (l => l, + r => r, + check_error => false); + end function "="; + function ">" ( + l, r : UNRESOLVED_float) -- inputs + return BOOLEAN is + begin -- function ">" + return gt (l => l, + r => r, + check_error => false); + end function ">"; + variable fract : UNSIGNED (fraction_width-1 downto 0); + variable expon : UNSIGNED (exponent_width-1 downto 0); + variable sign : STD_ULOGIC; + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable validfpx, validfpy : valid_fpstate; -- Valid FP state + begin -- fp_Nextafter + -- If Y > X, add one to the fraction, otherwise subtract. + validfpx := classfp (x, check_error); + validfpy := classfp (y, check_error); + if validfpx = isx or validfpy = isx then + result := (others => 'X'); + return result; + elsif (validfpx = nan or validfpy = nan) then + return nanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif (validfpx = quiet_nan or validfpy = quiet_nan) then + return qnanfp (fraction_width => fraction_width, + exponent_width => exponent_width); + elsif x = y then -- Return X + return x; + else + fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction + expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent + sign := x(exponent_width); -- sign bit + if (y > x) then + -- Increase the number given + if validfpx = neg_inf then + -- return most negative number + expon := (others => '1'); + expon (0) := '0'; + fract := (others => '1'); + elsif validfpx = pos_zero or validfpx = neg_zero then + -- return smallest denormal number + sign := '0'; + expon := (others => '0'); + fract := (others => '0'); + fract(0) := '1'; + elsif validfpx = pos_normal then + if and (fract) = '1' then -- fraction is all "1". + if and (expon (exponent_width-1 downto 1)) = '1' + and expon (0) = '0' then + -- Exponent is one away from infinity. + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "FP_NEXTAFTER: NextAfter overflow" + severity warning; + return pos_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + expon := expon + 1; + fract := (others => '0'); + end if; + else + fract := fract + 1; + end if; + elsif validfpx = pos_denormal then + if and (fract) = '1' then -- fraction is all "1". + -- return smallest possible normal number + expon := (others => '0'); + expon(0) := '1'; + fract := (others => '0'); + else + fract := fract + 1; + end if; + elsif validfpx = neg_normal then + if or (fract) = '0' then -- fraction is all "0". + if or (expon (exponent_width-1 downto 1)) = '0' and + expon (0) = '1' then -- Smallest exponent + -- return the largest negative denormal number + expon := (others => '0'); + fract := (others => '1'); + else + expon := expon - 1; + fract := (others => '1'); + end if; + else + fract := fract - 1; + end if; + elsif validfpx = neg_denormal then + if or (fract(fract'high downto 1)) = '0' + and fract (0) = '1' then -- Smallest possible fraction + return zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + fract := fract - 1; + end if; + end if; + else + -- Decrease the number + if validfpx = pos_inf then + -- return most positive number + expon := (others => '1'); + expon (0) := '0'; + fract := (others => '1'); + elsif validfpx = pos_zero + or classfp (x) = neg_zero then + -- return smallest negative denormal number + sign := '1'; + expon := (others => '0'); + fract := (others => '0'); + fract(0) := '1'; + elsif validfpx = neg_normal then + if and (fract) = '1' then -- fraction is all "1". + if and (expon (exponent_width-1 downto 1)) = '1' + and expon (0) = '0' then + -- Exponent is one away from infinity. + assert NO_WARNING + report FLOAT_GENERIC_PKG'instance_name + & "FP_NEXTAFTER: NextAfter overflow" + severity warning; + return neg_inffp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + expon := expon + 1; -- Fraction overflow + fract := (others => '0'); + end if; + else + fract := fract + 1; + end if; + elsif validfpx = neg_denormal then + if and (fract) = '1' then -- fraction is all "1". + -- return smallest possible normal number + expon := (others => '0'); + expon(0) := '1'; + fract := (others => '0'); + else + fract := fract + 1; + end if; + elsif validfpx = pos_normal then + if or (fract) = '0' then -- fraction is all "0". + if or (expon (exponent_width-1 downto 1)) = '0' and + expon (0) = '1' then -- Smallest exponent + -- return the largest positive denormal number + expon := (others => '0'); + fract := (others => '1'); + else + expon := expon - 1; + fract := (others => '1'); + end if; + else + fract := fract - 1; + end if; + elsif validfpx = pos_denormal then + if or (fract(fract'high downto 1)) = '0' + and fract (0) = '1' then -- Smallest possible fraction + return zerofp (fraction_width => fraction_width, + exponent_width => exponent_width); + else + fract := fract - 1; + end if; + end if; + end if; + result (-1 downto -fraction_width) := UNRESOLVED_float(fract); + result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); + result (exponent_width) := sign; + return result; + end if; + end function Nextafter; + + -- Returns True if X is unordered with Y. + function Unordered ( + x, y : UNRESOLVED_float) -- floating point input + return BOOLEAN + is + variable lfptype, rfptype : valid_fpstate; + begin + lfptype := classfp (x); + rfptype := classfp (y); + if (lfptype = nan or lfptype = quiet_nan or + rfptype = nan or rfptype = quiet_nan or + lfptype = isx or rfptype = isx) then + return true; + else + return false; + end if; + end function Unordered; + + function Finite ( + x : UNRESOLVED_float) + return BOOLEAN + is + variable fp_state : valid_fpstate; -- fp state + begin + fp_state := Classfp (x); + if (fp_state = pos_inf) or (fp_state = neg_inf) then + return true; + else + return false; + end if; + end function Finite; + + function Isnan ( + x : UNRESOLVED_float) + return BOOLEAN + is + variable fp_state : valid_fpstate; -- fp state + begin + fp_state := Classfp (x); + if (fp_state = nan) or (fp_state = quiet_nan) then + return true; + else + return false; + end if; + end function Isnan; + + -- Function to return constants. + function zerofp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + return result; + end function zerofp; + + function nanfp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + result (exponent_width-1 downto 0) := (others => '1'); + -- Exponent all "1" + result (-1) := '1'; -- MSB of Fraction "1" + -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" + -- The difference between a signaling NAN and a quiet NAN is that + -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a + -- "0" in a quiet NAN. + return result; + end function nanfp; + + function qnanfp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + result (exponent_width-1 downto 0) := (others => '1'); + -- Exponent all "1" + result (-fraction_width) := '1'; -- LSB of Fraction "1" + -- (Could have been any bit) + return result; + end function qnanfp; + + function pos_inffp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" + return result; + end function pos_inffp; + + function neg_inffp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + result (exponent_width downto 0) := (others => '1'); -- top bits all "1" + return result; + end function neg_inffp; + + function neg_zerofp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := + (others => '0'); -- zero + begin + result (exponent_width) := '1'; + return result; + end function neg_zerofp; + + -- size_res versions + function zerofp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return zerofp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function zerofp; + + function nanfp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return nanfp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function nanfp; + + function qnanfp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return qnanfp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function qnanfp; + + function pos_inffp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return pos_inffp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function pos_inffp; + + function neg_inffp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return neg_inffp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function neg_inffp; + + function neg_zerofp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float is + begin + return neg_zerofp ( + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function neg_zerofp; + + -- Textio functions + -- purpose: writes float into a line (NOTE changed basetype) + type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); + type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; + type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; + type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; + + constant NBSP : CHARACTER := CHARACTER'val(160); -- space character + constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; + constant char_to_MVL9 : MVL9_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); + constant char_to_MVL9plus : MVL9plus_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); + + -- purpose: Skips white space + procedure skip_whitespace ( + L : inout LINE) is + variable readOk : BOOLEAN; + variable c : CHARACTER; + begin + while L /= null and L.all'length /= 0 loop + if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then + read (l, c, readOk); + else + exit; + end if; + end loop; + end procedure skip_whitespace; + + -- purpose: Checks the punctuation in a line + procedure check_punctuation ( + arg : in STRING; + colon : out BOOLEAN; -- There was a colon in the line + dot : out BOOLEAN; -- There was a dot in the line + good : out BOOLEAN; -- True if enough characters found + chars : in INTEGER) is + -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" + alias xarg : STRING (1 to arg'length) is arg; -- make it downto range + variable icolon, idot : BOOLEAN; -- internal + variable j : INTEGER := 0; -- charters read + begin + good := false; + icolon := false; + idot := false; + for i in 1 to arg'length loop + if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then + exit; + elsif xarg(i) = ':' then + icolon := true; + elsif xarg(i) = '.' then + idot := true; + elsif xarg (i) /= '_' then + j := j + 1; + end if; + end loop; + if j = chars then + good := true; -- There are enough charactes to read + end if; + colon := icolon; + if idot and icolon then + dot := false; + else + dot := idot; + end if; + end procedure check_punctuation; + + -- purpose: Searches a line for a ":" and replaces it with a ".". + procedure fix_colon ( + arg : inout STRING; + chars : in integer) is + alias xarg : STRING (1 to arg'length) is arg; -- make it downto range + variable j : INTEGER := 0; -- charters read + begin + for i in 1 to arg'length loop + if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then + exit; + elsif xarg(i) = ':' then + xarg (i) := '.'; + elsif xarg (i) /= '_' then + j := j + 1; + end if; + end loop; + end procedure fix_colon; + + procedure WRITE ( + L : inout LINE; -- input line + VALUE : in UNRESOLVED_float; -- floating point input + JUSTIFIED : in SIDE := right; + FIELD : in WIDTH := 0) is + variable s : STRING(1 to value'high - value'low +3); + variable sindx : INTEGER; + begin -- function write + s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); + s(2) := ':'; + sindx := 3; + for i in VALUE'high-1 downto 0 loop + s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); + sindx := sindx + 1; + end loop; + s(sindx) := ':'; + sindx := sindx + 1; + for i in -1 downto VALUE'low loop + s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); + sindx := sindx + 1; + end loop; + WRITE (L, s, JUSTIFIED, FIELD); + end procedure WRITE; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is + -- Possible data: 0:0000:0000000 + -- 000000000000 + variable c : CHARACTER; + variable mv : UNRESOLVED_float (VALUE'range); + variable readOk : BOOLEAN; + variable lastu : BOOLEAN := false; -- last character was an "_" + variable i : INTEGER; -- index variable + begin -- READ + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + READ (l, c, readOk); + if VALUE'length > 0 then + i := value'high; + readloop : loop + if readOk = false then -- Bail out if there was a bad read + report float_generic_pkg'instance_name + & "READ(float): " + & "Error end of file encountered." + severity error; + return; + elsif c = ' ' or c = CR or c = HT then -- reading done. + if (i /= value'low) then + report float_generic_pkg'instance_name + & "READ(float): " + & "Warning: Value truncated." + severity warning; + return; + end if; + elsif c = '_' then + if i = value'high then -- Begins with an "_" + report float_generic_pkg'instance_name + & "READ(float): " + & "String begins with an ""_""" severity error; + return; + elsif lastu then -- "__" detected + report float_generic_pkg'instance_name + & "READ(float): " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + elsif c = ':' or c = '.' then -- separator, ignore + if not (i = -1 or i = value'high-1) then + report float_generic_pkg'instance_name + & "READ(float): " + & "Warning: Separator point does not match number format: '" + & c & "' encountered at location " & INTEGER'image(i) & "." + severity warning; + end if; + lastu := false; + elsif (char_to_MVL9plus(c) = error) then + report float_generic_pkg'instance_name + & "READ(float): " + & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." + severity error; + return; + else + mv (i) := char_to_MVL9(c); + i := i - 1; + if i < value'low then + VALUE := mv; + return; + end if; + lastu := false; + end if; + READ (l, c, readOk); + end loop readloop; + end if; + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is + -- Possible data: 0:0000:0000000 + -- 000000000000 + variable c : CHARACTER; + variable mv : UNRESOLVED_float (VALUE'range); + variable lastu : BOOLEAN := false; -- last character was an "_" + variable i : INTEGER; -- index variable + variable readOk : BOOLEAN; + begin -- READ + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + READ (l, c, readOk); + if VALUE'length > 0 then + i := value'high; + good := false; + readloop : loop + if readOk = false then -- Bail out if there was a bad read + return; + elsif c = ' ' or c = CR or c = HT then -- reading done + return; + elsif c = '_' then + if i = 0 then -- Begins with an "_" + return; + elsif lastu then -- "__" detected + return; + else + lastu := true; + end if; + elsif c = ':' or c = '.' then -- separator, ignore + -- good := (i = -1 or i = value'high-1); + lastu := false; + elsif (char_to_MVL9plus(c) = error) then + return; + else + mv (i) := char_to_MVL9(c); + i := i - 1; + if i < value'low then + good := true; + VALUE := mv; + return; + end if; + lastu := false; + end if; + READ (l, c, readOk); + end loop readloop; + else + good := true; -- read into a null array + end if; + end procedure READ; + + procedure OWRITE ( + L : inout LINE; -- access type (pointer) + VALUE : in UNRESOLVED_float; -- value to write + JUSTIFIED : in SIDE := right; -- which side to justify text + FIELD : in WIDTH := 0) is -- width of field + begin + WRITE (L => L, + VALUE => to_ostring(VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure OWRITE; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is + constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad + variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv + variable slvu : ufixed (VALUE'range); -- Unsigned fixed point + variable c : CHARACTER; + variable ok : BOOLEAN; + variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits + variable colon, dot : BOOLEAN; + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + check_punctuation (arg => L.all, + colon => colon, + dot => dot, + good => ok, + chars => ne/3); + if not ok then + report float_generic_pkg'instance_name & "OREAD: " + & "short string encounted: " & L.all + & " needs to have " & integer'image (ne/3) + & " valid octal characters." + severity error; + return; + elsif dot then + OREAD (L, slvu, ok); -- read it like a UFIXED number + if not ok then + report float_generic_pkg'instance_name & "OREAD: " + & "error encounted reading STRING " & L.all + severity error; + return; + else + VALUE := UNRESOLVED_float (slvu); + end if; + elsif colon then + OREAD (L, nybble, ok); -- read the sign bit + if not ok then + report float_generic_pkg'instance_name & "OREAD: " + & "End of string encountered" + severity error; + return; + elsif nybble (2 downto 1) /= "00" then + report float_generic_pkg'instance_name & "OREAD: " + & "Illegal sign bit STRING encounted " + severity error; + return; + end if; + read (l, c, ok); -- read the colon + fix_colon (L.all, ne/3); -- replaces the colon with a ".". + OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number + if not ok then + report float_generic_pkg'instance_name & "OREAD: " + & "error encounted reading STRING " & L.all + severity error; + return; + else + slvu (slvu'high) := nybble (0); + VALUE := UNRESOLVED_float (slvu); + end if; + else + OREAD (L, slv, ok); + if not ok then + report float_generic_pkg'instance_name & "OREAD: " + & "Error encounted during read" + severity error; + return; + end if; + if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then + report float_generic_pkg'instance_name & "OREAD: " + & "Vector truncated." + severity error; + return; + end if; + VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), + VALUE'high, -VALUE'low); + end if; + end if; + end procedure OREAD; + + procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is + constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad + variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv + variable slvu : ufixed (VALUE'range); -- Unsigned fixed point + variable c : CHARACTER; + variable ok : BOOLEAN; + variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits + variable colon, dot : BOOLEAN; + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + GOOD := false; + Skip_whitespace (L); + if VALUE'length > 0 then + check_punctuation (arg => L.all, + colon => colon, + dot => dot, + good => ok, + chars => ne/3); + if not ok then + return; + elsif dot then + OREAD (L, slvu, ok); -- read it like a UFIXED number + if not ok then + return; + else + VALUE := UNRESOLVED_float (slvu); + end if; + elsif colon then + OREAD (L, nybble, ok); -- read the sign bit + if not ok then + return; + elsif nybble (2 downto 1) /= "00" then + return; + end if; + read (l, c, ok); -- read the colon + fix_colon (L.all, ne/3); -- replaces the colon with a ".". + OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number + if not ok then + return; + else + slvu (slvu'high) := nybble (0); + VALUE := UNRESOLVED_float (slvu); + end if; + else + OREAD (L, slv, ok); + if not ok then + return; + end if; + if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then + return; + end if; + VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), + VALUE'high, -VALUE'low); + end if; + GOOD := true; + end if; + end procedure OREAD; + + procedure HWRITE ( + L : inout LINE; -- access type (pointer) + VALUE : in UNRESOLVED_float; -- value to write + JUSTIFIED : in SIDE := right; -- which side to justify text + FIELD : in WIDTH := 0) is -- width of field + begin + WRITE (L => L, + VALUE => to_hstring(VALUE), + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure HWRITE; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is + constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad + variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv + variable slvu : ufixed (VALUE'range); -- Unsigned fixed point + variable c : CHARACTER; + variable ok : BOOLEAN; + variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits + variable colon, dot : BOOLEAN; + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + check_punctuation (arg => L.all, + colon => colon, + dot => dot, + good => ok, + chars => ne/4); + if not ok then + report float_generic_pkg'instance_name & "HREAD: " + & "short string encounted: " & L.all + & " needs to have " & integer'image (ne/4) + & " valid hex characters." + severity error; + return; + elsif dot then + HREAD (L, slvu, ok); -- read it like a UFIXED number + if not ok then + report float_generic_pkg'instance_name & "HREAD: " + & "error encounted reading STRING " & L.all + severity error; + return; + else + VALUE := UNRESOLVED_float (slvu); + end if; + elsif colon then + HREAD (L, nybble, ok); -- read the sign bit + if not ok then + report float_generic_pkg'instance_name & "HREAD: " + & "End of string encountered" + severity error; + return; + elsif nybble (3 downto 1) /= "000" then + report float_generic_pkg'instance_name & "HREAD: " + & "Illegal sign bit STRING encounted " + severity error; + return; + end if; + read (l, c, ok); -- read the colon + fix_colon (L.all, ne/4); -- replaces the colon with a ".". + HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number + if not ok then + report float_generic_pkg'instance_name & "HREAD: " + & "error encounted reading STRING " & L.all + severity error; + return; + else + slvu (slvu'high) := nybble (0); + VALUE := UNRESOLVED_float (slvu); + end if; + else + HREAD (L, slv, ok); + if not ok then + report float_generic_pkg'instance_name & "HREAD: " + & "Error encounted during read" + severity error; + return; + end if; + if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then + report float_generic_pkg'instance_name & "HREAD: " + & "Vector truncated." + severity error; + return; + end if; + VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), + VALUE'high, -VALUE'low); + end if; + end if; + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is + constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad + variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv + variable slvu : ufixed (VALUE'range); -- Unsigned fixed point + variable c : CHARACTER; + variable ok : BOOLEAN; + variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits + variable colon, dot : BOOLEAN; + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + GOOD := false; + Skip_whitespace (L); + if VALUE'length > 0 then + check_punctuation (arg => L.all, + colon => colon, + dot => dot, + good => ok, + chars => ne/4); + if not ok then + return; + elsif dot then + HREAD (L, slvu, ok); -- read it like a UFIXED number + if not ok then + return; + else + VALUE := UNRESOLVED_float (slvu); + end if; + elsif colon then + HREAD (L, nybble, ok); -- read the sign bit + if not ok then + return; + elsif nybble (3 downto 1) /= "000" then + return; + end if; + read (l, c, ok); -- read the colon + fix_colon (L.all, ne/4); -- replaces the colon with a ".". + HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number + if not ok then + return; + else + slvu (slvu'high) := nybble (0); + VALUE := UNRESOLVED_float (slvu); + end if; + else + HREAD (L, slv, ok); + if not ok then + return; + end if; + if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then + return; + end if; + VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), + VALUE'high, -VALUE'low); + end if; + GOOD := true; + end if; + end procedure HREAD; + + function to_string (value : UNRESOLVED_float) return STRING is + variable s : STRING(1 to value'high - value'low +3); + variable sindx : INTEGER; + begin -- function write + s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); + s(2) := ':'; + sindx := 3; + for i in VALUE'high-1 downto 0 loop + s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); + sindx := sindx + 1; + end loop; + s(sindx) := ':'; + sindx := sindx + 1; + for i in -1 downto VALUE'low loop + s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); + sindx := sindx + 1; + end loop; + return s; + end function to_string; + + function to_hstring (value : UNRESOLVED_float) return STRING is + variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); + begin + floop : for i in slv'range loop + slv(i) := to_X01Z (value(i + value'low)); + end loop floop; + return to_hstring (slv); + end function to_hstring; + + function to_ostring (value : UNRESOLVED_float) return STRING is + variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); + begin + floop : for i in slv'range loop + slv(i) := to_X01Z (value(i + value'low)); + end loop floop; + return to_ostring (slv); + end function to_ostring; + + function from_string ( + bstring : STRING; -- binary string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(bstring); + READ (L, result, good); + deallocate (L); + assert (good) + report FLOAT_GENERIC_PKG'instance_name + & "from_string: Bad string " & bstring + severity error; + return result; + end function from_string; + + function from_ostring ( + ostring : STRING; -- Octal string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(ostring); + OREAD (L, result, good); + deallocate (L); + assert (good) + report FLOAT_GENERIC_PKG'instance_name + & "from_ostring: Bad string " & ostring + severity error; + return result; + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float + is + variable result : UNRESOLVED_float (exponent_width downto -fraction_width); + variable L : LINE; + variable good : BOOLEAN; + begin + L := new STRING'(hstring); + HREAD (L, result, good); + deallocate (L); + assert (good) + report FLOAT_GENERIC_PKG'instance_name + & "from_hstring: Bad string " & hstring + severity error; + return result; + end function from_hstring; + + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float is + begin + return from_string (bstring => bstring, + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function from_string; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float is + begin + return from_ostring (ostring => ostring, + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function from_ostring; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float is + begin + return from_hstring (hstring => hstring, + exponent_width => size_res'high, + fraction_width => -size_res'low); + end function from_hstring; + +end package body float_generic_pkg; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg.vhdl new file mode 100644 index 0000000..12c4753 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_generic_pkg.vhdl @@ -0,0 +1,1000 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Floating-point package (Generic package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary floating point +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +use STD.TEXTIO.all; +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.fixed_float_types.all; + +package float_generic_pkg is + generic ( + -- Defaults for sizing routines, when you do a "to_float" this will be + -- the default size. Example float32 would be 8 and 23 (8 downto -23) + float_exponent_width : NATURAL := 8; + float_fraction_width : NATURAL := 23; + -- Rounding algorithm, "round_nearest" is default, other valid values + -- are "round_zero" (truncation), "round_inf" (round up), and + -- "round_neginf" (round down) + float_round_style : round_type := round_nearest; + -- Denormal numbers (very small numbers near zero) true or false + float_denormalize : BOOLEAN := true; + -- Turns on NAN processing (invalid numbers and overflow) true of false + float_check_error : BOOLEAN := true; + -- Guard bits are added to the bottom of every operation for rounding. + -- any natural number (including 0) are valid. + float_guard_bits : NATURAL := 3; + -- If TRUE, then turn off warnings on "X" propagation + no_warning : BOOLEAN := false; + package fixed_pkg is new IEEE.fixed_generic_pkg + generic map (<>) ); + + -- Author David Bishop (dbishop@vhdl.org) + constant CopyRightNotice : STRING := + "Copyright 2008 by IEEE. All rights reserved."; + + use fixed_pkg.all; + + -- Note that this is "INTEGER range <>", thus if you use a literal, then the + -- default range will be (INTEGER'low to INTEGER'low + X) + type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type + alias U_float is UNRESOLVED_float; + + subtype float is (resolved) UNRESOLVED_float; + ----------------------------------------------------------------------------- + -- Use the float type to define your own floating point numbers. + -- There must be a negative index or the packages will error out. + -- Minimum supported is "subtype float7 is float (3 downto -3);" + -- "subtype float16 is float (6 downto -9);" is probably the smallest + -- practical one to use. + ----------------------------------------------------------------------------- + + -- IEEE 754 single precision + subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23); + alias U_float32 is UNRESOLVED_float32; + subtype float32 is float (8 downto -23); + ----------------------------------------------------------------------------- + -- IEEE-754 single precision floating point. This is a "float" + -- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and + -- the fraction is 23 bits wide. This format can hold roughly 7 decimal + -- digits. Infinity is 2**127 = 1.7E38 in this number system. + -- The bit representation is as follows: + -- 1 09876543 21098765432109876543210 + -- 8 76543210 12345678901234567890123 + -- 0 00000000 00000000000000000000000 + -- 8 7 0 -1 -23 + -- +/- exp. fraction + ----------------------------------------------------------------------------- + + -- IEEE 754 double precision + subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52); + alias U_float64 is UNRESOLVED_float64; + subtype float64 is float (11 downto -52); + ----------------------------------------------------------------------------- + -- IEEE-754 double precision floating point. This is a "double float" + -- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and + -- the fraction is 52 bits wide. This format can hold roughly 15 decimal + -- digits. Infinity is 2**2047 in this number system. + -- The bit representation is as follows: + -- 3 21098765432 1098765432109876543210987654321098765432109876543210 + -- 1 09876543210 1234567890123456789012345678901234567890123456789012 + -- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + -- 11 10 0 -1 -52 + -- +/- exponent fraction + ----------------------------------------------------------------------------- + + -- IEEE 854 & C extended precision + subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112); + alias U_float128 is UNRESOLVED_float128; + subtype float128 is float (15 downto -112); + ----------------------------------------------------------------------------- + -- The 128 bit floating point number is "long double" in C (on + -- some systems this is a 70 bit floating point number) and FLOAT*32 + -- in Fortran. The exponent is 15 bits wide and the fraction is 112 + -- bits wide. This number can handle approximately 33 decimal digits. + -- Infinity is 2**32,767 in this number system. + ----------------------------------------------------------------------------- + + -- purpose: Checks for a valid floating point number + type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN) + quiet_nan, -- Quiet NaN (C FP_NAN) + neg_inf, -- Negative infinity (C FP_INFINITE) + neg_normal, -- negative normalized nonzero + neg_denormal, -- negative denormalized (FP_SUBNORMAL) + neg_zero, -- -0 (C FP_ZERO) + pos_zero, -- +0 (C FP_ZERO) + pos_denormal, -- Positive denormalized (FP_SUBNORMAL) + pos_normal, -- positive normalized nonzero + pos_inf, -- positive infinity + isx); -- at least one input is unknown + + -- This deferred constant will tell you if the package body is synthesizable + -- or implemented as real numbers. + constant fphdlsynth_or_real : BOOLEAN; -- deferred constant + + -- Returns the class which X falls into + function Classfp ( + x : UNRESOLVED_float; -- floating point input + check_error : BOOLEAN := float_check_error) -- check for errors + return valid_fpstate; + + -- Arithmetic functions, these operators do not require parameters. + function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float; + function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float; + + -- These allows the base math functions to use the default values + -- of their parameters. Thus they do full IEEE floating point. + + function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + + -- Basic parameter list + -- round_style - Selects the rounding algorithm to use + -- guard - extra bits added to the end if the operation to add precision + -- check_error - When "false" turns off NAN and overflow checks + -- denormalize - When "false" turns off denormal number processing + + function add ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function subtract ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function multiply ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function divide ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function remainder ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function modulo ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- reciprocal + function reciprocal ( + arg : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function dividebyp2 ( + l, r : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- Multiply accumulate result = l*r + c + function mac ( + l, r, c : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant guard : NATURAL := float_guard_bits; -- number of guard bits + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- Square root (all 754 based implementations need this) + function sqrt ( + arg : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; + constant guard : NATURAL := float_guard_bits; + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_float; + + function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN; + + ----------------------------------------------------------------------------- + -- compare functions + -- =, /=, >=, <=, <, >, maximum, minimum + + function eq ( -- equal = + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + function ne ( -- not equal /= + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + function lt ( -- less than < + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + function gt ( -- greater than > + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + function le ( -- less than or equal to <= + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + function ge ( -- greater than or equal to >= + l, r : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; + constant denormalize : BOOLEAN := float_denormalize) + return BOOLEAN; + + -- Need to overload the default versions of these + function "=" (l, r : UNRESOLVED_float) return BOOLEAN; + function "/=" (l, r : UNRESOLVED_float) return BOOLEAN; + function ">=" (l, r : UNRESOLVED_float) return BOOLEAN; + function "<=" (l, r : UNRESOLVED_float) return BOOLEAN; + function ">" (l, r : UNRESOLVED_float) return BOOLEAN; + function "<" (l, r : UNRESOLVED_float) return BOOLEAN; + + function "?=" (l, r : UNRESOLVED_float) return STD_ULOGIC; + function "?/=" (l, r : UNRESOLVED_float) return STD_ULOGIC; + function "?>" (l, r : UNRESOLVED_float) return STD_ULOGIC; + function "?>=" (l, r : UNRESOLVED_float) return STD_ULOGIC; + function "?<" (l, r : UNRESOLVED_float) return STD_ULOGIC; + function "?<=" (l, r : UNRESOLVED_float) return STD_ULOGIC; + + function std_match (l, r : UNRESOLVED_float) return BOOLEAN; + function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) + return INTEGER; + function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) + return INTEGER; + function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float; + + -- conversion functions + -- Converts one floating point number into another. + + function resize ( + arg : UNRESOLVED_float; -- Floating point input + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function resize ( + arg : UNRESOLVED_float; -- Floating point input + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + function to_float32 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float32; + + function to_float64 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float64; + + function to_float128 ( + arg : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; + constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float128; + + -- Converts an fp into an SLV (needed for synthesis) + function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR; + alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR]; + alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR]; + + -- Converts an fp into an std_ulogic_vector (sulv) + function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR; + alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR]; + alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR]; + + -- std_ulogic_vector to float + function to_float ( + arg : STD_ULOGIC_VECTOR; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction + return UNRESOLVED_float; + + -- Integer to float + function to_float ( + arg : INTEGER; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- real to float + function to_float ( + arg : REAL; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- unsigned to float + function to_float ( + arg : UNRESOLVED_UNSIGNED; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- signed to float + function to_float ( + arg : UNRESOLVED_SIGNED; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- unsigned fixed point to float + function to_float ( + arg : UNRESOLVED_ufixed; -- unsigned fixed point input + constant exponent_width : NATURAL := float_exponent_width; -- width of exponent + constant fraction_width : NATURAL := float_fraction_width; -- width of fraction + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions + return UNRESOLVED_float; + + -- signed fixed point to float + function to_float ( + arg : UNRESOLVED_sfixed; + constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent + constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- rounding option + return UNRESOLVED_float; + + -- size_res functions + -- Integer to float + function to_float ( + arg : INTEGER; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- real to float + function to_float ( + arg : REAL; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- unsigned to float + function to_float ( + arg : UNRESOLVED_UNSIGNED; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- signed to float + function to_float ( + arg : UNRESOLVED_SIGNED; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style) -- rounding option + return UNRESOLVED_float; + + -- sulv to float + function to_float ( + arg : STD_ULOGIC_VECTOR; + size_res : UNRESOLVED_float) + return UNRESOLVED_float; + + -- unsigned fixed point to float + function to_float ( + arg : UNRESOLVED_ufixed; -- unsigned fixed point input + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions + return UNRESOLVED_float; + + -- signed fixed point to float + function to_float ( + arg : UNRESOLVED_sfixed; + size_res : UNRESOLVED_float; + constant round_style : round_type := float_round_style; -- rounding + constant denormalize : BOOLEAN := float_denormalize) -- rounding option + return UNRESOLVED_float; + + -- float to unsigned + function to_unsigned ( + arg : UNRESOLVED_float; -- floating point input + constant size : NATURAL; -- length of output + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_UNSIGNED; + + -- float to signed + function to_signed ( + arg : UNRESOLVED_float; -- floating point input + constant size : NATURAL; -- length of output + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_SIGNED; + + -- purpose: Converts a float to unsigned fixed point + function to_ufixed ( + arg : UNRESOLVED_float; -- fp input + constant left_index : INTEGER; -- integer part + constant right_index : INTEGER; -- fraction part + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_ufixed; + + -- float to signed fixed point + function to_sfixed ( + arg : UNRESOLVED_float; -- fp input + constant left_index : INTEGER; -- integer part + constant right_index : INTEGER; -- fraction part + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_sfixed; + + -- size_res versions + -- float to unsigned + function to_unsigned ( + arg : UNRESOLVED_float; -- floating point input + size_res : UNRESOLVED_UNSIGNED; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_UNSIGNED; + + -- float to signed + function to_signed ( + arg : UNRESOLVED_float; -- floating point input + size_res : UNRESOLVED_SIGNED; + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return UNRESOLVED_SIGNED; + + -- purpose: Converts a float to unsigned fixed point + function to_ufixed ( + arg : UNRESOLVED_float; -- fp input + size_res : UNRESOLVED_ufixed; + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_ufixed; + + -- float to signed fixed point + function to_sfixed ( + arg : UNRESOLVED_float; -- fp input + size_res : UNRESOLVED_sfixed; + constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate + constant round_style : fixed_round_style_type := fixed_round_style; -- rounding + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_sfixed; + + -- float to real + function to_real ( + arg : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return REAL; + + -- float to integer + function to_integer ( + arg : UNRESOLVED_float; -- floating point input + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error) -- check for errors + return INTEGER; + + -- For Verilog compatability + function realtobits (arg : REAL) return STD_ULOGIC_VECTOR; + function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL; + + -- Maps metalogical values + function to_01 ( + arg : UNRESOLVED_float; -- floating point input + XMAP : STD_LOGIC := '0') + return UNRESOLVED_float; + + function Is_X (arg : UNRESOLVED_float) return BOOLEAN; + function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float; + function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float; + function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float; + + -- These two procedures were copied out of the body because they proved + -- very useful for vendor specific algorithm development + -- Break_number converts a floating point number into it's parts + -- Exponent is biased by -1 + + procedure break_number ( + arg : in UNRESOLVED_float; + denormalize : in BOOLEAN := float_denormalize; + check_error : in BOOLEAN := float_check_error; + fract : out UNRESOLVED_UNSIGNED; + expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent! + sign : out STD_ULOGIC); + + procedure break_number ( + arg : in UNRESOLVED_float; + denormalize : in BOOLEAN := float_denormalize; + check_error : in BOOLEAN := float_check_error; + fract : out UNRESOLVED_ufixed; -- a number between 1.0 and 2.0 + expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent! + sign : out STD_ULOGIC); + + -- Normalize takes a fraction and and exponent and converts them into + -- a floating point number. Does the shifting and the rounding. + -- Exponent is assumed to be biased by -1 + + function normalize ( + fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized + expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent + constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float; + + -- Exponent is assumed to be biased by -1 + function normalize ( + fract : UNRESOLVED_ufixed; -- unsigned fixed point + expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent + constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float; + + function normalize ( + fract : UNRESOLVED_UNSIGNED; -- unsigned + expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + size_res : UNRESOLVED_float; -- used for sizing only + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float; + + -- Exponent is assumed to be biased by -1 + function normalize ( + fract : UNRESOLVED_ufixed; -- unsigned fixed point + expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized + sign : STD_ULOGIC; -- sign bit + sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) + size_res : UNRESOLVED_float; -- used for sizing only + constant round_style : round_type := float_round_style; -- rounding option + constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP + constant nguard : NATURAL := float_guard_bits) -- guard bits + return UNRESOLVED_float; + + -- overloaded versions + function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + + -- overloaded compare functions + function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN; + function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN; + function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN; + function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN; + function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC; + function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC; + function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC; + function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC; + -- minimum and maximum overloads + function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float; + function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float; + function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float; + function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; + function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float; +---------------------------------------------------------------------------- + -- logical functions + ---------------------------------------------------------------------------- + + function "not" (l : UNRESOLVED_float) return UNRESOLVED_float; + function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float; + -- Vector and std_ulogic functions, same as functions in numeric_std + function "and" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "and" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + function "or" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "or" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float) + return UNRESOLVED_float; + function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC) + return UNRESOLVED_float; + -- Reduction operators, same as numeric_std functions + function "and" (l : UNRESOLVED_float) return STD_ULOGIC; + function "nand" (l : UNRESOLVED_float) return STD_ULOGIC; + function "or" (l : UNRESOLVED_float) return STD_ULOGIC; + function "nor" (l : UNRESOLVED_float) return STD_ULOGIC; + function "xor" (l : UNRESOLVED_float) return STD_ULOGIC; + function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC; + + -- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented. + + ----------------------------------------------------------------------------- + -- Recommended Functions from the IEEE 754 Appendix + ----------------------------------------------------------------------------- + + -- returns x with the sign of y. + function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float; + + -- Returns y * 2**n for integral values of N without computing 2**n + function Scalb ( + y : UNRESOLVED_float; -- floating point input + N : INTEGER; -- exponent to add + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- Returns y * 2**n for integral values of N without computing 2**n + function Scalb ( + y : UNRESOLVED_float; -- floating point input + N : UNRESOLVED_SIGNED; -- exponent to add + constant round_style : round_type := float_round_style; -- rounding option + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP + return UNRESOLVED_float; + + -- returns the unbiased exponent of x + function Logb (x : UNRESOLVED_float) return INTEGER; + function Logb (x : UNRESOLVED_float) return UNRESOLVED_SIGNED; + + -- returns the next representable neighbor of x in the direction toward y + function Nextafter ( + x, y : UNRESOLVED_float; -- floating point input + constant check_error : BOOLEAN := float_check_error; -- check for errors + constant denormalize : BOOLEAN := float_denormalize) + return UNRESOLVED_float; + + -- Returns TRUE if X is unordered with Y. + function Unordered (x, y : UNRESOLVED_float) return BOOLEAN; + function Finite (x : UNRESOLVED_float) return BOOLEAN; + function Isnan (x : UNRESOLVED_float) return BOOLEAN; + + -- Function to return constants. + function zerofp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + function nanfp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + function qnanfp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + function pos_inffp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + function neg_inffp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + function neg_zerofp ( + constant exponent_width : NATURAL := float_exponent_width; -- exponent + constant fraction_width : NATURAL := float_fraction_width) -- fraction + return UNRESOLVED_float; + -- size_res versions + function zerofp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + function nanfp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + function qnanfp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + function pos_inffp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + function neg_inffp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + function neg_zerofp ( + size_res : UNRESOLVED_float) -- variable is only use for sizing + return UNRESOLVED_float; + + --=========================================================================== + -- string and textio Functions + --=========================================================================== + + -- writes S:EEEE:FFFFFFFF + procedure WRITE ( + L : inout LINE; -- access type (pointer) + VALUE : in UNRESOLVED_float; -- value to write + JUSTIFIED : in SIDE := right; -- which side to justify text + FIELD : in WIDTH := 0); -- width of field + + -- Reads SEEEEFFFFFFFF, "." and ":" are ignored + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float); + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; + GOOD : out BOOLEAN); + + alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN]; + alias BREAD is READ [LINE, UNRESOLVED_float]; + alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH]; + alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN]; + alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT]; + alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH]; + + procedure OWRITE ( + L : inout LINE; -- access type (pointer) + VALUE : in UNRESOLVED_float; -- value to write + JUSTIFIED : in SIDE := right; -- which side to justify text + FIELD : in WIDTH := 0); -- width of field + + -- Octal read with padding, no separators used + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float); + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float; + GOOD : out BOOLEAN); + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT]; + alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH]; + + -- Hex write with padding, no separators + procedure HWRITE ( + L : inout LINE; -- access type (pointer) + VALUE : in UNRESOLVED_float; -- value to write + JUSTIFIED : in SIDE := right; -- which side to justify text + FIELD : in WIDTH := 0); -- width of field + + -- Hex read with padding, no separators used + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float); + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; + GOOD : out BOOLEAN); + alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT]; + alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH]; + + -- returns "S:EEEE:FFFFFFFF" + function to_string (value : UNRESOLVED_float) return STRING; + alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING]; + alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING]; + + -- Returns a HEX string, with padding + function to_hstring (value : UNRESOLVED_float) return STRING; + alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING]; + + -- Returns and octal string, with padding + function to_ostring (value : UNRESOLVED_float) return STRING; + alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING]; + + function from_string ( + bstring : STRING; -- binary string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float; + alias from_bstring is from_string [STRING, NATURAL, NATURAL + return UNRESOLVED_float]; + alias from_binary_string is from_string [STRING, NATURAL, NATURAL + return UNRESOLVED_float]; + function from_ostring ( + ostring : STRING; -- Octal string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float; + alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL + return UNRESOLVED_float]; + + function from_hstring ( + hstring : STRING; -- hex string + constant exponent_width : NATURAL := float_exponent_width; + constant fraction_width : NATURAL := float_fraction_width) + return UNRESOLVED_float; + alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL + return UNRESOLVED_float]; + + function from_string ( + bstring : STRING; -- binary string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float; + alias from_bstring is from_string [STRING, UNRESOLVED_float + return UNRESOLVED_float]; + alias from_binary_string is from_string [STRING, UNRESOLVED_float + return UNRESOLVED_float]; + + function from_ostring ( + ostring : STRING; -- Octal string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float; + alias from_octal_string is from_ostring [STRING, UNRESOLVED_float + return UNRESOLVED_float]; + + function from_hstring ( + hstring : STRING; -- hex string + size_res : UNRESOLVED_float) -- used for sizing only + return UNRESOLVED_float; + alias from_hex_string is from_hstring [STRING, UNRESOLVED_float + return UNRESOLVED_float]; + +end package float_generic_pkg; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_pkg.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_pkg.vhdl new file mode 100644 index 0000000..a1068dc --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_pkg.vhdl @@ -0,0 +1,55 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Floating-point package (Instantiated package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines basic binary floating point +-- : arithmetic functions +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library ieee; + +package float_pkg is new IEEE.float_generic_pkg + generic map ( + float_exponent_width => 8, -- float32'high + float_fraction_width => 23, -- -float32'low + float_round_style => IEEE.fixed_float_types.round_nearest, -- round nearest algorithm + float_denormalize => true, -- Use IEEE extended floating + float_check_error => true, -- Turn on NAN and overflow processing + float_guard_bits => 3, -- number of guard bits + no_warning => false, -- show warnings + fixed_pkg => IEEE.fixed_pkg + ); diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex-body.vhdl new file mode 100644 index 0000000..9d03aff --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex-body.vhdl @@ -0,0 +1,1603 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Mathematical Packages +-- : (MATH_COMPLEX package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- : +-- Purpose : This package defines a standard for designers to use in +-- : describing VHDL models that make use of common COMPLEX +-- : constants and common COMPLEX mathematical functions and +-- : operators. +-- : +-- Limitation: The values generated by the functions in this package +-- : may vary from platform to platform, and the precision +-- : of results is only guaranteed to be the minimum required +-- : by IEEE Std 1076-2008. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +use WORK.MATH_REAL.all; + +package body MATH_COMPLEX is + + -- + -- Equality and Inequality Operators for COMPLEX_POLAR + -- + function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns FALSE on error + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in =(L,R)" + severity ERROR; + return FALSE; + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in =(L,R)" + severity ERROR; + return FALSE; + end if; + + -- Get special values + if ( L.MAG = 0.0 and R.MAG = 0.0 ) then + return TRUE; + end if; + + -- Get value for general case + if ( L.MAG = R.MAG and L.ARG = R.ARG ) then + return TRUE; + end if; + + return FALSE; + end function "="; + + + function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns FALSE on error + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in /=(L,R)" + severity ERROR; + return FALSE; + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in /=(L,R)" + severity ERROR; + return FALSE; + end if; + + -- Get special values + if ( L.MAG = 0.0 and R.MAG = 0.0 ) then + return FALSE; + end if; + + -- Get value for general case + if ( L.MAG = R.MAG and L.ARG = R.ARG ) then + return FALSE; + end if; + + return TRUE; + end function "/="; + + -- + -- Other Functions Start Here + -- + + function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(X, Y); + end function CMPLX; + + + function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + variable TEMP: REAL; + begin + -- Check if already a principal value + if ( X > -MATH_PI and X <= MATH_PI ) then + return PRINCIPAL_VALUE'(X); + end if; + + -- Get principal value + TEMP := X; + while ( TEMP <= -MATH_PI ) loop + TEMP := TEMP + MATH_2_PI; + end loop; + while (TEMP > MATH_PI ) loop + TEMP := TEMP - MATH_2_PI; + end loop; + + return PRINCIPAL_VALUE'(TEMP); + end function GET_PRINCIPAL_VALUE; + + function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + variable TEMP: REAL; + begin + -- Get value for special cases + if ( Z.RE = 0.0 ) then + if ( Z.IM = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + elsif ( Z.IM > 0.0 ) then + return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2); + else + return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2); + end if; + end if; + + if ( Z.IM = 0.0 ) then + if ( Z.RE = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + elsif ( Z.RE > 0.0 ) then + return COMPLEX_POLAR'(Z.RE, 0.0); + else + return COMPLEX_POLAR'(-Z.RE, MATH_PI); + end if; + end if; + + -- Get principal value for general case + TEMP := ARCTAN(Z.IM, Z.RE); + + return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM), + GET_PRINCIPAL_VALUE(TEMP)); + end function COMPLEX_TO_POLAR; + + function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns MATH_CZERO on error + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)" + severity ERROR; + return MATH_CZERO; + end if; + + -- Get value for general case + return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) ); + end function POLAR_TO_COMPLEX; + + + function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) + + begin + -- Get value for general case + return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM)); + end function "ABS"; + + function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ABS(Z) = Z.MAG + -- b) Returns 0.0 on error + + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in ABS(Z)" + severity ERROR; + return 0.0; + end if; + + -- Get value for general case + return Z.MAG; + end function "ABS"; + + + function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARG(Z) = ARCTAN(Z.IM, Z.RE) + + variable ZTEMP : COMPLEX_POLAR; + begin + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + return ZTEMP.ARG; + end function ARG; + + function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARG(Z) = Z.ARG + -- b) Returns 0.0 on error + + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in ARG(Z)" + severity ERROR; + return 0.0; + end if; + + -- Get value for general case + return Z.ARG; + end function ARG; + + function "-" (Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns -x -jy for Z = x + jy + begin + -- Get value for general case + return COMPLEX'(-Z.RE, -Z.IM); + end function "-"; + + function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (Z.MAG, Z.ARG + MATH_PI) + -- b) Returns Z on error + variable TEMP: REAL; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in -(Z)" + severity ERROR; + return Z; + end if; + + -- Get principal value for general case + TEMP := REAL'(Z.ARG) + MATH_PI; + + return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP)); + end function "-"; + + function CONJ (Z: in COMPLEX) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns x - jy for Z = x + jy + begin + -- Get value for general case + return COMPLEX'(Z.RE, -Z.IM); + end function CONJ; + + function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG) + -- b) Returns Z on error + -- + variable TEMP: PRINCIPAL_VALUE; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in CONJ(Z)" + severity ERROR; + return Z; + end if; + + -- Get principal value for general case + if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then + TEMP := Z.ARG; + else + TEMP := -Z.ARG; + end if; + + return COMPLEX_POLAR'(Z.MAG, TEMP); + end function CONJ; + + function SQRT(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + variable ZTEMP : COMPLEX_POLAR; + variable ZOUT : COMPLEX; + variable TMAG : REAL; + variable TARG : REAL; + begin + -- Get value for special cases + if ( Z = MATH_CZERO ) then + return MATH_CZERO; + end if; + + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + TMAG := SQRT(ZTEMP.MAG); + TARG := 0.5*ZTEMP.ARG; + + if ( COS(TARG) > 0.0 ) then + ZOUT.RE := TMAG*COS(TARG); + ZOUT.IM := TMAG*SIN(TARG); + return ZOUT; + end if; + + if ( COS(TARG) < 0.0 ) then + ZOUT.RE := TMAG*COS(TARG + MATH_PI); + ZOUT.IM := TMAG*SIN(TARG + MATH_PI); + return ZOUT; + end if; + + if ( SIN(TARG) > 0.0 ) then + ZOUT.RE := 0.0; + ZOUT.IM := TMAG*SIN(TARG); + return ZOUT; + end if; + + ZOUT.RE := 0.0; + ZOUT.IM := TMAG*SIN(TARG + MATH_PI); + return ZOUT; + end function SQRT; + + function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns Z on error + + variable ZOUT : COMPLEX_POLAR; + variable TMAG : REAL; + variable TARG : REAL; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in SQRT(Z)" + severity ERROR; + return Z; + end if; + + -- Get value for special cases + if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then + return Z; + end if; + + -- Get principal value for general case + TMAG := SQRT(Z.MAG); + TARG := 0.5*Z.ARG; + + ZOUT.MAG := POSITIVE_REAL'(TMAG); + + if ( COS(TARG) < 0.0 ) then + TARG := TARG + MATH_PI; + end if; + + if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then + TARG := TARG + MATH_PI; + end if; + + ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG); + return ZOUT; + end function SQRT; + + function EXP(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + + variable TEMP: REAL; + begin + -- Get value for special cases + if ( Z = MATH_CZERO ) then + return MATH_CBASE_1; + end if; + + if ( Z.RE = 0.0 ) then + if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then + return COMPLEX'(-1.0, 0.0); + end if; + + if ( Z.IM = MATH_PI_OVER_2 ) then + return MATH_CBASE_J; + end if; + + if ( Z.IM = -MATH_PI_OVER_2 ) then + return COMPLEX'(0.0, -1.0); + end if; + end if; + + -- Get value for general case + TEMP := EXP(Z.RE); + return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM)); + end function EXP; + + function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns Z on error + + variable ZTEMP : COMPLEX; + variable temp: REAL; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in EXP(Z)" + severity ERROR; + return Z; + end if; + + -- Get value for special cases + if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or + Z.ARG = -MATH_PI_OVER_2 )) then + return COMPLEX_POLAR'(1.0, MATH_PI); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 ) then + if ( Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2); + end if; + + if ( Z.ARG = -MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2); + end if; + end if; + + -- Get principal value for general case + ZTEMP := POLAR_TO_COMPLEX(Z); + ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE)); + ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM); + + return ZOUT; + end function EXP; + + function LOG(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'LOW, 0.0) on error + + variable ZTEMP : COMPLEX_POLAR; + variable TEMP : REAL; + begin + -- Check validity of input arguments + if ( Z.RE = 0.0 and Z.IM = 0.0 ) then + assert FALSE + report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)" + severity ERROR; + return COMPLEX'(REAL'LOW, 0.0); + end if; + + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = -1.0 ) then + return COMPLEX'(0.0, MATH_PI); + end if; + if ( Z.RE = MATH_E ) then + return MATH_CBASE_1; + end if; + if ( Z.RE = 1.0 ) then + return MATH_CZERO; + end if; + end if; + + if ( Z.RE = 0.0 ) then + if (Z.IM = 1.0) then + return COMPLEX'(0.0, MATH_PI_OVER_2); + end if; + if (Z.IM = -1.0) then + return COMPLEX'(0.0, -MATH_PI_OVER_2); + end if; + end if; + + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + TEMP := LOG(ZTEMP.MAG); + return COMPLEX'(TEMP, ZTEMP.ARG); + end function LOG; + + function LOG2(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'LOW, 0.0) on error + + variable ZTEMP : COMPLEX_POLAR; + variable TEMP : REAL; + begin + + -- Check validity of input arguments + if ( Z.RE = 0.0 and Z.IM = 0.0 ) then + assert FALSE + report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)" + severity ERROR; + return COMPLEX'(REAL'LOW, 0.0); + end if; + + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = 2.0 ) then + return MATH_CBASE_1; + end if; + if ( Z.RE = 1.0 ) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG); + return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG); + end function LOG2; + + function LOG10(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'LOW, 0.0) on error + + variable ZTEMP : COMPLEX_POLAR; + variable TEMP : REAL; + begin + -- Check validity of input arguments + if ( Z.RE = 0.0 and Z.IM = 0.0 ) then + assert FALSE + report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)" + severity ERROR; + return COMPLEX'(REAL'LOW, 0.0); + end if; + + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = 10.0 ) then + return MATH_CBASE_1; + end if; + if ( Z.RE = 1.0 ) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG); + return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG); + end function LOG10; + + + function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error + + variable ZTEMP : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.MAG <= 0.0 ) then + assert FALSE + report "Z.MAG <= 0.0 in LOG(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in LOG(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + -- Compute value for special cases + if (Z.MAG = 1.0 ) then + if ( Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.ARG = MATH_PI ) then + return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2); + end if; + + if ( Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2); + end if; + + if ( Z.ARG = -MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2); + end if; + end if; + + if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + -- Compute value for general case + ZTEMP.RE := LOG(Z.MAG); + ZTEMP.IM := Z.ARG; + ZOUT := COMPLEX_TO_POLAR(ZTEMP); + return ZOUT; + end function LOG; + + + + function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error + + variable ZTEMP : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.MAG <= 0.0 ) then + assert FALSE + report "Z.MAG <= 0.0 in LOG2(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in LOG2(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + -- Compute value for special cases + if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + -- Compute value for general case + ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG); + ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG; + ZOUT := COMPLEX_TO_POLAR(ZTEMP); + return ZOUT; + end function LOG2; + + function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error + variable ZTEMP : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.MAG <= 0.0 ) then + assert FALSE + report "Z.MAG <= 0.0 in LOG10(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in LOG10(Z)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + -- Compute value for special cases + if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + -- Compute value for general case + ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG); + ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG; + ZOUT := COMPLEX_TO_POLAR(ZTEMP); + return ZOUT; + end function LOG10; + + function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'LOW, 0.0) on error + + variable ZTEMP : COMPLEX_POLAR; + variable TEMPRE : REAL; + variable TEMPIM : REAL; + begin + -- Check validity of input arguments + if ( Z.RE = 0.0 and Z.IM = 0.0 ) then + assert FALSE + report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)" + severity ERROR; + return COMPLEX'(REAL'LOW, 0.0); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)" + severity ERROR; + return COMPLEX'(REAL'LOW, 0.0); + end if; + + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = BASE ) then + return MATH_CBASE_1; + end if; + if ( Z.RE = 1.0 ) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + ZTEMP := COMPLEX_TO_POLAR(Z); + TEMPRE := LOG(ZTEMP.MAG, BASE); + TEMPIM := ZTEMP.ARG/LOG(BASE); + return COMPLEX'(TEMPRE, TEMPIM); + end function LOG; + + function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error + + variable ZTEMP : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.MAG <= 0.0 ) then + assert FALSE + report "Z.MAG <= 0.0 in LOG(Z,BASE)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in LOG(Z,BASE)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, MATH_PI); + end if; + + -- Compute value for special cases + if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = BASE and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + -- Compute value for general case + ZTEMP.RE := LOG(Z.MAG, BASE); + ZTEMP.IM := Z.ARG/LOG(BASE); + ZOUT := COMPLEX_TO_POLAR(ZTEMP); + return ZOUT; + end function LOG; + + + function SIN(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = 0.0 or Z.RE = MATH_PI) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM)); + end function SIN; + + function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(0.0, 0.0) on error + + variable Z1, Z2 : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in SIN(Z)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for special cases + if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for general case + Z1 := POLAR_TO_COMPLEX(Z); + Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM)); + ZOUT := COMPLEX_TO_POLAR(Z2); + return ZOUT; + end function SIN; + + function COS(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + + + -- Get value for special cases + if ( Z.IM = 0.0 ) then + if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM)); + end function COS; + + function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(0.0, 0.0) on error + + variable Z1, Z2 : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in COS(Z)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for special cases + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for general case + Z1 := POLAR_TO_COMPLEX(Z); + Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM)); + ZOUT := COMPLEX_TO_POLAR(Z2); + return ZOUT; + end function COS; + + function SINH(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + -- Get value for special cases + if ( Z.RE = 0.0 ) then + if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then + return MATH_CZERO; + end if; + + + + if ( Z.IM = MATH_PI_OVER_2 ) then + return MATH_CBASE_J; + end if; + + if ( Z.IM = -MATH_PI_OVER_2 ) then + return -MATH_CBASE_J; + end if; + end if; + + -- Get value for general case + return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM)); + end function SINH; + + function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(0.0, 0.0) on error + + variable Z1, Z2 : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in SINH(Z)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for special cases + if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2); + end if; + + -- Compute value for general case + Z1 := POLAR_TO_COMPLEX(Z); + Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM)); + ZOUT := COMPLEX_TO_POLAR(Z2); + return ZOUT; + end function SINH; + + + function COSH(Z: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + -- Get value for special cases + if ( Z.RE = 0.0 ) then + if ( Z.IM = 0.0 ) then + return MATH_CBASE_1; + end if; + + if ( Z.IM = MATH_PI ) then + return -MATH_CBASE_1; + end if; + + if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then + return MATH_CZERO; + end if; + end if; + + -- Get value for general case + return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM)); + end function COSH; + + function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR(0.0, 0.0) on error + + variable Z1, Z2 : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( Z.ARG = -MATH_PI ) then + assert FALSE + report "Z.ARG = -MATH_PI in COSH(Z)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for special cases + if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then + return COMPLEX_POLAR'(1.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(1.0, MATH_PI); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Compute value for general case + Z1 := POLAR_TO_COMPLEX(Z); + Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM)); + ZOUT := COMPLEX_TO_POLAR(Z2); + return ZOUT; + end function COSH; + + + -- + -- Arithmetic Operators + -- + function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE + R.RE, L.IM + R.IM); + end function "+"; + + function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L + R.RE, R.IM); + end function "+"; + + function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE + R, L.IM); + end function "+"; + + function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR) + return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZL, ZR : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in +(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in +(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZL := POLAR_TO_COMPLEX( L ); + ZR := POLAR_TO_COMPLEX( R ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM)); + return ZOUT; + end function "+"; + + function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + variable ZR : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in +(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZR := POLAR_TO_COMPLEX( R ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM)); + return ZOUT; + end function "+"; + + function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZL : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in +(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZL := POLAR_TO_COMPLEX( L ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM)); + return ZOUT; + end function "+"; + + function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE - R.RE, L.IM - R.IM); + end function "-"; + + function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L - R.RE, -1.0 * R.IM); + end function "-"; + + function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE - R, L.IM); + end function "-"; + + function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR) + return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZL, ZR : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in -(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in -(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + -- Get principal value + ZL := POLAR_TO_COMPLEX( L ); + ZR := POLAR_TO_COMPLEX( R ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM)); + return ZOUT; + end function "-"; + + function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZR : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in -(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZR := POLAR_TO_COMPLEX( R ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM)); + return ZOUT; + end function "-"; + + function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZL : COMPLEX; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in -(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZL := POLAR_TO_COMPLEX( L ); + ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM)); + return ZOUT; + end function "-"; + + + function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE); + end function "*"; + + + function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L * R.RE, L * R.IM); + end function "*"; + + function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + return COMPLEX'(L.RE * R, L.IM * R); + end function "*"; + + function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR) + return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in *(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in *(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZOUT.MAG := L.MAG * R.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG); + + return ZOUT; + end function "*"; + + function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZL : COMPLEX_POLAR; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in *(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZL.MAG := POSITIVE_REAL'(ABS(L)); + if ( L < 0.0 ) then + ZL.ARG := MATH_PI; + else + ZL.ARG := 0.0; + end if; + + ZOUT.MAG := ZL.MAG * R.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG); + + return ZOUT; + end function "*"; + + function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error + -- + variable ZR : COMPLEX_POLAR; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in *(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZR.MAG := POSITIVE_REAL'(ABS(R)); + if ( R < 0.0 ) then + ZR.ARG := MATH_PI; + else + ZR.ARG := 0.0; + end if; + + ZOUT.MAG := L.MAG * ZR.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG); + + return ZOUT; + end function "*"; + + function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error + -- + variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM; + begin + -- Check validity of input arguments + if (TEMP = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX by (0.0, 0.0)" + severity ERROR; + return COMPLEX'(REAL'HIGH, 0.0); + end if; + + -- Get value + return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP, + (L.IM * R.RE - L.RE * R.IM) / TEMP); + end function "/"; + + function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error + -- + variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM; + begin + -- Check validity of input arguments + if (TEMP = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX by (0.0, 0.0)" + severity ERROR; + return COMPLEX'(REAL'HIGH, 0.0); + end if; + + -- Get value + TEMP := L / TEMP; + return COMPLEX'( TEMP * R.RE, -TEMP * R.IM ); + end function "/"; + + function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error + begin + -- Check validity of input arguments + if (R = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX by 0.0" + severity ERROR; + return COMPLEX'(REAL'HIGH, 0.0); + end if; + + -- Get value + return COMPLEX'(L.RE / R, L.IM / R); + end function "/"; + + + function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR) + return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error + -- + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if (R.MAG = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, 0.0); + end if; + + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in /(L,R)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, 0.0); + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_PI in /(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZOUT.MAG := L.MAG/R.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG); + + return ZOUT; + end function "/"; + + function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error + -- + variable ZR : COMPLEX_POLAR; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if (R = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX_POLAR by 0.0" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, 0.0); + end if; + + if ( L.ARG = -MATH_PI ) then + assert FALSE + report "L.ARG = -MATH_PI in /(L,R)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, 0.0); + end if; + + -- Get principal value + ZR.MAG := POSITIVE_REAL'(ABS(R)); + if R < 0.0 then + ZR.ARG := MATH_PI; + else + ZR.ARG := 0.0; + end if; + + ZOUT.MAG := L.MAG/ZR.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG); + + return ZOUT; + end function "/"; + + function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error + -- + variable ZL : COMPLEX_POLAR; + variable ZOUT : COMPLEX_POLAR; + begin + -- Check validity of input arguments + if (R.MAG = 0.0) then + assert FALSE + report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)" + severity ERROR; + return COMPLEX_POLAR'(REAL'HIGH, 0.0); + end if; + + if ( R.ARG = -MATH_PI ) then + assert FALSE + report "R.ARG = -MATH_P in /(L,R)" + severity ERROR; + return COMPLEX_POLAR'(0.0, 0.0); + end if; + + -- Get principal value + ZL.MAG := POSITIVE_REAL'(ABS(L)); + if L < 0.0 then + ZL.ARG := MATH_PI; + else + ZL.ARG := 0.0; + end if; + + ZOUT.MAG := ZL.MAG/R.MAG; + ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG); + + return ZOUT; + end function "/"; + +end package body MATH_COMPLEX; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex.vhdl new file mode 100644 index 0000000..26e6ddd --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_complex.vhdl @@ -0,0 +1,1144 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Mathematical Packages +-- : (MATH_COMPLEX package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- : +-- Purpose : This package defines a standard for designers to use in +-- : describing VHDL models that make use of common COMPLEX +-- : constants and common COMPLEX mathematical functions and +-- : operators. +-- : +-- Limitation: The values generated by the functions in this package +-- : may vary from platform to platform, and the precision +-- : of results is only guaranteed to be the minimum required +-- : by IEEE Std 1076-2008. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +use WORK.MATH_REAL.all; +package MATH_COMPLEX is + constant CopyRightNotice : STRING + := "Copyright 2008 IEEE. All rights reserved."; + + -- + -- Type Definitions + -- + type COMPLEX is + record + RE : REAL; -- Real part + IM : REAL; -- Imaginary part + end record; + + subtype POSITIVE_REAL is REAL range 0.0 to REAL'high; + + subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI; + + type COMPLEX_POLAR is + record + MAG : POSITIVE_REAL; -- Magnitude + ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal + end record; + + -- + -- Constant Definitions + -- + constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0); + constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0); + constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0); + + + -- + -- Overloaded equality and inequality operators for COMPLEX_POLAR + -- (equality and inequality operators for COMPLEX are predefined) + -- + + function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; + -- Purpose: + -- Returns TRUE if L is equal to R and returns FALSE otherwise + -- Special values: + -- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE + -- regardless of the value of X and Y. + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- "="(L,R) is either TRUE or FALSE + -- Notes: + -- None + + function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; + -- Purpose: + -- Returns TRUE if L is not equal to R and returns FALSE + -- otherwise + -- Special values: + -- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns + -- FALSE regardless of the value of X and Y. + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- "/="(L,R) is either TRUE or FALSE + -- Notes: + -- None + + -- + -- Function Declarations + -- + function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX; + -- Purpose: + -- Returns COMPLEX number X + iY + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- CMPLX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE; + -- Purpose: + -- Returns principal value of angle X; X in radians + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI + -- Notes: + -- None + + function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value COMPLEX_POLAR of Z + -- Special values: + -- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0) + -- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM), + -- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0 + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX; + -- Purpose: + -- Returns COMPLEX value of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- POLAR_TO_COMPLEX(Z) is mathematically unbounded + -- Notes: + -- None + + function "ABS"(Z : in COMPLEX) return POSITIVE_REAL; + -- Purpose: + -- Returns absolute value (magnitude) of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- ABS(Z) is mathematically unbounded + -- Notes: + -- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) + + function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL; + -- Purpose: + -- Returns absolute value (magnitude) of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- ABS(Z) >= 0.0 + -- Notes: + -- ABS(Z) = Z.MAG + + function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE; + -- Purpose: + -- Returns argument (angle) in radians of the principal + -- value of Z + -- Special values: + -- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0 + -- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0 + -- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0 + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- -MATH_PI < ARG(Z) <= MATH_PI + -- Notes: + -- ARG(Z) = ARCTAN(Z.IM, Z.RE) + + function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE; + -- Purpose: + -- Returns argument (angle) in radians of the principal + -- value of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- -MATH_PI < ARG(Z) <= MATH_PI + -- Notes: + -- ARG(Z) = Z.ARG + + + function "-" (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns unary minus of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "-"(Z) is mathematically unbounded + -- Notes: + -- Returns -x -jy for Z= x + jy + + function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of unary minus of Z + -- Special values: + -- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if + -- Z.ARG /= 0.0 + + function CONJ (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns complex conjugate of Z + -- Special values: + -- None + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- CONJ(Z) is mathematically unbounded + -- Notes: + -- Returns x -jy for Z= x + jy + + function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of complex conjugate of Z + -- Special values: + -- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI + + function SQRT(Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns square root of Z with positive real part + -- or, if the real part is zero, the one with nonnegative + -- imaginary part + -- Special values: + -- SQRT(MATH_CZERO) = MATH_CZERO + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- SQRT(Z) is mathematically unbounded + -- Notes: + -- None + + function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns square root of Z with positive real part + -- or, if the real part is zero, the one with nonnegative + -- imaginary part + -- Special values: + -- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function EXP(Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns exponential of Z + -- Special values: + -- EXP(MATH_CZERO) = MATH_CBASE_1 + -- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI + -- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and + -- ABS(Z.IM) = MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- EXP(Z) is mathematically unbounded + -- Notes: + -- None + + + + function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of exponential of Z + -- Special values: + -- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and + -- Z.ARG = 0.0 + -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and + -- ABS(Z.ARG) = MATH_PI_OVER_2 + -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if + -- Z.MAG = MATH_PI_OVER_2 and + -- Z.ARG = MATH_PI_OVER_2 + -- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if + -- Z.MAG = MATH_PI_OVER_2 and + -- Z.ARG = -MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function LOG(Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns natural logarithm of Z + -- Special values: + -- LOG(MATH_CBASE_1) = MATH_CZERO + -- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI) + -- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2) + -- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2) + -- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0) + -- Domain: + -- Z in COMPLEX and ABS(Z) /= 0.0 + -- Error conditions: + -- Error if ABS(Z) = 0.0 + -- Range: + -- LOG(Z) is mathematically unbounded + -- Notes: + -- None + + function LOG2(Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns logarithm base 2 of Z + -- Special values: + -- LOG2(MATH_CBASE_1) = MATH_CZERO + -- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0) + -- Domain: + -- Z in COMPLEX and ABS(Z) /= 0.0 + -- Error conditions: + -- Error if ABS(Z) = 0.0 + -- Range: + -- LOG2(Z) is mathematically unbounded + -- Notes: + -- None + + function LOG10(Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns logarithm base 10 of Z + -- Special values: + -- LOG10(MATH_CBASE_1) = MATH_CZERO + -- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0) + -- Domain: + -- Z in COMPLEX and ABS(Z) /= 0.0 + -- Error conditions: + -- Error if ABS(Z) = 0.0 + -- Range: + -- LOG10(Z) is mathematically unbounded + -- Notes: + -- None + + function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of natural logarithm of Z + -- Special values: + -- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and + -- Z.ARG = 0.0 + -- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if + -- Z.MAG = 1.0 and Z.ARG = MATH_PI + -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if + -- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2 + -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if + -- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2 + -- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and + -- Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Z.MAG /= 0.0 + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Error if Z.MAG = 0.0 + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of logarithm base 2 of Z + -- Special values: + -- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and + -- Z.ARG = 0.0 + -- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and + -- Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Z.MAG /= 0.0 + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Error if Z.MAG = 0.0 + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of logarithm base 10 of Z + -- Special values: + -- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and + -- Z.ARG = 0.0 + -- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and + -- Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Z.MAG /= 0.0 + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Error if Z.MAG = 0.0 + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX; + -- Purpose: + -- Returns logarithm base BASE of Z + -- Special values: + -- LOG(MATH_CBASE_1, BASE) = MATH_CZERO + -- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0) + -- Domain: + -- Z in COMPLEX and ABS(Z) /= 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if ABS(Z) = 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(Z,BASE) is mathematically unbounded + -- Notes: + -- None + + function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of logarithm base BASE of Z + -- Special values: + -- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and + -- Z.ARG = 0.0 + -- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and + -- Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Z.MAG /= 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Error if Z.MAG = 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function SIN (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns sine of Z + -- Special values: + -- SIN(MATH_CZERO) = MATH_CZERO + -- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0) + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) + + -- SINH(Z.IM)*SINH(Z.IM)) + -- Notes: + -- None + + function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of sine of Z + -- Special values: + -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and + -- Z.ARG = 0.0 + -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and + -- Z.ARG = 0.0 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function COS (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns cosine of Z + -- Special values: + -- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0) + -- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0) + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) + + -- SINH(Z.IM)*SINH(Z.IM)) + -- Notes: + -- None + + + function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of cosine of Z + -- Special values: + -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 + -- and Z.ARG = 0.0 + -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 + -- and Z.ARG = MATH_PI + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function SINH (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns hyperbolic sine of Z + -- Special values: + -- SINH(MATH_CZERO) = MATH_CZERO + -- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI + -- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and + -- Z.IM = MATH_PI_OVER_2 + -- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and + -- Z.IM = -MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + + -- SIN(Z.IM)*SIN(Z.IM)) + -- Notes: + -- None + + function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of hyperbolic sine of Z + -- Special values: + -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and + -- Z.ARG = 0.0 + -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and + -- Z.ARG = MATH_PI_OVER_2 + -- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG = + -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 + -- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG = + -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function COSH (Z : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns hyperbolic cosine of Z + -- Special values: + -- COSH(MATH_CZERO) = MATH_CBASE_1 + -- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI + -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2 + -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX + -- Error conditions: + -- None + -- Range: + -- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + + -- COS(Z.IM)*COS(Z.IM)) + -- Notes: + -- None + + + function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns principal value of hyperbolic cosine of Z + -- Special values: + -- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and + -- Z.ARG = 0.0 + -- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and + -- Z.ARG = MATH_PI_OVER_2 + -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = + -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 + -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = + -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 + -- Domain: + -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI + -- Error conditions: + -- Error if Z.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + -- + -- Arithmetic Operators + -- + + function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "+"(Z) is mathematically unbounded + -- Notes: + -- None + + function "+" (L : in REAL; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "+"(Z) is mathematically unbounded + -- Notes: + -- None + + function "+" (L : in COMPLEX; R : in REAL) return COMPLEX; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in REAL + -- Error conditions: + -- None + -- Range: + -- "+"(Z) is mathematically unbounded + -- Notes: + -- None + + function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) + return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + + function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic addition of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in REAL + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "-"(Z) is mathematically unbounded + -- Notes: + -- None + + function "-" (L : in REAL; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "-"(Z) is mathematically unbounded + -- Notes: + -- None + + function "-" (L : in COMPLEX; R : in REAL) return COMPLEX; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in REAL + -- Error conditions: + -- None + -- Range: + -- "-"(Z) is mathematically unbounded + -- Notes: + -- None + + function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) + return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + + function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic subtraction of L minus R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in REAL + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "*"(Z) is mathematically unbounded + -- Notes: + -- None + + function "*" (L : in REAL; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX + -- Error conditions: + -- None + -- Range: + -- "*"(Z) is mathematically unbounded + -- Notes: + -- None + + function "*" (L : in COMPLEX; R : in REAL) return COMPLEX; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in REAL + -- Error conditions: + -- None + + -- Range: + -- "*"(Z) is mathematically unbounded + -- Notes: + -- None + + function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) + return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- Error conditions: + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic multiplication of L and R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in REAL + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + + function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in COMPLEX and R /= MATH_CZERO + -- Error conditions: + -- Error if R = MATH_CZERO + -- Range: + -- "/"(Z) is mathematically unbounded + -- Notes: + -- None + + function "/" (L : in REAL; R : in COMPLEX) return COMPLEX; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX and R /= MATH_CZERO + -- Error conditions: + -- Error if R = MATH_CZERO + -- Range: + -- "/"(Z) is mathematically unbounded + -- Notes: + -- None + + function "/" (L : in COMPLEX; R : in REAL) return COMPLEX; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX + -- R in REAL and R /= 0.0 + -- Error conditions: + -- Error if R = 0.0 + -- Range: + -- "/"(Z) is mathematically unbounded + -- Notes: + -- None + + function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) + return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- R.MAG > 0.0 + -- Error conditions: + -- Error if R.MAG <= 0.0 + -- Error if L.ARG = -MATH_PI + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in REAL + -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI + -- R.MAG > 0.0 + -- Error conditions: + -- Error if R.MAG <= 0.0 + -- Error if R.ARG = -MATH_PI + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; + -- Purpose: + -- Returns arithmetic division of L by R + -- Special values: + -- None + -- Domain: + -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI + -- R /= 0.0 + -- Error conditions: + -- Error if L.ARG = -MATH_PI + -- Error if R = 0.0 + -- Range: + -- result.MAG >= 0.0 + -- -MATH_PI < result.ARG <= MATH_PI + -- Notes: + -- None + + attribute foreign of MATH_COMPLEX: package is "NO C code generation"; + + attribute foreign of "="[complex_polar, complex_polar return boolean]:function is "ieee_math_complex_equal_polar"; + attribute foreign of "/="[complex_polar, complex_polar return boolean]:function is "ieee_math_complex_not_equal_polar"; + attribute foreign of cmplx[real, real return complex]:function is "ieee_math_complex_cmplx"; + attribute foreign of get_principal_value[real return principal_value]:function is "ieee_math_complex_get_principal_value"; + attribute foreign of complex_to_polar[complex return complex_polar]:function is "ieee_math_complex_complex_to_polar"; + attribute foreign of polar_to_complex[complex_polar return complex]:function is "ieee_math_complex_polar_to_complex"; + attribute foreign of "ABS"[complex return positive_real]:function is "ieee_math_complex_abs"; + attribute foreign of "ABS"[complex_polar return positive_real]:function is "ieee_math_complex_abs_polar"; + attribute foreign of arg[complex return principal_value]:function is "ieee_math_complex_arg"; + attribute foreign of arg[complex_polar return principal_value]:function is "ieee_math_complex_arg_polar"; + attribute foreign of "-"[complex return complex]:function is "ieee_math_complex_negation"; + attribute foreign of "-"[complex_polar return complex_polar]:function is "ieee_math_complex_negation_polar"; + attribute foreign of conj[complex return complex]:function is "ieee_math_complex_conj"; + attribute foreign of conj[complex_polar return complex_polar]:function is "ieee_math_complex_conj_polar"; + attribute foreign of sqrt[complex return complex]:function is "ieee_math_complex_sqrt"; + attribute foreign of sqrt[complex_polar return complex_polar]:function is "ieee_math_complex_sqrt_polar"; + attribute foreign of exp[complex return complex]:function is "ieee_math_complex_exp"; + attribute foreign of exp[complex_polar return complex_polar]:function is "ieee_math_complex_exp_polar"; + attribute foreign of log[complex return complex]:function is "ieee_math_complex_log"; + attribute foreign of log2[complex return complex]:function is "ieee_math_complex_log2"; + attribute foreign of log[complex_polar return complex_polar]:function is "ieee_math_complex_log_polar"; + attribute foreign of log2[complex_polar return complex_polar]:function is "ieee_math_complex_log2_polar"; + attribute foreign of log10[complex_polar return complex_polar]:function is "ieee_math_complex_log10_polar"; + attribute foreign of log[complex, real return complex]:function is "ieee_math_complex_log_base"; + attribute foreign of log[complex_polar, real return complex_polar]:function is "ieee_math_complex_log_base_polar"; + attribute foreign of sin[complex return complex]:function is "ieee_math_complex_sin"; + attribute foreign of sin[complex_polar return complex_polar]:function is "ieee_math_complex_sin_polar"; + attribute foreign of cos[complex return complex]:function is "ieee_math_complex_cos"; + attribute foreign of cos[complex_polar return complex_polar]:function is "ieee_math_complex_cos_polar"; + attribute foreign of sinh[complex return complex]:function is "ieee_math_complex_sinh"; + attribute foreign of sinh[complex_polar return complex_polar]:function is "ieee_math_complex_sinh_polar"; + attribute foreign of cosh[complex return complex]:function is "ieee_math_complex_cosh"; + attribute foreign of cosh[complex_polar return complex_polar]:function is "ieee_math_complex_cosh_polar"; + attribute foreign of "+"[complex, complex return complex]:function is "ieee_math_complex_add_cc"; + attribute foreign of "+"[real, complex return complex]:function is "ieee_math_complex_add_rc"; + attribute foreign of "+"[complex, real return complex]:function is "ieee_math_complex_add_cr"; + attribute foreign of "+"[complex_polar, complex_polar return complex_polar]:function is "ieee_math_complex_add_polar_cc"; + attribute foreign of "+"[real, complex_polar return complex_polar]:function is "ieee_math_complex_add_polar_rc"; + attribute foreign of "+"[complex_polar, real return complex_polar]:function is "ieee_math_complex_add_polar_cr"; + attribute foreign of "-"[complex, complex return complex]:function is "ieee_math_complex_subtract_cc"; + attribute foreign of "-"[real, complex return complex]:function is "ieee_math_complex_subtract_rc"; + attribute foreign of "-"[complex, real return complex]:function is "ieee_math_complex_subtract_cr"; + attribute foreign of "-"[complex_polar, complex_polar return complex_polar]:function is "ieee_math_complex_subtract_polar_cc"; + attribute foreign of "-"[real, complex_polar return complex_polar]:function is "ieee_math_complex_subtract_polar_rc"; + attribute foreign of "-"[complex_polar, real return complex_polar]:function is "ieee_math_complex_subtract_polar_cr"; + attribute foreign of "*"[complex, complex return complex]:function is "ieee_math_complex_multiply_cc"; + attribute foreign of "*"[real, complex return complex]:function is "ieee_math_complex_multiply_rc"; + attribute foreign of "*"[complex, real return complex]:function is "ieee_math_complex_multiply_cr"; + attribute foreign of "*"[complex_polar, complex_polar return complex_polar]:function is "ieee_math_complex_multiply_polar_cc"; + attribute foreign of "*"[real, complex_polar return complex_polar]:function is "ieee_math_complex_multiply_polar_rc"; + attribute foreign of "*"[complex_polar, real return complex_polar]:function is "ieee_math_complex_multiply_polar_cr"; + attribute foreign of "/"[complex, complex return complex]:function is "ieee_math_complex_divide_cc"; + attribute foreign of "/"[real, complex return complex]:function is "ieee_math_complex_divide_rc"; + attribute foreign of "/"[complex, real return complex]:function is "ieee_math_complex_divide_cr"; + attribute foreign of "/"[complex_polar, complex_polar return complex_polar]:function is "ieee_math_complex_divide_polar_cc"; + attribute foreign of "/"[real, complex_polar return complex_polar]:function is "ieee_math_complex_divide_polar_rc"; + attribute foreign of "/"[complex_polar, real return complex_polar]:function is "ieee_math_complex_divide_polar_cr"; + +end package MATH_COMPLEX; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real-body.vhdl new file mode 100644 index 0000000..ff2abd4 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real-body.vhdl @@ -0,0 +1,1934 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Mathematical Packages +-- : (MATH_REAL package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- : +-- Purpose : This package defines a standard for designers to use in +-- : describing VHDL models that make use of common REAL +-- : constants and common REAL elementary mathematical +-- : functions. +-- : +-- Limitation: The values generated by the functions in this package +-- : may vary from platform to platform, and the precision +-- : of results is only guaranteed to be the minimum required +-- : by IEEE Std 1076-2008. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end function POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end function CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end function SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end function CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end function FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end function ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end function TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end function "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end function REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end function REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end procedure UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end function SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end function CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end function "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end function "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end function EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end function ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end function LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end function LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end function LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end function LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end function LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + -- adjust for rounding error + XLOCAL := 0.0; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end function SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + -- adjust for rounding error + XLOCAL := 0.0; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end function COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + -- adjust for rounding error + XLOCAL := 0.0; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end function TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end function ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end function ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end function ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end function ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end function SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end function COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end function TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end function ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end function ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end function ARCTANH; + +end package body MATH_REAL; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real.vhdl new file mode 100644 index 0000000..b9ea185 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real.vhdl @@ -0,0 +1,658 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Mathematical Packages +-- : (MATH_REAL package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- : +-- Purpose : This package defines a standard for designers to use in +-- : describing VHDL models that make use of common REAL +-- : constants and common REAL elementary mathematical +-- : functions. +-- : +-- Limitation: The values generated by the functions in this package +-- : may vary from platform to platform, and the precision +-- : of results is only guaranteed to be the minimum required +-- : by IEEE Std 1076-2008. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice : STRING + := "Copyright 2008 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X : in REAL) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y : in REAL) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X : in REAL; BASE : in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS (X : in REAL) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + attribute foreign of MATH_REAL: package is "NO C code generation"; + + attribute foreign of sign[real return real]:function is "ieee_math_real_sign"; + attribute foreign of ceil[real return real]:function is "ieee_math_real_ceil"; + attribute foreign of floor[real return real]:function is "ieee_math_real_floor"; + attribute foreign of trunc[real return real]:function is "ieee_math_real_trunc"; + attribute foreign of round[real return real]:function is "ieee_math_real_round"; + attribute foreign of "MOD"[real, real return real]:function is "ieee_math_real_mod"; + attribute foreign of realmax[real, real return real]:function is "ieee_math_real_realmax"; + attribute foreign of realmin[real, real return real]:function is "ieee_math_real_realmin"; + attribute foreign of uniform[positive, positive,real]:procedure is "ieee_math_real_uniform"; + attribute foreign of sqrt[real return real]:function is "ieee_math_real_sqrt"; + attribute foreign of cbrt[real return real]:function is "ieee_math_real_cbrt"; + attribute foreign of "**"[integer, real return real]:function is "ieee_math_real_pow_int"; + attribute foreign of "**"[real, real return real]:function is "ieee_math_real_pow_real"; + attribute foreign of exp[real return real]:function is "ieee_math_real_exp"; + attribute foreign of log[real return real]:function is "ieee_math_real_log"; + attribute foreign of log2[real return real]:function is "ieee_math_real_log2"; + attribute foreign of log10[real return real]:function is "ieee_math_real_log10"; + attribute foreign of log[real, real return real]:function is "ieee_math_real_log_base"; + attribute foreign of sin[real return real]:function is "ieee_math_real_sin"; + attribute foreign of cos[real return real]:function is "ieee_math_real_cos"; + attribute foreign of tan[real return real]:function is "ieee_math_real_tan"; + attribute foreign of arcsin[real return real]:function is "ieee_math_real_arcsin"; + attribute foreign of arccos[real return real]:function is "ieee_math_real_arccos"; + attribute foreign of arctan[real return real]:function is "ieee_math_real_arctan"; + attribute foreign of arctan[real,real return real]:function is "ieee_math_real_arctan2"; + attribute foreign of sinh[real return real]:function is "ieee_math_real_sinh"; + attribute foreign of cosh[real return real]:function is "ieee_math_real_cosh"; + attribute foreign of tanh[real return real]:function is "ieee_math_real_tanh"; + attribute foreign of arcsinh[real return real]:function is "ieee_math_real_arcsinh"; + attribute foreign of arccosh[real return real]:function is "ieee_math_real_arccosh"; + attribute foreign of arctanh[real return real]:function is "ieee_math_real_arctanh"; + +end package MATH_REAL; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit-body.vhdl new file mode 100644 index 0000000..18b3835 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit-body.vhdl @@ -0,0 +1,3045 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_BIT package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC Synthesis Working Group, +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Two numeric types are defined: +-- : -- > UNSIGNED: represents an UNSIGNED number in vector form +-- : -- > SIGNED: represents a SIGNED number in vector form +-- : The base element type is type BIT. +-- : The leftmost bit is treated as the most significant bit. +-- : Signed vectors are represented in two's complement form. +-- : This package contains overloaded arithmetic operators on +-- : the SIGNED and UNSIGNED types. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package body NUMERIC_BIT is + + -- null range array constants + + constant NAU : UNSIGNED(0 downto 1) := (others => '0'); + constant NAS : SIGNED(0 downto 1) := (others => '0'); + + -- implementation controls + + constant NO_WARNING : BOOLEAN := false; -- default to emit warnings + + -- =========================Local Subprograms ================================= + + function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is + variable NBITS : NATURAL; + variable N : NATURAL; + begin + if ARG >= 0 then + N := ARG; + else + N := -(ARG+1); + end if; + NBITS := 1; + while N > 0 loop + NBITS := NBITS+1; + N := N / 2; + end loop; + return NBITS; + end function SIGNED_NUM_BITS; + + function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is + variable NBITS : NATURAL; + variable N : NATURAL; + begin + N := ARG; + NBITS := 1; + while N > 1 loop + NBITS := NBITS+1; + N := N / 2; + end loop; + return NBITS; + end function UNSIGNED_NUM_BITS; + + ------------------------------------------------------------------------------ + -- this internal function computes the addition of two UNSIGNED + -- with input carry + -- * the two arguments are of the same length + + function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNSIGNED(L_LEFT downto 0) is R; + variable RESULT : UNSIGNED(L_LEFT downto 0); + variable CBIT : BIT := C; + begin + for I in 0 to L_LEFT loop + RESULT(I) := CBIT xor XL(I) xor XR(I); + CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); + end loop; + return RESULT; + end function ADD_UNSIGNED; + + -- this internal function computes the addition of two SIGNED + -- with input carry + -- * the two arguments are of the same length + + function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is + constant L_LEFT : INTEGER := L'length-1; + alias XL : SIGNED(L_LEFT downto 0) is L; + alias XR : SIGNED(L_LEFT downto 0) is R; + variable RESULT : SIGNED(L_LEFT downto 0); + variable CBIT : BIT := C; + begin + for I in 0 to L_LEFT loop + RESULT(I) := CBIT xor XL(I) xor XR(I); + CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); + end loop; + return RESULT; + end function ADD_SIGNED; + + ------------------------------------------------------------------------------ + + -- this internal procedure computes UNSIGNED division + -- giving the quotient and remainder. + procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is + variable TEMP : UNSIGNED(NUM'length downto 0); + variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0); + alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; + variable TOPBIT : INTEGER; + begin + TEMP := "0"&NUM; + QUOT := (others => '0'); + TOPBIT := -1; + for J in DENOM'range loop + if DENOM(J) = '1' then + TOPBIT := J; + exit; + end if; + end loop; + assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero" + severity error; + + for J in NUM'length-(TOPBIT+1) downto 0 loop + if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then + TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) + -("0"&DENOM(TOPBIT downto 0)); + QUOT(J) := '1'; + end if; + assert TEMP(TOPBIT+J+1) = '0' + report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm" + severity error; + end loop; + XQUOT := RESIZE(QUOT, XQUOT'length); + XREMAIN := RESIZE(TEMP, XREMAIN'length); + end procedure DIVMOD; + + -----------------Local Subprograms - shift/rotate ops------------------------- + + function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0'); + begin + if COUNT <= ARG_L then + RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); + end if; + return RESULT; + end function XSLL; + + function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0'); + begin + if COUNT <= ARG_L then + RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); + end if; + return RESULT; + end function XSRL; + + function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : BIT_VECTOR(ARG_L downto 0); + variable XCOUNT : NATURAL := COUNT; + begin + if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; + else + if (XCOUNT > ARG_L) then XCOUNT := ARG_L; + end if; + RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); + RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); + end if; + return RESULT; + end function XSRA; + + function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG; + variable COUNTM : INTEGER; + begin + COUNTM := COUNT mod (ARG_L + 1); + if COUNTM /= 0 then + RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); + RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); + end if; + return RESULT; + end function XROL; + + function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG; + variable COUNTM : INTEGER; + begin + COUNTM := COUNT mod (ARG_L + 1); + if COUNTM /= 0 then + RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); + RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); + end if; + return RESULT; + end function XROR; + + ---------------- Local Subprograms - Relational Operators -------------------- + + -- + -- General "=" for UNSIGNED vectors, same length + -- + function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is + begin + return BIT_VECTOR(L) = BIT_VECTOR(R); + end function UNSIGNED_EQUAL; + + -- + -- General "=" for SIGNED vectors, same length + -- + function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is + begin + return BIT_VECTOR(L) = BIT_VECTOR(R); + end function SIGNED_EQUAL; + + -- + -- General "<" for UNSIGNED vectors, same length + -- + function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is + begin + return BIT_VECTOR(L) < BIT_VECTOR(R); + end function UNSIGNED_LESS; + + -- + -- General "<" function for SIGNED vectors, same length + -- + function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is + -- Need aliases to assure index direction + variable INTERN_L : SIGNED(0 to L'length-1); + variable INTERN_R : SIGNED(0 to R'length-1); + begin + INTERN_L := L; + INTERN_R := R; + INTERN_L(0) := not INTERN_L(0); + INTERN_R(0) := not INTERN_R(0); + return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R); + end function SIGNED_LESS; + + -- + -- General "<=" function for UNSIGNED vectors, same length + -- + function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is + begin + return BIT_VECTOR(L) <= BIT_VECTOR(R); + end function UNSIGNED_LESS_OR_EQUAL; + + -- + -- General "<=" function for SIGNED vectors, same length + -- + function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is + -- Need aliases to assure index direction + variable INTERN_L : SIGNED(0 to L'length-1); + variable INTERN_R : SIGNED(0 to R'length-1); + begin + INTERN_L := L; + INTERN_R := R; + INTERN_L(0) := not INTERN_L(0); + INTERN_R(0) := not INTERN_R(0); + return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R); + end function SIGNED_LESS_OR_EQUAL; + + -- ====================== Exported Functions ================================== + + -- Id: A.1 + function "abs" (ARG : SIGNED) return SIGNED is + constant ARG_LEFT : INTEGER := ARG'length-1; + variable RESULT : SIGNED(ARG_LEFT downto 0); + begin + if ARG'length < 1 then return NAS; + end if; + RESULT := ARG; + if RESULT(RESULT'left) = '1' then + RESULT := -RESULT; + end if; + return RESULT; + end function "abs"; + + -- Id: A.2 + function "-" (ARG : SIGNED) return SIGNED is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT : SIGNED(ARG_LEFT downto 0); + variable CBIT : BIT := '1'; + begin + if ARG'length < 1 then return NAS; + end if; + for I in 0 to RESULT'left loop + RESULT(I) := not(XARG(I)) xor CBIT; + CBIT := CBIT and not(XARG(I)); + end loop; + return RESULT; + end function "-"; + + -- ============================================================================ + + -- Id: A.3 + function "+" (L, R : UNSIGNED) return UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0'); + end function "+"; + + -- Id: A.3R + function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is + variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L + XR); + end function "+"; + + -- Id: A.3L + function "+" (L : BIT; R : UNSIGNED) return UNSIGNED is + variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL + R); + end function "+"; + + -- Id: A.4 + function "+" (L, R : SIGNED) return SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0'); + end function "+"; + + -- Id: A.4R + function "+" (L : SIGNED; R : BIT) return SIGNED is + variable XR : SIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L + XR); + end function "+"; + + -- Id: A.4L + function "+" (L : BIT; R : SIGNED) return SIGNED is + variable XL : SIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL + R); + end function "+"; + + -- Id: A.5 + function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + begin + return L + TO_UNSIGNED(R, L'length); + end function "+"; + + -- Id: A.6 + function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) + R; + end function "+"; + + -- Id: A.7 + function "+" (L : SIGNED; R : INTEGER) return SIGNED is + begin + return L + TO_SIGNED(R, L'length); + end function "+"; + + -- Id: A.8 + function "+" (L : INTEGER; R : SIGNED) return SIGNED is + begin + return TO_SIGNED(L, R'length) + R; + end function "+"; + + -- ============================================================================ + + -- Id: A.9 + function "-" (L, R : UNSIGNED) return UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + return ADD_UNSIGNED(RESIZE(L, SIZE), + not(RESIZE(R, SIZE)), + '1'); + end function "-"; + + -- Id: A.9R + function "-" (L : UNSIGNED; R : BIT) return UNSIGNED is + variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L - XR); + end function "-"; + + -- Id: A.9L + function "-" (L : BIT; R : UNSIGNED) return UNSIGNED is + variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL - R); + end function "-"; + + -- Id: A.10 + function "-" (L, R : SIGNED) return SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + return ADD_SIGNED(RESIZE(L, SIZE), + not(RESIZE(R, SIZE)), + '1'); + end function "-"; + + -- Id: A.10R + function "-" (L : SIGNED; R : BIT) return SIGNED is + variable XR : SIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L - XR); + end function "-"; + + -- Id: A.10L + function "-" (L : BIT; R : SIGNED) return SIGNED is + variable XL : SIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL - R); + end function "-"; + + -- Id: A.11 + function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + begin + return L - TO_UNSIGNED(R, L'length); + end function "-"; + + -- Id: A.12 + function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) - R; + end function "-"; + + -- Id: A.13 + function "-" (L : SIGNED; R : INTEGER) return SIGNED is + begin + return L - TO_SIGNED(R, L'length); + end function "-"; + + -- Id: A.14 + function "-" (L : INTEGER; R : SIGNED) return SIGNED is + begin + return TO_SIGNED(L, R'length) - R; + end function "-"; + + -- ============================================================================ + + -- Id: A.15 + function "*" (L, R : UNSIGNED) return UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNSIGNED(R_LEFT downto 0) is R; + variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0'); + variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + ADVAL := RESIZE(XR, RESULT'length); + for I in 0 to L_LEFT loop + if XL(I) = '1' then RESULT := RESULT + ADVAL; + end if; + ADVAL := SHIFT_LEFT(ADVAL, 1); + end loop; + return RESULT; + end function "*"; + + -- Id: A.16 + function "*" (L, R : SIGNED) return SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + variable XL : SIGNED(L_LEFT downto 0); + variable XR : SIGNED(R_LEFT downto 0); + variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); + variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0); + begin + if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; + end if; + XL := L; + XR := R; + ADVAL := RESIZE(XR, RESULT'length); + for I in 0 to L_LEFT-1 loop + if XL(I) = '1' then RESULT := RESULT + ADVAL; + end if; + ADVAL := SHIFT_LEFT(ADVAL, 1); + end loop; + if XL(L_LEFT) = '1' then + RESULT := RESULT - ADVAL; + end if; + return RESULT; + end function "*"; + + -- Id: A.17 + function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + begin + return L * TO_UNSIGNED(R, L'length); + end function "*"; + + -- Id: A.18 + function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) * R; + end function "*"; + + -- Id: A.19 + function "*" (L : SIGNED; R : INTEGER) return SIGNED is + begin + return L * TO_SIGNED(R, L'length); + end function "*"; + + -- Id: A.20 + function "*" (L : INTEGER; R : SIGNED) return SIGNED is + begin + return TO_SIGNED(L, R'length) * R; + end function "*"; + + -- ============================================================================ + + -- Id: A.21 + function "/" (L, R : UNSIGNED) return UNSIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + DIVMOD(L, R, FQUOT, FREMAIN); + return FQUOT; + end function "/"; + + -- Id: A.22 + function "/" (L, R : SIGNED) return SIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + variable XNUM : UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNSIGNED(R'length-1 downto 0); + variable QNEG : BOOLEAN := false; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + if L(L'left) = '1' then + XNUM := UNSIGNED(-L); + QNEG := true; + else + XNUM := UNSIGNED(L); + end if; + if R(R'left) = '1' then + XDENOM := UNSIGNED(-R); + QNEG := not QNEG; + else + XDENOM := UNSIGNED(R); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if QNEG then FQUOT := "0"-FQUOT; + end if; + return SIGNED(FQUOT); + end function "/"; + + -- Id: A.23 + function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAU; + end if; + if (R_LENGTH > L'length) then + QUOT := (others => '0'); + return RESIZE(QUOT, L'length); + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + QUOT := RESIZE((L / XR), QUOT'length); + return RESIZE(QUOT, L'length); + end function "/"; + + -- Id: A.24 + function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAU; + end if; + XL := TO_UNSIGNED(L, L_LENGTH); + QUOT := RESIZE((XL / R), QUOT'length); + if L_LENGTH > R'length + and QUOT(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated" + severity warning; + end if; + return RESIZE(QUOT, R'length); + end function "/"; + + -- Id: A.25 + function "/" (L : SIGNED; R : INTEGER) return SIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAS; + end if; + if (R_LENGTH > L'length) then + QUOT := (others => '0'); + return RESIZE(QUOT, L'length); + end if; + XR := TO_SIGNED(R, R_LENGTH); + QUOT := RESIZE((L / XR), QUOT'length); + return RESIZE(QUOT, L'length); + end function "/"; + + -- Id: A.26 + function "/" (L : INTEGER; R : SIGNED) return SIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + QUOT := RESIZE((XL / R), QUOT'length); + if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) + then + assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated" + severity warning; + end if; + return RESIZE(QUOT, R'length); + end function "/"; + + -- ============================================================================ + + -- Id: A.27 + function "rem" (L, R : UNSIGNED) return UNSIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + DIVMOD(L, R, FQUOT, FREMAIN); + return FREMAIN; + end function "rem"; + + -- Id: A.28 + function "rem" (L, R : SIGNED) return SIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + variable XNUM : UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNSIGNED(R'length-1 downto 0); + variable RNEG : BOOLEAN := false; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + if L(L'left) = '1' then + XNUM := UNSIGNED(-L); + RNEG := true; + else + XNUM := UNSIGNED(L); + end if; + if R(R'left) = '1' then + XDENOM := UNSIGNED(-R); + else + XDENOM := UNSIGNED(R); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if RNEG then + FREMAIN := "0"-FREMAIN; + end if; + return SIGNED(FREMAIN); + end function "rem"; + + -- Id: A.29 + function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAU; + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + XREM := RESIZE((L rem XR), XREM'length); + if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => '0') + then + assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "rem"; + + -- Id: A.30 + function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAU; + end if; + XL := TO_UNSIGNED(L, L_LENGTH); + XREM := RESIZE((XL rem R), XREM'length); + if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "rem"; + + -- Id: A.31 + function "rem" (L : SIGNED; R : INTEGER) return SIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, XREM : SIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAS; + end if; + XR := TO_SIGNED(R, R_LENGTH); + XREM := RESIZE((L rem XR), XREM'length); + if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) + then + assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "rem"; + + -- Id: A.32 + function "rem" (L : INTEGER; R : SIGNED) return SIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, XREM : SIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + XREM := RESIZE((XL rem R), XREM'length); + if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) + then + assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "rem"; + + -- ============================================================================ + + -- Id: A.33 + function "mod" (L, R : UNSIGNED) return UNSIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + DIVMOD(L, R, FQUOT, FREMAIN); + return FREMAIN; + end function "mod"; + + -- Id: A.34 + function "mod" (L, R : SIGNED) return SIGNED is + variable FQUOT : UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNSIGNED(R'length-1 downto 0); + variable XNUM : UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNSIGNED(R'length-1 downto 0); + variable RNEG : BOOLEAN := false; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + if L(L'left) = '1' then + XNUM := UNSIGNED(-L); + else + XNUM := UNSIGNED(L); + end if; + if R(R'left) = '1' then + XDENOM := UNSIGNED(-R); + RNEG := true; + else + XDENOM := UNSIGNED(R); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if RNEG and L(L'left) = '1' then + FREMAIN := "0"-FREMAIN; + elsif RNEG and FREMAIN /= "0" then + FREMAIN := FREMAIN-XDENOM; + elsif L(L'left) = '1' and FREMAIN /= "0" then + FREMAIN := XDENOM-FREMAIN; + end if; + return SIGNED(FREMAIN); + end function "mod"; + + -- Id: A.35 + function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAU; + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + XREM := RESIZE((L mod XR), XREM'length); + if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => '0') + then + assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "mod"; + + -- Id: A.36 + function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAU; + end if; + XL := TO_UNSIGNED(L, L_LENGTH); + XREM := RESIZE((XL mod R), XREM'length); + if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "mod"; + + -- Id: A.37 + function "mod" (L : SIGNED; R : INTEGER) return SIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, XREM : SIGNED(R_LENGTH-1 downto 0); + begin + if (L'length < 1) then return NAS; + end if; + XR := TO_SIGNED(R, R_LENGTH); + XREM := RESIZE((L mod XR), XREM'length); + if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) + then + assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "mod"; + + -- Id: A.38 + function "mod" (L : INTEGER; R : SIGNED) return SIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, XREM : SIGNED(L_LENGTH-1 downto 0); + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + XREM := RESIZE((XL mod R), XREM'length); + if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) + then + assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "mod"; + + -- ============================================================================ + -- Id: A.39 + function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER is + begin + for INDEX in ARG'range loop + if ARG(INDEX) = Y then + return INDEX; + end if; + end loop; + return -1; + end function find_leftmost; + + -- Id: A.40 + function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER is + begin + for INDEX in ARG'range loop + if ARG(INDEX) = Y then + return INDEX; + end if; + end loop; + return -1; + end function find_leftmost; + + -- Id: A.41 + function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER is + begin + for INDEX in ARG'reverse_range loop + if ARG(INDEX) = Y then + return INDEX; + end if; + end loop; + return -1; + end function find_rightmost; + + -- Id: A.42 + function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER is + begin + for INDEX in ARG'reverse_range loop + if ARG(INDEX) = Y then + return INDEX; + end if; + end loop; + return -1; + end function find_rightmost; + + -- ============================================================================ + + -- Id: C.1 + function ">" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function ">"; + + -- Id: C.2 + function ">" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function ">"; + + -- Id: C.3 + function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R); + end function ">"; + + -- Id: C.4 + function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R); + end function ">"; + + -- Id: C.5 + function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return false; + end if; + return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length)); + end function ">"; + + -- Id: C.6 + function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length)); + end function ">"; + + -- ============================================================================ + + -- Id: C.7 + function "<" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "<"; + + -- Id: C.8 + function "<" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "<"; + + -- Id: C.9 + function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R); + end function "<"; + + -- Id: C.10 + function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return SIGNED_LESS(TO_SIGNED(L, R'length), R); + end function "<"; + + -- Id: C.11 + function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length)); + end function "<"; + + -- Id: C.12 + function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return SIGNED_LESS(L, TO_SIGNED(R, L'length)); + end function "<"; + + -- ============================================================================ + + -- Id: C.13 + function "<=" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "<="; + + -- Id: C.14 + function "<=" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "<="; + + -- Id: C.15 + function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R); + end function "<="; + + -- Id: C.16 + function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R); + end function "<="; + + -- Id: C.17 + function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length)); + end function "<="; + + -- Id: C.18 + function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length)); + end function "<="; + + -- ============================================================================ + + -- Id: C.19 + function ">=" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function ">="; + + -- Id: C.20 + function ">=" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function ">="; + + -- Id: C.21 + function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R); + end function ">="; + + -- Id: C.22 + function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not SIGNED_LESS(TO_SIGNED(L, R'length), R); + end function ">="; + + -- Id: C.23 + function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length)); + end function ">="; + + -- Id: C.24 + function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not SIGNED_LESS(L, TO_SIGNED(R, L'length)); + end function ">="; + + -- ============================================================================ + + -- Id: C.25 + function "=" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "="; + + -- Id: C.26 + function "=" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)); + end function "="; + + -- Id: C.27 + function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return false; + end if; + return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R); + end function "="; + + -- Id: C.28 + function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return false; + end if; + return SIGNED_EQUAL(TO_SIGNED(L, R'length), R); + end function "="; + + -- Id: C.29 + function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return false; + end if; + return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)); + end function "="; + + -- Id: C.30 + function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return false; + end if; + return SIGNED_EQUAL(L, TO_SIGNED(R, L'length)); + end function "="; + + -- ============================================================================ + + -- Id: C.31 + function "/=" (L, R : UNSIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE))); + end function "/="; + + -- Id: C.32 + function "/=" (L, R : SIGNED) return BOOLEAN is + variable SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE))); + end function "/="; + + -- Id: C.33 + function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R)); + end function "/="; + + -- Id: C.34 + function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + if SIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R)); + end function "/="; + + -- Id: C.35 + function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return true; + end if; + return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length))); + end function "/="; + + -- Id: C.36 + function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + if SIGNED_NUM_BITS(R) > L'length then return true; + end if; + return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length))); + end function "/="; + + -- ============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : UNSIGNED) return UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then + return RESIZE(L, SIZE); + else + return RESIZE(R, SIZE); + end if; + end function MINIMUM; + + -- Id: C.38 + function MINIMUM (L, R : SIGNED) return SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then + return RESIZE(L, SIZE); + else + return RESIZE(R, SIZE); + end if; + end function MINIMUM; + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is + begin + return MINIMUM(TO_UNSIGNED(L, R'length), R); + end function MINIMUM; + + -- Id: C.40 + function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED is + begin + return MINIMUM(TO_SIGNED(L, R'length), R); + end function MINIMUM; + + -- Id: C.41 + function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is + begin + return MINIMUM(L, TO_UNSIGNED(R, L'length)); + end function MINIMUM; + + -- Id: C.42 + function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED is + begin + return MINIMUM(L, TO_SIGNED(R, L'length)); + end function MINIMUM; + + -- ============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then + return RESIZE(R, SIZE); + else + return RESIZE(L, SIZE); + end if; + end function MAXIMUM; + + -- Id: C.44 + function MAXIMUM (L, R : SIGNED) return SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then + return RESIZE(R, SIZE); + else + return RESIZE(L, SIZE); + end if; + end function MAXIMUM; + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is + begin + return MAXIMUM(TO_UNSIGNED(L, R'length), R); + end function MAXIMUM; + + -- Id: C.46 + function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED is + begin + return MAXIMUM(TO_SIGNED(L, R'length), R); + end function MAXIMUM; + + -- Id: C.47 + function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is + begin + return MAXIMUM(L, TO_UNSIGNED(R, L'length)); + end function MAXIMUM; + + -- Id: C.48 + function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED is + begin + return MAXIMUM(L, TO_SIGNED(R, L'length)); + end function MAXIMUM; + + -- ============================================================================ + + -- Id: C.49 + function "?>" (L, R : UNSIGNED) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- Id: C.50 + function "?>" (L, R : SIGNED) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- Id: C.51 + function "?>" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- Id: C.52 + function "?>" (L : INTEGER; R : SIGNED) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- Id: C.53 + function "?>" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- Id: C.54 + function "?>" (L : SIGNED; R : INTEGER) return BIT is + begin + if L > R then + return '1'; + else + return '0'; + end if; + end function "?>"; + + -- ============================================================================ + + -- Id: C.55 + function "?<" (L, R : UNSIGNED) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- Id: C.56 + function "?<" (L, R : SIGNED) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- Id: C.57 + function "?<" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- Id: C.58 + function "?<" (L : INTEGER; R : SIGNED) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- Id: C.59 + function "?<" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- Id: C.60 + function "?<" (L : SIGNED; R : INTEGER) return BIT is + begin + if L < R then + return '1'; + else + return '0'; + end if; + end function "?<"; + + -- ============================================================================ + + -- Id: C.61 + function "?<=" (L, R : UNSIGNED) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- Id: C.62 + function "?<=" (L, R : SIGNED) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- Id: C.63 + function "?<=" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- Id: C.64 + function "?<=" (L : INTEGER; R : SIGNED) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- Id: C.65 + function "?<=" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- Id: C.66 + function "?<=" (L : SIGNED; R : INTEGER) return BIT is + begin + if L <= R then + return '1'; + else + return '0'; + end if; + end function "?<="; + + -- ============================================================================ + + -- Id: C.67 + function "?>=" (L, R : UNSIGNED) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- Id: C.68 + function "?>=" (L, R : SIGNED) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- Id: C.69 + function "?>=" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- Id: C.70 + function "?>=" (L : INTEGER; R : SIGNED) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- Id: C.71 + function "?>=" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- Id: C.72 + function "?>=" (L : SIGNED; R : INTEGER) return BIT is + begin + if L >= R then + return '1'; + else + return '0'; + end if; + end function "?>="; + + -- ============================================================================ + + -- Id: C.73 + function "?=" (L, R : UNSIGNED) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- Id: C.74 + function "?=" (L, R : SIGNED) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- Id: C.75 + function "?=" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- Id: C.76 + function "?=" (L : INTEGER; R : SIGNED) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- Id: C.77 + function "?=" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- Id: C.78 + function "?=" (L : SIGNED; R : INTEGER) return BIT is + begin + if L = R then + return '1'; + else + return '0'; + end if; + end function "?="; + + -- ============================================================================ + + -- Id: C.79 + function "?/=" (L, R : UNSIGNED) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- Id: C.80 + function "?/=" (L, R : SIGNED) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- Id: C.81 + function "?/=" (L : NATURAL; R : UNSIGNED) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- Id: C.82 + function "?/=" (L : INTEGER; R : SIGNED) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- Id: C.83 + function "?/=" (L : UNSIGNED; R : NATURAL) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- Id: C.84 + function "?/=" (L : SIGNED; R : INTEGER) return BIT is + begin + if L /= R then + return '1'; + else + return '0'; + end if; + end function "?/="; + + -- ============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT)); + end function SHIFT_LEFT; + + -- Id: S.2 + function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT)); + end function SHIFT_RIGHT; + + -- Id: S.3 + function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT)); + end function SHIFT_LEFT; + + -- Id: S.4 + function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT)); + end function SHIFT_RIGHT; + + -- ============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT)); + end function ROTATE_LEFT; + + -- Id: S.6 + function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT)); + end function ROTATE_RIGHT; + + -- Id: S.7 + function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return SIGNED(XROL(BIT_VECTOR(ARG), COUNT)); + end function ROTATE_LEFT; + + -- Id: S.8 + function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return SIGNED(XROR(BIT_VECTOR(ARG), COUNT)); + end function ROTATE_RIGHT; + + -- ============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.9 + function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sll"; + + ------------------------------------------------------------------------------ + -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.10 + function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT)); + end if; + end function "sll"; + + ------------------------------------------------------------------------------ + -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.11 + function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "srl"; + + ------------------------------------------------------------------------------ + -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.12 + function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT)); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "srl"; + + ------------------------------------------------------------------------------ + -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.13 + function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return ROTATE_LEFT(ARG, COUNT); + else + return ROTATE_RIGHT(ARG, -COUNT); + end if; + end function "rol"; + + ------------------------------------------------------------------------------ + -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.14 + function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return ROTATE_LEFT(ARG, COUNT); + else + return ROTATE_RIGHT(ARG, -COUNT); + end if; + end function "rol"; + + ------------------------------------------------------------------------------ + -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.15 + function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return ROTATE_RIGHT(ARG, COUNT); + else + return ROTATE_LEFT(ARG, -COUNT); + end if; + end function "ror"; + + ------------------------------------------------------------------------------ + -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.16 + function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return ROTATE_RIGHT(ARG, COUNT); + else + return ROTATE_LEFT(ARG, -COUNT); + end if; + end function "ror"; + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sla"; + + ------------------------------------------------------------------------------ + -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.18 + function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sla"; + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "sra"; + + ------------------------------------------------------------------------------ + -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.20 + function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "sra"; + + -- ============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : UNSIGNED) return NATURAL is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT : NATURAL := 0; + begin + if (ARG'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0" + severity warning; + return 0; + end if; + for I in XARG'range loop + RESULT := RESULT+RESULT; + if XARG(I) = '1' then + RESULT := RESULT + 1; + end if; + end loop; + return RESULT; + end function TO_INTEGER; + + -- Id: D.2 + function TO_INTEGER (ARG : SIGNED) return INTEGER is + begin + if (ARG'length < 1) then + assert NO_WARNING + report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0" + severity warning; + return 0; + end if; + if ARG(ARG'left) = '0' then + return TO_INTEGER(UNSIGNED(ARG)); + else + return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1); + end if; + end function TO_INTEGER; + + -- Id: D.3 + function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is + variable RESULT : UNSIGNED(SIZE-1 downto 0); + variable I_VAL : NATURAL := ARG; + begin + if (SIZE < 1) then return NAU; + end if; + for I in 0 to RESULT'left loop + if (I_VAL mod 2) = 0 then + RESULT(I) := '0'; + else RESULT(I) := '1'; + end if; + I_VAL := I_VAL/2; + end loop; + if not(I_VAL = 0) then + assert NO_WARNING + report "NUMERIC_BIT.TO_UNSIGNED: vector truncated" + severity warning; + end if; + return RESULT; + end function TO_UNSIGNED; + + -- Id: D.4 + function TO_SIGNED (ARG : INTEGER; + SIZE : NATURAL) return SIGNED is + variable RESULT : SIGNED(SIZE-1 downto 0); + variable B_VAL : BIT := '0'; + variable I_VAL : INTEGER := ARG; + begin + if (SIZE < 1) then return NAS; + end if; + if (ARG < 0) then + B_VAL := '1'; + I_VAL := -(ARG+1); + end if; + for I in 0 to RESULT'left loop + if (I_VAL mod 2) = 0 then + RESULT(I) := B_VAL; + else + RESULT(I) := not B_VAL; + end if; + I_VAL := I_VAL/2; + end loop; + if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then + assert NO_WARNING + report "NUMERIC_BIT.TO_SIGNED: vector truncated" + severity warning; + end if; + return RESULT; + end function TO_SIGNED; + + function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) + return UNSIGNED is + begin + return TO_UNSIGNED (ARG => ARG, + SIZE => SIZE_RES'length); + end function TO_UNSIGNED; + + function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) + return SIGNED is + begin + return TO_SIGNED (ARG => ARG, + SIZE => SIZE_RES'length); + end function TO_SIGNED; + + -- ============================================================================ + + -- Id: R.1 + function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is + alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG; + variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); + constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; + begin + if (NEW_SIZE < 1) then return NAS; + end if; + if (ARG'length = 0) then return RESULT; + end if; + RESULT := (others => ARG(ARG'left)); + if BOUND >= 0 then + RESULT(BOUND downto 0) := INVEC(BOUND downto 0); + end if; + return RESULT; + end function RESIZE; + + -- Id: R.2 + function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); + begin + if (NEW_SIZE < 1) then return NAU; + end if; + if XARG'length = 0 then return RESULT; + end if; + if (RESULT'length < ARG'length) then + RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); + else + RESULT(RESULT'left downto XARG'left+1) := (others => '0'); + RESULT(XARG'left downto 0) := XARG; + end if; + return RESULT; + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : UNSIGNED) + return UNSIGNED is + begin + return RESIZE (ARG => ARG, + NEW_SIZE => SIZE_RES'length); + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : SIGNED) + return SIGNED is + begin + return RESIZE (ARG => ARG, + NEW_SIZE => SIZE_RES'length); + end function RESIZE; + + -- ============================================================================ + + -- Id: L.1 + function "not" (L : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(not(BIT_VECTOR(L))); + return RESULT; + end function "not"; + + -- Id: L.2 + function "and" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R)); + return RESULT; + end function "and"; + + -- Id: L.3 + function "or" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R)); + return RESULT; + end function "or"; + + -- Id: L.4 + function "nand" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R)); + return RESULT; + end function "nand"; + + -- Id: L.5 + function "nor" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R)); + return RESULT; + end function "nor"; + + -- Id: L.6 + function "xor" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R)); + return RESULT; + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.7 + function "xnor" (L, R : UNSIGNED) return UNSIGNED is + variable RESULT : UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R)); + return RESULT; + end function "xnor"; + + -- Id: L.8 + function "not" (L : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(not(BIT_VECTOR(L))); + return RESULT; + end function "not"; + + -- Id: L.9 + function "and" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R)); + return RESULT; + end function "and"; + + -- Id: L.10 + function "or" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R)); + return RESULT; + end function "or"; + + -- Id: L.11 + function "nand" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R)); + return RESULT; + end function "nand"; + + -- Id: L.12 + function "nor" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R)); + return RESULT; + end function "nor"; + + -- Id: L.13 + function "xor" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R)); + return RESULT; + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.14 + function "xnor" (L, R : SIGNED) return SIGNED is + variable RESULT : SIGNED(L'length-1 downto 0); + begin + RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R)); + return RESULT; + end function "xnor"; + + -- Id: L.15 + function "and" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L and BIT_VECTOR(R)); + end function "and"; + + -- Id: L.16 + function "and" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) and R); + end function "and"; + + -- Id: L.17 + function "or" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L or BIT_VECTOR(R)); + end function "or"; + + -- Id: L.18 + function "or" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) or R); + end function "or"; + + -- Id: L.19 + function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L nand BIT_VECTOR(R)); + end function "nand"; + + -- Id: L.20 + function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) nand R); + end function "nand"; + + -- Id: L.21 + function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L nor BIT_VECTOR(R)); + end function "nor"; + + -- Id: L.22 + function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) nor R); + end function "nor"; + + -- Id: L.23 + function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L xor BIT_VECTOR(R)); + end function "xor"; + + -- Id: L.24 + function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) xor R); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.25 + function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED is + begin + return UNSIGNED (L xnor BIT_VECTOR(R)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.26 + function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED is + begin + return UNSIGNED (BIT_VECTOR(L) xnor R); + end function "xnor"; + + -- Id: L.27 + function "and" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L and BIT_VECTOR(R)); + end function "and"; + + -- Id: L.28 + function "and" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) and R); + end function "and"; + + -- Id: L.29 + function "or" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L or BIT_VECTOR(R)); + end function "or"; + + -- Id: L.30 + function "or" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) or R); + end function "or"; + + -- Id: L.31 + function "nand" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L nand BIT_VECTOR(R)); + end function "nand"; + + -- Id: L.32 + function "nand" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) nand R); + end function "nand"; + + -- Id: L.33 + function "nor" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L nor BIT_VECTOR(R)); + end function "nor"; + + -- Id: L.34 + function "nor" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) nor R); + end function "nor"; + + -- Id: L.35 + function "xor" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L xor BIT_VECTOR(R)); + end function "xor"; + + -- Id: L.36 + function "xor" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) xor R); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.37 + function "xnor" (L : BIT; R : SIGNED) return SIGNED is + begin + return SIGNED (L xnor BIT_VECTOR(R)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.38 + function "xnor" (L : SIGNED; R : BIT) return SIGNED is + begin + return SIGNED (BIT_VECTOR(L) xnor R); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.39 + function "and" (L : SIGNED) return BIT is + begin + return and (BIT_VECTOR (L)); + end function "and"; + + ------------------------------------------------------------------------------ + -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.40 + function "and" (L : UNSIGNED) return BIT is + begin + return and (BIT_VECTOR (L)); + end function "and"; + + ------------------------------------------------------------------------------ + -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.41 + function "nand" (L : SIGNED) return BIT is + begin + return nand (BIT_VECTOR (L)); + end function "nand"; + + ------------------------------------------------------------------------------ + -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.42 + function "nand" (L : UNSIGNED) return BIT is + begin + return nand (BIT_VECTOR (L)); + end function "nand"; + + ------------------------------------------------------------------------------ + -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.43 + function "or" (L : SIGNED) return BIT is + begin + return or (BIT_VECTOR (L)); + end function "or"; + + ------------------------------------------------------------------------------ + -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.44 + function "or" (L : UNSIGNED) return BIT is + begin + return or (BIT_VECTOR (L)); + end function "or"; + + ------------------------------------------------------------------------------ + -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.45 + function "nor" (L : SIGNED) return BIT is + begin + return nor (BIT_VECTOR (L)); + end function "nor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.46 + function "nor" (L : UNSIGNED) return BIT is + begin + return nor (BIT_VECTOR (L)); + end function "nor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.47 + function "xor" (L : SIGNED) return BIT is + begin + return xor (BIT_VECTOR (L)); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.48 + function "xor" (L : UNSIGNED) return BIT is + begin + return xor (BIT_VECTOR (L)); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.49 + function "xnor" (L : SIGNED) return BIT is + begin + return xnor (BIT_VECTOR (L)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.50 + function "xnor" (L : UNSIGNED) return BIT is + begin + return xnor (BIT_VECTOR (L)); + end function "xnor"; + + -- ============================================================================ + -- string conversion and write operations + -- ============================================================================ + function to_ostring (value : UNSIGNED) return STRING is + begin + return to_ostring(BIT_VECTOR (value)); + end function to_ostring; + + function to_ostring (value : SIGNED) return STRING is + constant result_length : INTEGER := (value'length+2)/3; + constant pad : BIT_VECTOR(1 to (result_length*3 - value'length)) + := (others => value (value'left)); -- Extend sign bit + begin + return to_ostring(pad & BIT_VECTOR (value)); + end function to_ostring; + + function to_hstring (value : UNSIGNED) return STRING is + begin + return to_hstring(BIT_VECTOR (value)); + end function to_hstring; + + function to_hstring (value : SIGNED) return STRING is + constant result_length : INTEGER := (value'length+3)/4; + constant pad : BIT_VECTOR(1 to (result_length*4 - value'length)) + := (others => value (value'left)); -- Extend sign bit + begin + return to_hstring(pad & BIT_VECTOR (value)); + end function to_hstring; + + procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is + variable ivalue : BIT_VECTOR(value'range); + begin + READ (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := UNSIGNED(ivalue); + end procedure READ; + + procedure READ(L : inout LINE; VALUE : out UNSIGNED) is + variable ivalue : BIT_VECTOR(value'range); + begin + READ (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure READ; + + procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is + variable ivalue : BIT_VECTOR(value'range); + begin + READ (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := SIGNED(ivalue); + end procedure READ; + + procedure READ(L : inout LINE; VALUE : out SIGNED) is + variable ivalue : BIT_VECTOR(value'range); + begin + READ (L => L, + VALUE => ivalue); + VALUE := SIGNED (ivalue); + end procedure READ; + + procedure WRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : BIT_VECTOR(value'range); + begin + ivalue := BIT_VECTOR (VALUE); + WRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure WRITE; + + procedure WRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : BIT_VECTOR(value'range); + begin + ivalue := BIT_VECTOR (VALUE); + WRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure WRITE; + + procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is + variable ivalue : BIT_VECTOR(value'range); + begin + OREAD (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := UNSIGNED(ivalue); + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is + constant ne : INTEGER := (value'length+2)/3; + constant pad : INTEGER := ne*3 - value'length; + variable ivalue : BIT_VECTOR(0 to ne*3-1); + variable ok : BOOLEAN; + begin + OREAD (L => L, + VALUE => ivalue, -- Read padded STRING + good => ok); + -- Bail out if there was a bad read + if not ok then + good := false; + return; + end if; + if (pad > 0) then + if (ivalue(0) = '0') then -- positive + if ivalue(0) = or (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + good := true; + else + good := false; + end if; + else -- negative + if ivalue(0) = and (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + good := true; + else + good := false; + end if; + end if; + else + good := true; + VALUE := SIGNED (ivalue); + end if; + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is + variable ivalue : BIT_VECTOR(value'range); + begin + OREAD (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out SIGNED) is + constant ne : INTEGER := (value'length+2)/3; + constant pad : INTEGER := ne*3 - value'length; + variable ivalue : BIT_VECTOR(0 to ne*3-1); + begin + OREAD (L => L, + VALUE => ivalue); -- Read padded string + if (pad > 0) then + if (ivalue(0) = '0') then -- positive + if ivalue(0) = or (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + assert false + report "NUMERIC_BIT.OREAD Error: Signed vector truncated" + severity error; + end if; + else -- negative + if ivalue(0) = and (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + assert false + report "NUMERIC_BIT.OREAD Error: Signed vector truncated" + severity error; + end if; + end if; + else + VALUE := SIGNED (ivalue); + end if; + end procedure OREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is + variable ivalue : BIT_VECTOR(value'range); + begin + HREAD (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := UNSIGNED(ivalue); + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is + constant ne : INTEGER := (value'length+3)/4; + constant pad : INTEGER := ne*4 - value'length; + variable ivalue : BIT_VECTOR(0 to ne*4-1); + variable ok : BOOLEAN; + begin + HREAD (L => L, + VALUE => ivalue, -- Read padded STRING + good => ok); + if not ok then + good := false; + return; + end if; + if (pad > 0) then + if (ivalue(0) = '0') then -- positive + if ivalue(0) = or (ivalue(0 to pad)) then + GOOD := true; + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + GOOD := false; + end if; + else -- negative + if ivalue(0) = and (ivalue(0 to pad)) then + GOOD := true; + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + GOOD := false; + end if; + end if; + else + GOOD := true; + VALUE := SIGNED (ivalue); + end if; + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is + variable ivalue : BIT_VECTOR(value'range); + begin + HREAD (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out SIGNED) is + constant ne : INTEGER := (value'length+3)/4; + constant pad : INTEGER := ne*4 - value'length; + variable ivalue : BIT_VECTOR(0 to ne*4-1); + begin + HREAD (L => L, + VALUE => ivalue); -- Read padded string + if (pad > 0) then + if (ivalue(0) = '0') then -- positive + if ivalue(0) = or (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + assert false + report "NUMERIC_BIT.HREAD Error: Signed vector truncated" + severity error; + end if; + else -- negative + if ivalue(0) = and (ivalue(0 to pad)) then + VALUE := SIGNED (ivalue (pad to ivalue'high)); + else + assert false + report "NUMERIC_BIT.HREAD Error: Signed vector truncated" + severity error; + end if; + end if; + else + VALUE := SIGNED (ivalue); + end if; + end procedure HREAD; + + procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : BIT_VECTOR(value'range); + begin + ivalue := BIT_VECTOR (VALUE); + OWRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure OWRITE; + + procedure OWRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + constant ne : INTEGER := (VALUE'length+2)/3; + constant pad : BIT_VECTOR(0 to (ne*3 - VALUE'length) - 1) + := (others => VALUE (VALUE'left)); + variable ivalue : BIT_VECTOR(value'range); + begin + ivalue := BIT_VECTOR (VALUE); + OWRITE (L => L, + VALUE => pad & ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure OWRITE; + + procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : BIT_VECTOR(value'range); + begin + ivalue := BIT_VECTOR (VALUE); + HWRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure HWRITE; + + procedure HWRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : BIT_VECTOR(value'range); + constant ne : INTEGER := (value'length+3)/4; + constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) + := (others => VALUE(VALUE'left)); + begin + ivalue := BIT_VECTOR (VALUE); + HWRITE (L => L, + VALUE => pad & ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure HWRITE; + +end package body NUMERIC_BIT; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit.vhdl new file mode 100644 index 0000000..0b8144e --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit.vhdl @@ -0,0 +1,1592 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_BIT package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC Synthesis Working Group, +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Two numeric types are defined: +-- : -- > UNSIGNED: represents an UNSIGNED number in vector form +-- : -- > SIGNED: represents a SIGNED number in vector form +-- : The base element type is type BIT. +-- : The leftmost bit is treated as the most significant bit. +-- : Signed vectors are represented in two's complement form. +-- : This package contains overloaded arithmetic operators on +-- : the SIGNED and UNSIGNED types. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +use STD.TEXTIO.all; + +package NUMERIC_BIT is + constant CopyRightNotice : STRING + := "Copyright © 2008 IEEE. All rights reserved."; + + --============================================================================ + -- Numeric Array Type Definitions + --============================================================================ + + type UNSIGNED is array (NATURAL range <>) of BIT; + type SIGNED is array (NATURAL range <>) of BIT; + + --============================================================================ + -- Arithmetic Operators: + --============================================================================ + + -- Id: A.1 + function "abs" (ARG : SIGNED) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Returns the absolute value of a SIGNED vector ARG. + + -- Id: A.2 + function "-" (ARG : SIGNED) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Returns the value of the unary minus operation on a + -- SIGNED vector ARG. + + --============================================================================ + + -- Id: A.3 + function "+" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Adds two UNSIGNED vectors that may be of different lengths. + + -- Id: A.3R + function "+"(L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.3 where R is a one bit UNSIGNED + + -- Id: A.3L + function "+"(L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.3 where L is a one bit UNSIGNED + + -- Id: A.4 + function "+" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Adds two SIGNED vectors that may be of different lengths. + + -- Id: A.4R + function "+"(L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.4 where R is bit 0 of a non-negative. + + -- Id: A.4L + function "+"(L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.4 where L is bit 0 of a non-negative. + + -- Id: A.5 + function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Adds an UNSIGNED vector, L, with a nonnegative INTEGER, R. + + -- Id: A.6 + function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Adds a nonnegative INTEGER, L, with an UNSIGNED vector, R. + + -- Id: A.7 + function "+" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED + -- vector, R. + + -- Id: A.8 + function "+" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Adds a SIGNED vector, L, to an INTEGER, R. + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. + + -- Id: A.9R + function "-"(L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.9 where R is a one bit UNSIGNED + + -- Id: A.9L + function "-"(L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.9 where L is a one bit UNSIGNED + + -- Id: A.10 + function "-" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L, + -- that may possibly be of different lengths. + + -- Id: A.10R + function "-"(L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.10 where R is bit 0 of a non-negative. + + -- Id: A.10L + function "-"(L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.10 where R is bit 0 of a non-negative. + + -- Id: A.11 + function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Subtracts a nonnegative INTEGER, R, from an UNSIGNED vector, L. + + -- Id: A.12 + function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Subtracts an UNSIGNED vector, R, from a nonnegative INTEGER, L. + + -- Id: A.13 + function "-" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Subtracts an INTEGER, R, from a SIGNED vector, L. + + -- Id: A.14 + function "-" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Subtracts a SIGNED vector, R, from an INTEGER, L. + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) + -- Result: Performs the multiplication operation on two UNSIGNED vectors + -- that may possibly be of different lengths. + + -- Id: A.16 + function "*" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies two SIGNED vectors that may possibly be of + -- different lengths. + + -- Id: A.17 + function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0) + -- Result: Multiplies an UNSIGNED vector, L, with a nonnegative + -- INTEGER, R. R is converted to an UNSIGNED vector of + -- size L'LENGTH before multiplication. + + -- Id: A.18 + function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies an UNSIGNED vector, R, with a nonnegative + -- INTEGER, L. L is converted to an UNSIGNED vector of + -- size R'LENGTH before multiplication. + + -- Id: A.19 + function "*" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0) + -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is + -- converted to a SIGNED vector of size L'LENGTH before + -- multiplication. + + -- Id: A.20 + function "*" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is + -- converted to a SIGNED vector of size R'LENGTH before + -- multiplication. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "/" operator, a severity level + -- of ERROR is issued. + + -- Id: A.21 + function "/" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. + + -- Id: A.22 + function "/" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an SIGNED vector, L, by another SIGNED vector, R. + + -- Id: A.23 + function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by a nonnegative INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.24 + function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Divides a nonnegative INTEGER, L, by an UNSIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.25 + function "/" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Divides a SIGNED vector, L, by an INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.26 + function "/" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Divides an INTEGER, L, by a SIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "rem" operator, a severity level + -- of ERROR is issued. + + -- Id: A.27 + function "rem" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. + + -- Id: A.28 + function "rem" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are SIGNED vectors. + + -- Id: A.29 + function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a + -- nonnegative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.30 + function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a + -- nonnegative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.31 + function "rem" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.32 + function "rem" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "mod" operator, a severity level + -- of ERROR is issued. + + -- Id: A.33 + function "mod" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. + + -- Id: A.34 + function "mod" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are SIGNED vectors. + + -- Id: A.35 + function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an UNSIGNED vector and R + -- is a nonnegative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.36 + function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where R is an UNSIGNED vector and L + -- is a nonnegative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.37 + function "mod" (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is a SIGNED vector and + -- R is an INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.38 + function "mod" (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an INTEGER and + -- R is a SIGNED vector. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.40 + function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.41 + function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.42 + function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + --============================================================================ + -- Comparison Operators + --============================================================================ + + -- Id: C.1 + function ">" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.2 + function ">" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.3 + function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.4 + function ">" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a INTEGER and + -- R is a SIGNED vector. + + -- Id: C.5 + function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.6 + function ">" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a SIGNED vector and + -- R is a INTEGER. + + --============================================================================ + + -- Id: C.7 + function "<" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.8 + function "<" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.9 + function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.10 + function "<" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.11 + function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.12 + function "<" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.13 + function "<=" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.14 + function "<=" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.15 + function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.16 + function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.17 + function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.18 + function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.19 + function ">=" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.20 + function ">=" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.21 + function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.22 + function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.23 + function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.24 + function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.25 + function "=" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.26 + function "=" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.27 + function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.28 + function "=" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.29 + function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.30 + function "=" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.31 + function "/=" (L, R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.32 + function "/=" (L, R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.33 + function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.34 + function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.35 + function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.36 + function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the lesser of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.38 + function MINIMUM (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the lesser of two SIGNED vectors that may be + -- of different lengths. + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the lesser of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.40 + function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the lesser of an INTEGER, L, and a SIGNED + -- vector, R. + + -- Id: C.41 + function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the lesser of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + -- Id: C.42 + function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the lesser of a SIGNED vector, L, and + -- an INTEGER, R. + + --============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the greater of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.44 + function MAXIMUM (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the greater of two SIGNED vectors that may be + -- of different lengths. + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the greater of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.46 + function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the greater of an INTEGER, L, and a SIGNED + -- vector, R. + + -- Id: C.47 + function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED + -- Result: Returns the greater of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + -- Id: C.48 + function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED; + -- Result subtype: SIGNED + -- Result: Returns the greater of a SIGNED vector, L, and + -- an INTEGER, R. + + --============================================================================ + + -- Id: C.49 + function "?>" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.50 + function "?>" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.51 + function "?>" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.52 + function "?>" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is a INTEGER and + -- R is a SIGNED vector. + + -- Id: C.53 + function "?>" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.54 + function "?>" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is a SIGNED vector and + -- R is a INTEGER. + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.56 + function "?<" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.57 + function "?<" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.58 + function "?<" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.59 + function "?<" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.60 + function "?<" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.62 + function "?<=" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.63 + function "?<=" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.64 + function "?<=" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.65 + function "?<=" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.66 + function "?<=" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.68 + function "?>=" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.69 + function "?>=" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.70 + function "?>=" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is an INTEGER and + -- R is a SIGNED vector. + + -- Id: C.71 + function "?>=" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.72 + function "?>=" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is a SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.74 + function "?=" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.75 + function "?=" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.76 + function "?=" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is an INTEGER and + -- R is an SIGNED vector. + + -- Id: C.77 + function "?=" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.78 + function "?=" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is an SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.80 + function "?/=" (L, R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L and R are SIGNED vectors possibly + -- of different lengths. + + -- Id: C.81 + function "?/=" (L : NATURAL; R : UNSIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.82 + function "?/=" (L : INTEGER; R : SIGNED) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is an INTEGER and + -- R is an SIGNED vector. + + -- Id: C.83 + function "?/=" (L : UNSIGNED; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.84 + function "?/=" (L : SIGNED; R : INTEGER) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is an SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + -- Shift and Rotate Functions + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with Bit '0'. + -- The COUNT leftmost bits are lost. + + -- Id: S.2 + function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with Bit '0'. + -- The COUNT rightmost bits are lost. + + -- Id: S.3 + function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on a SIGNED vector COUNT times. + -- The vacated positions are filled with Bit '0'. + -- The COUNT leftmost bits are lost. + + -- Id: S.4 + function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on a SIGNED vector COUNT times. + -- The vacated positions are filled with the leftmost bit, ARG'LEFT. + -- The COUNT rightmost bits are lost. + + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times. + + -- Id: S.6 + function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times. + + -- Id: S.7 + function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a logical rotate-left of a SIGNED vector COUNT times. + + -- Id: S.8 + function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a logical rotate-right of a SIGNED vector COUNT times. + + --============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.9 + function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.10 + function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.11 + function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.12 + function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT)) + + ------------------------------------------------------------------------------ + -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.13 + function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.14 + function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.15 + function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.16 + function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.18 + function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.20 + function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; + -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + --============================================================================ + -- RESIZE Functions + --============================================================================ + + -- Id: R.1 + function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED; + -- Result subtype: SIGNED(NEW_SIZE-1 downto 0) + -- Result: Resizes the SIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with the sign bit (ARG'LEFT). When truncating, + -- the sign bit is retained along with the rightmost part. + + -- Id: R.2 + function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0) + -- Result: Resizes the UNSIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with '0'. When truncating, the leftmost bits + -- are dropped. + + function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0) + + function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED; + -- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Conversion Functions + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : UNSIGNED) return NATURAL; + -- Result subtype: NATURAL. Value cannot be negative since parameter is an + -- UNSIGNED vector. + -- Result: Converts the UNSIGNED vector to an INTEGER. + + -- Id: D.2 + function TO_INTEGER (ARG : SIGNED) return INTEGER; + -- Result subtype: INTEGER + -- Result: Converts a SIGNED vector to an INTEGER. + + -- Id: D.3 + function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED; + -- Result subtype: UNSIGNED(SIZE-1 downto 0) + -- Result: Converts a nonnegative INTEGER to an UNSIGNED vector with + -- the specified size. + + -- Id: D.4 + function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED; + -- Result subtype: SIGNED(SIZE-1 downto 0) + -- Result: Converts an INTEGER to a SIGNED vector of the specified size. + + function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0) + + function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Logical Operators + --============================================================================ + + -- Id: L.1 + function "not" (L : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Termwise inversion + + -- Id: L.2 + function "and" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector AND operation + + -- Id: L.3 + function "or" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector OR operation + + -- Id: L.4 + function "nand" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NAND operation + + -- Id: L.5 + function "nor" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NOR operation + + -- Id: L.6 + function "xor" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.7 + function "xnor" (L, R : UNSIGNED) return UNSIGNED; + -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XNOR operation + + -- Id: L.8 + function "not" (L : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Termwise inversion + + -- Id: L.9 + function "and" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector AND operation + + -- Id: L.10 + function "or" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector OR operation + + -- Id: L.11 + function "nand" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NAND operation + + -- Id: L.12 + function "nor" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NOR operation + + -- Id: L.13 + function "xor" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.14 + function "xnor" (L, R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XNOR operation + + -- Id: L.15 + function "and" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector AND operation + + -- Id: L.16 + function "and" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar AND operation + + -- Id: L.17 + function "or" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector OR operation + + -- Id: L.18 + function "or" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar OR operation + + -- Id: L.19 + function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NAND operation + + -- Id: L.20 + function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NAND operation + + -- Id: L.21 + function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NOR operation + + -- Id: L.22 + function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NOR operation + + -- Id: L.23 + function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XOR operation + + -- Id: L.24 + function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.25 + function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.26 + function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XNOR operation + + -- Id: L.27 + function "and" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector AND operation + + -- Id: L.28 + function "and" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar AND operation + + -- Id: L.29 + function "or" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector OR operation + + -- Id: L.30 + function "or" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar OR operation + + -- Id: L.31 + function "nand" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NAND operation + + -- Id: L.32 + function "nand" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NAND operation + + -- Id: L.33 + function "nor" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NOR operation + + -- Id: L.34 + function "nor" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NOR operation + + -- Id: L.35 + function "xor" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XOR operation + + -- Id: L.36 + function "xor" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.37 + function "xnor" (L : BIT; R : SIGNED) return SIGNED; + -- Result subtype: SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.38 + function "xnor" (L : SIGNED; R : BIT) return SIGNED; + -- Result subtype: SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.39 + function "and" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of and'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.40 + function "nand" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of nand'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.41 + function "or" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of or'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.42 + function "nor" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of nor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.43 + function "xor" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of xor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.44 + function "xnor" (L : SIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of xnor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.45 + function "and" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of and'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.46 + function "nand" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of nand'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.47 + function "or" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of or'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.48 + function "nor" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of nor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.49 + function "xor" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of xor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.50 + function "xnor" (L : UNSIGNED) return BIT; + -- Result subtype: BIT. + -- Result: Result of xnor'ing all of the bits of the vector. + + --============================================================================ + -- Edge Detection Functions + --============================================================================ + + -- Id: E.1 + alias RISING_EDGE is STD.STANDARD.RISING_EDGE + [STD.STANDARD.BIT return STD.STANDARD.BOOLEAN]; + -- Result subtype: BOOLEAN + -- Result: Returns TRUE if an event is detected on signal S and the + -- value changed from a '0' to a '1'. + + -- Id: E.2 + alias FALLING_EDGE is STD.STANDARD.FALLING_EDGE + [STD.STANDARD.BIT return STD.STANDARD.BOOLEAN]; + -- Result subtype: BOOLEAN + -- Result: Returns TRUE if an event is detected on signal S and the + -- value changed from a '1' to a '0'. + + --============================================================================ + -- string conversion and write operations + --============================================================================ + -- the following operations are predefined + + -- FUNCTION to_string ( value : UNSIGNED ) RETURN string; + -- FUNCTION to_string ( value : SIGNED ) RETURN string; + + -- explicitly defined operations + + alias to_bstring is to_string [UNSIGNED return STRING]; + alias to_bstring is to_string [SIGNED return STRING]; + alias to_binary_string is to_string [UNSIGNED return STRING]; + alias to_binary_string is to_string [SIGNED return STRING]; + + function to_ostring (value : UNSIGNED) return STRING; + function to_ostring (value : SIGNED) return STRING; + alias to_octal_string is to_ostring [UNSIGNED return STRING]; + alias to_octal_string is to_ostring [SIGNED return STRING]; + + function to_hstring (value : UNSIGNED) return STRING; + function to_hstring (value : SIGNED) return STRING; + alias to_hex_string is to_hstring [UNSIGNED return STRING]; + alias to_hex_string is to_hstring [SIGNED return STRING]; + + procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN); + + procedure READ(L : inout LINE; VALUE : out UNSIGNED); + + procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN); + + procedure READ(L : inout LINE; VALUE : out SIGNED); + + procedure WRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure WRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias BREAD is READ [LINE, UNSIGNED, BOOLEAN]; + alias BREAD is READ [LINE, SIGNED, BOOLEAN]; + + alias BREAD is READ [LINE, UNSIGNED]; + alias BREAD is READ [LINE, SIGNED]; + + alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN]; + alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN]; + + alias BINARY_READ is READ [LINE, UNSIGNED]; + alias BINARY_READ is READ [LINE, SIGNED]; + + procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN); + procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN); + + procedure OREAD (L : inout LINE; VALUE : out UNSIGNED); + procedure OREAD (L : inout LINE; VALUE : out SIGNED); + + alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN]; + + alias OCTAL_READ is OREAD [LINE, UNSIGNED]; + alias OCTAL_READ is OREAD [LINE, SIGNED]; + + procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN); + procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN); + + procedure HREAD (L : inout LINE; VALUE : out UNSIGNED); + procedure HREAD (L : inout LINE; VALUE : out SIGNED); + + alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN]; + alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN]; + + alias HEX_READ is HREAD [LINE, UNSIGNED]; + alias HEX_READ is HREAD [LINE, SIGNED]; + + alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH]; + alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH]; + + alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH]; + alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH]; + + procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure OWRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH]; + alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH]; + + procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure HWRITE (L : inout LINE; VALUE : in SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH]; + alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH]; + +end package NUMERIC_BIT; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned-body.vhdl new file mode 100644 index 0000000..347eb70 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned-body.vhdl @@ -0,0 +1,592 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_BIT_UNSIGNED package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Values of type BIT_VECTOR +-- : are interpreted as unsigned numbers in vector form. +-- : The leftmost bit is treated as the most significant bit. +-- : This package contains overloaded arithmetic operators on +-- : the BIT_VECTOR type. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library ieee; +use ieee.numeric_bit.all; + +package body NUMERIC_BIT_UNSIGNED is + + -- Id: A.3 + function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) + UNSIGNED(R)); + end function "+"; + + -- Id: A.3R + function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) + R); + end function "+"; + + -- Id: A.3L + function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L + UNSIGNED(R)); + end function "+"; + + -- Id: A.5 + function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) + R); + end function "+"; + + -- Id: A.6 + function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L + UNSIGNED(R)); + end function "+"; + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) - UNSIGNED(R)); + end function "-"; + + -- Id: A.9R + function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) - R); + end function "-"; + + -- Id: A.9L + function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L - UNSIGNED(R)); + end function "-"; + + -- Id: A.11 + function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) - R); + end function "-"; + + -- Id: A.12 + function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L - UNSIGNED(R)); + end function "-"; + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) * UNSIGNED(R)); + end function "*"; + + -- Id: A.17 + function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) * R); + end function "*"; + + -- Id: A.18 + function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L * UNSIGNED(R)); + end function "*"; + + --============================================================================ + + -- Id: A.21 + function "/" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) / UNSIGNED(R)); + end function "/"; + + -- Id: A.23 + function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) / R); + end function "/"; + + -- Id: A.24 + function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L / UNSIGNED(R)); + end function "/"; + + --============================================================================ + + -- Id: A.27 + function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) rem UNSIGNED(R)); + end function "rem"; + + -- Id: A.29 + function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) rem R); + end function "rem"; + + -- Id: A.30 + function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L rem UNSIGNED(R)); + end function "rem"; + + --============================================================================ + + -- Id: A.33 + function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) mod UNSIGNED(R)); + end function "mod"; + + -- Id: A.35 + function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(L) mod R); + end function "mod"; + + -- Id: A.36 + function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (L mod UNSIGNED(R)); + end function "mod"; + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is + begin + return find_leftmost(UNSIGNED(ARG), Y); + end function find_leftmost; + + -- Id: A.41 + function find_rightmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is + begin + return find_rightmost(UNSIGNED(ARG), Y); + end function find_rightmost; + + --============================================================================ + -- Id: C.1 + function ">" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) > UNSIGNED(R); + end function ">"; + + -- Id: C.3 + function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L > UNSIGNED(R); + end function ">"; + + -- Id: C.5 + function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) > R; + end function ">"; + + --============================================================================ + -- Id: C.7 + function "<" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) < UNSIGNED(R); + end function "<"; + + -- Id: C.9 + function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L < UNSIGNED(R); + end function "<"; + + -- Id: C.11 + function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) < R; + end function "<"; + + --============================================================================ + -- Id: C.13 + function "<=" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) <= UNSIGNED(R); + end function "<="; + + -- Id: C.15 + function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L <= UNSIGNED(R); + end function "<="; + + -- Id: C.17 + function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) <= R; + end function "<="; + + --============================================================================ + -- Id: C.19 + function ">=" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) >= UNSIGNED(R); + end function ">="; + + -- Id: C.21 + function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L >= UNSIGNED(R); + end function ">="; + + -- Id: C.23 + function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) >= R; + end function ">="; + + --============================================================================ + -- Id: C.25 + function "=" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) = UNSIGNED(R); + end function "="; + + -- Id: C.27 + function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L = UNSIGNED(R); + end function "="; + + -- Id: C.29 + function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) = R; + end function "="; + + --============================================================================ + -- Id: C.31 + function "/=" (L, R : BIT_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) /= UNSIGNED(R); + end function "/="; + + -- Id: C.33 + function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is + begin + return L /= UNSIGNED(R); + end function "/="; + + -- Id: C.35 + function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) /= R; + end function "/="; + + --============================================================================ + -- Id: C.37 + function MINIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R))); + end function MINIMUM; + + -- Id: C.39 + function MINIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (MINIMUM(L, UNSIGNED(R))); + end function MINIMUM; + + -- Id: C.41 + function MINIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (MINIMUM(UNSIGNED(L), R)); + end function MINIMUM; + + --============================================================================ + -- Id: C.43 + function MAXIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R))); + end function MAXIMUM; + + -- Id: C.45 + function MAXIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR (MAXIMUM(L, UNSIGNED(R))); + end function MAXIMUM; + + -- Id: C.47 + function MAXIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (MAXIMUM(UNSIGNED(L), R)); + end function MAXIMUM; + + --============================================================================ + + -- Id: C.49 + function "?>" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?> UNSIGNED(R); + end function "?>"; + + -- Id: C.51 + function "?>" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?> UNSIGNED(R); + end function "?>"; + + -- Id: C.53 + function "?>" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?> R; + end function "?>"; + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?< UNSIGNED(R); + end function "?<"; + + -- Id: C.57 + function "?<" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?< UNSIGNED(R); + end function "?<"; + + -- Id: C.59 + function "?<" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?< R; + end function "?<"; + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?<= UNSIGNED(R); + end function "?<="; + + -- Id: C.63 + function "?<=" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?<= UNSIGNED(R); + end function "?<="; + + -- Id: C.65 + function "?<=" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?<= R; + end function "?<="; + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?>= UNSIGNED(R); + end function "?>="; + + -- Id: C.69 + function "?>=" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?>= UNSIGNED(R); + end function "?>="; + + -- Id: C.71 + function "?>=" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?>= R; + end function "?>="; + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?= UNSIGNED(R); + end function "?="; + + -- Id: C.75 + function "?=" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?= UNSIGNED(R); + end function "?="; + + -- Id: C.77 + function "?=" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?= R; + end function "?="; + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R: BIT_VECTOR) return BIT is + begin + return UNSIGNED(L) ?/= UNSIGNED(R); + end function "?/="; + + -- Id: C.81 + function "?/=" (L: NATURAL; R: BIT_VECTOR) return BIT is + begin + return L ?/= UNSIGNED(R); + end function "?/="; + + -- Id: C.83 + function "?/=" (L: BIT_VECTOR; R: NATURAL) return BIT is + begin + return UNSIGNED(L) ?/= R; + end function "?/="; + + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (shift_left (ARG => UNSIGNED(ARG), + COUNT => COUNT)); + end function SHIFT_LEFT; + + -- Id: S.2 + function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (shift_right (ARG => UNSIGNED(ARG), + COUNT => COUNT)); + end function SHIFT_RIGHT; + + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (rotate_left (ARG => UNSIGNED(ARG), + COUNT => COUNT)); + end function ROTATE_LEFT; + + -- Id: S.6 + function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (rotate_right (ARG => UNSIGNED(ARG), + COUNT => COUNT)); + end function ROTATE_RIGHT; + + --============================================================================ + + -- Id: S.9 + function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) sll COUNT); + end function "sll"; + + -- Id: S.11 + function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) srl COUNT); + end function "srl"; + + -- Id: S.13 + function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) rol COUNT); + end function "rol"; + + -- Id: S.15 + function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) ror COUNT); + end function "ror"; + + -- Id: S.17 + function "sla" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) sla COUNT); + end function "sla"; + + -- Id: S.19 + function "sra" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is + begin + return BIT_VECTOR (UNSIGNED(ARG) sra COUNT); + end function "sra"; + + --============================================================================ + + -- Id: R.2 + function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR ( + resize (arg => UNSIGNED(ARG), + NEW_SIZE => NEW_SIZE)); + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR is + begin + return BIT_VECTOR ( + RESIZE (ARG => UNSIGNED(ARG), + NEW_SIZE => SIZE_RES'length)); + end function RESIZE; + + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL is + begin + return TO_INTEGER (UNSIGNED(ARG)); + end function TO_INTEGER; + + -- Id: D.3 + function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR is + begin + return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE)); + end function To_BitVector; + + function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR) + return BIT_VECTOR is + begin + return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE_RES'length)); + end function To_BitVector; + +end package body NUMERIC_BIT_UNSIGNED; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned.vhdl new file mode 100644 index 0000000..55516cf --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned.vhdl @@ -0,0 +1,623 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_BIT_UNSIGNED package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Values of type BIT_VECTOR +-- : are interpreted as unsigned numbers in vector form. +-- : The leftmost bit is treated as the most significant bit. +-- : This package contains overloaded arithmetic operators on +-- : the BIT_VECTOR type. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +package NUMERIC_BIT_UNSIGNED is + constant CopyRightNotice : STRING := + "Copyright 2008 IEEE. All rights reserved."; + + -- Id: A.3 + function "+" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0). + -- Result: Adds two UNSIGNED vectors that may be of different lengths. + + -- Id: A.3R + function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Similar to A.3 where R is a one bit bit_vector + + -- Id: A.3L + function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Similar to A.3 where L is a one bit UNSIGNED + + -- Id: A.5 + function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0). + -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R. + + -- Id: A.6 + function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0). + -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R. + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0). + -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. + + -- Id: A.9R + function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Similar to A.9 where R is a one bit UNSIGNED + + -- Id: A.9L + function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Similar to A.9 where L is a one bit UNSIGNED + + -- Id: A.11 + function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0). + -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L. + + -- Id: A.12 + function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0). + -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L. + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0). + -- Result: Performs the multiplication operation on two UNSIGNED vectors + -- that may possibly be of different lengths. + + -- Id: A.17 + function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0). + -- Result: Multiplies an UNSIGNED vector, L, with a non-negative + -- INTEGER, R. R is converted to an UNSIGNED vector of + -- SIZE L'LENGTH before multiplication. + + -- Id: A.18 + function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0). + -- Result: Multiplies an UNSIGNED vector, R, with a non-negative + -- INTEGER, L. L is converted to an UNSIGNED vector of + -- SIZE R'LENGTH before multiplication. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "/" operator, a severity level + -- of ERROR is issued. + + -- Id: A.21 + function "/" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. + + -- Id: A.23 + function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.24 + function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "rem" operator, a severity level + -- of ERROR is issued. + + -- Id: A.27 + function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. + + -- Id: A.29 + function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a + -- non-negative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.30 + function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a + -- non-negative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "mod" operator, a severity level + -- of ERROR is issued. + + -- Id: A.33 + function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. + + -- Id: A.35 + function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an UNSIGNED vector and R + -- is a non-negative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.36 + function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: bit_vector(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where R is an UNSIGNED vector and L + -- is a non-negative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.41 + function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + --============================================================================ + -- Comparison Operators + --============================================================================ + -- Id: C.1 + function ">" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.3 + function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.5 + function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + -- Id: C.7 + function "<" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.9 + function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.11 + function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + -- Id: C.13 + function "<=" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.15 + function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.17 + function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + -- Id: C.19 + function ">=" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.21 + function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.23 + function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + -- Id: C.25 + function "=" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.27 + function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.29 + function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.31 + function "/=" (L, R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.33 + function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.35 + function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the lesser of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the lesser of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.41 + function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the lesser of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + --============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the greater of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the greater of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.47 + function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR + -- Result: Returns the greater of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + --============================================================================ + -- Id: C.49 + function "?>" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.51 + function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.53 + function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.57 + function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.59 + function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.63 + function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.65 + function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.69 + function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.71 + function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.75 + function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.77 + function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.81 + function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.83 + function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT; + -- Result subtype: BIT + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + -- Shift and Rotate Functions + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times. + + -- Id: S.6 + function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times. + + + --============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.9 + function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.11 + function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.13 + function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.15 + function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + + --============================================================================ + -- RESIZE Functions + --============================================================================ + + -- Id: R.2 + function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(NEW_SIZE-1 downto 0) + -- Result: Resizes the UNSIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with '0'. When truncating, the leftmost bits + -- are dropped. + + function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR; + -- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Conversion Functions + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL; + -- Result subtype: NATURAL. Value cannot be negative since parameter is an + -- UNSIGNED vector. + -- Result: Converts the UNSIGNED vector to an INTEGER. + + -- Id: D.3 + function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR; + -- Result subtype: bit_vector(SIZE-1 downto 0) + -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with + -- the specified size. + + function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR) + return BIT_VECTOR; + -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0) + +-- begin LCS-2006-130 + alias To_Bit_Vector is + To_BitVector[NATURAL, NATURAL return BIT_VECTOR]; + alias To_BV is + To_BitVector[NATURAL, NATURAL return BIT_VECTOR]; + + alias To_Bit_Vector is + To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR]; + alias To_BV is + To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR]; + +end package NUMERIC_BIT_UNSIGNED; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std-body.vhdl new file mode 100644 index 0000000..18ddfa7 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std-body.vhdl @@ -0,0 +1,4459 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_STD package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC Synthesis Working Group, +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Two numeric types are defined: +-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number +-- : in vector form +-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number +-- : in vector form +-- : The base element type is type STD_ULOGIC. +-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types +-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. +-- : Two numeric subtypes are defined: +-- : -- > UNSIGNED: represents UNSIGNED number in vector form +-- : -- > SIGNED: represents a SIGNED number in vector form +-- : The element subtypes are the same subtype as STD_LOGIC. +-- : The leftmost bit is treated as the most significant bit. +-- : Signed vectors are represented in two's complement form. +-- : This package contains overloaded arithmetic operators on +-- : the SIGNED and UNSIGNED types. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1.4 $ +-- $Date: 2015/08/13 10:28:07 $ +-- -------------------------------------------------------------------- + +package body NUMERIC_STD is + + -- null range array constants + + constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0'); + constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0'); + + -- implementation controls + + constant NO_WARNING : BOOLEAN := false; -- default to emit warnings + + -- =========================Local Subprograms ================================= + + function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is + variable NBITS : NATURAL; + variable N : NATURAL; + begin + if ARG >= 0 then + N := ARG; + else + N := -(ARG+1); + end if; + NBITS := 1; + while N > 0 loop + NBITS := NBITS+1; + N := N / 2; + end loop; + return NBITS; + end function SIGNED_NUM_BITS; + + function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is + variable NBITS : NATURAL; + variable N : NATURAL; + begin + N := ARG; + NBITS := 1; + while N > 1 loop + NBITS := NBITS+1; + N := N / 2; + end loop; + return NBITS; + end function UNSIGNED_NUM_BITS; + + ------------------------------------------------------------------------ + + -- this internal function computes the addition of two UNRESOLVED_UNSIGNED + -- with input CARRY + -- * the two arguments are of the same length + + function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC) + return UNRESOLVED_UNSIGNED + is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R; + variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable CBIT : STD_LOGIC := C; + begin + for I in 0 to L_LEFT loop + RESULT(I) := CBIT xor XL(I) xor XR(I); + CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); + end loop; + return RESULT; + end function ADD_UNSIGNED; + + -- this internal function computes the addition of two UNRESOLVED_SIGNED + -- with input CARRY + -- * the two arguments are of the same length + + function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC) + return UNRESOLVED_SIGNED + is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R; + variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable CBIT : STD_LOGIC := C; + begin + for I in 0 to L_LEFT loop + RESULT(I) := CBIT xor XL(I) xor XR(I); + CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); + end loop; + return RESULT; + end function ADD_SIGNED; + + ----------------------------------------------------------------------------- + + -- this internal procedure computes UNSIGNED division + -- giving the quotient and remainder. + procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED; + XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is + variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0); + variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 + downto 0); + alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; + variable TOPBIT : INTEGER; + begin + TEMP := "0"&NUM; + QUOT := (others => '0'); + TOPBIT := -1; + for J in DENOM'range loop + if DENOM(J) = '1' then + TOPBIT := J; + exit; + end if; + end loop; + assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero" + severity error; + + for J in NUM'length-(TOPBIT+1) downto 0 loop + if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then + TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) + -("0"&DENOM(TOPBIT downto 0)); + QUOT(J) := '1'; + end if; + assert TEMP(TOPBIT+J+1) = '0' + report "NUMERIC_STD.DIVMOD: internal error in the division algorithm" + severity error; + end loop; + XQUOT := RESIZE(QUOT, XQUOT'length); + XREMAIN := RESIZE(TEMP, XREMAIN'length); + end procedure DIVMOD; + + -----------------Local Subprograms - shift/rotate ops------------------------- + + function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR + is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT: variable is "SLL" ; + begin + if COUNT <= ARG_L then + RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); + end if; + return RESULT; + end function XSLL; + + function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR + is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "SRL" ; + begin + if COUNT <= ARG_L then + RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); + end if; + return RESULT; + end function XSRL; + + function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR + is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0); + variable XCOUNT : NATURAL := COUNT; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "SRA" ; + begin + if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; + else + if (XCOUNT > ARG_L) then XCOUNT := ARG_L; + end if; + RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); + RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); + end if; + return RESULT; + end function XSRA; + + function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR + is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; + variable COUNTM : INTEGER; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "ROL" ; + begin + COUNTM := COUNT mod (ARG_L + 1); + if COUNTM /= 0 then + RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); + RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); + end if; + return RESULT; + end function XROL; + + function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR + is + constant ARG_L : INTEGER := ARG'length-1; + alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; + variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; + variable COUNTM : INTEGER; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "ROR" ; + begin + COUNTM := COUNT mod (ARG_L + 1); + if COUNTM /= 0 then + RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); + RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); + end if; + return RESULT; + end function XROR; + + -----------------Local Subprograms - Relational ops--------------------------- + + -- + -- General "=" for UNRESOLVED_UNSIGNED vectors, same length + -- + function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + begin + return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); + end function UNSIGNED_EQUAL; + + -- + -- General "=" for UNRESOLVED_SIGNED vectors, same length + -- + function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + begin + return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); + end function SIGNED_EQUAL; + + -- + -- General "<" for UNRESOLVED_UNSIGNED vectors, same length + -- + function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R); + end function UNSIGNED_LESS; + + -- + -- General "<" function for UNRESOLVED_SIGNED vectors, same length + -- + function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); + variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + INTERN_L := L; + INTERN_R := R; + INTERN_L(0) := not INTERN_L(0); + INTERN_R(0) := not INTERN_R(0); + return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R); + end function SIGNED_LESS; + + -- + -- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length + -- + function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED) + return BOOLEAN is + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R); + end function UNSIGNED_LESS_OR_EQUAL; + + -- + -- General "<=" function for UNRESOLVED_SIGNED vectors, same length + -- + function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + -- Need aliases to assure index direction + variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); + variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + INTERN_L := L; + INTERN_R := R; + INTERN_L(0) := not INTERN_L(0); + INTERN_R(0) := not INTERN_R(0); + return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R); + end function SIGNED_LESS_OR_EQUAL; + + -- =========================Exported Functions ========================== + + -- Id: A.1 + function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0); + -- Synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "ABS" ; + begin + if ARG'length < 1 then return NAS; + end if; + RESULT := TO_01(XARG, 'X'); + if (RESULT(RESULT'left) = 'X') then return RESULT; + end if; + if RESULT(RESULT'left) = '1' then + RESULT := -RESULT; + end if; + return RESULT; + end function "abs"; + + -- Id: A.2 + function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0); + variable CBIT : STD_LOGIC := '1'; + -- Synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute IS_SIGNED of RESULT:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "UMINUS" ; + begin + if ARG'length < 1 then return NAS; + end if; + XARG01 := TO_01(ARG, 'X'); + if (XARG01(XARG01'left) = 'X') then return XARG01; + end if; + for I in 0 to RESULT'left loop + RESULT(I) := not(XARG01(I)) xor CBIT; + CBIT := CBIT and not(XARG01(I)); + end loop; + return RESULT; + end function "-"; + + -- ============================================================================ + + -- Id: A.3 + function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of L01:variable is "ADD" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + return ADD_UNSIGNED(L01, R01, '0'); + end function "+"; + + -- Id: A.3R + function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED + is + variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L + XR); + end function "+"; + + -- Id: A.3L + function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED + is + variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL + R); + end function "+"; + + -- Id: A.4 + function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of L01:variable is TRUE ; + attribute SYNTHESIS_RETURN of L01:variable is "ADD" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + return ADD_SIGNED(L01, R01, '0'); + end function "+"; + + -- Id: A.4R + function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED + is + variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L + XR); + end function "+"; + + -- Id: A.4L + function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED + is + variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL + R); + end function "+"; + + -- Id: A.5 + function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + return L + TO_UNSIGNED(R, L'length); + end function "+"; + + -- Id: A.6 + function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) + R; + end function "+"; + + -- Id: A.7 + function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED is + begin + return L + TO_SIGNED(R, L'length); + end function "+"; + + -- Id: A.8 + function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return TO_SIGNED(L, R'length) + R; + end function "+"; + + -- ============================================================================ + + -- Id: A.9 + function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of L01:variable is "SUB" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + return ADD_UNSIGNED(L01, not(R01), '1'); + end function "-"; + + -- Id: A.9R + function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED + is + variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L - XR); + end function "-"; + + -- Id: A.9L + function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED + is + variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL - R); + end function "-"; + + -- Id: A.10 + function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of L01:variable is TRUE ; + attribute SYNTHESIS_RETURN of L01:variable is "SUB" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + return ADD_SIGNED(L01, not(R01), '1'); + end function "-"; + + -- Id: A.10R + function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED + is + variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); + begin + XR(0) := R; + return (L - XR); + end function "-"; + + -- Id: A.10L + function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED + is + variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); + begin + XL(0) := L; + return (XL - R); + end function "-"; + + -- Id: A.11 + function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + return L - TO_UNSIGNED(R, L'length); + end function "-"; + + -- Id: A.12 + function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) - R; + end function "-"; + + -- Id: A.13 + function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is + begin + return L - TO_SIGNED(R, L'length); + end function "-"; + + -- Id: A.14 + function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + begin + return TO_SIGNED(L, R'length) - R; + end function "-"; + + -- ============================================================================ + + -- Id: A.15 + function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) := + (others => '0'); + variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "MULT" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + RESULT := (others => 'X'); + return RESULT; + end if; + ADVAL := RESIZE(XR, RESULT'length); + for I in 0 to L_LEFT loop + if XL(I) = '1' then RESULT := RESULT + ADVAL; + end if; + ADVAL := SHIFT_LEFT(ADVAL, 1); + end loop; + return RESULT; + end function "*"; + + -- Id: A.16 + function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); + variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) := + (others => '0'); + variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0); + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "MULT" ; + begin + if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; + end if; + XL := TO_01(L, 'X'); + XR := TO_01(R, 'X'); + if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then + RESULT := (others => 'X'); + return RESULT; + end if; + ADVAL := RESIZE(XR, RESULT'length); + for I in 0 to L_LEFT-1 loop + if XL(I) = '1' then RESULT := RESULT + ADVAL; + end if; + ADVAL := SHIFT_LEFT(ADVAL, 1); + end loop; + if XL(L_LEFT) = '1' then + RESULT := RESULT - ADVAL; + end if; + return RESULT; + end function "*"; + + -- Id: A.17 + function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + return L * TO_UNSIGNED(R, L'length); + end function "*"; + + -- Id: A.18 + function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return TO_UNSIGNED(L, R'length) * R; + end function "*"; + + -- Id: A.19 + function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED is + begin + return L * TO_SIGNED(R, L'length); + end function "*"; + + -- Id: A.20 + function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + begin + return TO_SIGNED(L, R'length) * R; + end function "*"; + + -- ============================================================================ + + -- Id: A.21 + function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of FQUOT:variable is "DIV" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + FQUOT := (others => 'X'); + return FQUOT; + end if; + DIVMOD(XL, XR, FQUOT, FREMAIN); + return FQUOT; + end function "/"; + + -- Id: A.22 + function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable QNEG : BOOLEAN := false; + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of FQUOT:variable is TRUE ; + attribute SYNTHESIS_RETURN of FQUOT:variable is "DIV" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + FQUOT := (others => 'X'); + return UNRESOLVED_SIGNED(FQUOT); + end if; + if XL(XL'left) = '1' then + XNUM := UNRESOLVED_UNSIGNED(-XL); + QNEG := true; + else + XNUM := UNRESOLVED_UNSIGNED(XL); + end if; + if XR(XR'left) = '1' then + XDENOM := UNRESOLVED_UNSIGNED(-XR); + QNEG := not QNEG; + else + XDENOM := UNRESOLVED_UNSIGNED(XR); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if QNEG then FQUOT := "0"-FQUOT; + end if; + return UNRESOLVED_SIGNED(FQUOT); + end function "/"; + + -- Id: A.23 + function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED + is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (L'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "DIV" ; + begin + if (L'length < 1) then return NAU; + end if; + if (R_LENGTH > L'length) then + QUOT := (others => '0'); + return RESIZE(QUOT, L'length); + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + QUOT := RESIZE((L / XR), QUOT'length); + return RESIZE(QUOT, L'length); + end function "/"; + + -- Id: A.24 + function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED + is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (R'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "DIV" ; + begin + if (R'length < 1) then return NAU; + end if; + XL := TO_UNSIGNED(L, L_LENGTH); + QUOT := RESIZE((XL / R), QUOT'length); + if L_LENGTH > R'length and QUOT(0) /= 'X' + and QUOT(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" + severity warning; + end if; + return RESIZE(QUOT, R'length); + end function "/"; + + -- Id: A.25 + function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (L'LENGTH-1 downto 0) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "DIV" ; + begin + if (L'length < 1) then return NAS; + end if; + if (R_LENGTH > L'length) then + QUOT := (others => '0'); + return RESIZE(QUOT, L'length); + end if; + XR := TO_SIGNED(R, R_LENGTH); + QUOT := RESIZE((L / XR), QUOT'length); + return RESIZE(QUOT, L'length); + end function "/"; + + -- Id: A.26 + function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (R'LENGTH-1 downto 0) ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "DIV" ; + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + QUOT := RESIZE((XL / R), QUOT'length); + if L_LENGTH > R'length and QUOT(0) /= 'X' + and QUOT(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) + then + assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" + severity warning; + end if; + return RESIZE(QUOT, R'length); + end function "/"; + + -- ============================================================================ + + -- Id: A.27 + function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of FREMAIN:variable is "REM" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + FREMAIN := (others => 'X'); + return FREMAIN; + end if; + DIVMOD(XL, XR, FQUOT, FREMAIN); + return FREMAIN; + end function "rem"; + + -- Id: A.28 + function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable RNEG : BOOLEAN := false; + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of FREMAIN:variable is "REM" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X')); + XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X')); + if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then + FREMAIN := (others => 'X'); + return UNRESOLVED_SIGNED(FREMAIN); + end if; + if XNUM(XNUM'left) = '1' then + XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM)); + RNEG := true; + else + XNUM := UNRESOLVED_UNSIGNED(XNUM); + end if; + if XDENOM(XDENOM'left) = '1' then + XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM)); + else + XDENOM := UNRESOLVED_UNSIGNED(XDENOM); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if RNEG then + FREMAIN := "0"-FREMAIN; + end if; + return UNRESOLVED_SIGNED(FREMAIN); + end function "rem"; + + -- Id: A.29 + function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED + is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (L'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "REM" ; + begin + if (L'length < 1) then return NAU; + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + XREM := L rem XR; + if R_LENGTH > L'length and XREM(0) /= 'X' + and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => '0') + then + assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "rem"; + + -- Id: A.30 + function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED + is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (R'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "REM" ; + begin + XL := TO_UNSIGNED(L, L_LENGTH); + XREM := XL rem R; + if L_LENGTH > R'length and XREM(0) /= 'X' + and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "rem"; + + -- Id: A.31 + function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED + is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (L'LENGTH-1 downto 0) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "REM" ; + begin + if (L'length < 1) then return NAS; + end if; + XR := TO_SIGNED(R, R_LENGTH); + XREM := RESIZE((L rem XR), XREM'length); + if R_LENGTH > L'length and XREM(0) /= 'X' + and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) + then + assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "rem"; + + -- Id: A.32 + function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED + is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (R'LENGTH-1 downto 0) ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "REM" ; + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + XREM := RESIZE((XL rem R), XREM'length); + if L_LENGTH > R'length and XREM(0) /= 'X' + and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) + then + assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "rem"; + + -- ============================================================================ + + -- Id: A.33 + function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of FREMAIN:variable is "MOD" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + FREMAIN := (others => 'X'); + return FREMAIN; + end if; + DIVMOD(XL, XR, FQUOT, FREMAIN); + return FREMAIN; + end function "mod"; + + -- Id: A.34 + function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); + variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); + variable RNEG : BOOLEAN := false; + -- Synthesis directives : + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of FREMAIN:variable is TRUE ; + attribute SYNTHESIS_RETURN of FREMAIN:variable is "MOD" ; + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + XL := TO_01(XXL, 'X'); + XR := TO_01(XXR, 'X'); + if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then + FREMAIN := (others => 'X'); + return UNRESOLVED_SIGNED(FREMAIN); + end if; + if XL(XL'left) = '1' then + XNUM := UNRESOLVED_UNSIGNED(-XL); + else + XNUM := UNRESOLVED_UNSIGNED(XL); + end if; + if XR(XR'left) = '1' then + XDENOM := UNRESOLVED_UNSIGNED(-XR); + RNEG := true; + else + XDENOM := UNRESOLVED_UNSIGNED(XR); + end if; + DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); + if RNEG and L(L'left) = '1' then + FREMAIN := "0"-FREMAIN; + elsif RNEG and FREMAIN /= "0" then + FREMAIN := FREMAIN-XDENOM; + elsif L(L'left) = '1' and FREMAIN /= "0" then + FREMAIN := XDENOM-FREMAIN; + end if; + return UNRESOLVED_SIGNED(FREMAIN); + end function "mod"; + + -- Id: A.35 + function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED + is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); + variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (L'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "MOD" ; + begin + if (L'length < 1) then return NAU; + end if; + XR := TO_UNSIGNED(R, R_LENGTH); + XREM := RESIZE((L mod XR), XREM'length); + if R_LENGTH > L'length and XREM(0) /= 'X' + and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => '0') + then + assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "mod"; + + -- Id: A.36 + function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED + is + constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : UNSIGNED (R'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "MOD" ; + begin + if (R'length < 1) then return NAU; + end if; + XL := TO_UNSIGNED(L, L_LENGTH); + XREM := RESIZE((XL mod R), XREM'length); + if L_LENGTH > R'length and XREM(0) /= 'X' + and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => '0') + then + assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "mod"; + + -- Id: A.37 + function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED + is + constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); + variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (L'LENGTH-1 downto 0) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "MOD" ; + begin + if (L'length < 1) then return NAS; + end if; + XR := TO_SIGNED(R, R_LENGTH); + XREM := RESIZE((L mod XR), XREM'length); + if R_LENGTH > L'length and XREM(0) /= 'X' + and XREM(R_LENGTH-1 downto L'length) + /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) + then + assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, L'length); + end function "mod"; + + -- Id: A.38 + function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED + is + constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); + variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); + -- Synthesis directives : + variable RESULT : SIGNED (R'LENGTH-1 downto 0) ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute IS_SIGNED of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "MOD" ; + begin + if (R'length < 1) then return NAS; + end if; + XL := TO_SIGNED(L, L_LENGTH); + XREM := RESIZE((XL mod R), XREM'length); + if L_LENGTH > R'length and XREM(0) /= 'X' + and XREM(L_LENGTH-1 downto R'length) + /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) + then + assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" + severity warning; + end if; + return RESIZE(XREM, R'length); + end function "mod"; + + -- ============================================================================ + -- Id: A.39 + function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) + return INTEGER is + begin + for INDEX in ARG'range loop + if ARG(INDEX) ?= Y then + return INDEX; + end if; + end loop; + return -1; + end function find_leftmost; + + -- Id: A.40 + function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) + return INTEGER is + begin + for INDEX in ARG'range loop + if ARG(INDEX) ?= Y then + return INDEX; + end if; + end loop; + return -1; + end function find_leftmost; + + -- Id: A.41 + function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) + return INTEGER is + begin + for INDEX in ARG'reverse_range loop + if ARG(INDEX) ?= Y then + return INDEX; + end if; + end loop; + return -1; + end function find_rightmost; + + -- Id: A.42 + function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) + return INTEGER is + begin + for INDEX in ARG'reverse_range loop + if ARG(INDEX) ?= Y then + return INDEX; + end if; + end loop; + return -1; + end function find_rightmost; + + -- ============================================================================ + + -- Id: C.1 + function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function ">"; + + -- Id: C.2 + function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function ">"; + + -- Id: C.3 + function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); + end function ">"; + + -- Id: C.4 + function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); + end function ">"; + + -- Id: C.5 + function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return false; + end if; + return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); + end function ">"; + + -- Id: C.6 + function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GT" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); + end function ">"; + + -- ============================================================================ + + -- Id: C.7 + function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "<"; + + -- Id: C.8 + function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "<"; + + -- Id: C.9 + function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); + end function "<"; + + -- Id: C.10 + function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return SIGNED_LESS(TO_SIGNED(L, R01'length), R01); + end function "<"; + + -- Id: C.11 + function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); + end function "<"; + + -- Id: C.12 + function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LT" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<"": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); + end function "<"; + + -- ============================================================================ + + -- Id: C.13 + function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "<="; + + -- Id: C.14 + function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "<="; + + -- Id: C.15 + function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); + end function "<="; + + -- Id: C.16 + function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L < 0; + end if; + return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); + end function "<="; + + -- Id: C.17 + function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if (L_LEFT < 0) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); + end function "<="; + + -- Id: C.18 + function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "LTE" ; + begin + if (L_LEFT < 0) then + assert NO_WARNING + report "NUMERIC_STD.""<="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 < R; + end if; + return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); + end function "<="; + + -- ============================================================================ + + -- Id: C.19 + function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function ">="; + + -- Id: C.20 + function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function ">="; + + -- Id: C.21 + function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); + end function ">="; + + -- Id: C.22 + function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return L > 0; + end if; + return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01); + end function ">="; + + -- Id: C.23 + function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); + end function ">="; + + -- Id: C.24 + function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "GTE" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD."">="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD."">="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return 0 > R; + end if; + return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); + end function ">="; + + -- ============================================================================ + + -- Id: C.25 + function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "="; + + -- Id: C.26 + function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); + end function "="; + + -- Id: C.27 + function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return false; + end if; + return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01); + end function "="; + + -- Id: C.28 + function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(L) > R'length then return false; + end if; + return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01); + end function "="; + + -- Id: C.29 + function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return false; + end if; + return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)); + end function "="; + + -- Id: C.30 + function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "EQ" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""="": null argument detected, returning FALSE" + severity warning; + return false; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""="": metavalue detected, returning FALSE" + severity warning; + return false; + end if; + if SIGNED_NUM_BITS(R) > L'length then return false; + end if; + return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)); + end function "="; + + -- ============================================================================ + + -- Id: C.31 + function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); + end function "/="; + + -- Id: C.32 + function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + L01 := TO_01(XL, 'X'); + R01 := TO_01(XR, 'X'); + if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); + end function "/="; + + -- Id: C.33 + function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + if UNSIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01)); + end function "/="; + + -- Id: C.34 + function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is + constant R_LEFT : INTEGER := R'length-1; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of R:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if (R'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + R01 := TO_01(XR, 'X'); + if (R01(R01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + if SIGNED_NUM_BITS(L) > R'length then return true; + end if; + return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01)); + end function "/="; + + -- Id: C.35 + function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + if UNSIGNED_NUM_BITS(R) > L'length then return true; + end if; + return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length))); + end function "/="; + + -- Id: C.36 + function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is + constant L_LEFT : INTEGER := L'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); + -- Synthesis directives : + variable RESULT : BOOLEAN ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "NEQ" ; + begin + if (L'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.""/="": null argument detected, returning TRUE" + severity warning; + return true; + end if; + L01 := TO_01(XL, 'X'); + if (L01(L01'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" + severity warning; + return true; + end if; + if SIGNED_NUM_BITS(R) > L'length then return true; + end if; + return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length))); + end function "/="; + + -- ============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + if UNSIGNED_LESS(L01, R01) then + return L01; + else + return R01; + end if; + end function MINIMUM; + + -- Id: C.38 + function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + if SIGNED_LESS(L01, R01) then + return L01; + else + return R01; + end if; + end function MINIMUM; + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return MINIMUM(TO_UNSIGNED(L, R'length), R); + end function MINIMUM; + + -- Id: C.40 + function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return MINIMUM(TO_SIGNED(L, R'length), R); + end function MINIMUM; + + -- Id: C.41 + function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + return MINIMUM(L, TO_UNSIGNED(R, L'length)); + end function MINIMUM; + + -- Id: C.42 + function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED is + begin + return MINIMUM(L, TO_SIGNED(R, L'length)); + end function MINIMUM; + + -- ============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAU; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + if UNSIGNED_LESS(L01, R01) then + return R01; + else + return L01; + end if; + end function MAXIMUM; + + -- Id: C.44 + function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); + begin + if ((L'length < 1) or (R'length < 1)) then return NAS; + end if; + L01 := TO_01(RESIZE(L, SIZE), 'X'); + if (L01(L01'left) = 'X') then return L01; + end if; + R01 := TO_01(RESIZE(R, SIZE), 'X'); + if (R01(R01'left) = 'X') then return R01; + end if; + if SIGNED_LESS(L01, R01) then + return R01; + else + return L01; + end if; + end function MAXIMUM; + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return MAXIMUM(TO_UNSIGNED(L, R'length), R); + end function MAXIMUM; + + -- Id: C.46 + function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return MAXIMUM(TO_SIGNED(L, R'length), R); + end function MAXIMUM; + + -- Id: C.47 + function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + return MAXIMUM(L, TO_UNSIGNED(R, L'length)); + end function MAXIMUM; + + -- Id: C.48 + function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) + return UNRESOLVED_SIGNED is + begin + return MAXIMUM(L, TO_SIGNED(R, L'length)); + end function MAXIMUM; + + -- ============================================================================ + + -- Id: C.49 + function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?>"": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?>"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?>"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L > R then + return '1'; + else + return '0'; + end if; + end if; + end function "?>"; + + -- Id: C.50 + function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?>"": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?>"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?>"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L > R then + return '1'; + else + return '0'; + end if; + end if; + end function "?>"; + + -- Id: C.51 + function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?> R; + end function "?>"; + + -- Id: C.52 + function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?> R; + end function "?>"; + + -- Id: C.53 + function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?> TO_UNSIGNED(R, L'length); + end function "?>"; + + -- Id: C.54 + function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?> TO_SIGNED(R, L'length); + end function "?>"; + + -- ============================================================================ + + -- Id: C.55 + function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?<"": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?<"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?<"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L < R then + return '1'; + else + return '0'; + end if; + end if; + end function "?<"; + + -- Id: C.56 + function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?<"": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?<"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?<"": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L < R then + return '1'; + else + return '0'; + end if; + end if; + end function "?<"; + + -- Id: C.57 + function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?< R; + end function "?<"; + + -- Id: C.58 + function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?< R; + end function "?<"; + + -- Id: C.59 + function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?< TO_UNSIGNED(R, L'length); + end function "?<"; + + -- Id: C.60 + function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?< TO_SIGNED(R, L'length); + end function "?<"; + + -- ============================================================================ + + -- Id: C.61 + function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?<="": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?<="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?<="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L <= R then + return '1'; + else + return '0'; + end if; + end if; + end function "?<="; + + -- Id: C.62 + function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?<="": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?<="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?<="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L <= R then + return '1'; + else + return '0'; + end if; + end if; + end function "?<="; + + -- Id: C.63 + function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?<= R; + end function "?<="; + + -- Id: C.64 + function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?<= R; + end function "?<="; + + -- Id: C.65 + function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?<= TO_UNSIGNED(R, L'length); + end function "?<="; + + -- Id: C.66 + function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?<= TO_SIGNED(R, L'length); + end function "?<="; + + -- ============================================================================ + + -- Id: C.67 + function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?>="": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?>="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?>="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L >= R then + return '1'; + else + return '0'; + end if; + end if; + end function "?>="; + + -- Id: C.68 + function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?>="": null detected, returning X" + severity warning; + return 'X'; + else + for i in L'range loop + if L(i) = '-' then + report "NUMERIC_STD.""?>="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + for i in R'range loop + if R(i) = '-' then + report "NUMERIC_STD.""?>="": '-' found in compare string" + severity error; + return 'X'; + end if; + end loop; + if Is_X(L) or Is_X(R) then + return 'X'; + elsif L >= R then + return '1'; + else + return '0'; + end if; + end if; + end function "?>="; + + -- Id: C.69 + function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?>= R; + end function "?>="; + + -- Id: C.70 + function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?>= R; + end function "?>="; + + -- Id: C.71 + function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?>= TO_UNSIGNED(R, L'length); + end function "?>="; + + -- Id: C.72 + function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?>= TO_SIGNED(R, L'length); + end function "?>="; + + -- ============================================================================ + + -- Id: C.73 + function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable result, result1 : STD_ULOGIC; -- result + begin + -- Logically identical to an "=" operator. + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?="": null detected, returning X" + severity warning; + return 'X'; + else + LX := RESIZE(XL, SIZE); + RX := RESIZE(XR, SIZE); + result := '1'; + for i in LX'low to LX'high loop + result1 := LX(i) ?= RX(i); + if result1 = 'U' then + return 'U'; + elsif result1 = 'X' or result = 'X' then + result := 'X'; + else + result := result and result1; + end if; + end loop; + return result; + end if; + end function "?="; + + -- Id: C.74 + function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable result, result1 : STD_ULOGIC; -- result + begin -- ?= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?="": null detected, returning X" + severity warning; + return 'X'; + else + LX := RESIZE(XL, SIZE); + RX := RESIZE(XR, SIZE); + result := '1'; + for i in LX'low to LX'high loop + result1 := LX(i) ?= RX(i); + if result1 = 'U' then + return 'U'; + elsif result1 = 'X' or result = 'X' then + result := 'X'; + else + result := result and result1; + end if; + end loop; + return result; + end if; + end function "?="; + + -- Id: C.75 + function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?= R; + end function "?="; + + -- Id: C.76 + function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?= R; + end function "?="; + + -- Id: C.77 + function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?= TO_UNSIGNED(R, L'length); + end function "?="; + + -- Id: C.78 + function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?= TO_SIGNED(R, L'length); + end function "?="; + + -- ============================================================================ + + -- Id: C.79 + function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable result, result1 : STD_ULOGIC; -- result + begin -- ?= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?/="": null detected, returning X" + severity warning; + return 'X'; + else + LX := RESIZE(XL, SIZE); + RX := RESIZE(XR, SIZE); + result := '0'; + for i in LX'low to LX'high loop + result1 := LX(i) ?/= RX(i); + if result1 = 'U' then + return 'U'; + elsif result1 = 'X' or result = 'X' then + result := 'X'; + else + result := result or result1; + end if; + end loop; + return result; + end if; + end function "?/="; + + -- Id: C.80 + function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is + constant L_LEFT : INTEGER := L'length-1; + constant R_LEFT : INTEGER := R'length-1; + alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; + alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; + constant SIZE : NATURAL := MAXIMUM(L'length, R'length); + variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable result, result1 : STD_ULOGIC; -- result + begin -- ?= + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.""?/="": null detected, returning X" + severity warning; + return 'X'; + else + LX := RESIZE(XL, SIZE); + RX := RESIZE(XR, SIZE); + result := '0'; + for i in LX'low to LX'high loop + result1 := LX(i) ?/= RX(i); + if result1 = 'U' then + return 'U'; + elsif result1 = 'X' or result = 'X' then + result := 'X'; + else + result := result or result1; + end if; + end loop; + return result; + end if; + end function "?/="; + + -- Id: C.81 + function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return TO_UNSIGNED(L, R'length) ?/= R; + end function "?/="; + + -- Id: C.82 + function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return TO_SIGNED(L, R'length) ?/= R; + end function "?/="; + + -- Id: C.83 + function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is + begin + return L ?/= TO_UNSIGNED(R, L'length); + end function "?/="; + + -- Id: C.84 + function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is + begin + return L ?/= TO_SIGNED(R, L'length); + end function "?/="; + + -- ============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function SHIFT_LEFT; + + -- Id: S.2 + function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function SHIFT_RIGHT; + + -- Id: S.3 + function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) + return UNRESOLVED_SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function SHIFT_LEFT; + + -- Id: S.4 + function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) + return UNRESOLVED_SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function SHIFT_RIGHT; + + -- ============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function ROTATE_LEFT; + + -- Id: S.6 + function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) + return UNRESOLVED_UNSIGNED is + begin + if (ARG'length < 1) then return NAU; + end if; + return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function ROTATE_RIGHT; + + + -- Id: S.7 + function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) + return UNRESOLVED_SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function ROTATE_LEFT; + + -- Id: S.8 + function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) + return UNRESOLVED_SIGNED is + begin + if (ARG'length < 1) then return NAS; + end if; + return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); + end function ROTATE_RIGHT; + + -- ============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.9 + function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SLL" ; + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sll"; + + ------------------------------------------------------------------------------ + -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.10 + function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SLL" ; + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT)); + end if; + end function "sll"; + + ------------------------------------------------------------------------------ + -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.11 + function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SRL" ; + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "srl"; + + ------------------------------------------------------------------------------ + -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.12 + function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SRL" ; + begin + if (COUNT >= 0) then + return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "srl"; + + ------------------------------------------------------------------------------ + -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.13 + function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "ROL" ; + begin + if (COUNT >= 0) then + return ROTATE_LEFT(ARG, COUNT); + else + return ROTATE_RIGHT(ARG, -COUNT); + end if; + end function "rol"; + + ------------------------------------------------------------------------------ + -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.14 + function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "ROL" ; + begin + if (COUNT >= 0) then + return ROTATE_LEFT(ARG, COUNT); + else + return ROTATE_RIGHT(ARG, -COUNT); + end if; + end function "rol"; + + ------------------------------------------------------------------------------ + -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.15 + function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "ROR" ; + begin + if (COUNT >= 0) then + return ROTATE_RIGHT(ARG, COUNT); + else + return ROTATE_LEFT(ARG, -COUNT); + end if; + end function "ror"; + + ------------------------------------------------------------------------------ + -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.16 + function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "ROR" ; + begin + if (COUNT >= 0) then + return ROTATE_RIGHT(ARG, COUNT); + else + return ROTATE_LEFT(ARG, -COUNT); + end if; + end function "ror"; + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + -- for numeric types SLA behaves as SLL + attribute SYNTHESIS_RETURN of RESULT:variable is "SLL" ; + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sla"; + + ------------------------------------------------------------------------------ + -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.18 + function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + -- for numeric types SLA behaves as SLL + attribute SYNTHESIS_RETURN of RESULT:variable is "SLL" ; + begin + if (COUNT >= 0) then + return SHIFT_LEFT(ARG, COUNT); + else + return SHIFT_RIGHT(ARG, -COUNT); + end if; + end function "sla"; + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT : UNSIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SRA" ; + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "sra"; + + ------------------------------------------------------------------------------ + -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.20 + function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT : SIGNED (ARG'LENGTH-1 downto 0) ; + attribute SYNTHESIS_RETURN of RESULT:variable is "SRA" ; + begin + if (COUNT >= 0) then + return SHIFT_RIGHT(ARG, COUNT); + else + return SHIFT_LEFT(ARG, -COUNT); + end if; + end function "sra"; + + -- ============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; + variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0); + variable RESULT : NATURAL := 0; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (ARG'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" + severity warning; + return 0; + end if; + XARG := TO_01(XXARG, 'X'); + if (XARG(XARG'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" + severity warning; + return 0; + end if; + for I in XARG'range loop + RESULT := RESULT+RESULT; + if XARG(I) = '1' then + RESULT := RESULT + 1; + end if; + end loop; + return RESULT; + end function TO_INTEGER; + + -- Id: D.2 + function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is + variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0); + -- Synthesis directives : + variable RESULT : INTEGER ; + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (ARG'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" + severity warning; + return 0; + end if; + XARG := TO_01(ARG, 'X'); + if (XARG(XARG'left) = 'X') then + assert NO_WARNING + report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" + severity warning; + return 0; + end if; + if XARG(XARG'left) = '0' then + return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG)); + else + return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1); + end if; + end function TO_INTEGER; + + -- Id: D.3 + function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); + variable I_VAL : NATURAL := ARG; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (SIZE < 1) then return NAU; + end if; + for I in 0 to RESULT'left loop + if (I_VAL mod 2) = 0 then + RESULT(I) := '0'; + else RESULT(I) := '1'; + end if; + I_VAL := I_VAL/2; + end loop; + if not(I_VAL = 0) then + assert NO_WARNING + report "NUMERIC_STD.TO_UNSIGNED: vector truncated" + severity warning; + end if; + return RESULT; + end function TO_UNSIGNED; + + -- Id: D.4 + function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0); + variable B_VAL : STD_LOGIC := '0'; + variable I_VAL : INTEGER := ARG; + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (SIZE < 1) then return NAS; + end if; + if (ARG < 0) then + B_VAL := '1'; + I_VAL := -(ARG+1); + end if; + for I in 0 to RESULT'left loop + if (I_VAL mod 2) = 0 then + RESULT(I) := B_VAL; + else + RESULT(I) := not B_VAL; + end if; + I_VAL := I_VAL/2; + end loop; + if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then + assert NO_WARNING + report "NUMERIC_STD.TO_SIGNED: vector truncated" + severity warning; + end if; + return RESULT; + end function TO_SIGNED; + + function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return TO_UNSIGNED (ARG => ARG, + SIZE => SIZE_RES'length); + end function TO_UNSIGNED; + + function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return TO_SIGNED (ARG => ARG, + SIZE => SIZE_RES'length); + end function TO_SIGNED; + + -- ============================================================================ + + -- Id: R.1 + function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) + return UNRESOLVED_SIGNED + is + alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG; + variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) := + (others => '0'); + constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; + -- VERIFIC: The RESIZE() function for signed does NOT behave the same as the FEEDTHROUGH pragma does. It does truncation a bit different. Cannot use pragma. Issue 2044 + -- attribute IS_SIGNED of ARG:constant is TRUE ; + ---attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (NEW_SIZE < 1) then return NAS; + end if; + if (ARG'length = 0) then return RESULT; + end if; + RESULT := (others => ARG(ARG'left)); + if BOUND >= 0 then + RESULT(BOUND downto 0) := INVEC(BOUND downto 0); + end if; + return RESULT; + end function RESIZE; + + -- Id: R.2 + function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) + return UNRESOLVED_UNSIGNED + is + constant ARG_LEFT : INTEGER := ARG'length-1; + alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; + variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) := + (others => '0'); + -- Synthesis directives : + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (NEW_SIZE < 1) then return NAU; + end if; + if XARG'length = 0 then return RESULT; + end if; + if (RESULT'length < ARG'length) then + RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); + else + RESULT(RESULT'left downto XARG'left+1) := (others => '0'); + RESULT(XARG'left downto 0) := XARG; + end if; + return RESULT; + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return RESIZE (ARG => ARG, + NEW_SIZE => SIZE_RES'length); + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return RESIZE (ARG => ARG, + NEW_SIZE => SIZE_RES'length); + end function RESIZE; + + -- ============================================================================ + + -- Id: L.1 + function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L))); + return RESULT; + end function "not"; + + -- Id: L.2 + function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "and"; + + -- Id: L.3 + function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "or"; + + -- Id: L.4 + function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "nand"; + + -- Id: L.5 + function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "nor"; + + -- Id: L.6 + function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.7 + function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "xnor"; + + -- Id: L.8 + function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L))); + return RESULT; + end function "not"; + + -- Id: L.9 + function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "and"; + + -- Id: L.10 + function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "or"; + + -- Id: L.11 + function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "nand"; + + -- Id: L.12 + function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "nor"; + + -- Id: L.13 + function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.14 + function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); + begin + RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor + STD_ULOGIC_VECTOR(R)); + return RESULT; + end function "xnor"; + + -- Id: L.15 + function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R)); + end function "and"; + + -- Id: L.16 + function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R); + end function "and"; + + -- Id: L.17 + function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R)); + end function "or"; + + -- Id: L.18 + function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R); + end function "or"; + + -- Id: L.19 + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R)); + end function "nand"; + + -- Id: L.20 + function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R); + end function "nand"; + + -- Id: L.21 + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R)); + end function "nor"; + + -- Id: L.22 + function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R); + end function "nor"; + + -- Id: L.23 + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R)); + end function "xor"; + + -- Id: L.24 + function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.25 + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.26 + function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) + return UNRESOLVED_UNSIGNED is + begin + return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R); + end function "xnor"; + + -- Id: L.27 + function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R)); + end function "and"; + + -- Id: L.28 + function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R); + end function "and"; + + -- Id: L.29 + function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R)); + end function "or"; + + -- Id: L.30 + function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R); + end function "or"; + + -- Id: L.31 + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R)); + end function "nand"; + + -- Id: L.32 + function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R); + end function "nand"; + + -- Id: L.33 + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R)); + end function "nor"; + + -- Id: L.34 + function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R); + end function "nor"; + + -- Id: L.35 + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R)); + end function "xor"; + + -- Id: L.36 + function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.37 + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.38 + function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) + return UNRESOLVED_SIGNED is + begin + return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.39 + function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return and (STD_ULOGIC_VECTOR (L)); + end function "and"; + + ------------------------------------------------------------------------------ + -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.40 + function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return and (STD_ULOGIC_VECTOR (L)); + end function "and"; + + ------------------------------------------------------------------------------ + -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.41 + function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return nand (STD_ULOGIC_VECTOR (L)); + end function "nand"; + + ------------------------------------------------------------------------------ + -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.42 + function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return nand (STD_ULOGIC_VECTOR (L)); + end function "nand"; + + ------------------------------------------------------------------------------ + -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.43 + function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return or (STD_ULOGIC_VECTOR (L)); + end function "or"; + + ------------------------------------------------------------------------------ + -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.44 + function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return or (STD_ULOGIC_VECTOR (L)); + end function "or"; + + ------------------------------------------------------------------------------ + -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.45 + function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return nor (STD_ULOGIC_VECTOR (L)); + end function "nor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.46 + function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return nor (STD_ULOGIC_VECTOR (L)); + end function "nor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.47 + function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return xor (STD_ULOGIC_VECTOR (L)); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.48 + function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return xor (STD_ULOGIC_VECTOR (L)); + end function "xor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.49 + function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is + begin + return xnor (STD_ULOGIC_VECTOR (L)); + end function "xnor"; + + ------------------------------------------------------------------------------ + -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.50 + function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is + begin + return xnor (STD_ULOGIC_VECTOR (L)); + end function "xnor"; + + -- ============================================================================ + + -- support constants for STD_MATCH: + + type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; + + constant MATCH_TABLE : BOOLEAN_TABLE := ( + -------------------------------------------------------------------------- + -- U X 0 1 Z W L H - + -------------------------------------------------------------------------- + (false, false, false, false, false, false, false, false, true), -- | U | + (false, false, false, false, false, false, false, false, true), -- | X | + (false, false, true, false, false, false, true, false, true), -- | 0 | + (false, false, false, true, false, false, false, true, true), -- | 1 | + (false, false, false, false, false, false, false, false, true), -- | Z | + (false, false, false, false, false, false, false, false, true), -- | W | + (false, false, true, false, false, false, true, false, true), -- | L | + (false, false, false, true, false, false, false, true, true), -- | H | + (true, true, true, true, true, true, true, true, true) -- | - | + ); + + -- Id: M.1 + function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is + variable VALUE : STD_ULOGIC; + begin + return MATCH_TABLE(L, R); + end function STD_MATCH; + + -- Id: M.2 + function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is + alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L; + alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" + severity warning; + return false; + end if; + if LV'length /= RV'length then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" + severity warning; + return false; + else + for I in LV'low to LV'high loop + if not (MATCH_TABLE(LV(I), RV(I))) then + return false; + end if; + end loop; + return true; + end if; + end function STD_MATCH; + + -- Id: M.3 + function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is + alias LV : UNRESOLVED_SIGNED(1 to L'length) is L; + alias RV : UNRESOLVED_SIGNED(1 to R'length) is R; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" + severity warning; + return false; + end if; + if LV'length /= RV'length then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" + severity warning; + return false; + else + for I in LV'low to LV'high loop + if not (MATCH_TABLE(LV(I), RV(I))) then + return false; + end if; + end loop; + return true; + end if; + end function STD_MATCH; + + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + -- Id: M.4 + function STD_MATCH (L, R: STD_LOGIC_VECTOR_93) return BOOLEAN is + alias LV: STD_LOGIC_VECTOR_93(1 to L'LENGTH) is L; + alias RV: STD_LOGIC_VECTOR_93(1 to R'LENGTH) is R; + begin + if ((L'LENGTH < 1) or (R'LENGTH < 1)) then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" + severity WARNING; + return FALSE; + end if; + if LV'LENGTH /= RV'LENGTH then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" + severity WARNING; + return FALSE; + else + for I in LV'LOW to LV'HIGH loop + if not (MATCH_TABLE(LV(I), RV(I))) then + return FALSE; + end if; + end loop; + return TRUE; + end if; + end STD_MATCH; + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + + -- Id: M.5 + function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L; + alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R; + begin + if ((L'length < 1) or (R'length < 1)) then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" + severity warning; + return false; + end if; + if LV'length /= RV'length then + assert NO_WARNING + report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" + severity warning; + return false; + else + for I in LV'low to LV'high loop + if not (MATCH_TABLE(LV(I), RV(I))) then + return false; + end if; + end loop; + return true; + end if; + end function STD_MATCH; + + -- ============================================================================ + + -- function TO_01 is used to convert vectors to the + -- correct form for exported functions, + -- and to report if there is an element which + -- is not in (0, 1, H, L). + + -- Id: T.1 + function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') + return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (S'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.TO_01: null detected, returning NAU" + severity warning; + return NAU; + end if; + return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); + end function TO_01; + + -- Id: T.2 + function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') + return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + if (S'length < 1) then + assert NO_WARNING + report "NUMERIC_STD.TO_01: null detected, returning NAS" + severity warning; + return NAS; + end if; + return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); + end function TO_01; + + -- Id: T.3 + function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); + end function TO_X01; + + -- Id: T.4 + function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); + end function TO_X01; + + -- Id: T.5 + function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); + end function TO_X01Z; + + -- Id: T.6 + function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); + end function TO_X01Z; + + -- Id: T.7 + function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); + end function TO_UX01; + + -- Id: T.8 + function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is + -- Synthesis directives : + variable RESULT: SIGNED(S'LENGTH-1 downto 0); + attribute SYNTHESIS_RETURN of RESULT:variable is "FEED_THROUGH" ; + begin + return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); + end function TO_UX01; + + -- Id: T.9 + function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is + begin + return IS_X(STD_ULOGIC_VECTOR(S)); + end function IS_X; + + -- Id: T.10 + function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is + begin + return IS_X(STD_ULOGIC_VECTOR(S)); + end function IS_X; + + -- ============================================================================ + -- string conversion and write operations + -- ============================================================================ + function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is + begin + return to_ostring(STD_ULOGIC_VECTOR (value)); + end function to_ostring; + + function to_ostring (value : UNRESOLVED_SIGNED) return STRING is + constant result_length : INTEGER := (value'length+2)/3; + constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 - + value'length)) + := (others => value (value'left)); -- Extend sign bit + begin + return to_ostring(pad & STD_ULOGIC_VECTOR (value)); + end function to_ostring; + + function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is + begin + return to_hstring(STD_ULOGIC_VECTOR (value)); + end function to_hstring; + + function to_hstring (value : UNRESOLVED_SIGNED) return STRING is + constant result_length : INTEGER := (value'length+3)/4; + constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 - + value'length)) + := (others => value (value'left)); -- Extend sign bit + begin + return to_hstring(pad & STD_ULOGIC_VECTOR (value)); + end function to_hstring; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; + GOOD : out BOOLEAN) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + READ (L => L, + VALUE => ivalue, + GOOD => GOOD) ; + VALUE := UNSIGNED(ivalue) ; + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + READ (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; + GOOD : out BOOLEAN) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + READ (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := SIGNED(ivalue); + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + READ (L => L, + VALUE => ivalue); + VALUE := SIGNED (ivalue); + end procedure READ; + + procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + WRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure WRITE; + + procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + WRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure WRITE; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; + GOOD : out BOOLEAN) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + OREAD (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := UNSIGNED(ivalue); + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; + GOOD : out BOOLEAN) is + constant ne : INTEGER := (value'length+2)/3; + constant pad : INTEGER := ne*3 - value'length; + variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); + variable ok : BOOLEAN; + variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); + -- verific synthesis ignore_subprogram + begin + OREAD (L => L, + VALUE => ivalue, -- Read padded STRING + GOOD => ok); + -- Bail out if there was a bad read + if not ok then + GOOD := false; + return; + end if; + expected_padding := (others => ivalue(pad)); + if ivalue(0 to pad-1) /= expected_padding then + GOOD := false; + else + GOOD := true; + VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); + end if; + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + OREAD (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is + constant ne : INTEGER := (value'length+2)/3; + constant pad : INTEGER := ne*3 - value'length; + variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); + variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); + -- verific synthesis ignore_subprogram + begin + OREAD (L => L, + VALUE => ivalue); -- Read padded string + expected_padding := (others => ivalue(pad)); + if ivalue(0 to pad-1) /= expected_padding then + assert false + report "NUMERIC_STD.OREAD Error: Signed vector truncated" + severity error; + else + VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); + end if; + end procedure OREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; + GOOD : out BOOLEAN) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + HREAD (L => L, + VALUE => ivalue, + GOOD => GOOD); + VALUE := UNSIGNED(ivalue); + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; + GOOD : out BOOLEAN) is + constant ne : INTEGER := (value'length+3)/4; + constant pad : INTEGER := ne*4 - value'length; + variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); + variable ok : BOOLEAN; + variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); + -- verific synthesis ignore_subprogram + begin + HREAD (L => L, + VALUE => ivalue, -- Read padded STRING + GOOD => ok); + if not ok then + GOOD := false; + return; + end if; + expected_padding := (others => ivalue(pad)); + if ivalue(0 to pad-1) /= expected_padding then + GOOD := false; + else + GOOD := true; + VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); + end if; + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + HREAD (L => L, + VALUE => ivalue); + VALUE := UNSIGNED (ivalue); + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is + constant ne : INTEGER := (value'length+3)/4; + constant pad : INTEGER := ne*4 - value'length; + variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); + variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); + -- verific synthesis ignore_subprogram + begin + HREAD (L => L, + VALUE => ivalue); -- Read padded string + expected_padding := (others => ivalue(pad)); + if ivalue(0 to pad-1) /= expected_padding then + assert false + report "NUMERIC_STD.HREAD Error: Signed vector truncated" + severity error; + else + VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); + end if; + end procedure HREAD; + + procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + OWRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure OWRITE; + + procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + constant ne : INTEGER := (VALUE'length+2)/3; + constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1) + := (others => VALUE (VALUE'left)); + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + OWRITE (L => L, + VALUE => pad & ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure OWRITE; + + procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + HWRITE (L => L, + VALUE => ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure HWRITE; + + procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable ivalue : STD_ULOGIC_VECTOR(value'range); + constant ne : INTEGER := (value'length+3)/4; + constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1) + := (others => VALUE(VALUE'left)); + -- verific synthesis ignore_subprogram + begin + ivalue := STD_ULOGIC_VECTOR (VALUE); + HWRITE (L => L, + VALUE => pad & ivalue, + JUSTIFIED => JUSTIFIED, + FIELD => FIELD); + end procedure HWRITE; + +end package body NUMERIC_STD; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std.vhdl new file mode 100644 index 0000000..27d91f7 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std.vhdl @@ -0,0 +1,1849 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_STD package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE DASC Synthesis Working Group, +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Two numeric types are defined: +-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number +-- : in vector form +-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number +-- : in vector form +-- : The base element type is type STD_ULOGIC. +-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types +-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. +-- : Two numeric subtypes are defined: +-- : -- > UNSIGNED: represents UNSIGNED number in vector form +-- : -- > SIGNED: represents a SIGNED number in vector form +-- : The element subtypes are the same subtype as STD_LOGIC. +-- : The leftmost bit is treated as the most significant bit. +-- : Signed vectors are represented in two's complement form. +-- : This package contains overloaded arithmetic operators on +-- : the SIGNED and UNSIGNED types. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1.4 $ +-- $Date: 2015/08/13 10:28:07 $ +-- -------------------------------------------------------------------- + +use STD.TEXTIO.all; +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package NUMERIC_STD is + constant CopyRightNotice : STRING + := "Copyright © 2008 IEEE. All rights reserved."; + + + --============================================================================ + -- Numeric Array Type Definitions + --============================================================================ + + type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC; + type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC; + + alias U_UNSIGNED is UNRESOLVED_UNSIGNED; + alias U_SIGNED is UNRESOLVED_SIGNED; + + subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED; + subtype SIGNED is (resolved) UNRESOLVED_SIGNED; + + --============================================================================ + -- Arithmetic Operators: + --=========================================================================== + + -- Id: A.1 + function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Returns the absolute value of an UNRESOLVED_SIGNED vector ARG. + + -- Id: A.2 + function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Returns the value of the unary minus operation on a + -- UNRESOLVED_SIGNED vector ARG. + + --============================================================================ + + -- Id: A.3 + function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Adds two UNRESOLVED_UNSIGNED vectors that may be of different lengths. + + -- Id: A.3R + function "+"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.3 where R is a one bit UNRESOLVED_UNSIGNED + + -- Id: A.3L + function "+"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.3 where L is a one bit UNRESOLVED_UNSIGNED + + -- Id: A.4 + function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Adds two UNRESOLVED_SIGNED vectors that may be of different lengths. + + -- Id: A.4R + function "+"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.4 where R is bit 0 of a non-negative. + + -- Id: A.4L + function "+"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.4 where L is bit 0 of a non-negative. + + -- Id: A.5 + function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Adds an UNRESOLVED_UNSIGNED vector, L, with a nonnegative INTEGER, R. + + -- Id: A.6 + function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Adds a nonnegative INTEGER, L, with an UNRESOLVED_UNSIGNED vector, R. + + -- Id: A.7 + function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Adds an INTEGER, L(may be positive or negative), to an UNRESOLVED_SIGNED + -- vector, R. + + -- Id: A.8 + function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Adds an UNRESOLVED_SIGNED vector, L, to an INTEGER, R. + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Subtracts two UNRESOLVED_UNSIGNED vectors that may be of different lengths. + + -- Id: A.9R + function "-"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.9 where R is a one bit UNRESOLVED_UNSIGNED + + -- Id: A.9L + function "-"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.9 where L is a one bit UNRESOLVED_UNSIGNED + + -- Id: A.10 + function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) + -- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from another UNRESOLVED_SIGNED vector, L, + -- that may possibly be of different lengths. + + -- Id: A.10R + function "-"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Similar to A.10 where R is bit 0 of a non-negative. + + -- Id: A.10L + function "-"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Similar to A.10 where R is bit 0 of a non-negative. + + -- Id: A.11 + function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Subtracts a nonnegative INTEGER, R, from an UNRESOLVED_UNSIGNED vector, L. + + -- Id: A.12 + function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Subtracts an UNRESOLVED_UNSIGNED vector, R, from a nonnegative INTEGER, L. + + -- Id: A.13 + function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Subtracts an INTEGER, R, from an UNRESOLVED_SIGNED vector, L. + + -- Id: A.14 + function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from an INTEGER, L. + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) + -- Result: Performs the multiplication operation on two UNRESOLVED_UNSIGNED vectors + -- that may possibly be of different lengths. + + -- Id: A.16 + function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies two UNRESOLVED_SIGNED vectors that may possibly be of + -- different lengths. + + -- Id: A.17 + function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0) + -- Result: Multiplies an UNRESOLVED_UNSIGNED vector, L, with a nonnegative + -- INTEGER, R. R is converted to an UNRESOLVED_UNSIGNED vector of + -- SIZE L'LENGTH before multiplication. + + -- Id: A.18 + function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies an UNRESOLVED_UNSIGNED vector, R, with a nonnegative + -- INTEGER, L. L is converted to an UNRESOLVED_UNSIGNED vector of + -- SIZE R'LENGTH before multiplication. + + -- Id: A.19 + function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+L'LENGTH-1) downto 0) + -- Result: Multiplies an UNRESOLVED_SIGNED vector, L, with an INTEGER, R. R is + -- converted to an UNRESOLVED_SIGNED vector of SIZE L'LENGTH before + -- multiplication. + + -- Id: A.20 + function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED((R'LENGTH+R'LENGTH-1) downto 0) + -- Result: Multiplies an UNRESOLVED_SIGNED vector, R, with an INTEGER, L. L is + -- converted to an UNRESOLVED_SIGNED vector of SIZE R'LENGTH before + -- multiplication. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "/" operator, a severity level + -- of ERROR is issued. + + -- Id: A.21 + function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by another UNRESOLVED_UNSIGNED vector, R. + + -- Id: A.22 + function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNRESOLVED_SIGNED vector, L, by another UNRESOLVED_SIGNED vector, R. + + -- Id: A.23 + function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by a nonnegative INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.24 + function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Divides a nonnegative INTEGER, L, by an UNRESOLVED_UNSIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.25 + function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Divides an UNRESOLVED_SIGNED vector, L, by an INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.26 + function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Divides an INTEGER, L, by an UNRESOLVED_SIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "rem" operator, a severity level + -- of ERROR is issued. + + -- Id: A.27 + function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are UNRESOLVED_UNSIGNED vectors. + + -- Id: A.28 + function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are UNRESOLVED_SIGNED vectors. + + -- Id: A.29 + function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is an UNRESOLVED_UNSIGNED vector and R is a + -- nonnegative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.30 + function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is an UNRESOLVED_UNSIGNED vector and L is a + -- nonnegative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.31 + function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is UNRESOLVED_SIGNED vector and R is an INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.32 + function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is UNRESOLVED_SIGNED vector and L is an INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "mod" operator, a severity level + -- of ERROR is issued. + + -- Id: A.33 + function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are UNRESOLVED_UNSIGNED vectors. + + -- Id: A.34 + function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are UNRESOLVED_SIGNED vectors. + + -- Id: A.35 + function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an UNRESOLVED_UNSIGNED vector and R + -- is a nonnegative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.36 + function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where R is an UNRESOLVED_UNSIGNED vector and L + -- is a nonnegative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + -- Id: A.37 + function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.38 + function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.40 + function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.41 + function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.42 + function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + --============================================================================ + -- Comparison Operators + --============================================================================ + + -- Id: C.1 + function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.2 + function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.3 + function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.4 + function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.5 + function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.6 + function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and + -- R is a INTEGER. + + --============================================================================ + + -- Id: C.7 + function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.8 + function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.9 + function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.10 + function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.11 + function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.12 + function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.13 + function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.14 + function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.15 + function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.16 + function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.17 + function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.18 + function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.19 + function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.20 + function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.21 + function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.22 + function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.23 + function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.24 + function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.25 + function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.26 + function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.27 + function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.28 + function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.29 + function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.30 + function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.31 + function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.32 + function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.33 + function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.34 + function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.35 + function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.36 + function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the lesser of two UNRESOLVED_UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.38 + function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the lesser of two UNRESOLVED_SIGNED vectors that may be + -- of different lengths. + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the lesser of a nonnegative INTEGER, L, and + -- an UNRESOLVED_UNSIGNED vector, R. + + -- Id: C.40 + function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the lesser of an INTEGER, L, and an UNRESOLVED_SIGNED + -- vector, R. + + -- Id: C.41 + function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the lesser of an UNRESOLVED_UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + -- Id: C.42 + function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the lesser of an UNRESOLVED_SIGNED vector, L, and + -- an INTEGER, R. + + --============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the greater of two UNRESOLVED_UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.44 + function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the greater of two UNRESOLVED_SIGNED vectors that may be + -- of different lengths. + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the greater of a nonnegative INTEGER, L, and + -- an UNRESOLVED_UNSIGNED vector, R. + + -- Id: C.46 + function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the greater of an INTEGER, L, and an UNRESOLVED_SIGNED + -- vector, R. + + -- Id: C.47 + function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED + -- Result: Returns the greater of an UNRESOLVED_UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + -- Id: C.48 + function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED + -- Result: Returns the greater of an UNRESOLVED_SIGNED vector, L, and + -- an INTEGER, R. + + --============================================================================ + + -- Id: C.49 + function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.50 + function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.51 + function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.52 + function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is a INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.53 + function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.54 + function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and + -- R is a INTEGER. + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.56 + function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.57 + function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.58 + function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.59 + function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.60 + function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.62 + function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.63 + function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.64 + function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.65 + function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.66 + function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.68 + function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.69 + function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.70 + function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.71 + function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.72 + function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.74 + function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.75 + function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.76 + function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.77 + function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.78 + function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.80 + function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly + -- of different lengths. + + -- Id: C.81 + function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNRESOLVED_UNSIGNED vector. + + -- Id: C.82 + function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is an INTEGER and + -- R is an UNRESOLVED_SIGNED vector. + + -- Id: C.83 + function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and + -- R is a nonnegative INTEGER. + + -- Id: C.84 + function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and + -- R is an INTEGER. + + --============================================================================ + -- Shift and Rotate Functions + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an UNRESOLVED_UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an UNRESOLVED_UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + + -- Id: S.3 + function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an UNRESOLVED_SIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.4 + function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an UNRESOLVED_SIGNED vector COUNT times. + -- The vacated positions are filled with the leftmost + -- element, ARG'LEFT. The COUNT rightmost elements are lost. + + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an UNRESOLVED_UNSIGNED vector COUNT times. + + -- Id: S.6 + function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an UNRESOLVED_UNSIGNED vector COUNT times. + + -- Id: S.7 + function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a logical rotate-left of an UNRESOLVED_SIGNED + -- vector COUNT times. + + -- Id: S.8 + function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a logical rotate-right of an UNRESOLVED_SIGNED + -- vector COUNT times. + + --============================================================================ + + --============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.9 + function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.10 + function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.11 + function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.12 + function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)) + + ------------------------------------------------------------------------------ + -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.13 + function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.14 + function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.15 + function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.16 + function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.18 + function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.20 + function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + --============================================================================ + -- RESIZE Functions + --============================================================================ + + -- Id: R.1 + function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) + -- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with the sign bit (ARG'LEFT). When truncating, + -- the sign bit is retained along with the rightmost part. + + -- Id: R.2 + function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) + -- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with '0'. When truncating, the leftmost bits + -- are dropped. + + function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0) + + function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Conversion Functions + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL; + -- Result subtype: NATURAL. Value cannot be negative since parameter is an + -- UNRESOLVED_UNSIGNED vector. + -- Result: Converts the UNRESOLVED_UNSIGNED vector to an INTEGER. + + -- Id: D.2 + function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER; + -- Result subtype: INTEGER + -- Result: Converts an UNRESOLVED_SIGNED vector to an INTEGER. + + -- Id: D.3 + function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0) + -- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with + -- the specified SIZE. + + -- Id: D.4 + function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0) + -- Result: Converts an INTEGER to a UNRESOLVED_SIGNED vector of the specified SIZE. + + function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0) + + function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Logical Operators + --============================================================================ + + -- Id: L.1 + function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Termwise inversion + + -- Id: L.2 + function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector AND operation + + -- Id: L.3 + function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector OR operation + + -- Id: L.4 + function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NAND operation + + -- Id: L.5 + function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NOR operation + + -- Id: L.6 + function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XOR operation + + -- --------------------------------------------------------------------------- + -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + -- --------------------------------------------------------------------------- + -- Id: L.7 + function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XNOR operation + + -- Id: L.8 + function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Termwise inversion + + -- Id: L.9 + function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector AND operation + + -- Id: L.10 + function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector OR operation + + -- Id: L.11 + function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NAND operation + + -- Id: L.12 + function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector NOR operation + + -- Id: L.13 + function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XOR operation + + -- --------------------------------------------------------------------------- + -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + -- --------------------------------------------------------------------------- + -- Id: L.14 + function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector XNOR operation + + -- Id: L.15 + function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector AND operation + + -- Id: L.16 + function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar AND operation + + -- Id: L.17 + function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector OR operation + + -- Id: L.18 + function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar OR operation + + -- Id: L.19 + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NAND operation + + -- Id: L.20 + function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NAND operation + + -- Id: L.21 + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NOR operation + + -- Id: L.22 + function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NOR operation + + -- Id: L.23 + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XOR operation + + -- Id: L.24 + function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.25 + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.26 + function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XNOR operation + + -- Id: L.27 + function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector AND operation + + -- Id: L.28 + function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar AND operation + + -- Id: L.29 + function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector OR operation + + -- Id: L.30 + function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar OR operation + + -- Id: L.31 + function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NAND operation + + -- Id: L.32 + function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NAND operation + + -- Id: L.33 + function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector NOR operation + + -- Id: L.34 + function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar NOR operation + + -- Id: L.35 + function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XOR operation + + -- Id: L.36 + function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.37 + function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0) + -- Result: Scalar/Vector XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: L.38 + function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0) + -- Result: Vector/Scalar XNOR operation + + ------------------------------------------------------------------------------ + -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.39 + function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.40 + function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.41 + function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.42 + function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.43 + function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.44 + function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.45 + function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of and'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.46 + function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of nand'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.47 + function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of or'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.48 + function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of nor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.49 + function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of xor'ing all of the bits of the vector. + + ------------------------------------------------------------------------------ + -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from + -- 1987 through 2002. Comment out the function (declaration and body) for + -- compatibility with these editions. + ------------------------------------------------------------------------------ + -- Id: L.50 + function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC. + -- Result: Result of xnor'ing all of the bits of the vector. + + --============================================================================ + -- Match Functions + --============================================================================ + + -- Id: M.1 + function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: terms compared per STD_LOGIC_1164 intent + + -- Id: M.2 + function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: terms compared per STD_LOGIC_1164 intent + + -- Id: M.3 + function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: terms compared per STD_LOGIC_1164 intent + + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + -- Id: M.4 + function STD_MATCH (L, R: STD_LOGIC_VECTOR_93) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: terms compared per STD_LOGIC_1164 intent + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + + -- Id: M.5 + function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: terms compared per STD_LOGIC_1164 intent + + --============================================================================ + -- Translation Functions + --============================================================================ + + -- Id: T.1 + function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', and 'L' is translated + -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, + -- the array is set to (others => XMAP), and a warning is + -- issued. + + -- Id: T.2 + function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', and 'L' is translated + -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, + -- the array is set to (others => XMAP), and a warning is + -- issued. + + -- Id: T.3 + function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than '0'|'1'|'H'|'L' are translated to 'X'. + + -- Id: T.4 + function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than '0'|'1'|'H'|'L' are translated to 'X'. + + -- Id: T.5 + function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'. + + -- Id: T.6 + function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'. + + -- Id: T.7 + function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED; + -- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'. + + -- Id: T.8 + function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED; + -- Result subtype: UNRESOLVED_SIGNED(S'RANGE) + -- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0', + -- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'. + + -- Id: T.9 + function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise. + + -- Id: T.10 + function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise. + + --============================================================================ + -- string conversion and write operations + --============================================================================ + -- the following operations are predefined + + -- function to_string (value : UNRESOLVED_UNSIGNED) return STRING; + -- function to_string (value : UNRESOLVED_SIGNED) return STRING; + + -- explicitly defined operations + + alias to_bstring is to_string [UNRESOLVED_UNSIGNED return STRING]; + alias to_bstring is to_string [UNRESOLVED_SIGNED return STRING]; + alias to_binary_string is to_string [UNRESOLVED_UNSIGNED return STRING]; + alias to_binary_string is to_string [UNRESOLVED_SIGNED return STRING]; + + function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING; + function to_ostring (value : UNRESOLVED_SIGNED) return STRING; + alias to_octal_string is to_ostring [UNRESOLVED_UNSIGNED return STRING]; + alias to_octal_string is to_ostring [UNRESOLVED_SIGNED return STRING]; + + function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING; + function to_hstring (value : UNRESOLVED_SIGNED) return STRING; + alias to_hex_string is to_hstring [UNRESOLVED_UNSIGNED return STRING]; + alias to_hex_string is to_hstring [UNRESOLVED_SIGNED return STRING]; + + procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN); + + procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED); + + procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN); + + procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED); + + procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN]; + alias BREAD is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN]; + + alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED]; + alias BREAD is READ [LINE, UNRESOLVED_SIGNED]; + + alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN]; + alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN]; + + alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED]; + alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED]; + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN); + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN); + + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED); + procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED); + + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN]; + + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED]; + alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED]; + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN); + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN); + + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED); + procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED); + + alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN]; + + alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED]; + alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED]; + + alias BWRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH]; + alias BWRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH]; + + alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH]; + alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH]; + + procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH]; + alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH]; + + procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH]; + alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH]; + + -- Synthesis Directives + -- Synthesis Directives are in the form of the following two attributes: + -- attribute SYNTHESIS_RETURN : STRING ; + -- attribute IS_SIGNED : BOOLEAN ; + + -- The SYNTHESIS_RETURN attribute is set on a return variable inside a function. + -- Verific will recognize the attribute and replace the function body by a + -- built-in definition for synthesis. + -- The variable on which the attribute is set defines the return (index) range + -- of the function. + -- The IS_SIGNED attribute is set on array parameters of the function that + -- should be interpreted as 2-complement values. + -- MSB is always the left most bit in an array (both for parameters and for + -- return values). + + attribute foreign of NUMERIC_STD: package is "NO C code generation"; +-- ============ A =================== + attribute foreign of "abs"[signed return signed] : function is "ieee_numeric_std_abs"; + attribute foreign of "-"[signed return signed] : function is "ieee_numeric_std_neg"; + + attribute foreign of "+"[signed, signed return signed] : function is "ieee_numeric_std_signed_add"; + attribute foreign of "+"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_add"; + attribute foreign of "+"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_add"; + attribute foreign of "+"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_add"; + attribute foreign of "+"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_add"; + attribute foreign of "+"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_add"; + + attribute foreign of "-"[signed, signed return signed] : function is "ieee_numeric_std_signed_subtract"; + attribute foreign of "-"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_subtract"; + attribute foreign of "-"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_subtract"; + attribute foreign of "-"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_subtract"; + attribute foreign of "-"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_subtract"; + attribute foreign of "-"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_subtract"; + + attribute foreign of "*"[signed, signed return signed] : function is "ieee_numeric_std_signed_multiply"; + attribute foreign of "*"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_multiply"; + attribute foreign of "*"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_multiply"; + attribute foreign of "*"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_multiply"; + attribute foreign of "*"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_multiply"; + attribute foreign of "*"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_multiply"; + + attribute foreign of "/"[signed, signed return signed] : function is "ieee_numeric_std_signed_divide"; + attribute foreign of "/"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_divide"; + attribute foreign of "/"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_divide"; + attribute foreign of "/"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_divide"; + attribute foreign of "/"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_divide"; + attribute foreign of "/"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_divide"; + + attribute foreign of "rem"[signed, signed return signed] : function is "ieee_numeric_std_signed_rem"; + attribute foreign of "rem"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_rem"; + attribute foreign of "rem"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_rem"; + attribute foreign of "rem"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_rem"; + attribute foreign of "rem"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_rem"; + attribute foreign of "rem"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_rem"; + + attribute foreign of "mod"[signed, signed return signed] : function is "ieee_numeric_std_signed_mod"; + attribute foreign of "mod"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_unsigned_mod"; + attribute foreign of "mod"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_nat_mod"; + attribute foreign of "mod"[natural, unsigned return unsigned] : function is "ieee_numeric_std_nat_unsigned_mod"; + attribute foreign of "mod"[signed, integer return signed] : function is "ieee_numeric_std_signed_int_mod"; + attribute foreign of "mod"[integer, signed return signed] : function is "ieee_numeric_std_int_signed_mod"; + +---- ============ C =================== + + attribute foreign of ">"[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_greater"; + attribute foreign of ">"[signed, signed return boolean] : function is "ieee_numeric_std_signed_greater"; + attribute foreign of ">"[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_greater"; + attribute foreign of ">"[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_greater"; + attribute foreign of ">"[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_greater"; + attribute foreign of ">"[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_greater"; + + attribute foreign of "<"[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_less"; + attribute foreign of "<"[signed, signed return boolean] : function is "ieee_numeric_std_signed_less"; + attribute foreign of "<"[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_less"; + attribute foreign of "<"[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_less"; + attribute foreign of "<"[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_less"; + attribute foreign of "<"[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_less"; + + attribute foreign of "<="[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_lequal"; + attribute foreign of "<="[signed, signed return boolean] : function is "ieee_numeric_std_signed_lequal"; + attribute foreign of "<="[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_lequal"; + attribute foreign of "<="[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_lequal"; + attribute foreign of "<="[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_lequal"; + attribute foreign of "<="[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_lequal"; + + attribute foreign of ">="[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_gequal"; + attribute foreign of ">="[signed, signed return boolean] : function is "ieee_numeric_std_signed_gequal"; + attribute foreign of ">="[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_gequal"; + attribute foreign of ">="[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_gequal"; + attribute foreign of ">="[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_gequal"; + attribute foreign of ">="[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_gequal"; + + attribute foreign of "="[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_equal"; + attribute foreign of "="[signed, signed return boolean] : function is "ieee_numeric_std_signed_equal"; + attribute foreign of "="[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_equal"; + attribute foreign of "="[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_equal"; + attribute foreign of "="[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_equal"; + attribute foreign of "="[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_equal"; + + attribute foreign of "/="[unsigned, unsigned return boolean] : function is "ieee_numeric_std_unsigned_nequal"; + attribute foreign of "/="[signed, signed return boolean] : function is "ieee_numeric_std_signed_nequal"; + attribute foreign of "/="[natural, unsigned return boolean] : function is "ieee_numeric_std_nat_unsigned_nequal"; + attribute foreign of "/="[unsigned, natural return boolean] : function is "ieee_numeric_std_unsigned_nat_nequal"; + attribute foreign of "/="[integer, signed return boolean] : function is "ieee_numeric_std_int_signed_nequal"; + attribute foreign of "/="[signed, integer return boolean] : function is "ieee_numeric_std_signed_int_nequal"; + + +-- ============ D =================== + attribute foreign of TO_INTEGER[unsigned return natural] : function is "ieee_numeric_std_unsigned_to_integer"; + attribute foreign of TO_INTEGER[signed return natural] : function is "ieee_numeric_std_signed_to_integer"; + attribute foreign of TO_UNSIGNED[natural, natural return unsigned] : function is "ieee_numeric_std_to_unsigned"; + attribute foreign of TO_SIGNED[integer, natural return signed] : function is "ieee_numeric_std_to_signed"; + +-- ============ L =================== + attribute foreign of "not"[unsigned return unsigned] : function is "ieee_numeric_std_not"; + attribute foreign of "and"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_and"; + attribute foreign of "or"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_or"; + attribute foreign of "nand"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_nand"; + attribute foreign of "nor"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_nor"; + attribute foreign of "xor"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_xor"; + attribute foreign of "xnor"[unsigned, unsigned return unsigned] : function is "ieee_numeric_std_xnor"; + attribute foreign of "not"[signed return signed] : function is "ieee_numeric_std_not"; + attribute foreign of "and"[signed, signed return signed] : function is "ieee_numeric_std_and"; + attribute foreign of "or"[signed, signed return signed] : function is "ieee_numeric_std_or"; + attribute foreign of "nand"[signed, signed return signed] : function is "ieee_numeric_std_nand"; + attribute foreign of "nor"[signed, signed return signed] : function is "ieee_numeric_std_nor"; + attribute foreign of "xor"[signed, signed return signed] : function is "ieee_numeric_std_xor"; + attribute foreign of "xnor"[signed, signed return signed] : function is "ieee_numeric_std_xnor"; + +-- ============ M =================== + attribute foreign of STD_MATCH[std_ulogic, std_ulogic return boolean] : function is "ieee_numeric_std_match_ulogic"; + attribute foreign of STD_MATCH[unsigned, unsigned return boolean] : function is "ieee_numeric_std_match"; + attribute foreign of STD_MATCH[signed, signed return boolean] : function is "ieee_numeric_std_match"; + attribute foreign of STD_MATCH[std_logic_vector, std_logic_vector return boolean] : function is "ieee_numeric_std_match"; + attribute foreign of STD_MATCH[std_ulogic_vector, std_ulogic_vector return boolean] : function is "ieee_numeric_std_match"; + +--============ S ================ + attribute foreign of SHIFT_LEFT[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_shift_left"; + attribute foreign of SHIFT_RIGHT[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_shift_right"; + attribute foreign of SHIFT_LEFT[signed, natural return signed] : function is "ieee_numeric_std_signed_shift_left"; + attribute foreign of SHIFT_RIGHT[signed, natural return signed] : function is "ieee_numeric_std_signed_shift_right"; + attribute foreign of ROTATE_LEFT[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_rotate_left"; + attribute foreign of ROTATE_RIGHT[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_rotate_right"; + attribute foreign of ROTATE_LEFT[signed, natural return signed] : function is "ieee_numeric_std_signed_rotate_left"; + attribute foreign of ROTATE_RIGHT[signed, natural return signed] : function is "ieee_numeric_std_signed_rotate_right"; + attribute foreign of "sll"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_sll"; + attribute foreign of "sll"[signed, natural return signed] : function is "ieee_numeric_std_signed_sll"; + attribute foreign of "srl"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_srl"; + attribute foreign of "srl"[signed, natural return signed] : function is "ieee_numeric_std_signed_srl"; + attribute foreign of "rol"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_rol"; + attribute foreign of "rol"[signed, natural return signed] : function is "ieee_numeric_std_signed_rol"; + attribute foreign of "ror"[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_ror"; + attribute foreign of "ror"[signed, natural return signed] : function is "ieee_numeric_std_signed_ror"; + +--============ R ================ + attribute foreign of RESIZE[unsigned, natural return unsigned] : function is "ieee_numeric_std_unsigned_resize"; + attribute foreign of RESIZE[signed, natural return signed] : function is "ieee_numeric_std_signed_resize"; + +--============Translation functions================ + attribute foreign of TO_01[unsigned, std_logic return unsigned] : function is "ieee_numeric_std_to_01"; + attribute foreign of TO_01[signed, std_logic return signed] : function is "ieee_numeric_std_to_01"; + + +end package NUMERIC_STD; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned-body.vhdl new file mode 100644 index 0000000..da8928f --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned-body.vhdl @@ -0,0 +1,595 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_STD_UNSIGNED package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR +-- : are interpreted as unsigned numbers in vector form. +-- : The leftmost bit is treated as the most significant bit. +-- : This package contains overloaded arithmetic operators on +-- : the STD_ULOGIC_VECTOR type. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library ieee; +use ieee.numeric_std.all; + +package body NUMERIC_STD_UNSIGNED is + + -- Id: A.3 + function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R)); + end function "+"; + + -- Id: A.3R + function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) + R); + end function "+"; + + -- Id: A.3L + function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L + UNSIGNED(R)); + end function "+"; + + -- Id: A.5 + function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) + R); + end function "+"; + + -- Id: A.6 + function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L + UNSIGNED(R)); + end function "+"; + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R)); + end function "-"; + + -- Id: A.9R + function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) - R); + end function "-"; + + -- Id: A.9L + function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L - UNSIGNED(R)); + end function "-"; + + -- Id: A.11 + function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) - R); + end function "-"; + + -- Id: A.12 + function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L - UNSIGNED(R)); + end function "-"; + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R)); + end function "*"; + + -- Id: A.17 + function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) * R); + end function "*"; + + -- Id: A.18 + function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L * UNSIGNED(R)); + end function "*"; + + --============================================================================ + + -- Id: A.21 + function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R)); + end function "/"; + + -- Id: A.23 + function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) / R); + end function "/"; + + -- Id: A.24 + function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L / UNSIGNED(R)); + end function "/"; + + --============================================================================ + + -- Id: A.27 + function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R)); + end function "rem"; + + -- Id: A.29 + function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R); + end function "rem"; + + -- Id: A.30 + function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L rem UNSIGNED(R)); + end function "rem"; + + --============================================================================ + + -- Id: A.33 + function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R)); + end function "mod"; + + -- Id: A.35 + function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R); + end function "mod"; + + -- Id: A.36 + function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (L mod UNSIGNED(R)); + end function "mod"; + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is + begin + return find_leftmost(UNSIGNED(ARG), Y); + end function find_leftmost; + + -- Id: A.41 + function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is + begin + return find_rightmost(UNSIGNED(ARG), Y); + end function find_rightmost; + + --============================================================================ + + -- Id: C.1 + function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) > UNSIGNED(R); + end function ">"; + + -- Id: C.3 + function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L > UNSIGNED(R); + end function ">"; + + -- Id: C.5 + function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) > R; + end function ">"; + + --============================================================================ + + -- Id: C.7 + function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) < UNSIGNED(R); + end function "<"; + + -- Id: C.9 + function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L < UNSIGNED(R); + end function "<"; + + -- Id: C.11 + function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) < R; + end function "<"; + + --============================================================================ + + -- Id: C.13 + function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) <= UNSIGNED(R); + end function "<="; + + -- Id: C.15 + function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L <= UNSIGNED(R); + end function "<="; + + -- Id: C.17 + function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) <= R; + end function "<="; + + --============================================================================ + + -- Id: C.19 + function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) >= UNSIGNED(R); + end function ">="; + + -- Id: C.21 + function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L >= UNSIGNED(R); + end function ">="; + + -- Id: C.23 + function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) >= R; + end function ">="; + + --============================================================================ + + -- Id: C.25 + function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) = UNSIGNED(R); + end function "="; + + -- Id: C.27 + function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L = UNSIGNED(R); + end function "="; + + -- Id: C.29 + function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) = R; + end function "="; + + --============================================================================ + + -- Id: C.31 + function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) /= UNSIGNED(R); + end function "/="; + + -- Id: C.33 + function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is + begin + return L /= UNSIGNED(R); + end function "/="; + + -- Id: C.35 + function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is + begin + return UNSIGNED(L) /= R; + end function "/="; + + --============================================================================ + + -- Id: C.37 + function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R))); + end function MINIMUM; + + -- Id: C.39 + function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R))); + end function MINIMUM; + + -- Id: C.41 + function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R)); + end function MINIMUM; + + --============================================================================ + -- Id: C.43 + function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R))); + end function MAXIMUM; + + -- Id: C.45 + function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R))); + end function MAXIMUM; + + -- Id: C.47 + function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R)); + end function MAXIMUM; + + --============================================================================ + + -- Id: C.49 + function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?> UNSIGNED(R); + end function "?>"; + + -- Id: C.51 + function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?> UNSIGNED(R); + end function "?>"; + + -- Id: C.53 + function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?> R; + end function "?>"; + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?< UNSIGNED(R); + end function "?<"; + + -- Id: C.57 + function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?< UNSIGNED(R); + end function "?<"; + + -- Id: C.59 + function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?< R; + end function "?<"; + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?<= UNSIGNED(R); + end function "?<="; + + -- Id: C.63 + function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?<= UNSIGNED(R); + end function "?<="; + + -- Id: C.65 + function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?<= R; + end function "?<="; + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?>= UNSIGNED(R); + end function "?>="; + + -- Id: C.69 + function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?>= UNSIGNED(R); + end function "?>="; + + -- Id: C.71 + function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?>= R; + end function "?>="; + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?= UNSIGNED(R); + end function "?="; + + -- Id: C.75 + function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?= UNSIGNED(R); + end function "?="; + + -- Id: C.77 + function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?= R; + end function "?="; + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return UNSIGNED(L) ?/= UNSIGNED(R); + end function "?/="; + + -- Id: C.81 + function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is + begin + return L ?/= UNSIGNED(R); + end function "?/="; + + -- Id: C.83 + function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is + begin + return UNSIGNED(L) ?/= R; + end function "?/="; + + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR is + begin + return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT)); + end function SHIFT_LEFT; + + -- Id: S.2 + function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR is + begin + return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT)); + end function SHIFT_RIGHT; + + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR is + begin + return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT)); + end function ROTATE_LEFT; + + -- Id: S.6 + function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR is + begin + return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT)); + end function ROTATE_RIGHT; + + --============================================================================ + + -- Id: S.17 + function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) + return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT); + end function "sla"; + + -- Id: S.19 + function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) + return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT); + end function "sra"; + + --============================================================================ + + -- Id: R.2 + function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL) + return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR ( + RESIZE (ARG => UNSIGNED(ARG), + NEW_SIZE => NEW_SIZE)); + end function RESIZE; + + function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR ( + RESIZE (ARG => UNSIGNED(ARG), + NEW_SIZE => SIZE_RES'length)); + end function RESIZE; + + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is + begin + return TO_INTEGER(UNSIGNED(ARG)); + end function TO_INTEGER; + + -- Id: D.3 + function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG, + SIZE => SIZE)); + end function To_StdLogicVector; + + -- Id: D.5 + function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG, + SIZE => SIZE)); + end function To_StdULogicVector; + + function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) + return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG => ARG, + SIZE => SIZE_RES'length)); + end function To_StdLogicVector; + + function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR is + begin + return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG => ARG, + SIZE => SIZE_RES'length)); + end function To_StdULogicVector; + +end package body NUMERIC_STD_UNSIGNED; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned.vhdl new file mode 100644 index 0000000..4f31e4b --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned.vhdl @@ -0,0 +1,616 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file +-- shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title : Standard VHDL Synthesis Packages +-- : (NUMERIC_STD_UNSIGNED package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This package defines numeric types and arithmetic functions +-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR +-- : are interpreted as unsigned numbers in vector form. +-- : The leftmost bit is treated as the most significant bit. +-- : This package contains overloaded arithmetic operators on +-- : the STD_ULOGIC_VECTOR type. The package also contains +-- : useful type conversions functions, clock detection +-- : functions, and other utility functions. +-- : +-- : If any argument to a function is a null array, a null array +-- : is returned (exceptions, if any, are noted individually). +-- +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1220 $ +-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ +-- -------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package NUMERIC_STD_UNSIGNED is + constant CopyRightNotice : STRING := + "Copyright 2008 IEEE. All rights reserved."; + + -- Id: A.3 + function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0). + -- Result: Adds two UNSIGNED vectors that may be of different lengths. + + -- Id: A.3R + function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR + + -- Id: A.3L + function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Similar to A.3 where L is a one bit UNSIGNED + + -- Id: A.5 + function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0). + -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R. + + -- Id: A.6 + function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0). + -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R. + + --============================================================================ + + -- Id: A.9 + function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0). + -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. + + -- Id: A.9R + function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Similar to A.9 where R is a one bit UNSIGNED + + -- Id: A.9L + function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Similar to A.9 where L is a one bit UNSIGNED + + -- Id: A.11 + function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0). + -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L. + + -- Id: A.12 + function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0). + -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L. + + --============================================================================ + + -- Id: A.15 + function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0). + -- Result: Performs the multiplication operation on two UNSIGNED vectors + -- that may possibly be of different lengths. + + -- Id: A.17 + function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0). + -- Result: Multiplies an UNSIGNED vector, L, with a non-negative + -- INTEGER, R. R is converted to an UNSIGNED vector of + -- SIZE L'LENGTH before multiplication. + + -- Id: A.18 + function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0). + -- Result: Multiplies an UNSIGNED vector, R, with a non-negative + -- INTEGER, L. L is converted to an UNSIGNED vector of + -- SIZE R'LENGTH before multiplication. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "/" operator, a severity level + -- of ERROR is issued. + + -- Id: A.21 + function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. + + -- Id: A.23 + function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.24 + function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "rem" operator, a severity level + -- of ERROR is issued. + + -- Id: A.27 + function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. + + -- Id: A.29 + function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a + -- non-negative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.30 + function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a + -- non-negative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- + -- NOTE: If second argument is zero for "mod" operator, a severity level + -- of ERROR is issued. + + -- Id: A.33 + function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. + + -- Id: A.35 + function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where L is an UNSIGNED vector and R + -- is a non-negative INTEGER. + -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. + + -- Id: A.36 + function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0) + -- Result: Computes "L mod R" where R is an UNSIGNED vector and L + -- is a non-negative INTEGER. + -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. + + --============================================================================ + -- Id: A.39 + function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + -- Id: A.41 + function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER; + -- Result subtype: INTEGER + -- Result: Finds the leftmost occurrence of the value of Y in ARG. + -- Returns the index of the occurrence if it exists, or -1 otherwise. + + --============================================================================ + -- Comparison Operators + --============================================================================ + + -- Id: C.1 + function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.3 + function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.5 + function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.7 + function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.9 + function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.11 + function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.13 + function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.15 + function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.17 + function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.19 + function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.21 + function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.23 + function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.25 + function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.27 + function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.29 + function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.31 + function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.33 + function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is a non-negative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.35 + function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN; + -- Result subtype: BOOLEAN + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a non-negative INTEGER. + + --============================================================================ + + -- Id: C.37 + function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the lesser of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.39 + function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the lesser of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.41 + function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the lesser of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + --============================================================================ + + -- Id: C.43 + function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the greater of two UNSIGNED vectors that may be + -- of different lengths. + + -- Id: C.45 + function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the greater of a nonnegative INTEGER, L, and + -- an UNSIGNED vector, R. + + -- Id: C.47 + function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR + -- Result: Returns the greater of an UNSIGNED vector, L, and + -- a nonnegative INTEGER, R. + + --============================================================================ + -- Id: C.49 + function "?>" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.51 + function "?>" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.53 + function "?>" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L > R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.55 + function "?<" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.57 + function "?<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.59 + function "?<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L < R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.61 + function "?<=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.63 + function "?<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.65 + function "?<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L <= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.67 + function "?>=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.69 + function "?>=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.71 + function "?>=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L >= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.73 + function "?=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.75 + function "?=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.77 + function "?=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L = R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + + -- Id: C.79 + function "?/=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly + -- of different lengths. + + -- Id: C.81 + function "?/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is a nonnegative INTEGER and + -- R is an UNSIGNED vector. + + -- Id: C.83 + function "?/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC; + -- Result subtype: STD_ULOGIC + -- Result: Computes "L /= R" where L is an UNSIGNED vector and + -- R is a nonnegative INTEGER. + + --============================================================================ + -- Shift and Rotate Functions + --============================================================================ + + -- Id: S.1 + function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR; + -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + --============================================================================ + + -- Id: S.5 + function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times. + + -- Id: S.6 + function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) + return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times. + + + --============================================================================ + + ------------------------------------------------------------------------------ + -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.17 + function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + ------------------------------------------------------------------------------ + -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment + -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. + ------------------------------------------------------------------------------ + -- Id: S.19 + function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + + --============================================================================ + -- RESIZE Functions + --============================================================================ + + -- Id: R.2 + function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL) + return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0) + -- Result: Resizes the UNSIGNED vector ARG to the specified size. + -- To create a larger vector, the new [leftmost] bit positions + -- are filled with '0'. When truncating, the leftmost bits + -- are dropped. + + function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0) + + --============================================================================ + -- Conversion Functions + --============================================================================ + + -- Id: D.1 + function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL; + -- Result subtype: NATURAL. Value cannot be negative since parameter is an + -- UNSIGNED vector. + -- Result: Converts the UNSIGNED vector to an INTEGER. + + -- Id: D.3 + function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR; + -- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0) + -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with + -- the specified SIZE. + + function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) + return STD_LOGIC_VECTOR; + -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0) + + alias To_Std_Logic_Vector is + To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR]; + alias To_SLV is + To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR]; + alias To_Std_Logic_Vector is + To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR]; + alias To_SLV is + To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR]; + + -- Id: D.5 + function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR; + -- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0) + -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with + -- the specified SIZE. + + function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR; + -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0) + + alias To_Std_ULogic_Vector is + To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR]; + alias To_SULV is + To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR]; + alias To_Std_ULogic_Vector is + To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR]; + alias To_SULV is + To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR]; + +end package NUMERIC_STD_UNSIGNED; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164-body.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164-body.vhdl new file mode 100644 index 0000000..8772fcd --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164-body.vhdl @@ -0,0 +1,1998 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- Title : Standard multivalue logic package +-- : (STD_LOGIC_1164 package body) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE model standards group (PAR 1164), +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines a standard for designers +-- : to use in describing the interconnection data types +-- : used in vhdl modeling. +-- : +-- Limitation: The logic system defined in this package may +-- : be insufficient for modeling switched transistors, +-- : since such a requirement is out of the scope of this +-- : effort. Furthermore, mathematics, primitives, +-- : timing standards, etc. are considered orthogonal +-- : issues as it relates to this package and are therefore +-- : beyond the scope of this effort. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1.4 $ +-- $Date: 2015/08/13 10:28:07 $ +-- -------------------------------------------------------------------- + +package body std_logic_1164 is + ------------------------------------------------------------------- + -- local types + ------------------------------------------------------------------- + type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC; + type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; + + ------------------------------------------------------------------- + -- resolution function + ------------------------------------------------------------------- + constant resolution_table : stdlogic_table := ( + -- --------------------------------------------------------- + -- | U X 0 1 Z W L H - | | + -- --------------------------------------------------------- + ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | + ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 | + ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 | + ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z | + ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W | + ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L | + ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | + ); + + function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := 'Z'; -- weakest state default + ATTRIBUTE synthesis_return OF result:VARIABLE IS "WIRED_THREE_STATE" ; + begin + -- the test for a single driver is essential otherwise the + -- loop would return 'X' for a single driver of '-' and that + -- would conflict with the value of a single driver unresolved + -- signal. + if (s'length = 1) then return s(s'low); + else + for i in s'range loop + result := resolution_table(result, s(i)); + end loop; + end if; + return result; + end function resolved; + + ------------------------------------------------------------------- + -- tables for logical operations + ------------------------------------------------------------------- + + -- truth table for "and" function + constant and_table : stdlogic_table := ( + -- ---------------------------------------------------- + -- | U X 0 1 Z W L H - | | + -- ---------------------------------------------------- + ('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U | + ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X | + ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 | + ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z | + ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W | + ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H | + ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - | + ); + + -- truth table for "or" function + constant or_table : stdlogic_table := ( + -- ---------------------------------------------------- + -- | U X 0 1 Z W L H - | | + -- ---------------------------------------------------- + ('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U | + ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | + ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 | + ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z | + ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | + ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H | + ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - | + ); + + -- truth table for "xor" function + constant xor_table : stdlogic_table := ( + -- ---------------------------------------------------- + -- | U X 0 1 Z W L H - | | + -- ---------------------------------------------------- + ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | + ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W | + ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | + ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H | + ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | + ); + + -- truth table for "not" function + constant not_table : stdlogic_1d := + -- ------------------------------------------------- + -- | U X 0 1 Z W L H - | + -- ------------------------------------------------- + ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'); + + ------------------------------------------------------------------- + -- overloaded logical operators ( with optimizing hints ) + ------------------------------------------------------------------- + + function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "AND" ; + begin + result := (and_table(l, r)); + return result; + end function "and"; + + function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NAND" ; + begin + result := (not_table (and_table(l, r))); + return result; + end function "nand"; + + function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "OR" ; + begin + result := (or_table(l, r)); + return result; + end function "or"; + + function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOR" ; + begin + result := (not_table (or_table(l, r))); + return result; + end function "nor"; + + function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ; + begin + result := (xor_table(l, r)); + return result; + end function "xor"; + + function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return ux01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XNOR" ; + begin + result := not_table(xor_table(l, r)); + return result; + end function "xnor"; + + function "not" (l : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOT" ; + begin + result := (not_table(l)); + return result; + end function "not"; + + ------------------------------------------------------------------- + -- and + ------------------------------------------------------------------- + function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "AND" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""and"": " + & "arguments of overloaded 'and' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := and_table (lv(i), rv(i)); + end loop; + end if; + return result; + end function "and"; + ------------------------------------------------------------------- + -- nand + ------------------------------------------------------------------- + function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NAND" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""nand"": " + & "arguments of overloaded 'nand' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := not_table(and_table (lv(i), rv(i))); + end loop; + end if; + return result; + end function "nand"; + ------------------------------------------------------------------- + -- or + ------------------------------------------------------------------- + function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "OR" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""or"": " + & "arguments of overloaded 'or' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := or_table (lv(i), rv(i)); + end loop; + end if; + return result; + end function "or"; + ------------------------------------------------------------------- + -- nor + ------------------------------------------------------------------- + function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOR" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""nor"": " + & "arguments of overloaded 'nor' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := not_table(or_table (lv(i), rv(i))); + end loop; + end if; + return result; + end function "nor"; + --------------------------------------------------------------------- + -- xor + ------------------------------------------------------------------- + function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""xor"": " + & "arguments of overloaded 'xor' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := xor_table (lv(i), rv(i)); + end loop; + end if; + return result; + end function "xor"; + ------------------------------------------------------------------- + -- xnor + ------------------------------------------------------------------- + function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XNOR" ; + begin + if (l'length /= r'length) then + assert false + report "STD_LOGIC_1164.""xnor"": " + & "arguments of overloaded 'xnor' operator are not of the same length" + severity failure; + else + for i in result'range loop + result(i) := not_table(xor_table (lv(i), rv(i))); + end loop; + end if; + return result; + end function "xnor"; + ------------------------------------------------------------------- + -- not + ------------------------------------------------------------------- + function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X'); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOT" ; + begin + for i in result'range loop + result(i) := not_table(lv(i)); + end loop; + return result; + end function "not"; + + ------------------------------------------------------------------- + -- and + ------------------------------------------------------------------- + function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "AND" ; + begin + for i in result'range loop + result(i) := and_table (lv(i), r); + end loop; + return result; + end function "and"; + ------------------------------------------------------------------- + function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "AND" ; + begin + for i in result'range loop + result(i) := and_table (l, rv(i)); + end loop; + return result; + end function "and"; + + ------------------------------------------------------------------- + -- nand + ------------------------------------------------------------------- + function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NAND" ; + begin + for i in result'range loop + result(i) := not_table(and_table (lv(i), r)); + end loop; + return result; + end function "nand"; + ------------------------------------------------------------------- + function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NAND" ; + begin + for i in result'range loop + result(i) := not_table(and_table (l, rv(i))); + end loop; + return result; + end function "nand"; + + ------------------------------------------------------------------- + -- or + ------------------------------------------------------------------- + function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "OR" ; + begin + for i in result'range loop + result(i) := or_table (lv(i), r); + end loop; + return result; + end function "or"; + ------------------------------------------------------------------- + function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "OR" ; + begin + for i in result'range loop + result(i) := or_table (l, rv(i)); + end loop; + return result; + end function "or"; + + ------------------------------------------------------------------- + -- nor + ------------------------------------------------------------------- + function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOR" ; + begin + for i in result'range loop + result(i) := not_table(or_table (lv(i), r)); + end loop; + return result; + end function "nor"; + ------------------------------------------------------------------- + function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOR" ; + begin + for i in result'range loop + result(i) := not_table(or_table (l, rv(i))); + end loop; + return result; + end function "nor"; + + ------------------------------------------------------------------- + -- xor + ------------------------------------------------------------------- + function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ; + begin + for i in result'range loop + result(i) := xor_table (lv(i), r); + end loop; + return result; + end function "xor"; + ------------------------------------------------------------------- + function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ; + begin + for i in result'range loop + result(i) := xor_table (l, rv(i)); + end loop; + return result; + end function "xor"; + + ------------------------------------------------------------------- + -- xnor + ------------------------------------------------------------------- + function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XNOR" ; + begin + for i in result'range loop + result(i) := not_table(xor_table (lv(i), r)); + end loop; + return result; + end function "xnor"; + ------------------------------------------------------------------- + function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; + variable result : STD_ULOGIC_VECTOR (1 to r'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XNOR" ; + begin + for i in result'range loop + result(i) := not_table(xor_table (l, rv(i))); + end loop; + return result; + end function "xnor"; + + ------------------------------------------------------------------- + -- and + ------------------------------------------------------------------- + function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '1'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_AND" ; + begin + for i in l'reverse_range loop + result := and_table (l(i), result); + end loop; + return result; + end function "and"; + + ------------------------------------------------------------------- + -- nand + ------------------------------------------------------------------- + function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '1'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_NAND" ; + begin + for i in l'reverse_range loop + result := and_table (l(i), result); + end loop; + return not_table(result); + end function "nand"; + + ------------------------------------------------------------------- + -- or + ------------------------------------------------------------------- + function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '0'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ; + begin + for i in l'reverse_range loop + result := or_table (l(i), result); + end loop; + return result; + end function "or"; + + ------------------------------------------------------------------- + -- nor + ------------------------------------------------------------------- + function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '0'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_NOR" ; + begin + for i in l'reverse_range loop + result := or_table (l(i), result); + end loop; + return not_table(result); + end function "nor"; + + ------------------------------------------------------------------- + -- xor + ------------------------------------------------------------------- + function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '0'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ; + begin + for i in l'reverse_range loop + result := xor_table (l(i), result); + end loop; + return result; + end function "xor"; + + ------------------------------------------------------------------- + -- xnor + ------------------------------------------------------------------- + function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is + variable result : STD_ULOGIC := '0'; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XNOR" ; + begin + for i in l'reverse_range loop + result := xor_table (l(i), result); + end loop; + return not_table(result); + end function "xnor"; + + ------------------------------------------------------------------- + -- shift operators + ------------------------------------------------------------------- + + ------------------------------------------------------------------- + -- sll + ------------------------------------------------------------------- + function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0'); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "SLL" ; + begin + if r >= 0 then + result(1 to l'length - r) := lv(r + 1 to l'length); + else + result := l srl -r; + end if; + return result; + end function "sll"; + + ------------------------------------------------------------------- + -- srl + ------------------------------------------------------------------- + function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0'); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "SRL" ; + begin + if r >= 0 then + result(r + 1 to l'length) := lv(1 to l'length - r); + else + result := l sll -r; + end if; + return result; + end function "srl"; + + ------------------------------------------------------------------- + -- rol + ------------------------------------------------------------------- + function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length); + constant rm : INTEGER := r mod l'length; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROL" ; + begin + if r >= 0 then + result(1 to l'length - rm) := lv(rm + 1 to l'length); + result(l'length - rm + 1 to l'length) := lv(1 to rm); + else + result := l ror -r; + end if; + return result; + end function "rol"; + + ------------------------------------------------------------------- + -- ror + ------------------------------------------------------------------- + function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) + return STD_ULOGIC_VECTOR + is + alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; + variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0'); + constant rm : INTEGER := r mod l'length; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROR" ; + begin + if r >= 0 then + result(rm + 1 to l'length) := lv(1 to l'length - rm); + result(1 to rm) := lv(l'length - rm + 1 to l'length); + else + result := l rol -r; + end if; + return result; + end function "ror"; + + ------------------------------------------------------------------- + -- conversion tables + ------------------------------------------------------------------- + type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01; + type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z; + type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01; + ---------------------------------------------------------- + -- table name : cvt_to_x01 + -- + -- parameters : + -- in : std_ulogic -- some logic value + -- returns : x01 -- state value of logic value + -- purpose : to convert state-strength to state only + -- + -- example : if (cvt_to_x01 (input_signal) = '1' ) then ... + -- + ---------------------------------------------------------- + constant cvt_to_x01 : logic_x01_table := ( + 'X', -- 'U' + 'X', -- 'X' + '0', -- '0' + '1', -- '1' + 'X', -- 'Z' + 'X', -- 'W' + '0', -- 'L' + '1', -- 'H' + 'X' -- '-' + ); + + ---------------------------------------------------------- + -- table name : cvt_to_x01z + -- + -- parameters : + -- in : std_ulogic -- some logic value + -- returns : x01z -- state value of logic value + -- purpose : to convert state-strength to state only + -- + -- example : if (cvt_to_x01z (input_signal) = '1' ) then ... + -- + ---------------------------------------------------------- + constant cvt_to_x01z : logic_x01z_table := ( + 'X', -- 'U' + 'X', -- 'X' + '0', -- '0' + '1', -- '1' + 'Z', -- 'Z' + 'X', -- 'W' + '0', -- 'L' + '1', -- 'H' + 'X' -- '-' + ); + + ---------------------------------------------------------- + -- table name : cvt_to_ux01 + -- + -- parameters : + -- in : std_ulogic -- some logic value + -- returns : ux01 -- state value of logic value + -- purpose : to convert state-strength to state only + -- + -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ... + -- + ---------------------------------------------------------- + constant cvt_to_ux01 : logic_ux01_table := ( + 'U', -- 'U' + 'X', -- 'X' + '0', -- '0' + '1', -- '1' + 'X', -- 'Z' + 'X', -- 'W' + '0', -- 'L' + '1', -- 'H' + 'X' -- '-' + ); + + ------------------------------------------------------------------- + -- conversion functions + ------------------------------------------------------------------- + function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is + VARIABLE result : BIT ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case s is + when '0' | 'L' => result := ('0'); + when '1' | 'H' => result := ('1'); + when others => result := xmap; + end case; + RETURN result ; + end function To_bit; + -------------------------------------------------------------------- + function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR is + alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; + variable result : BIT_VECTOR (s'length-1 downto 0); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case sv(i) is + when '0' | 'L' => result(i) := '0'; + when '1' | 'H' => result(i) := '1'; + when others => result(i) := xmap; + end case; + end loop; + return result; + end function To_bitvector; + -------------------------------------------------------------------- + function To_StdULogic (b : BIT) return STD_ULOGIC is + VARIABLE result : std_ulogic ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case b is + when '0' => result := '0'; + when '1' => result := '1'; + end case; + RETURN result ; + end function To_StdULogic; + -------------------------------------------------------------------- + function To_StdLogicVector (b : BIT_VECTOR) + return STD_LOGIC_VECTOR + is + alias bv : BIT_VECTOR (b'length-1 downto 0) is b; + variable result : STD_LOGIC_VECTOR (b'length-1 downto 0); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case bv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end function To_StdLogicVector; + -------------------------------------------------------------------- + function To_StdLogicVector (s : STD_ULOGIC_VECTOR) + return STD_LOGIC_VECTOR + is + alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; + variable result : STD_LOGIC_VECTOR (s'length-1 downto 0); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := sv(i); + end loop; + return result; + end function To_StdLogicVector; + -------------------------------------------------------------------- + function To_StdULogicVector (b : BIT_VECTOR) + return STD_ULOGIC_VECTOR + is + alias bv : BIT_VECTOR (b'length-1 downto 0) is b; + variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case bv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end function To_StdULogicVector; + -------------------------------------------------------------------- + function To_StdULogicVector (s : STD_LOGIC_VECTOR) + return STD_ULOGIC_VECTOR + is + alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s; + variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := sv(i); + end loop; + return result; + end function To_StdULogicVector; + + ------------------------------------------------------------------- + -- strength strippers and type convertors + ------------------------------------------------------------------- + -- to_01 + ------------------------------------------------------------------- + function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0') + return STD_ULOGIC_VECTOR + is + variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0); + variable BAD_ELEMENT : BOOLEAN := false; + alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for I in RESULT'range loop + case XS(I) is + when '0' | 'L' => RESULT(I) := '0'; + when '1' | 'H' => RESULT(I) := '1'; + when others => BAD_ELEMENT := true; + end case; + end loop; + if BAD_ELEMENT then + for I in RESULT'range loop + RESULT(I) := XMAP; -- standard fixup + end loop; + end if; + return RESULT; + end function TO_01; + ------------------------------------------------------------------- + function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is + VARIABLE result : std_ulogic ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case s is + when '0' | 'L' => result := '0'; + when '1' | 'H' => result := '1'; + when others => result := xmap; + end case; + return RESULT; + end function TO_01; + ------------------------------------------------------------------- + function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0') + return STD_ULOGIC_VECTOR + is + variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0); + alias XS : BIT_VECTOR(s'length-1 downto 0) is s; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for I in RESULT'range loop + case XS(I) is + when '0' => RESULT(I) := '0'; + when '1' => RESULT(I) := '1'; + end case; + end loop; + return RESULT; + end function TO_01; + ------------------------------------------------------------------- + function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is + VARIABLE result : std_ulogic ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case s is + when '0' => result := '0'; + when '1' => result := '1'; + end case; + RETURN result ; + end function TO_01; + ------------------------------------------------------------------- + -- to_x01 + ------------------------------------------------------------------- + function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; + variable result : STD_ULOGIC_VECTOR (1 to s'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := cvt_to_x01 (sv(i)); + end loop; + return result; + end function To_X01; + -------------------------------------------------------------------- + function To_X01 (s : STD_ULOGIC) return X01 is + VARIABLE result : X01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + result := (cvt_to_x01(s)); + return result ; + end function To_X01; + -------------------------------------------------------------------- + function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is + alias bv : BIT_VECTOR (1 to b'length) is b; + variable result : STD_ULOGIC_VECTOR (1 to b'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case bv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end function To_X01; + -------------------------------------------------------------------- + function To_X01 (b : BIT) return X01 is + VARIABLE result : X01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case b is + when '0' => result := ('0'); + when '1' => result := ('1'); + end case; + return result ; + end function To_X01; + -------------------------------------------------------------------- + -- to_x01z + ------------------------------------------------------------------- + function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; + variable result : STD_ULOGIC_VECTOR (1 to s'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := cvt_to_x01z (sv(i)); + end loop; + return result; + end function To_X01Z; + -------------------------------------------------------------------- + function To_X01Z (s : STD_ULOGIC) return X01Z is + VARIABLE result : X01Z ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + result := (cvt_to_x01z(s)); + return result ; + end function To_X01Z; + -------------------------------------------------------------------- + function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is + alias bv : BIT_VECTOR (1 to b'length) is b; + variable result : STD_ULOGIC_VECTOR (1 to b'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case bv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end function To_X01Z; + -------------------------------------------------------------------- + function To_X01Z (b : BIT) return X01Z is + VARIABLE result : X01Z ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case b is + when '0' => result := ('0'); + when '1' => result := ('1'); + end case; + return result ; + end function To_X01Z; + -------------------------------------------------------------------- + -- to_ux01 + ------------------------------------------------------------------- + function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; + variable result : STD_ULOGIC_VECTOR (1 to s'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := cvt_to_ux01 (sv(i)); + end loop; + return result; + end function To_UX01; + -------------------------------------------------------------------- + function To_UX01 (s : STD_ULOGIC) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + result := (cvt_to_ux01(s)); + return result ; + end function To_UX01; + -------------------------------------------------------------------- + function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is + alias bv : BIT_VECTOR (1 to b'length) is b; + variable result : STD_ULOGIC_VECTOR (1 to b'length); + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + case bv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end function To_UX01; + -------------------------------------------------------------------- + function To_UX01 (b : BIT) return UX01 is + VARIABLE result : UX01 ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + case b is + when '0' => result := ('0'); + when '1' => result := ('1'); + end case; + return result ; + end function To_UX01; + + function "??" (l : STD_ULOGIC) return BOOLEAN is + begin + return l = '1' or l = 'H'; + end function "??"; + + ------------------------------------------------------------------- + -- edge detection + ------------------------------------------------------------------- + function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is + -- Verific synthesizes this function from the native source code + begin + return (s'event and (To_X01(s) = '1') and + (To_X01(s'last_value) = '0')); + end function rising_edge; + + function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is + -- Verific synthesizes this function from the native source code + begin + return (s'event and (To_X01(s) = '0') and + (To_X01(s'last_value) = '1')); + end function falling_edge; + + ------------------------------------------------------------------- + -- object contains an unknown + ------------------------------------------------------------------- + function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is + -- Verific synthesizes this function from the native source code + begin + for i in s'range loop + case s(i) is + when 'U' | 'X' | 'Z' | 'W' | '-' => return true; + when others => null; + end case; + end loop; + return false; + end function Is_X; + -------------------------------------------------------------------- + function Is_X (s : STD_ULOGIC) return BOOLEAN is + -- Verific synthesizes this function from the native source code + begin + case s is + when 'U' | 'X' | 'Z' | 'W' | '-' => return true; + when others => null; + end case; + return false; + end function Is_X; + + ------------------------------------------------------------------- + -- string conversion and write operations + ------------------------------------------------------------------- + + function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is + constant result_length : NATURAL := (value'length+2)/3; + variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length); + variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3); + variable result : STRING(1 to result_length); + variable tri : STD_ULOGIC_VECTOR(1 to 3); + begin + if value (value'left) = 'Z' then + pad := (others => 'Z'); + else + pad := (others => '0'); + end if; + padded_value := pad & value; + for i in 1 to result_length loop + tri := To_X01Z(padded_value(3*i-2 to 3*i)); + case tri is + when o"0" => result(i) := '0'; + when o"1" => result(i) := '1'; + when o"2" => result(i) := '2'; + when o"3" => result(i) := '3'; + when o"4" => result(i) := '4'; + when o"5" => result(i) := '5'; + when o"6" => result(i) := '6'; + when o"7" => result(i) := '7'; + when "ZZZ" => result(i) := 'Z'; + when others => result(i) := 'X'; + end case; + end loop; + return result; + end function to_ostring; + + function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is + constant result_length : NATURAL := (value'length+3)/4; + variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length); + variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4); + variable result : STRING(1 to result_length); + variable quad : STD_ULOGIC_VECTOR(1 to 4); + begin + if value (value'left) = 'Z' then + pad := (others => 'Z'); + else + pad := (others => '0'); + end if; + padded_value := pad & value; + for i in 1 to result_length loop + quad := To_X01Z(padded_value(4*i-3 to 4*i)); + case quad is + when x"0" => result(i) := '0'; + when x"1" => result(i) := '1'; + when x"2" => result(i) := '2'; + when x"3" => result(i) := '3'; + when x"4" => result(i) := '4'; + when x"5" => result(i) := '5'; + when x"6" => result(i) := '6'; + when x"7" => result(i) := '7'; + when x"8" => result(i) := '8'; + when x"9" => result(i) := '9'; + when x"A" => result(i) := 'A'; + when x"B" => result(i) := 'B'; + when x"C" => result(i) := 'C'; + when x"D" => result(i) := 'D'; + when x"E" => result(i) := 'E'; + when x"F" => result(i) := 'F'; + when "ZZZZ" => result(i) := 'Z'; + when others => result(i) := 'X'; + end case; + end loop; + return result; + end function to_hstring; + + -- Type and constant definitions used to map STD_ULOGIC values + -- into/from character values. + type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); + type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; + type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; + type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; + constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; + constant char_to_MVL9 : MVL9_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); + constant char_to_MVL9plus : MVL9plus_indexed_by_char := + ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', + 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); + + constant NBSP : CHARACTER := CHARACTER'val(160); -- space character + + -- purpose: Skips white space + procedure skip_whitespace ( + L : inout LINE) is + variable readOk : BOOLEAN; + variable c : CHARACTER; + begin + while L /= null and L.all'length /= 0 loop + if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then + read (l, c, readOk); + else + exit; + end if; + end loop; + end procedure skip_whitespace; + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; + GOOD : out BOOLEAN) is + variable c : CHARACTER; + variable readOk : BOOLEAN; + ATTRIBUTE synthesis_return OF L:variable IS "read" ; + -- verific synthesis read + begin + VALUE := 'U'; -- initialize to a "U" + Skip_whitespace (L); + read (l, c, readOk); + if not readOk then + good := false; + else + if char_to_MVL9plus(c) = error then + good := false; + else + VALUE := char_to_MVL9(c); + good := true; + end if; + end if; + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; + GOOD : out BOOLEAN) is + variable m : STD_ULOGIC; + variable c : CHARACTER; + variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1); + variable readOk : BOOLEAN; + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "read" ; + -- verific synthesis read + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + read (l, c, readOk); + i := 0; + good := true; + while i < VALUE'length loop + if not readOk then -- Bail out if there was a bad read + good := false; + return; + elsif c = '_' then + if i = 0 then + good := false; -- Begins with an "_" + return; + elsif lastu then + good := false; -- "__" detected + return; + else + lastu := true; + end if; + elsif (char_to_MVL9plus(c) = error) then + good := false; -- Illegal character + return; + else + mv(i) := char_to_MVL9(c); + i := i + 1; + if i > mv'high then -- reading done + VALUE := mv; + return; + end if; + lastu := false; + end if; + read(L, c, readOk); + end loop; + else + good := true; -- read into a null array + end if; + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is + variable c : CHARACTER; + variable readOk : BOOLEAN; + ATTRIBUTE synthesis_return OF L:variable IS "read" ; + -- verific synthesis read + begin + VALUE := 'U'; -- initialize to a "U" + Skip_whitespace (L); + read (l, c, readOk); + if not readOk then + report "STD_LOGIC_1164.READ(STD_ULOGIC) " + & "End of string encountered" + severity error; + return; + elsif char_to_MVL9plus(c) = error then + report + "STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" & + c & "' read, expected STD_ULOGIC literal." + severity error; + else + VALUE := char_to_MVL9(c); + end if; + end procedure READ; + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is + variable m : STD_ULOGIC; + variable c : CHARACTER; + variable readOk : BOOLEAN; + variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1); + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "read" ; + -- verific synthesis read + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then -- non Null input string + read (l, c, readOk); + i := 0; + while i < VALUE'length loop + if readOk = false then -- Bail out if there was a bad read + report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) " + & "End of string encountered" + severity error; + return; + elsif c = '_' then + if i = 0 then + report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) " + & "String begins with an ""_""" severity error; + return; + elsif lastu then + report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + elsif char_to_MVL9plus(c) = error then + report + "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" & + c & "' read, expected STD_ULOGIC literal." + severity error; + return; + else + mv(i) := char_to_MVL9(c); + i := i + 1; + if i > mv'high then + VALUE := mv; + return; + end if; + lastu := false; + end if; + read(L, c, readOk); + end loop; + end if; + end procedure READ; + + procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + ATTRIBUTE synthesis_return OF L:variable IS "write" ; + -- verific synthesis write + begin + write(l, MVL9_to_char(VALUE), justified, field); + end procedure WRITE; + + procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + variable s : STRING(1 to VALUE'length); + alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE; + ATTRIBUTE synthesis_return OF L:variable IS "write" ; + -- verific synthesis write + begin + for i in 1 to VALUE'length loop + s(i) := MVL9_to_char(m(i)); + end loop; + write(l, s, justified, field); + end procedure WRITE; + + procedure Char2TriBits (C : in CHARACTER; + RESULT : out STD_ULOGIC_VECTOR(2 downto 0); + GOOD : out BOOLEAN; + ISSUE_ERROR : in BOOLEAN) is + begin + case c is + when '0' => result := o"0"; good := true; + when '1' => result := o"1"; good := true; + when '2' => result := o"2"; good := true; + when '3' => result := o"3"; good := true; + when '4' => result := o"4"; good := true; + when '5' => result := o"5"; good := true; + when '6' => result := o"6"; good := true; + when '7' => result := o"7"; good := true; + when 'Z' => result := "ZZZ"; good := true; + when 'X' => result := "XXX"; good := true; + when others => + assert not ISSUE_ERROR + report + "STD_LOGIC_1164.OREAD Error: Read a '" & c & + "', expected an Octal character (0-7)." + severity error; + good := false; + end case; + end procedure Char2TriBits; + + procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; + GOOD : out BOOLEAN) is + variable ok : BOOLEAN; + variable c : CHARACTER; + constant ne : INTEGER := (VALUE'length+2)/3; + constant pad : INTEGER := ne*3 - VALUE'length; + variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1); + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "oread" ; + -- verific synthesis oread + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + read (l, c, ok); + i := 0; + while i < ne loop + -- Bail out if there was a bad read + if not ok then + good := false; + return; + elsif c = '_' then + if i = 0 then + good := false; -- Begins with an "_" + return; + elsif lastu then + good := false; -- "__" detected + return; + else + lastu := true; + end if; + else + Char2TriBits(c, sv(3*i to 3*i+2), ok, false); + if not ok then + good := false; + return; + end if; + i := i + 1; + lastu := false; + end if; + if i < ne then + read(L, c, ok); + end if; + end loop; + if or (sv (0 to pad-1)) = '1' then + good := false; -- vector was truncated. + else + good := true; + VALUE := sv (pad to sv'high); + end if; + else + good := true; -- read into a null array + end if; + end procedure OREAD; + + procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is + variable c : CHARACTER; + variable ok : BOOLEAN; + constant ne : INTEGER := (VALUE'length+2)/3; + constant pad : INTEGER := ne*3 - VALUE'length; + variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1); + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "oread" ; + -- verific synthesis oread + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + read (l, c, ok); + i := 0; + while i < ne loop + -- Bail out if there was a bad read + if not ok then + report "STD_LOGIC_1164.OREAD " + & "End of string encountered" + severity error; + return; + elsif c = '_' then + if i = 0 then + report "STD_LOGIC_1164.OREAD " + & "String begins with an ""_""" severity error; + return; + elsif lastu then + report "STD_LOGIC_1164.OREAD " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + else + Char2TriBits(c, sv(3*i to 3*i+2), ok, true); + if not ok then + return; + end if; + i := i + 1; + lastu := false; + end if; + if i < ne then + read(L, c, ok); + end if; + end loop; + if or (sv (0 to pad-1)) = '1' then + report "STD_LOGIC_1164.OREAD Vector truncated" + severity error; + else + VALUE := sv (pad to sv'high); + end if; + end if; + end procedure OREAD; + + procedure Char2QuadBits (C : CHARACTER; + RESULT : out STD_ULOGIC_VECTOR(3 downto 0); + GOOD : out BOOLEAN; + ISSUE_ERROR : in BOOLEAN) is + begin + case c is + when '0' => result := x"0"; good := true; + when '1' => result := x"1"; good := true; + when '2' => result := x"2"; good := true; + when '3' => result := x"3"; good := true; + when '4' => result := x"4"; good := true; + when '5' => result := x"5"; good := true; + when '6' => result := x"6"; good := true; + when '7' => result := x"7"; good := true; + when '8' => result := x"8"; good := true; + when '9' => result := x"9"; good := true; + when 'A' | 'a' => result := x"A"; good := true; + when 'B' | 'b' => result := x"B"; good := true; + when 'C' | 'c' => result := x"C"; good := true; + when 'D' | 'd' => result := x"D"; good := true; + when 'E' | 'e' => result := x"E"; good := true; + when 'F' | 'f' => result := x"F"; good := true; + when 'Z' => result := "ZZZZ"; good := true; + when 'X' => result := "XXXX"; good := true; + when others => + assert not ISSUE_ERROR + report + "STD_LOGIC_1164.HREAD Error: Read a '" & c & + "', expected a Hex character (0-F)." + severity error; + good := false; + end case; + end procedure Char2QuadBits; + + procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; + GOOD : out BOOLEAN) is + variable ok : BOOLEAN; + variable c : CHARACTER; + constant ne : INTEGER := (VALUE'length+3)/4; + constant pad : INTEGER := ne*4 - VALUE'length; + variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1); + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "hread" ; + -- verific synthesis hread + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then + read (l, c, ok); + i := 0; + while i < ne loop + -- Bail out if there was a bad read + if not ok then + good := false; + return; + elsif c = '_' then + if i = 0 then + good := false; -- Begins with an "_" + return; + elsif lastu then + good := false; -- "__" detected + return; + else + lastu := true; + end if; + else + Char2QuadBits(c, sv(4*i to 4*i+3), ok, false); + if not ok then + good := false; + return; + end if; + i := i + 1; + lastu := false; + end if; + if i < ne then + read(L, c, ok); + end if; + end loop; + if or (sv (0 to pad-1)) = '1' then + good := false; -- vector was truncated. + else + good := true; + VALUE := sv (pad to sv'high); + end if; + else + good := true; -- Null input string, skips whitespace + end if; + end procedure HREAD; + + procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is + variable ok : BOOLEAN; + variable c : CHARACTER; + constant ne : INTEGER := (VALUE'length+3)/4; + constant pad : INTEGER := ne*4 - VALUE'length; + variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1); + variable i : INTEGER; + variable lastu : BOOLEAN := false; -- last character was an "_" + ATTRIBUTE synthesis_return OF L:variable IS "hread" ; + -- verific synthesis hread + begin + VALUE := (VALUE'range => 'U'); -- initialize to a "U" + Skip_whitespace (L); + if VALUE'length > 0 then -- non Null input string + read (l, c, ok); + i := 0; + while i < ne loop + -- Bail out if there was a bad read + if not ok then + report "STD_LOGIC_1164.HREAD " + & "End of string encountered" + severity error; + return; + end if; + if c = '_' then + if i = 0 then + report "STD_LOGIC_1164.HREAD " + & "String begins with an ""_""" severity error; + return; + elsif lastu then + report "STD_LOGIC_1164.HREAD " + & "Two underscores detected in input string ""__""" + severity error; + return; + else + lastu := true; + end if; + else + Char2QuadBits(c, sv(4*i to 4*i+3), ok, true); + if not ok then + return; + end if; + i := i + 1; + lastu := false; + end if; + if i < ne then + read(L, c, ok); + end if; + end loop; + if or (sv (0 to pad-1)) = '1' then + report "STD_LOGIC_1164.HREAD Vector truncated" + severity error; + else + VALUE := sv (pad to sv'high); + end if; + end if; + end procedure HREAD; + + procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + ATTRIBUTE synthesis_return OF L:variable IS "owrite" ; + -- verific synthesis owrite + begin + write (L, to_ostring(VALUE), JUSTIFIED, FIELD); + end procedure OWRITE; + + procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is + ATTRIBUTE synthesis_return OF L:variable IS "hwrite" ; + -- verific synthesis hwrite + begin + write (L, to_hstring (VALUE), JUSTIFIED, FIELD); + end procedure HWRITE; + + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + + ------------------------------------------------------------------- + FUNCTION "and" ( l,r : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + ALIAS rv : std_logic_vector_93 ( 1 TO r'LENGTH ) IS r ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "AND" ; + BEGIN + IF ( l'LENGTH /= r'LENGTH ) THEN + ASSERT FALSE + REPORT "arguments of overloaded 'and' operator are not of the same length" + SEVERITY FAILURE ; + ELSE + FOR i IN result'RANGE LOOP + result(i) := and_table (lv(i), rv(i)) ; + END LOOP ; + END IF ; + RETURN result ; + END "and" ; + ------------------------------------------------------------------- + FUNCTION "nand" ( l,r : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + ALIAS rv : std_logic_vector_93 ( 1 TO r'LENGTH ) IS r ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NAND" ; + BEGIN + IF ( l'LENGTH /= r'LENGTH ) THEN + ASSERT FALSE + REPORT "arguments of overloaded 'nand' operator are not of the same length" + SEVERITY FAILURE ; + ELSE + FOR i IN result'RANGE LOOP + result(i) := not_table(and_table (lv(i), rv(i))) ; + END LOOP ; + END IF ; + RETURN result ; + END "nand" ; + ------------------------------------------------------------------- + FUNCTION "or" ( l,r : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + ALIAS rv : std_logic_vector_93 ( 1 TO r'LENGTH ) IS r ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "OR" ; + BEGIN + IF ( l'LENGTH /= r'LENGTH ) THEN + ASSERT FALSE + REPORT "arguments of overloaded 'or' operator are not of the same length" + SEVERITY FAILURE ; + ELSE + FOR i IN result'RANGE LOOP + result(i) := or_table (lv(i), rv(i)) ; + END LOOP ; + END IF ; + RETURN result ; + END "or" ; + ------------------------------------------------------------------- + FUNCTION "nor" ( l,r : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + ALIAS rv : std_logic_vector_93 ( 1 TO r'LENGTH ) IS r ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOR" ; + BEGIN + IF ( l'LENGTH /= r'LENGTH ) THEN + ASSERT FALSE + REPORT "arguments of overloaded 'nor' operator are not of the same length" + SEVERITY FAILURE ; + ELSE + FOR i IN result'RANGE LOOP + result(i) := not_table(or_table (lv(i), rv(i))) ; + END LOOP ; + END IF ; + RETURN result ; + END "nor" ; + ------------------------------------------------------------------- + FUNCTION "xor" ( l,r : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + ALIAS rv : std_logic_vector_93 ( 1 TO r'LENGTH ) IS r ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ; + BEGIN + IF ( l'LENGTH /= r'LENGTH ) THEN + ASSERT FALSE + REPORT "arguments of overloaded 'xor' operator are not of the same length" + SEVERITY FAILURE ; + ELSE + FOR i IN result'RANGE LOOP + result(i) := xor_table (lv(i), rv(i)) ; + END LOOP ; + END IF ; + RETURN result ; + END "xor" ; + ----------------------------------------------------------------------- + function "xnor" ( l,r : std_logic_vector_93 ) return std_logic_vector_93 is + alias lv : std_logic_vector_93 ( 1 to l'length ) is l ; + alias rv : std_logic_vector_93 ( 1 to r'length ) is r ; + variable result : std_logic_vector_93 ( 1 to l'length ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "XNOR" ; + begin + if ( l'length /= r'length ) then + assert false + report "arguments of overloaded 'xnor' operator are not of the same length" + severity failure ; + else + for i in result'range loop + result(i) := not_table(xor_table (lv(i), rv(i))) ; + end loop ; + end if ; + return result ; + end "xnor" ; + ------------------------------------------------------------------- + FUNCTION "not" ( l : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS lv : std_logic_vector_93 ( 1 TO l'LENGTH ) IS l ; + VARIABLE result : std_logic_vector_93 ( 1 TO l'LENGTH ) := (OTHERS => 'X') ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOT" ; + BEGIN + FOR i IN result'RANGE LOOP + result(i) := not_table( lv(i) ) ; + END LOOP ; + RETURN result ; + END ; + -------------------------------------------------------------------- + FUNCTION To_bitvector ( s : std_logic_vector_93 ; xmap : BIT := '0') RETURN BIT_VECTOR IS + ALIAS sv : std_logic_vector_93 ( s'LENGTH-1 DOWNTO 0 ) IS s ; + VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + CASE sv(i) IS + WHEN '0' | 'L' => result(i) := '0' ; + WHEN '1' | 'H' => result(i) := '1' ; + WHEN OTHERS => result(i) := xmap ; + END CASE ; + END LOOP ; + RETURN result ; + END ; + ------------------------------------------------------------------- + FUNCTION To_X01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS sv : std_logic_vector_93 ( 1 TO s'LENGTH ) IS s ; + VARIABLE result : std_logic_vector_93 ( 1 TO s'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + result(i) := cvt_to_x01 (sv(i)) ; + END LOOP ; + RETURN result ; + END ; + -------------------------------------------------------------------- + FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 IS + ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b ; + VARIABLE result : std_logic_vector_93 ( 1 TO b'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + CASE bv(i) IS + WHEN '0' => result(i) := '0' ; + WHEN '1' => result(i) := '1' ; + END CASE ; + END LOOP ; + RETURN result ; + END ; + ------------------------------------------------------------------- + FUNCTION To_X01Z ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS sv : std_logic_vector_93 ( 1 TO s'LENGTH ) IS s ; + VARIABLE result : std_logic_vector_93 ( 1 TO s'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + result(i) := cvt_to_x01z (sv(i)) ; + END LOOP ; + RETURN result ; + END ; + -------------------------------------------------------------------- + FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector_93 IS + ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b ; + VARIABLE result : std_logic_vector_93 ( 1 TO b'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + CASE bv(i) IS + WHEN '0' => result(i) := '0' ; + WHEN '1' => result(i) := '1' ; + END CASE ; + END LOOP ; + RETURN result ; + END ; + ------------------------------------------------------------------- + FUNCTION To_UX01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 IS + ALIAS sv : std_logic_vector_93 ( 1 TO s'LENGTH ) IS s ; + VARIABLE result : std_logic_vector_93 ( 1 TO s'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + result(i) := cvt_to_ux01 (sv(i)) ; + END LOOP ; + RETURN result ; + END ; + -------------------------------------------------------------------- + FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 IS + ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b ; + VARIABLE result : std_logic_vector_93 ( 1 TO b'LENGTH ) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + BEGIN + FOR i IN result'RANGE LOOP + CASE bv(i) IS + WHEN '0' => result(i) := '0' ; + WHEN '1' => result(i) := '1' ; + END CASE ; + END LOOP ; + RETURN result ; + END ; + -------------------------------------------------------------------- + FUNCTION Is_X ( s : std_logic_vector_93 ) RETURN BOOLEAN IS + -- Verific synthesizes this function from the native source code + VARIABLE result : std_logic_vector_93 ( 1 TO s'LENGTH ) ; + BEGIN + FOR i IN s'RANGE LOOP + CASE s(i) IS + WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE ; + WHEN OTHERS => NULL ; + END CASE ; + END LOOP ; + RETURN FALSE ; + END ; + -------------------------------------------------------------------- + function To_StdULogicVector (s : STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR is + alias sv : STD_LOGIC_VECTOR_93 (s'length-1 downto 0) is s ; + variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := sv(i) ; + end loop ; + return result ; + end function To_StdULogicVector ; + -------------------------------------------------------------------- + function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93 is + alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s ; + variable result : STD_LOGIC_VECTOR_93 (s'length-1 downto 0) ; + ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ; + begin + for i in result'range loop + result(i) := sv(i) ; + end loop ; + return result ; + end function To_StdLogicVector ; + -------------------------------------------------------------------- + procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + READ(L, value_temp) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure READ ; + -------------------------------------------------------------------- + procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + READ(L, value_temp, GOOD) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure READ ; + -------------------------------------------------------------------- + procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is + begin + WRITE(L, To_StdULogicVector(VALUE), JUSTIFIED, FIELD) ; + end procedure WRITE ; + -------------------------------------------------------------------- + + procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + HREAD(L, value_temp) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure HREAD ; + -------------------------------------------------------------------- + procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + HREAD(L, value_temp, GOOD) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure HREAD ; + -------------------------------------------------------------------- + procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is + begin + HWRITE(L, To_StdULogicVector(VALUE), JUSTIFIED, FIELD) ; + end procedure HWRITE ; + -------------------------------------------------------------------- + + procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + OREAD(L, value_temp) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure OREAD ; + -------------------------------------------------------------------- + procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN) is + variable value_temp : STD_ULOGIC_VECTOR (VALUE'length-1 downto 0) ; + begin + OREAD(L, value_temp, GOOD) ; + VALUE := To_StdLogicVector(value_temp) ; + end procedure OREAD ; + -------------------------------------------------------------------- + procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is + begin + OWRITE(L, To_StdULogicVector(VALUE), JUSTIFIED, FIELD) ; + end procedure OWRITE ; + -------------------------------------------------------------------- + + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + +end package body std_logic_1164; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164.vhdl new file mode 100644 index 0000000..cb5b9d6 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164.vhdl @@ -0,0 +1,369 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- Title : Standard multivalue logic package +-- : (STD_LOGIC_1164 package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: IEEE model standards group (PAR 1164), +-- : Accellera VHDL-TC, and IEEE P1076 Working Group +-- : +-- Purpose : This packages defines a standard for designers +-- : to use in describing the interconnection data types +-- : used in vhdl modeling. +-- : +-- Limitation: The logic system defined in this package may +-- : be insufficient for modeling switched transistors, +-- : since such a requirement is out of the scope of this +-- : effort. Furthermore, mathematics, primitives, +-- : timing standards, etc. are considered orthogonal +-- : issues as it relates to this package and are therefore +-- : beyond the scope of this effort. +-- : +-- Note : This package may be modified to include additional data +-- : required by tools, but it must in no way change the +-- : external interfaces or simulation behavior of the +-- : description. It is permissible to add comments and/or +-- : attributes to the package declarations, but not to change +-- : or delete any original lines of the package declaration. +-- : The package body may be changed only in accordance with +-- : the terms of Clause 16 of this standard. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1.5 $ +-- $Date: 2016/04/08 07:56:22 $ +-- -------------------------------------------------------------------- + +use STD.TEXTIO.all; + +package std_logic_1164 is + + ------------------------------------------------------------------- + -- logic state system (unresolved) + ------------------------------------------------------------------- + type STD_ULOGIC is ( 'U', -- Uninitialized + 'X', -- Forcing Unknown + '0', -- Forcing 0 + '1', -- Forcing 1 + 'Z', -- High Impedance + 'W', -- Weak Unknown + 'L', -- Weak 0 + 'H', -- Weak 1 + '-' -- Don't care + ); + + ------------------------------------------------------------------- + -- Directives for synthesis of std_ulogic. + -- Declare the type encoding attribute and set the value for std_ulogic + -- Directives for the resolution function and all other function are + -- in the package body + ------------------------------------------------------------------- + ATTRIBUTE logic_type_encoding : string ; + ATTRIBUTE logic_type_encoding of std_ulogic:type is + -- ('U','X','0','1','Z','W','L','H','-') + ('X','X','0','1','Z','X','0','1','X') ; + + ------------------------------------------------------------------- + -- Declare the synthesis-directive attribute; to be set on + -- basic functions that are difficult for synthesis + ------------------------------------------------------------------- + ATTRIBUTE synthesis_return : string ; + ATTRIBUTE is_signed : boolean ; + + ------------------------------------------------------------------- + -- unconstrained array of std_ulogic for use with the resolution function + -- and for use in declaring signal arrays of unresolved elements + ------------------------------------------------------------------- + type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC; + + ------------------------------------------------------------------- + -- resolution function + ------------------------------------------------------------------- + function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC; + + + ------------------------------------------------------------------- + -- logic state system (resolved) + ------------------------------------------------------------------- + subtype STD_LOGIC is resolved STD_ULOGIC; + + -- Xilinx begin (160405) + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ; + -- Xilinx end (160405) + ------------------------------------------------------------------- + -- unconstrained array of resolved std_ulogic for use in declaring + -- signal arrays of resolved elements + ------------------------------------------------------------------- + subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR; + + ------------------------------------------------------------------- + -- common subtypes + ------------------------------------------------------------------- + subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1') + subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z') + subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1') + subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z') + + ------------------------------------------------------------------- + -- overloaded logical operators + ------------------------------------------------------------------- + + function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01; + function "not" (l : STD_ULOGIC) return UX01; + + ------------------------------------------------------------------- + -- vectorized overloaded logical operators + ------------------------------------------------------------------- + function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR; + function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC; + + ------------------------------------------------------------------- + -- shift operators + ------------------------------------------------------------------- + + function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR; + function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR; + function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR; + function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR; + + ------------------------------------------------------------------- + -- conversion functions + ------------------------------------------------------------------- + function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT; + function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR; + + function To_StdULogic (b : BIT) return STD_ULOGIC; + function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR; + function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR; + function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR; + function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR; + + alias To_Bit_Vector is + To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR]; + alias To_BV is + To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR]; + + alias To_Std_Logic_Vector is + To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR]; + alias To_SLV is + To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR]; + + alias To_Std_Logic_Vector is + To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR]; + alias To_SLV is + To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR]; + + alias To_Std_ULogic_Vector is + To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR]; + alias To_SULV is + To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR]; + + alias To_Std_ULogic_Vector is + To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR]; + alias To_SULV is + To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR]; + + ------------------------------------------------------------------- + -- strength strippers and type convertors + ------------------------------------------------------------------- + + function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0') + return STD_ULOGIC_VECTOR; + function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') + return STD_ULOGIC; + function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0') + return STD_ULOGIC_VECTOR; + function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') + return STD_ULOGIC; + + function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function To_X01 (s : STD_ULOGIC) return X01; + function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR; + function To_X01 (b : BIT) return X01; + + function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function To_X01Z (s : STD_ULOGIC) return X01Z; + function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR; + function To_X01Z (b : BIT) return X01Z; + + function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR; + function To_UX01 (s : STD_ULOGIC) return UX01; + function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR; + function To_UX01 (b : BIT) return UX01; + + function "??" (l : STD_ULOGIC) return BOOLEAN; + + ------------------------------------------------------------------- + -- edge detection + ------------------------------------------------------------------- + function rising_edge (signal s : STD_ULOGIC) return BOOLEAN; + function falling_edge (signal s : STD_ULOGIC) return BOOLEAN; + + ------------------------------------------------------------------- + -- object contains an unknown + ------------------------------------------------------------------- + function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN; + function Is_X (s : STD_ULOGIC) return BOOLEAN; + + ------------------------------------------------------------------- + -- matching relational operators + ------------------------------------------------------------------- + -- the following operations are predefined + + -- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC; + -- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; + + -- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC; + -- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; + + -- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC; + -- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC; + -- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC; + -- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC; + + ------------------------------------------------------------------- + -- string conversion and write operations + ------------------------------------------------------------------- + -- the following operations are predefined + + -- function to_string (value : STD_ULOGIC) return STRING; + -- function to_string (value : STD_ULOGIC_VECTOR) return STRING; + + -- explicitly defined operations + + alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING]; + alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING]; + function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING; + alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING]; + function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING; + alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING]; + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN); + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC); + + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN); + procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR); + + procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + + alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias BREAD is READ [LINE, STD_ULOGIC_VECTOR]; + alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR]; + + procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN); + procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR); + alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR]; + + procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN); + procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR); + alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR]; + + alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + + procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + + procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR; + JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); + alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + -- Xilinx begin (160405) + -- type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ; + -- Xilinx end (160405) + + -- Viper #10710: Following two are redundant. To_StdULogicVector and + -- To_StdLogicVector already declared before w.r.t. STD_LOGIC_VECTOR + -- function To_StdULogicVector (s : STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR; + -- function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93; + + FUNCTION "and" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "nand" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "or" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "nor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "xor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "xnor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION "not" ( l : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION To_bitvector ( s : std_logic_vector_93 ; xmap : BIT := '0') RETURN BIT_VECTOR ; + FUNCTION To_X01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ; + FUNCTION To_X01Z ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ; + FUNCTION To_UX01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ; + FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ; + FUNCTION Is_X ( s : std_logic_vector_93 ) RETURN BOOLEAN ; + + -- Read and Write procedures for STD_LOGIC_VECTOR_93 + procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93); + procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN); + procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0); + + procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93); + procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN); + procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0); + + procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93); + procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN); + procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93; + JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0); + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + +end package std_logic_1164; diff --git a/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_textio.vhdl b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_textio.vhdl new file mode 100644 index 0000000..f3a8d61 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_textio.vhdl @@ -0,0 +1,66 @@ +-- -------------------------------------------------------------------- +-- +-- Copyright © 2008 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076-2008, +-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This +-- source file may be used and distributed without restriction. +-- Modifications to this source file as permitted in IEEE Std 1076-2008 +-- may also be made and distributed. All other uses require permission +-- from the IEEE Standards Department(stds-ipr@ieee.org). +-- All other rights reserved. +-- +-- Title : Standard multivalue logic package +-- : (STD_LOGIC_TEXTIO package declaration) +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group +-- : +-- Purpose : This packages is provided as a replacement for non-standard +-- : implementations of the package provided by implementers of +-- : previous versions of this standard. The declarations that +-- : appeared in those non-standard implementations appear in the +-- : package STD_LOGIC_1164 in this standard. +-- : +-- Note : No declarations or definitions shall be included in, +-- : or excluded from this package. +-- : +-- -------------------------------------------------------------------- +-- $Revision: 1.3 $ +-- $Date: 2016/04/07 08:10:20 $ +-- -------------------------------------------------------------------- +library ieee ; -- RD added. +use STD.TEXTIO.all; +use IEEE.std_logic_1164.all; + +PACKAGE std_logic_textio IS + + alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC]; + alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC, BOOLEAN]; + alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR]; + alias READ is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93]; + alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias READ is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93, BOOLEAN]; + alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC, SIDE, WIDTH]; + alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH]; + + alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR]; + alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + + alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93]; + alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN]; + alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH]; + + alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR]; + alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN]; + alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH]; + + alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93]; + alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN]; + alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH]; + +END PACKAGE std_logic_textio; diff --git a/resources/dide-lsp/static/vhdl_std_lib/std/env.vhd b/resources/dide-lsp/static/vhdl_std_lib/std/env.vhd new file mode 100644 index 0000000..abbf201 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/std/env.vhd @@ -0,0 +1,11 @@ +-- Package env as defined by IEEE 1076-2008 + +package env is + procedure stop(status : integer); + procedure stop; + + procedure finish(status : integer); + procedure finish; + + function resolution_limit return delay_length; +end package; diff --git a/resources/dide-lsp/static/vhdl_std_lib/std/standard.vhd b/resources/dide-lsp/static/vhdl_std_lib/std/standard.vhd new file mode 100644 index 0000000..e60cc2d --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/std/standard.vhd @@ -0,0 +1,94 @@ +-- Package standard as defined by IEEE 1076-2008 + +package standard is + + -- Predefined enumeration types: + type BOOLEAN is (FALSE, TRUE); + type BIT is ('0', '1'); + + type CHARACTER is ( + NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, + BS, HT, LF, VT, FF, CR, SO, SI, + DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, + CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, + + ' ', '!', '"', '#', '$', '%', '&', ''', + '(', ')', '*', '+', ',', '-', '.', '/', + '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', ':', ';', '<', '=', '>', '?', + + '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', + 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', + 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', + 'X', 'Y', 'Z', '[', '\', ']', '^', '_', + + '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', + 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', + 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', + 'x', 'y', 'z', '{', '|', '}', '~', DEL, + + C128, C129, C130, C131, C132, C133, C134, C135, + C136, C137, C138, C139, C140, C141, C142, C143, + C144, C145, C146, C147, C148, C149, C150, C151, + C152, C153, C154, C155, C156, C157, C158, C159, + + ' ', '¡', '¢', '£', '¤', '¥', '¦', '§', + '¨', '©', 'ª', '«', '¬', '­', '®', '¯', + '°', '±', '²', '³', '´', 'µ', '¶', '·', + '¸', '¹', 'º', '»', '¼', '½', '¾', '¿', + 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç', + 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï', + 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×', + 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß', + 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç', + 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï', + 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷', + 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ'); + + type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE); + type INTEGER is range -2147483647 to 2147483647; + type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308; + + type TIME is range -9223372036854775807 to 9223372036854775807 + units + fs; -- femtosecond + ps = 1000 fs; -- picosecond + ns = 1000 ps; -- nanosecond + us = 1000 ns; -- microsecond + ms = 1000 us; -- millisecond + sec = 1000 ms; -- second + min = 60 sec; -- minute + hr= 60 min; -- hour + end units; + + subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH; + impure function NOW return DELAY_LENGTH; + + subtype NATURAL is INTEGER range 0 to INTEGER'HIGH; + subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH; + + type STRING is array (POSITIVE range <>) of CHARACTER; + + type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN; + type BIT_VECTOR is array (NATURAL range <>) of BIT; + type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER; + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type TIME_VECTOR is array (NATURAL range <>) of TIME; + + type FILE_OPEN_KIND is (READ_MODE, + WRITE_MODE, + APPEND_MODE); + + type FILE_OPEN_STATUS is (OPEN_OK, + STATUS_ERROR, + NAME_ERROR, + MODE_ERROR); + + attribute FOREIGN: STRING; + + function RISING_EDGE(signal S: BOOLEAN) return BOOLEAN; + function RISING_EDGE(signal B: BIT) return BOOLEAN; + function FALLING_EDGE(signal S: BOOLEAN) return BOOLEAN; + function FALLING_EDGE(signal B: BIT) return BOOLEAN; + +end package; diff --git a/resources/dide-lsp/static/vhdl_std_lib/std/textio.vhd b/resources/dide-lsp/static/vhdl_std_lib/std/textio.vhd new file mode 100644 index 0000000..02bbc72 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/std/textio.vhd @@ -0,0 +1,73 @@ +-- Package texio as defined by IEEE 1076-2008 + +package textio is + type LINE is access STRING; + type TEXT is file of STRING; + + procedure FILE_REWIND (file F: TEXT); + function FILE_MODE (file F: TEXT) return FILE_OPEN_KIND; + function FILE_SIZE (file F: TEXT) return INTEGER; + + type SIDE is (RIGHT, LEFT); + subtype WIDTH is NATURAL; -- For specifying widths of output fields. + + function JUSTIFY (VALUE: STRING; JUSTIFIED: SIDE := RIGHT; FIELD: WIDTH := 0 ) return STRING; + -- Standard text files: + file INPUT: TEXT open READ_MODE is "STD_INPUT"; + file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT"; + + -- Input routines for standard types: + procedure READLINE (file F: TEXT; L: inout LINE); + procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out BIT); + procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out BIT_VECTOR); + procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out CHARACTER); + procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out INTEGER); + procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out REAL); + procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out STRING); + procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN); + procedure READ (L: inout LINE; VALUE: out TIME); + procedure SREAD (L: inout LINE; VALUE: out STRING; STRLEN: out NATURAL); + alias STRING_READ is SREAD [LINE, STRING, NATURAL]; + alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN]; + alias BREAD is READ [LINE, BIT_VECTOR]; + alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN]; + alias BINARY_READ is READ [LINE, BIT_VECTOR]; + procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); + procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR); + alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN]; + alias OCTAL_READ is OREAD [LINE, BIT_VECTOR]; + procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); + procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR); + alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN]; + alias HEX_READ is HREAD [LINE, BIT_VECTOR]; + + -- Output routines for standard types: + procedure WRITELINE (file F: TEXT; L: inout LINE); + procedure TEE (file F: TEXT; L: inout LINE); + procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0); + procedure WRITE (L: inout LINE; VALUE: in REAL; FORMAT: in STRING); + procedure WRITE (L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); + procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns); + alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH]; + alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH]; + alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH]; + alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH]; + procedure OWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0); + alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH]; + procedure HWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0); + alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH]; + +end package; diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/arithmetic.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/arithmetic.vhd new file mode 100644 index 0000000..d4a2fb7 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/arithmetic.vhd @@ -0,0 +1,2117 @@ +-------------------------------------------------------------------------- +-- -- +-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved. -- +-- -- +-- This source file may be used and distributed without restriction -- +-- provided that this copyright statement is not removed from the file -- +-- and that any derivative work contains this copyright notice. -- +-- -- +-- Package name: ARITHMETIC +-- +-- Purpose: +-- A set of arithemtic, conversion, and comparison functions +-- for SIGNED, UNSIGNED, and MVL7_VECTOR. +-- +-------------------------------------------------------------------------- +-- Exemplar : Added Synthsis directives for the functions in this package. +-- These are attributes that operate like the Synopsys pragmas. +-------------------------------------------------------------------------- + +library synopsys; +use synopsys.types.all; + +package arithmetic is + + type UNSIGNED is array (INTEGER range <>) of MVL7; + type SIGNED is array (INTEGER range <>) of MVL7; + subtype SMALL_INT is INTEGER range 0 to 1; + + function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: SIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: SIGNED) return SIGNED; + function "+"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED; + function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: INTEGER) return SIGNED; + function "+"(L: INTEGER; R: SIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: MVL7) return UNSIGNED; + function "+"(L: MVL7; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: MVL7) return SIGNED; + function "+"(L: MVL7; R: SIGNED) return SIGNED; + + function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: SIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: SIGNED) return SIGNED; + function "-"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED; + function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: INTEGER) return SIGNED; + function "-"(L: INTEGER; R: SIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: MVL7) return UNSIGNED; + function "-"(L: MVL7; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: MVL7) return SIGNED; + function "-"(L: MVL7; R: SIGNED) return SIGNED; + + function "+"(L: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED) return SIGNED; + function "-"(L: SIGNED) return SIGNED; + function "ABS"(L: SIGNED) return SIGNED; + + function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "*"(L: SIGNED; R: SIGNED) return SIGNED; + function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; + + function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: SIGNED) return BOOLEAN; + function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: SIGNED) return BOOLEAN; + function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: SIGNED) return BOOLEAN; + + function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: SIGNED) return BOOLEAN; + function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; + function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; + function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; + function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; + + function CONV_INTEGER(ARG: INTEGER) return INTEGER; + function CONV_INTEGER(ARG: UNSIGNED) return INTEGER; + function CONV_INTEGER(ARG: SIGNED) return INTEGER; + function CONV_INTEGER(ARG: MVL7) return SMALL_INT; + function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: MVL7; SIZE: INTEGER) return UNSIGNED; + function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: MVL7; SIZE: INTEGER) return SIGNED; + + function "and" (L, R: UNSIGNED) return UNSIGNED; + function "nand" (L, R: UNSIGNED) return UNSIGNED; + function "or" (L, R: UNSIGNED) return UNSIGNED; + function "nor" (L, R: UNSIGNED) return UNSIGNED; + function "xor" (L, R: UNSIGNED) return UNSIGNED; + function nxor (L, R: UNSIGNED) return UNSIGNED; + function "not" (R: UNSIGNED) return UNSIGNED; + function buf (R: UNSIGNED) return UNSIGNED; + + function "and" (L, R: SIGNED) return SIGNED; + function "nand" (L, R: SIGNED) return SIGNED; + function "or" (L, R: SIGNED) return SIGNED; + function "nor" (L, R: SIGNED) return SIGNED; + function "xor" (L, R: SIGNED) return SIGNED; + function nxor (L, R: SIGNED) return SIGNED; + function "not" (R: SIGNED) return SIGNED; + function buf (R: SIGNED) return SIGNED; + + function AND_REDUCE(ARG: MVL7_VECTOR) return MVL7; + function NAND_REDUCE(ARG: MVL7_VECTOR) return MVL7; + function OR_REDUCE(ARG: MVL7_VECTOR) return MVL7; + function NOR_REDUCE(ARG: MVL7_VECTOR) return MVL7; + function XOR_REDUCE(ARG: MVL7_VECTOR) return MVL7; + function XNOR_REDUCE(ARG: MVL7_VECTOR) return MVL7; + +-- Declare Exemplar Synthesis Directive attributes + attribute SYNTHESIS_RETURN : STRING ; + attribute IS_SIGNED : BOOLEAN ; +end arithmetic; + +package body arithmetic is + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- synopsys synthesis_off + type tbl_type is array (MVL7) of MVL7; + constant tbl_BINARY : tbl_type := + ('0', '0', '1', '0', '0', '0', '1'); + -- synopsys synthesis_on + + function MAKE_BINARY(A : MVL7) return MVL7 is + -- synopsys built_in SYN_FEED_THRU + variable result : MVL7 ; + -- Exemplar synthesis directive attribute for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := tbl_BINARY(A); + return result ; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : MVL7; + variable result : UNSIGNED (A'range); + -- Exemplar synthesis directive attribute for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : UNSIGNED) return SIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : MVL7; + variable result : SIGNED (A'range); + -- Exemplar synthesis directive attribute for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : SIGNED) return UNSIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : MVL7; + variable result : UNSIGNED (A'range); + -- Exemplar synthesis directive attribute for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : SIGNED) return SIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : MVL7; + variable result : SIGNED (A'range); + -- Exemplar synthesis directive attribute for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + + + -- Type propagation function which returns a signed type with the + -- size of the left arg. + function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is + variable Z: SIGNED (A'left downto 0); + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns an unsigned type with the + -- size of the left arg. + function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is + variable Z: UNSIGNED (A'left downto 0); + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns a signed type with the + -- size of the result of a signed multiplication + function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is + variable Z: SIGNED ((A'length+B'length-1) downto 0); + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns an unsigned type with the + -- size of the result of a unsigned multiplication + function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is + variable Z: UNSIGNED ((A'length+B'length-1) downto 0); + -- pragma return_port_name Z + begin + return(Z); + end; + + function mult(A,B: SIGNED) return SIGNED is + + variable BA: SIGNED((A'length+B'length-1) downto 0); + variable PA: SIGNED((A'length+B'length-1) downto 0); + variable AA: SIGNED(A'length downto 0); + variable neg: MVL7; + constant one : UNSIGNED(1 downto 0) := "01"; + + -- pragma map_to_operator MULT_TC_OP + -- pragma type_function MULT_SIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of PA:variable is TRUE ; + attribute SYNTHESIS_RETURN of PA:variable is "MULT" ; + begin + PA := (others => '0'); + neg := B(B'left) xor A(A'left); + BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length)); + AA := '0' & ABS(A); + for i in 0 to A'length-1 loop + if AA(i) = '1' then + PA := PA+BA; + end if; + BA := SHL(BA,one); + end loop; + if (neg= '1') then + return (-PA); + else + return (PA); + end if; + end; + + function mult(A,B: UNSIGNED) return UNSIGNED is + + variable BA: UNSIGNED((A'length+B'length-1) downto 0); + variable PA: UNSIGNED((A'length+B'length-1) downto 0); + constant one : UNSIGNED(1 downto 0) := "01"; + + -- pragma map_to_operator MULT_UNS_OP + -- pragma type_function MULT_UNSIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of PA:variable is "MULT" ; + begin + PA := (others => '0'); + BA := CONV_UNSIGNED(B,(A'length+B'length)); + for i in 0 to A'length-1 loop + if A(i) = '1' then + PA := PA+BA; + end if; + BA := SHL(BA,one); + end loop; + return(PA); + end; + + -- subtract two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function minus(A, B: SIGNED) return SIGNED is + variable carry: MVL7; + variable BV: MVL7_VECTOR (A'left downto 0); + variable sum: SIGNED (A'left downto 0); + + -- pragma map_to_operator SUB_TC_OP + + -- pragma type_function LEFT_SIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of sum:variable is TRUE ; + attribute SYNTHESIS_RETURN of sum:variable is "SUB" ; + begin + carry := '1'; + BV := not MVL7_VECTOR(B); + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + + -- add two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function plus(A, B: SIGNED) return SIGNED is + variable carry: MVL7; + variable BV, sum: SIGNED (A'left downto 0); + + -- pragma map_to_operator ADD_TC_OP + -- pragma type_function LEFT_SIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of sum:variable is TRUE ; + attribute SYNTHESIS_RETURN of sum:variable is "ADD" ; + begin + carry := '0'; + BV := B; + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + + + -- subtract two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is + variable carry: MVL7; + variable BV: MVL7_VECTOR (A'left downto 0); + variable sum: UNSIGNED (A'left downto 0); + + -- pragma map_to_operator SUB_UNS_OP + -- pragma type_function LEFT_UNSIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of sum:variable is "SUB" ; + begin + carry := '1'; + BV := not MVL7_VECTOR(B); + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + + -- add two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is + variable carry: MVL7; + variable BV, sum: UNSIGNED (A'left downto 0); + + -- pragma map_to_operator ADD_UNS_OP + -- pragma type_function LEFT_UNSIGNED_ARG + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of sum:variable is "ADD" ; + begin + carry := '0'; + BV := B; + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + +-- All of the following actual different forms of arithmetic operations +-- will be compiled as is by Exemplar. + + function "*"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to mult + begin + return mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to mult + begin + return mult(CONV_UNSIGNED(L, L'length), + CONV_UNSIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + begin + return mult(CONV_SIGNED(L, L'length+1), + CONV_SIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to plus + begin + return mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length+1)); -- pragma label mult + end; + + + function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. R will be interpreted as (signed) integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. L will be interpreted as (signed) integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "+"(L: SIGNED; R: INTEGER) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: INTEGER; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: MVL7) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)) ; -- pragma label plus + end; + + + function "+"(L: MVL7; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: MVL7) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: MVL7; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + + + + function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_minus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- subtractor. R will be interpreted as (signed) integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- subtractor. L will be interpreted as (signed) integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: SIGNED; R: INTEGER) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: INTEGER; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: MVL7) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- subtractor. R is unsigned since CONV_SIGNED does zero-extend + -- for MVL7. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: MVL7; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- subtractor. L is unsigned since CONV_SIGNED does zero-extend + -- for MVL7. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: SIGNED; R: MVL7) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: MVL7; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + + + function "+"(L: UNSIGNED) return UNSIGNED is + begin + return L; + end; + + + function "+"(L: SIGNED) return SIGNED is + begin + return L; + end; + + + function "-"(L: SIGNED) return SIGNED is + -- pragma label_applies_to minus + variable result : SIGNED(L'RANGE) ; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "UMINUS" ; + begin + result := 0 - L; -- pragma label minus + return result ; + end; + + + function "ABS"(L: SIGNED) return SIGNED is + variable result : SIGNED(L'RANGE) ; + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "ABS" ; + begin + if L(L'left) = '0' then + result := L; + else + result := 0 - L; + end if; + return result ; + end; + + + -- Type propagation function which returns the type BOOLEAN + function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is + variable Z: BOOLEAN; + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns the type BOOLEAN + function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is + variable Z: BOOLEAN; + -- pragma return_port_name Z + begin + return(Z); + end; + + + -- compare two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function is_less(A, B: SIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LT_TC_OP + -- pragma type_function SIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "LT" ; + begin + if A(sign) /= B(sign) then + result := A(sign) = '1'; + else + result := FALSE; + for i in 0 to sign-1 loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + end if; + return result; + end; + + + -- compare two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function is_less_or_equal(A, B: SIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LEQ_TC_OP + -- pragma type_function SIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "LTE" ; + begin + if A(sign) /= B(sign) then + result := A(sign) = '1'; + else + result := TRUE; + for i in 0 to sign-1 loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + end if; + return result; + end; + + + + -- compare two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LT_UNS_OP + -- pragma type_function UNSIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "LT" ; + begin + result := FALSE; + for i in 0 to sign loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + return result; + end; + + + -- compare two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LEQ_UNS_OP + -- pragma type_function UNSIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "LTE" ; + begin + result := TRUE; + for i in 0 to sign loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + return result; + end; + +-- All of the following actual different forms of relational operations +-- will be compiled as is by Exemplar. + + + function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := L'length + 1; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := R'length + 1; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := L'length; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := R'length; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + + + function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := L'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := R'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := L'length; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := R'length; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + + + function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less(CONV_UNSIGNED(R, length), + CONV_UNSIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := L'length + 1; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := R'length + 1; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := L'length; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := R'length; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + + + function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length), + CONV_UNSIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := L'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := R'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := L'length; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := R'length; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + + + -- for internal use only. Assumes SIGNED arguments of equal length. + function bitwise_eql(L: MVL7_VECTOR; R: MVL7_VECTOR) + return BOOLEAN is + -- pragma built_in SYN_EQL + variable result : BOOLEAN := TRUE ; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "EQ" ; + begin + for i in L'range loop + if L(i) /= R(i) then + result := FALSE; + exit ; + end if; + end loop; + return result; + end; + + -- for internal use only. Assumes SIGNED arguments of equal length. + function bitwise_neq(L: MVL7_VECTOR; R: MVL7_VECTOR) + return BOOLEAN is + -- pragma built_in SYN_NEQ + variable result : BOOLEAN := FALSE ; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NEQ" ; + begin + for i in L'range loop + if L(i) /= R(i) then + result := TRUE; + exit ; + end if; + end loop; + return result ; + end; + +-- All of the following actual different forms of relational operations +-- will be compiled as is by Exemplar. + + + function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_eql( MVL7_VECTOR( CONV_UNSIGNED(L, length) ), + MVL7_VECTOR( CONV_UNSIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: SIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length + 1, R'length); + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length + 1); + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + constant length: INTEGER := L'length + 1; + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := R'length + 1; + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: INTEGER) return BOOLEAN is + constant length: INTEGER := L'length; + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: INTEGER; R: SIGNED) return BOOLEAN is + constant length: INTEGER := R'length; + begin + return bitwise_eql( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + + + function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_neq( MVL7_VECTOR( CONV_UNSIGNED(L, length) ), + MVL7_VECTOR( CONV_UNSIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length + 1, R'length); + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := max(L'length, R'length + 1); + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + constant length: INTEGER := L'length + 1; + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + constant length: INTEGER := R'length + 1; + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is + constant length: INTEGER := L'length; + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is + constant length: INTEGER := R'length; + begin + return bitwise_neq( MVL7_VECTOR( CONV_SIGNED(L, length) ), + MVL7_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + + function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is UNSIGNED (result_msb downto 0); + variable result, temp: rtype; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "SLL" ; + begin + control := MAKE_BINARY(COUNT); + result := ARG; + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => '0'); + if 2**i < result_msb then + temp(result_msb downto 2**i) := + result(result_msb - 2**i downto 0); + end if; + result := temp; + end if; + end loop; + return result; + end; + + function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is SIGNED (result_msb downto 0); + variable result, temp: rtype; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "SLL" ; + begin + control := MAKE_BINARY(COUNT); + result := ARG; + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => '0'); + if 2**i < result_msb then + temp(result_msb downto 2**i) := + result(result_msb - 2**i downto 0); + end if; + result := temp; + end if; + end loop; + return result; + end; + + + function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is UNSIGNED (result_msb downto 0); + variable result, temp: rtype; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "SRL" ; + begin + control := MAKE_BINARY(COUNT); + result := ARG; + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => '0'); + if 2**i < result_msb then + temp(result_msb - 2**i downto 0) := + result(result_msb downto 2**i); + end if; + result := temp; + end if; + end loop; + return result; + end; + + function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is SIGNED (result_msb downto 0); + variable result, temp: rtype; + variable sign_bit: MVL7; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "SRA" ; + begin + control := MAKE_BINARY(COUNT); + result := ARG; + sign_bit := ARG(ARG'left); + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => sign_bit); + if 2**i < result_msb then + temp(result_msb - 2**i downto 0) := + result(result_msb downto 2**i); + end if; + result := temp; + end if; + end loop; + return result; + end; + + + + + function CONV_INTEGER(ARG: INTEGER) return INTEGER is + begin + return ARG; + end; + + function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is + variable result: INTEGER; + -- synopsys built_in SYN_UNSIGNED_TO_INTEGER; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + assert ARG'length <= 31 + report "ARG is too large in CONV_INTEGER" + severity FAILURE; + result := 0; + for i in ARG'range loop + result := result * 2; + if tbl_BINARY(ARG(i)) = '1' then + result := result + 1; + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + + function CONV_INTEGER(ARG: SIGNED) return INTEGER is + variable result: INTEGER; + -- synopsys built_in SYN_SIGNED_TO_INTEGER; + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + assert ARG'length <= 32 + report "ARG is too large in CONV_INTEGER" + severity FAILURE; + result := 0; + for i in ARG'range loop + if i /= ARG'left then + result := result * 2; + if tbl_BINARY(ARG(i)) = '1' then + result := result + 1; + end if; + end if; + end loop; + if tbl_BINARY(ARG(ARG'left)) = '1' then + if ARG'length = 32 then + result := (result - 2**30) - 2**30; + else + result := result - (2 ** (ARG'length-1)); + end if; + end if; + return result; + -- synopsys synthesis_on + end; + + + function CONV_INTEGER(ARG: MVL7) return SMALL_INT is + begin + if MAKE_BINARY(ARG) = '0' then + return 0; + else + return 1; + end if; + end; + + + -- convert an integer to a unsigned MVL7_VECTOR + function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is + variable result: UNSIGNED(SIZE-1 downto 0); + variable temp: integer; + -- synopsys built_in SYN_INTEGER_TO_UNSIGNED + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp / 2; + else + temp := (temp - 1) / 2; -- simulate ASR + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + + function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is UNSIGNED (SIZE-1 downto 0); + variable new_bounds: UNSIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + new_bounds := MAKE_BINARY(ARG); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is UNSIGNED (SIZE-1 downto 0); + variable new_bounds: UNSIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_UNSIGNED(ARG: MVL7; SIZE: INTEGER) return UNSIGNED is + subtype rtype is UNSIGNED (SIZE-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + result(0) := MAKE_BINARY(ARG); + return result; + -- synopsys synthesis_on + end; + + + -- convert an integer to a 2's complement MVL7_VECTOR + function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is + variable result: SIGNED (SIZE-1 downto 0); + variable temp: integer; + -- synopsys built_in SYN_INTEGER_TO_SIGNED + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp / 2; + else + temp := (temp - 1) / 2; -- simulate ASR + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + + function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is SIGNED (SIZE-1 downto 0); + variable new_bounds : SIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + new_bounds := MAKE_BINARY(ARG); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is SIGNED (SIZE-1 downto 0); + variable new_bounds : SIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_SIGNED(ARG: MVL7; SIZE: INTEGER) return SIGNED is + subtype rtype is SIGNED (SIZE-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + result(0) := MAKE_BINARY(ARG); + return result; + -- synopsys synthesis_on + end; + + + + + function "and" (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_AND +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "AND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) and RV (i); + end loop; + return result; +--synopsys synthesis_on + end "and"; + + + function "nand" (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_NAND +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NAND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := not(LV (i) and RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "nand"; + + + function "or" (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_OR +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "OR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) or RV (i); + end loop; + return result; +--synopsys synthesis_on + end "or"; + + + function "nor" (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_NOR +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := not(LV (i) or RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "nor"; + + + function "xor" (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_XOR +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "XOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) xor RV (i); + end loop; + return result; +--synopsys synthesis_on + end "xor"; + + + function nxor (L, R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_XNOR +--synopsys synthesis_off + alias LV: UNSIGNED (L'length-1 downto 0) is L; + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "XNOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result(i) := not(LV(i) xor RV(i)); + end loop; + return result; +--synopsys synthesis_on + end nxor; + + + function "not" (R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_NOT +--synopsys synthesis_off + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (R'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NOT" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + result (i) := not RV(i); + end loop; + return result; +--synopsys synthesis_on + end "not"; + + + function buf (R: UNSIGNED) return UNSIGNED is + -- pragma built_in SYN_BUF +--synopsys synthesis_off + alias RV: UNSIGNED (R'length-1 downto 0) is R; + variable result: UNSIGNED (R'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + -- only portable way to perform buf + result(i) := not( not RV(i) ); + end loop; + return result; +--synopsys synthesis_on + end buf; + + + + + function "and" (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_AND +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "AND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) and RV (i); + end loop; + return result; +--synopsys synthesis_on + end "and"; + + + function "nand" (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_NAND +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NAND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := not(LV (i) and RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "nand"; + + + function "or" (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_OR +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "OR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) or RV (i); + end loop; + return result; +--synopsys synthesis_on + end "or"; + + + function "nor" (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_NOR +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := not(LV (i) or RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "nor"; + + + function "xor" (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_XOR +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "XOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := LV (i) xor RV (i); + end loop; + return result; +--synopsys synthesis_on + end "xor"; + + + function nxor (L, R: SIGNED) return SIGNED is + -- pragma built_in SYN_XNOR +--synopsys synthesis_off + alias LV: SIGNED (L'length-1 downto 0) is L; + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (L'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "XNOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result(i) := not(LV(i) xor RV(i)); + end loop; + return result; +--synopsys synthesis_on + end nxor; + + + function "not" (R: SIGNED) return SIGNED is + -- pragma built_in SYN_NOT +--synopsys synthesis_off + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (R'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "NOT" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + result (i) := not RV(i); + end loop; + return result; +--synopsys synthesis_on + end "not"; + + + function buf (R: SIGNED) return SIGNED is + -- pragma built_in SYN_BUF +--synopsys synthesis_off + alias RV: SIGNED (R'length-1 downto 0) is R; + variable result: SIGNED (R'length-1 downto 0); + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + -- only portable way to perform buf + result(i) := not( not RV(i) ); + end loop; + return result; +--synopsys synthesis_on + end buf; + + + + + function AND_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + variable result: MVL7; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ; + begin + result := '1'; + for i in ARG'range loop + result := result and ARG(i); + end loop; + return result; + end; + + function NAND_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + begin + return not AND_REDUCE(ARG); + end; + + function OR_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + variable result: MVL7; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ; + begin + result := '0'; + for i in ARG'range loop + result := result or ARG(i); + end loop; + return result; + end; + + function NOR_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + begin + return not OR_REDUCE(ARG); + end; + + function XOR_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + variable result: MVL7; + -- Exemplar synthesis directive attributes for this function + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ; + begin + result := '0'; + for i in ARG'range loop + result := result xor ARG(i); + end loop; + return result; + end; + + function XNOR_REDUCE(ARG: MVL7_VECTOR) return MVL7 is + begin + return not XOR_REDUCE(ARG); + end; + +end arithmetic; diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/attributes.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/attributes.vhd new file mode 100644 index 0000000..483839a --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/attributes.vhd @@ -0,0 +1,213 @@ +---------------------------------------------------------------------------- +-- +-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved. +-- +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +-- +-- Package name: ATTRIBUTES +-- +-- Purpose: This package defines the attributes associated with +-- the Synopsys VHDL System Simulator and the HDL compiler. +-- The simulator specific attributes are built into the +-- the analyzer, so this source should not be analyzed on +-- the Synopsys VHDL System Simulator. It is provided for +-- reference and portability to other systems. +-- +-- Author: JT, PH, GWH, RV +-- +-- Modified. Added translate_off and translate_on pairs because +-- HDL compiler does not use/support the simulator specific attributes +-- in this package. +-- +-- Modified: Apr 30, 1996, PZ: Moved the three BC attributes +-- (dont_unroll, variables, synthesis_type) to this package. +-- Modified: Nov 25, 1996, PZ: Removed the three BC attributes +-- (dont_unroll, variables, synthesis_type) from this package. +-- They are now in the behavioral package again. +-- +---------------------------------------------------------------------------- +-- Simulator specific attributes +----------------------------------------------------------------------- +-- +-- attributes for type conversion functions, SDF backannotation and +-- resolution functions +-- +----------------------------------------------------------------------- + +package ATTRIBUTES is +--synopsys translate_off + attribute CLOSELY_RELATED_TCF: boolean; + attribute PROPAGATE_VALUE: string; + attribute SDT_CONDITION: string; + attribute SDT_VALUE_NAME: string; + attribute SDT_VALUE: string; + attribute REFLEXIVE: boolean; + attribute COMMUTATIVE: boolean; + attribute ASSOCIATIVE: boolean; + attribute RESULT_INITIAL_VALUE: integer; + attribute TABLE_NAME: string; + attribute REAL_NAME: string; + + attribute PRIVATE: boolean; + attribute UNPRIVATE: boolean; + attribute ASIC_CELL: boolean; + attribute DIVERT_MESSAGES: boolean; + + -- Note: type BUILTIN_TYPE and attributes BUILTIN and EXTRA_SPACE + -- will be phased out after Elroy. This is to move towards + -- the upcoming '92 standard. + + type BUILTIN_TYPE is (VHDL_SYSTEM_PRIMITIVE, LMSI, C_BEHAVIOR, + VHDL_SYSTEM_PRIMITIVE_STD_LOGIC); + attribute BUILTIN: BUILTIN_TYPE; + attribute EXTRA_SPACE: positive; + + -- Note: ### For the '92 standard, attribute FOREIGN must be + -- moved to package STANDARD. + + attribute FOREIGN : STRING; + + -- CLI (C Language Interface) attributes + + type CLI_PIN_SENSITIVITY is (CLI_PASSIVE, CLI_EVENT, CLI_ACTIVE); + + attribute CLI_ELABORATE : STRING; -- components only + attribute CLI_EVALUATE : STRING; -- components only + attribute CLI_ERROR : STRING; -- components only + attribute CLI_CLOSE : STRING; -- components only + attribute CLI_PIN : CLI_PIN_SENSITIVITY; -- components only + + attribute CLI_FUNCTION : STRING; -- functions only + attribute CLI_PROCEDURE : STRING; -- procedures only + + attribute CLI_POSTPONED : BOOLEAN; -- components only + + -- Logic Modeling Corporation (LMC) interface attributes: + + type LMSI_DELAY_TYPE_TYPE is (TYPICAL, MINIMUM, MAXIMUM); + attribute LMSI_DELAY_TYPE : LMSI_DELAY_TYPE_TYPE; + + type LMSI_TIMING_MEASUREMENT_TYPE is (DISABLED, ENABLED); + attribute LMSI_TIMING_MEASUREMENT: LMSI_TIMING_MEASUREMENT_TYPE; + + type LMSI_LOG_TYPE is (DISABLED, ENABLED); + attribute LMSI_LOG: LMSI_LOG_TYPE; + + type LMSI_DELAY_ED_TYPE is (ENABLED, DISABLED); + attribute LMSI_DELAY: LMSI_DELAY_ED_TYPE; + + type LMSI_TIMING_VIOLATIONS_TYPE is (ENABLED, DISABLED); + attribute LMSI_TIMING_VIOLATIONS: LMSI_TIMING_VIOLATIONS_TYPE; + + type LMSI_XPROP_TYPE is (DISABLED, ENABLED); + attribute LMSI_XPROP: LMSI_XPROP_TYPE; + + type LMSI_XPROP_METHOD_TYPE is (PREVIOUS, HIGH, LOW, FLOAT); + attribute LMSI_XPROP_METHOD: LMSI_XPROP_METHOD_TYPE; + + -- Zycad XP interface attributes: + + type BACKPLANE_TYPE is (XP, VERILOG, VIP); + attribute BACKPLANE: BACKPLANE_TYPE; + + -- Attribute to instantiate a Model Bank component in the Zycad + -- XP box. + + type ENCRYPTION_TYPE is (MODELBANK); + attribute ENCRYPTION: ENCRYPTION_TYPE; + + -- Attribute to specify the EDIF file for an architecture. This + -- attribute can be specified in architecture(s) where the structural + -- information is in EDIF and we want to use it. This should be used + -- in conjunction with BACKPLANE attribute. + attribute EDIF_FILE_FOR_THIS_ARCHITECTURE: string; + attribute VERILOG_FILES_FOR_THIS_ARCHITECTURE: string; + + -- The following two attributes are used to specify the physical + -- filename of the EDIF file containing the definitions of cell(s) or + -- entity(s) from a package and the EDIF library name used in the + -- above EDIF file. + attribute EDIF_LIBRARY_FILENAME: string; + attribute EDIF_LIBRARY_NAME: string; + + -- XPMSW + -- XP attribute for a component which is described by a ZYCAD + -- CBMOD. + attribute ZYCAD_XP_CBMOD : BOOLEAN; + + -- This attribute is used to specify the initialization file for + -- RAM(s) and ROM(s). + attribute MVL7_MEM_INITFILE: string; + + -- attributes for the function units bus (funbus) + type FUNBUS_TYPE is (LAI,CBMOD); + attribute FUNBUS : FUNBUS_TYPE; + + attribute CHANGE_SIMPLE_NAME : string; + attribute CHECKOUT_LICENSE : string; + attribute COMPILED_SYSTEM : boolean; + attribute USE_FULL_NAME : boolean; + attribute USE_SIMPLE_NAME : boolean; + +--synopsys translate_on +-------------------------------------------------------------------- +-- HDL compiler specific Attributes + attribute async_set_reset : string; + attribute sync_set_reset : string; + attribute async_set_reset_local : string; + attribute sync_set_reset_local : string; + attribute async_set_reset_local_all : string; + attribute sync_set_reset_local_all : string; + + attribute one_hot : string; + attribute one_cold : string; + attribute infer_mux : string; + +-------------------------------------------------------------------- +-- design compiler constraints and attributes + attribute ARRIVAL : REAL; + attribute DONT_TOUCH : BOOLEAN; + attribute DONT_TOUCH_NETWORK : BOOLEAN; + attribute DRIVE_STRENGTH : REAL; + attribute EQUAL : BOOLEAN; + attribute FALL_ARRIVAL : REAL; + attribute FALL_DRIVE : REAL; + attribute LOAD : REAL; + attribute LOGIC_ONE : BOOLEAN; + attribute LOGIC_ZERO : BOOLEAN; + attribute MAX_AREA : REAL; + attribute MAX_DELAY : REAL; + attribute MAX_FALL_DELAY : REAL; + attribute MAX_RISE_DELAY : REAL; + attribute MAX_TRANSITION : REAL; + attribute MIN_DELAY : REAL; + attribute MIN_FALL_DELAY : REAL; + attribute MIN_RISE_DELAY : REAL; + attribute OPPOSITE : BOOLEAN; + attribute RISE_ARRIVAL : REAL; + attribute RISE_DRIVE : REAL; + attribute UNCONNECTED : BOOLEAN; + attribute INFER_MULTIBIT : STRING; + +-- state machine attributes + attribute STATE_VECTOR : STRING; + +-- resource sharing attributes + subtype resource is integer; + attribute ADD_OPS : STRING; + attribute DONT_MERGE_WITH : STRING; + attribute MAP_TO_MODULE : STRING; + attribute IMPLEMENTATION : STRING; + attribute MAY_MERGE_WITH : STRING; + attribute OPS : STRING; + +-- general attributes + attribute ENUM_ENCODING : STRING; + +-- optimization attributes + attribute TRANSFORM_CONST_MULT : boolean; + +-- +end ATTRIBUTES; diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_arith.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_arith.vhd new file mode 100644 index 0000000..f71b010 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_arith.vhd @@ -0,0 +1,2945 @@ +-------------------------------------------------------------------------- +-- -- +-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. -- +-- -- +-- This source file may be used and distributed without restriction -- +-- provided that this copyright statement is not removed from the file -- +-- and that any derivative work contains this copyright notice. -- +-- -- +-- Package name: STD_LOGIC_ARITH -- +-- -- +-- Purpose: -- +-- A set of arithemtic, conversion, and comparison functions -- +-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, -- +-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. -- +-- -- +-------------------------------------------------------------------------- +-- Exemplar : Added synthesis directive attributes for the functions in +-- this package. +-- These work similar to the Synopsys pragmas +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- +-- Modifications : +-- Attributes added and sources modified for Xilinx specific optimizations +-- function has_x(s : unsigned) added for detecting 'x' in an unsigned array +-------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; + +package std_logic_arith is + + type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; + type SIGNED is array (NATURAL range <>) of STD_LOGIC; + subtype SMALL_INT is INTEGER range 0 to 1; + + function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: SIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: SIGNED) return SIGNED; + function "+"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED; + function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: INTEGER) return SIGNED; + function "+"(L: INTEGER; R: SIGNED) return SIGNED; + function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED; + function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED; + function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED; + + function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR; + function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR; + function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR; + function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR; + function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR; + function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR; + + function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: SIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: SIGNED) return SIGNED; + function "-"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED; + function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: INTEGER) return SIGNED; + function "-"(L: INTEGER; R: SIGNED) return SIGNED; + function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED; + function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED; + function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED; + function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED; + + function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR; + function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR; + function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR; + function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR; + function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR; + function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR; + + function "+"(L: UNSIGNED) return UNSIGNED; + function "+"(L: SIGNED) return SIGNED; + function "-"(L: SIGNED) return SIGNED; + function "ABS"(L: SIGNED) return SIGNED; + + function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR; + function "+"(L: SIGNED) return STD_LOGIC_VECTOR; + function "-"(L: SIGNED) return STD_LOGIC_VECTOR; + function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR; + + function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; + function "*"(L: SIGNED; R: SIGNED) return SIGNED; + function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; + function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; + + function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; + function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR; + + function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: SIGNED) return BOOLEAN; + function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "<"(L: SIGNED; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "<="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: SIGNED) return BOOLEAN; + function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function ">"(L: SIGNED; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: SIGNED) return BOOLEAN; + + function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: SIGNED) return BOOLEAN; + function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function ">="(L: SIGNED; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: SIGNED) return BOOLEAN; + function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN; + function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN; + function "/="(L: SIGNED; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: SIGNED) return BOOLEAN; + + function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; + function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; + function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; + function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; + + function CONV_INTEGER(ARG: INTEGER) return INTEGER; + function CONV_INTEGER(ARG: UNSIGNED) return INTEGER; + function CONV_INTEGER(ARG: SIGNED) return INTEGER; + function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT; + + function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED; + function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED; + + function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED; + function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED; + + function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) + return STD_LOGIC_VECTOR; + function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) + return STD_LOGIC_VECTOR; + function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) + return STD_LOGIC_VECTOR; + function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) + return STD_LOGIC_VECTOR; + -- zero extend STD_LOGIC_VECTOR (ARG) to SIZE, + -- SIZE < 0 is same as SIZE = 0 + -- returns STD_LOGIC_VECTOR(SIZE-1 downto 0) + function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR; + + -- sign extend STD_LOGIC_VECTOR (ARG) to SIZE, + -- SIZE < 0 is same as SIZE = 0 + -- return STD_LOGIC_VECTOR(SIZE-1 downto 0) + function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR; + + + function mult(A,B: SIGNED) return SIGNED; + function mult(A,B: UNSIGNED) return UNSIGNED; + function plus(A, B: SIGNED) return SIGNED; + function unsigned_plus(A, B: UNSIGNED) return UNSIGNED; + function minus(A, B: SIGNED) return SIGNED; + function unsigned_minus(A, B: UNSIGNED) return UNSIGNED; + function is_less(A, B: SIGNED) return BOOLEAN; + function is_less_or_equal(A, B: SIGNED) return BOOLEAN; + function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN; + function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN; + + --attribute foreign of mult[SIGNED, SIGNED return SIGNED]:function is "ieee_std_logic_arith_mult_signed"; + --attribute foreign of mult[UNSIGNED, UNSIGNED return UNSIGNED]:function is "ieee_std_logic_arith_mult_unsigned"; + --attribute foreign of plus[SIGNED, SIGNED return SIGNED]:function is "ieee_std_logic_arith_plus_signed"; + --attribute foreign of unsigned_plus[UNSIGNED, UNSIGNED return UNSIGNED]:function is "ieee_std_logic_arith_plus_unsigned"; + --attribute foreign of minus[SIGNED, SIGNED return SIGNED]:function is "ieee_std_logic_arith_minus_signed"; + --attribute foreign of unsigned_minus[UNSIGNED, UNSIGNED return UNSIGNED]:function is "ieee_std_logic_arith_minus_unsigned"; + + --attribute foreign of is_less[SIGNED, SIGNED return BOOLEAN]:function is "ieee_std_logic_arith_signed_is_less"; + --attribute foreign of is_less_or_equal[SIGNED, SIGNED return BOOLEAN]:function is "ieee_std_logic_arith_signed_is_less_or_equal"; + --attribute foreign of unsigned_is_less[UNSIGNED, UNSIGNED return BOOLEAN]:function is "ieee_std_logic_arith_unsigned_is_less"; + --attribute foreign of unsigned_is_less_or_equal[UNSIGNED, UNSIGNED return BOOLEAN]:function is "ieee_std_logic_arith_unsigned_is_less_or_equal"; + + --attribute foreign of CONV_INTEGER[UNSIGNED return INTEGER]:function is "ieee_std_logic_arith_conv_integer_unsigned"; + --attribute foreign of CONV_INTEGER[SIGNED return INTEGER]:function is "ieee_std_logic_arith_conv_integer_signed"; + --attribute foreign of CONV_INTEGER[STD_ULOGIC return SMALL_INT]:function is "ieee_std_logic_arith_conv_integer_ulogic"; + + --attribute foreign of CONV_UNSIGNED[INTEGER, INTEGER return UNSIGNED]:function is "ieee_std_logic_arith_conv_unsigned_integer"; + --attribute foreign of CONV_UNSIGNED[UNSIGNED, INTEGER return UNSIGNED]:function is "ieee_std_logic_arith_conv_unsigned_zeroext"; + --attribute foreign of CONV_UNSIGNED[SIGNED, INTEGER return UNSIGNED]:function is "ieee_std_logic_arith_conv_unsigned_signext"; + + --attribute foreign of CONV_SIGNED[INTEGER, INTEGER return SIGNED]:function is "ieee_std_logic_arith_conv_signed_integer"; + --attribute foreign of CONV_SIGNED[UNSIGNED, INTEGER return SIGNED]:function is "ieee_std_logic_arith_conv_signed_zeroext"; + --attribute foreign of CONV_SIGNED[SIGNED, INTEGER return SIGNED]:function is "ieee_std_logic_arith_conv_signed_signext"; + + --attribute foreign of "="[UNSIGNED, UNSIGNED return BOOLEAN]:function is "ieee_std_logic_arith_equal_unsigned_unsigned"; + --attribute foreign of ">"[UNSIGNED, UNSIGNED return BOOLEAN]:function is "ieee_std_logic_arith_greater_unsigned_unsigned"; + + attribute foreign of plus[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_plus"; + attribute foreign of unsigned_plus[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_plus"; + + attribute foreign of "+"[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_signed_plus"; + attribute foreign of "+"[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_unsigned_plus"; + attribute foreign of "+"[UNSIGNED, SIGNED return SIGNED]:function is "std_logic_arith_unsigned_signed_plus"; + attribute foreign of "+"[SIGNED, UNSIGNED return SIGNED]:function is "std_logic_arith_signed_unsigned_plus"; + attribute foreign of "+"[INTEGER, UNSIGNED return UNSIGNED]:function is "std_logic_arith_integer_unsigned_plus"; + attribute foreign of "+"[UNSIGNED, INTEGER return UNSIGNED]:function is "std_logic_arith_unsigned_integer_plus"; + attribute foreign of "+"[INTEGER, SIGNED return SIGNED]:function is "std_logic_arith_integer_signed_plus"; + attribute foreign of "+"[SIGNED, INTEGER return SIGNED]:function is "std_logic_arith_signed_integer_plus"; + attribute foreign of "+"[std_ulogic, unsigned return unsigned]:function is "std_logic_arith_ulogic_unsigned_plus"; + attribute foreign of "+"[unsigned, std_ulogic return unsigned]:function is "std_logic_arith_unsigned_ulogic_plus"; + attribute foreign of "+"[std_ulogic, signed return signed]:function is "std_logic_arith_ulogic_signed_plus"; + attribute foreign of "+"[signed, std_ulogic return signed]:function is "std_logic_arith_signed_ulogic_plus"; + + attribute foreign of "+"[SIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_signed_signed_plus"; + attribute foreign of "+"[UNSIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_unsigned_plus"; + attribute foreign of "+"[UNSIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_signed_plus"; + attribute foreign of "+"[SIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_signed_unsigned_plus"; + attribute foreign of "+"[INTEGER, UNSIGNED return std_logic_vector]:function is "std_logic_arith_integer_unsigned_plus"; + attribute foreign of "+"[UNSIGNED, INTEGER return std_logic_vector]:function is "std_logic_arith_unsigned_integer_plus"; + attribute foreign of "+"[INTEGER, SIGNED return std_logic_vector]:function is "std_logic_arith_integer_signed_plus"; + attribute foreign of "+"[SIGNED, INTEGER return std_logic_vector]:function is "std_logic_arith_signed_integer_plus"; + attribute foreign of "+"[std_ulogic, unsigned return std_logic_vector]:function is "std_logic_arith_ulogic_unsigned_plus"; + attribute foreign of "+"[unsigned, std_ulogic return std_logic_vector]:function is "std_logic_arith_unsigned_ulogic_plus"; + attribute foreign of "+"[std_ulogic, signed return std_logic_vector]:function is "std_logic_arith_ulogic_signed_plus"; + attribute foreign of "+"[signed, std_ulogic return std_logic_vector]:function is "std_logic_arith_signed_ulogic_plus"; + + + attribute foreign of minus[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_minus"; + attribute foreign of unsigned_minus[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_minus"; + + attribute foreign of "-"[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_signed_minus"; + attribute foreign of "-"[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_unsigned_minus"; + attribute foreign of "-"[UNSIGNED, SIGNED return SIGNED]:function is "std_logic_arith_unsigned_signed_minus"; + attribute foreign of "-"[SIGNED, UNSIGNED return SIGNED]:function is "std_logic_arith_signed_unsigned_minus"; + attribute foreign of "-"[INTEGER, UNSIGNED return UNSIGNED]:function is "std_logic_arith_integer_unsigned_minus"; + attribute foreign of "-"[UNSIGNED, INTEGER return UNSIGNED]:function is "std_logic_arith_unsigned_integer_minus"; + attribute foreign of "-"[INTEGER, SIGNED return SIGNED]:function is "std_logic_arith_integer_signed_minus"; + attribute foreign of "-"[SIGNED, INTEGER return SIGNED]:function is "std_logic_arith_signed_integer_minus"; + attribute foreign of "-"[std_ulogic, unsigned return unsigned]:function is "std_logic_arith_ulogic_unsigned_minus"; + attribute foreign of "-"[unsigned, std_ulogic return unsigned]:function is "std_logic_arith_unsigned_ulogic_minus"; + attribute foreign of "-"[std_ulogic, signed return signed]:function is "std_logic_arith_ulogic_signed_minus"; + attribute foreign of "-"[signed, std_ulogic return signed]:function is "std_logic_arith_signed_ulogic_minus"; + + attribute foreign of "-"[SIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_signed_signed_minus"; + attribute foreign of "-"[UNSIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_unsigned_minus"; + attribute foreign of "-"[UNSIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_signed_minus"; + attribute foreign of "-"[SIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_signed_unsigned_minus"; + attribute foreign of "-"[INTEGER, UNSIGNED return std_logic_vector]:function is "std_logic_arith_integer_unsigned_minus"; + attribute foreign of "-"[UNSIGNED, INTEGER return std_logic_vector]:function is "std_logic_arith_unsigned_integer_minus"; + attribute foreign of "-"[INTEGER, SIGNED return std_logic_vector]:function is "std_logic_arith_integer_signed_minus"; + attribute foreign of "-"[SIGNED, INTEGER return std_logic_vector]:function is "std_logic_arith_signed_integer_minus"; + attribute foreign of "-"[std_ulogic, unsigned return std_logic_vector]:function is "std_logic_arith_ulogic_unsigned_minus"; + attribute foreign of "-"[unsigned, std_ulogic return std_logic_vector]:function is "std_logic_arith_unsigned_ulogic_minus"; + attribute foreign of "-"[std_ulogic, signed return std_logic_vector]:function is "std_logic_arith_ulogic_signed_minus"; + attribute foreign of "-"[signed, std_ulogic return std_logic_vector]:function is "std_logic_arith_signed_ulogic_minus"; + + attribute foreign of mult[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_mult"; + attribute foreign of mult[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_mult"; + + attribute foreign of "*"[SIGNED, SIGNED return SIGNED]:function is "std_logic_arith_signed_signed_mult"; + attribute foreign of "*"[UNSIGNED, UNSIGNED return UNSIGNED]:function is "std_logic_arith_unsigned_unsigned_mult"; + attribute foreign of "*"[UNSIGNED, SIGNED return SIGNED]:function is "std_logic_arith_unsigned_signed_mult"; + attribute foreign of "*"[SIGNED, UNSIGNED return SIGNED]:function is "std_logic_arith_signed_unsigned_mult"; + attribute foreign of "*"[SIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_signed_signed_mult"; + attribute foreign of "*"[UNSIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_unsigned_mult"; + attribute foreign of "*"[UNSIGNED, SIGNED return std_logic_vector]:function is "std_logic_arith_unsigned_signed_mult"; + attribute foreign of "*"[SIGNED, UNSIGNED return std_logic_vector]:function is "std_logic_arith_signed_unsigned_mult"; + + attribute foreign of "+"[UNSIGNED return UNSIGNED]:function is "std_logic_arith_unary_plus"; + attribute foreign of "+"[SIGNED return SIGNED]:function is "std_logic_arith_unary_plus"; + attribute foreign of "-"[SIGNED return SIGNED]:function is "std_logic_arith_signed_unary_minus"; + attribute foreign of "ABS"[SIGNED return SIGNED]:function is "std_logic_arith_signed_unary_abs"; + attribute foreign of "+"[UNSIGNED return std_logic_vector]:function is "std_logic_arith_unary_plus"; + attribute foreign of "+"[SIGNED return std_logic_vector]:function is "std_logic_arith_unary_plus"; + attribute foreign of "-"[SIGNED return std_logic_vector]:function is "std_logic_arith_signed_unary_minus"; + attribute foreign of "ABS"[SIGNED return std_logic_vector]:function is "std_logic_arith_signed_unary_abs"; + + attribute foreign of is_less[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_is_less"; + attribute foreign of is_less_or_equal[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_is_less_or_equal"; + attribute foreign of unsigned_is_less[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_is_less"; + attribute foreign of unsigned_is_less_or_equal[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_is_less_or_equal"; + attribute foreign of "<"[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less"; + attribute foreign of "<"[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less"; + attribute foreign of "<"[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_less"; + attribute foreign of "<"[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_less"; + attribute foreign of "<"[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less"; + attribute foreign of "<"[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less"; + attribute foreign of "<"[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less"; + attribute foreign of "<"[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less"; + attribute foreign of "<="[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less_or_equal"; + attribute foreign of "<="[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less_or_equal"; + attribute foreign of "<="[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_less_or_equal"; + attribute foreign of "<="[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_less_or_equal"; + attribute foreign of "<="[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less_or_equal"; + attribute foreign of "<="[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less_or_equal"; + attribute foreign of "<="[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less_or_equal"; + attribute foreign of "<="[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less_or_equal"; + attribute foreign of ">"[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater"; + attribute foreign of ">"[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater"; + attribute foreign of ">"[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_greater"; + attribute foreign of ">"[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_greater"; + attribute foreign of ">"[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater"; + attribute foreign of ">"[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater"; + attribute foreign of ">"[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater"; + attribute foreign of ">"[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater"; + attribute foreign of ">="[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater_or_equal"; + attribute foreign of ">="[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater_or_equal"; + attribute foreign of ">="[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_greater_or_equal"; + attribute foreign of ">="[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_greater_or_equal"; + attribute foreign of ">="[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater_or_equal"; + attribute foreign of ">="[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater_or_equal"; + attribute foreign of ">="[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater_or_equal"; + attribute foreign of ">="[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater_or_equal"; + attribute foreign of "="[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_equal"; + attribute foreign of "="[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_equal"; + attribute foreign of "="[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_equal"; + attribute foreign of "="[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_equal"; + attribute foreign of "="[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_equal"; + attribute foreign of "="[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_equal"; + attribute foreign of "="[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_equal"; + attribute foreign of "="[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_equal"; + attribute foreign of "/="[UNSIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_not_equal"; + attribute foreign of "/="[SIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_signed_signed_is_not_equal"; + attribute foreign of "/="[UNSIGNED, SIGNED return BOOLEAN]:function is "std_logic_arith_unsigned_signed_is_not_equal"; + attribute foreign of "/="[SIGNED, UNSIGNED return BOOLEAN]:function is "std_logic_arith_signed_unsigned_is_not_equal"; + attribute foreign of "/="[UNSIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_not_equal"; + attribute foreign of "/="[INTEGER, UNSIGNED return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_not_equal"; + attribute foreign of "/="[SIGNED, INTEGER return BOOLEAN]:function is "std_logic_arith_signed_integer_is_not_equal"; + attribute foreign of "/="[INTEGER, SIGNED return BOOLEAN]:function is "std_logic_arith_integer_signed_is_not_equal"; + + attribute foreign of SHL[unsigned, unsigned return unsigned]:function is "std_logic_arith_unsigned_shl"; + attribute foreign of SHL[signed, unsigned return signed]:function is "std_logic_arith_signed_shl"; + attribute foreign of SHR[unsigned, unsigned return unsigned]:function is "std_logic_arith_unsigned_shr"; + attribute foreign of SHR[signed, unsigned return signed]:function is "std_logic_arith_signed_shr"; + + attribute foreign of conv_integer[integer return integer]:function is "std_logic_arith_conv_integer_to_integer"; + attribute foreign of conv_integer[unsigned return integer]:function is "std_logic_arith_conv_unsigned_to_integer"; + attribute foreign of conv_integer[signed return integer]:function is "std_logic_arith_conv_signed_to_integer"; + attribute foreign of conv_integer[std_ulogic return integer]:function is "std_logic_arith_conv_ulogic_to_integer"; + + attribute foreign of conv_unsigned[integer, integer return unsigned]:function is "std_logic_arith_conv_integer_to_unsigned"; + attribute foreign of conv_unsigned[unsigned, integer return unsigned]:function is "std_logic_arith_conv_unsigned_to_unsigned"; + attribute foreign of conv_unsigned[signed, integer return unsigned]:function is "std_logic_arith_conv_signed_to_unsigned"; + attribute foreign of conv_unsigned[std_ulogic, integer return unsigned]:function is "std_logic_arith_conv_ulogic_to_unsigned"; + + attribute foreign of conv_signed[integer, integer return signed]:function is "std_logic_arith_conv_integer_to_signed"; + attribute foreign of conv_signed[unsigned, integer return signed]:function is "std_logic_arith_conv_unsigned_to_signed"; + attribute foreign of conv_signed[signed, integer return signed]:function is "std_logic_arith_conv_signed_to_signed"; + attribute foreign of conv_signed[std_ulogic, integer return signed]:function is "std_logic_arith_conv_ulogic_to_signed"; + + attribute foreign of conv_std_logic_vector[integer, integer return std_logic_vector]:function is "std_logic_arith_conv_integer_to_vector"; + attribute foreign of conv_std_logic_vector[unsigned, integer return std_logic_vector]:function is "std_logic_arith_conv_unsigned_to_vector"; + attribute foreign of conv_std_logic_vector[signed, integer return std_logic_vector]:function is "std_logic_arith_conv_signed_to_vector"; + attribute foreign of conv_std_logic_vector[std_ulogic, integer return std_logic_vector]:function is "std_logic_arith_conv_ulogic_to_vector"; + + attribute foreign of ext[std_logic_vector, integer return std_logic_vector]:function is "std_logic_arith_ext"; + attribute foreign of sxt[std_logic_vector, integer return std_logic_vector]:function is "std_logic_arith_sxt"; + + attribute foreign of Std_logic_arith: package is "copy extra C function"; +-- Verific : attributes re-declaration causes use-clause inclusion conflicts if re-declared here. + -- Exemplar Synthesis Directive Attributes + attribute IS_SIGNED : BOOLEAN ; + attribute SYNTHESIS_RETURN : STRING ; + +end Std_logic_arith; + + +library IEEE; +use IEEE.std_logic_1164.all; + +package body std_logic_arith is + + function has_x(s : unsigned) return boolean is + constant len: integer:=s'length; + alias sv: unsigned(1 to len) is s; + begin + for i in 1 to len loop + case sv(i) is + when '0'|'1'|'H'|'L' => null; + when others => return true; + end case; + end loop; + return false; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- synopsys synthesis_off + type tbl_type is array (STD_ULOGIC) of STD_ULOGIC; + constant tbl_BINARY : tbl_type := + ('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X'); + -- synopsys synthesis_on + + -- synopsys synthesis_off + type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean; + constant IS_X : tbl_mvl9_boolean := + (true, true, false, false, true, true, false, false, true); + -- synopsys synthesis_on + + + + function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is + -- synopsys built_in SYN_FEED_THRU + variable result : STD_ULOGIC ; + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + if (IS_X(A)) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := ('X'); + return result ; + end if; + result := tbl_BINARY(A); + return result ; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : UNSIGNED (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : UNSIGNED) return SIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : SIGNED (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : SIGNED) return UNSIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : UNSIGNED (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : SIGNED) return SIGNED is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : SIGNED (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : STD_LOGIC_VECTOR (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : STD_LOGIC_VECTOR (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is + -- synopsys built_in SYN_FEED_THRU + -- variable one_bit : STD_ULOGIC; + variable result : STD_LOGIC_VECTOR (A'range); + -- Add Exemplar synthesis attribute + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + for i in A'range loop + if (IS_X(A(i))) then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + end if; + result(i) := tbl_BINARY(A(i)); + end loop; + return result; + -- synopsys synthesis_on + end; + + + + -- Type propagation function which returns a signed type with the + -- size of the left arg. + function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is + variable Z: SIGNED (A'left downto 0) := (others=>'X') ; + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns an unsigned type with the + -- size of the left arg. + function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is + variable Z: UNSIGNED (A'left downto 0) := (others=>'X') ; + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns a signed type with the + -- size of the result of a signed multiplication + function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is + variable Z: SIGNED ((A'length+B'length-1) downto 0) := (others=>'X') ; + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns an unsigned type with the + -- size of the result of a unsigned multiplication + function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is + variable Z: UNSIGNED ((A'length+B'length-1) downto 0) := (others=>'X') ; + -- pragma return_port_name Z + begin + return(Z); + end; + + + + function mult(A,B: SIGNED) return SIGNED is + + variable BA: SIGNED((A'length+B'length-1) downto 0); + variable PA: SIGNED((A'length+B'length-1) downto 0); + variable AA: SIGNED(A'length downto 0); + variable neg: STD_ULOGIC; + constant one : UNSIGNED(1 downto 0) := "01"; + + -- pragma map_to_operator MULT_TC_OP + -- pragma type_function MULT_SIGNED_ARG + -- pragma return_port_name Z + + -- pragma label_applies_to mult + + -- Add Exemplar synthesis attributes + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of PA:variable is TRUE ; + attribute SYNTHESIS_RETURN of PA:variable is "MULT" ; + begin + if (A(A'left) = 'X' or B(B'left) = 'X') then + PA := (others => 'X'); + return(PA); + end if; + PA := (others => '0'); + neg := B(B'left) xor A(A'left); + BA := CONV_SIGNED(('0' & SIGNED'(ABS(B))),(A'length+B'length)); + AA := '0' & SIGNED'(ABS(A)); + for i in 0 to A'length-1 loop + if AA(i) = '1' then + PA := PA+BA; + end if; + BA := SHL(BA,one); + end loop; + if (neg= '1') then + return(-PA); + else + return(PA); + end if; + end; + +-- this is the Xilinx customized 'mult(A,B: UNSIGNED) return UNSIGNED' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + + function mult(A,B: UNSIGNED) return UNSIGNED is + + constant msb: integer:=A'length+B'length-1; + variable BA: UNSIGNED(msb downto 0); + variable PA: UNSIGNED(msb downto 0); + + -- pragma map_to_operator MULT_UNS_OP + -- pragma type_function MULT_UNSIGNED_ARG + -- pragma return_port_name Z + + begin + if (A(A'left) = 'X' or B(B'left) = 'X') then + PA := (others => 'X'); + return(PA); + end if; + PA := (others => '0'); + BA := CONV_UNSIGNED(B,(A'length+B'length)); + for i in 0 to A'length-1 loop + if A(i) = '1' then + PA := PA+BA; + end if; + for j in msb downto 1 loop + BA(j):=BA(j-1); + end loop; + BA(0) := '0'; + end loop; + return(PA); + end; + + --function mult(A,B: UNSIGNED) return UNSIGNED is + + -- variable BA: UNSIGNED((A'length+B'length-1) downto 0); + -- variable PA: UNSIGNED((A'length+B'length-1) downto 0); + -- constant one : UNSIGNED(1 downto 0) := "01"; + + -- -- pragma map_to_operator MULT_UNS_OP + -- -- pragma type_function MULT_UNSIGNED_ARG + -- -- pragma return_port_name Z + + ---- pragma label_applies_to mult + + -- -- Add Exemplar synthesis attributes + -- attribute SYNTHESIS_RETURN of PA:variable is "MULT" ; + -- begin + --if (A(A'left) = 'X' or B(B'left) = 'X') then + -- PA := (others => 'X'); + -- return(PA); + --end if; + -- PA := (others => '0'); + -- BA := CONV_UNSIGNED(B,(A'length+B'length)); + -- for i in 0 to A'length-1 loop + -- if A(i) = '1' then + -- PA := PA+BA; + -- end if; + -- BA := SHL(BA,one); + -- end loop; + -- return(PA); + -- end; + + -- subtract two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function minus(A, B: SIGNED) return SIGNED is + variable carry: STD_ULOGIC; + variable BV: STD_ULOGIC_VECTOR (A'left downto 0); + variable sum: SIGNED (A'left downto 0); + + -- pragma map_to_operator SUB_TC_OP + + -- pragma type_function LEFT_SIGNED_ARG + -- pragma return_port_name Z + -- pragma label_applies_to minus + + -- Add Exemplar synthesis attributes + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of sum:variable is TRUE ; + attribute SYNTHESIS_RETURN of sum:variable is "SUB" ; + begin + if (A(A'left) = 'X' or B(B'left) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + carry := '1'; + BV := not STD_ULOGIC_VECTOR(B); + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + + -- add two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function plus(A, B: SIGNED) return SIGNED is + variable carry: STD_ULOGIC; + variable BV, sum: SIGNED (A'left downto 0); + + -- pragma map_to_operator ADD_TC_OP + -- pragma type_function LEFT_SIGNED_ARG + -- pragma return_port_name Z + -- pragma label_applies_to plus + + -- Add Exemplar synthesis attributes + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute is_signed of sum:variable is TRUE ; + attribute SYNTHESIS_RETURN of sum:variable is "ADD" ; + begin + if (A(A'left) = 'X' or B(B'left) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + carry := '0'; + BV := B; + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + + + -- subtract two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is + variable carry: STD_ULOGIC; + variable BV: STD_ULOGIC_VECTOR (A'left downto 0); + variable sum: UNSIGNED (A'left downto 0); + + -- pragma map_to_operator SUB_UNS_OP + -- pragma type_function LEFT_UNSIGNED_ARG + -- pragma return_port_name Z + -- pragma label_applies_to minus + + -- Add Exemplar synthesis attributes + attribute SYNTHESIS_RETURN of sum:variable is "SUB" ; + begin + if (A(A'left) = 'X' or B(B'left) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + carry := '1'; + BV := not STD_ULOGIC_VECTOR(B); + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + +-- this is the Xilinx customized 'unsigned_plus(A,B: UNSIGNED) return UNSIGNED' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + -- add two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is + variable carry,x: STD_ULOGIC; + constant msb: natural:=a'length-1; + variable sum: UNSIGNED (msb downto 0); + alias av: Unsigned(msb downto 0) is a; + alias bv: Unsigned(msb downto 0) is B; + + -- pragma map_to_operator ADD_UNS_OP + -- pragma type_function LEFT_UNSIGNED_ARG + -- pragma return_port_name Z + + begin + if (Av(msb) = 'X' or Bv(msb) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + + sum(0) := Av(0) xor BV(0); + carry := Av(0) and BV(0); + for i in 1 to msb-1 loop + x := Av(i) xor Bv(i); + sum(i) := x xor carry; + carry := (Av(i) and BV(i)) + or (carry and x); + end loop; + if msb>0 then + sum(msb) := Av(msb) xor BV(msb) xor carry; + end if; + return sum; + end; + + + -- add two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + --function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is + --variable carry: STD_ULOGIC; + --variable BV, sum: UNSIGNED (A'left downto 0); + + ---- pragma map_to_operator ADD_UNS_OP + ---- pragma type_function LEFT_UNSIGNED_ARG + -- -- pragma return_port_name Z + ---- pragma label_applies_to plus + + -- -- Add Exemplar synthesis attributes + -- attribute SYNTHESIS_RETURN of sum:variable is "ADD" ; + --begin + --if (A(A'left) = 'X' or B(B'left) = 'X') then + -- sum := (others => 'X'); + -- return(sum); + --end if; + --carry := '0'; + --BV := B; + + --for i in 0 to A'left loop + -- sum(i) := A(i) xor BV(i) xor carry; + -- carry := (A(i) and BV(i)) or + -- (A(i) and carry) or + -- (carry and BV(i)); + --end loop; + --return sum; + --end; + + + + function "*"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to mult + begin + return mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to mult + begin + return mult(CONV_UNSIGNED(L, L'length), + CONV_UNSIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + begin + return mult(CONV_SIGNED(L, L'length+1), + CONV_SIGNED(R, R'length)); -- pragma label mult + end; + + function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to plus + begin + return mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length+1)); -- pragma label mult + end; + + + function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to mult + begin + return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length))); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to mult + begin + return STD_LOGIC_VECTOR (mult(CONV_UNSIGNED(L, L'length), + CONV_UNSIGNED(R, R'length))); -- pragma label mult + end; + + function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + begin + return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length+1), + CONV_SIGNED(R, R'length))); -- pragma label mult + end; + + function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + begin + return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length), + CONV_SIGNED(R, R'length+1))); -- pragma label mult + end; + + + function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. R will be interpreted as signed integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. L will be interpreted as signed integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "+"(L: SIGNED; R: INTEGER) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: INTEGER; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)) ; -- pragma label plus + end; + + + function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label plus + end; + + + + function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length); + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. R will be interpreted as signed integer. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- adder. L will be interpreted as signed integer. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "ADD" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + plus( -- pragma label plus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length))) ; -- pragma label plus + end; + + + function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := L'length; + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := R'length; + begin + return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label plus + end; + + + + function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_minus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. R will be interpreted as signed integer. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor (L will be interpreted as (signed) integer). + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: SIGNED; R: INTEGER) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: INTEGER; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. R is unsigned since CONV_SIGNED on + -- std_ulogic does zero-extension. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. L is unsigned since CONV_SIGNED on + -- std_ulogic does zero-extension. + variable result : UNSIGNED(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1); + return result ; + end; + + + function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label minus + end; + + + + + function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return STD_LOGIC_VECTOR (unsigned_minus(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length); + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length + 1, R'length); + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := max(L'length, R'length + 1); + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. R will be interpreted as signed or + -- unsigned, depending on its range. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. L will be interpreted as signed or + -- unsigned, depending on its range. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := L'length + 1; + -- It does not make sense to extend L one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. R is unsigned since CONV_SIGNED does + -- zero-extend on std_ulogic. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := R'length + 1; + -- It does not make sense to extend R one bit and eliminate + -- the MSB result bit. For Exemplar : build a length-1 + -- unsigned subtractor. L is unsigned since CONV_SIGNED does + -- zero-extend on std_ulogic. + variable result : STD_LOGIC_VECTOR(length-2 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "SUB" ; + begin + result := STD_LOGIC_VECTOR (CONV_UNSIGNED( + minus( -- pragma label minus + CONV_SIGNED(L, length), + CONV_SIGNED(R, length)), + length-1)); + return result ; + end; + + + function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := L'length; + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := R'length; + begin + return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length), + CONV_SIGNED(R, length))); -- pragma label minus + end; + + + + + function "+"(L: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to plus + begin + return L; + end; + + + function "+"(L: SIGNED) return SIGNED is + -- pragma label_applies_to plus + begin + return L; + end; + + + function "-"(L: SIGNED) return SIGNED is + -- pragma label_applies_to minus + variable result : SIGNED(L'range) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute is_signed of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "UMINUS" ; + begin + result := 0 - L; -- pragma label minus + return result ; + end; + + + function "ABS"(L: SIGNED) return SIGNED is + -- pragma label_applies_to abs + + variable result : SIGNED(L'range) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "ABS" ; + begin + if (L(L'left) = '0' or L(L'left) = 'L') then + result := L; + else + result := 0 - L; + end if; + return result ; + end; + + + function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + begin + return STD_LOGIC_VECTOR (L); + end; + + + function "+"(L: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + begin + return STD_LOGIC_VECTOR (L); + end; + + + function "-"(L: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable tmp: SIGNED(L'length-1 downto 0); + variable result : STD_LOGIC_VECTOR(tmp'range) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute is_signed of result:variable is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "UMINUS" ; + begin + tmp := 0 - L; -- pragma label minus + result := STD_LOGIC_VECTOR (tmp); + return result ; + end; + + + function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is + -- pragma label_applies_to abs + + variable tmp: SIGNED(L'length-1 downto 0); + variable result : STD_LOGIC_VECTOR(tmp'range) ; + attribute IS_SIGNED of L:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "ABS" ; + begin + if (L(L'left) = '0' or L(L'left) = 'L') then + result := STD_LOGIC_VECTOR (L); + else + tmp := 0 - L; + result := STD_LOGIC_VECTOR (tmp); + end if; + return result ; + end; + + + -- Type propagation function which returns the type BOOLEAN + function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is + variable Z: BOOLEAN := FALSE ; + -- pragma return_port_name Z + begin + return(Z); + end; + + -- Type propagation function which returns the type BOOLEAN + function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is + variable Z: BOOLEAN := FALSE ; + -- pragma return_port_name Z + begin + return(Z); + end; + + + -- compare two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function is_less(A, B: SIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LT_TC_OP + -- pragma type_function SIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + -- pragma label_applies_to lt + + -- Exemplar synthesis directives + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "LT" ; + begin + if A(sign) /= B(sign) then + result := A(sign) = '1'; + else + result := FALSE; + for i in 0 to sign-1 loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + end if; + return result; + end; + + + -- compare two signed numbers of the same length + -- both arrays must have range (msb downto 0) + function is_less_or_equal(A, B: SIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LEQ_TC_OP + -- pragma type_function SIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + -- pragma label_applies_to leq + + -- Exemplar synthesis directives + attribute IS_SIGNED of A:constant is TRUE ; + attribute IS_SIGNED of B:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "LTE" ; + begin + if A(sign) /= B(sign) then + result := A(sign) = '1'; + else + result := TRUE; + for i in 0 to sign-1 loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + end if; + return result; + end; + + + + -- compare two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LT_UNS_OP + -- pragma type_function UNSIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + -- pragma label_applies_to leq + + -- Exemplar synthesis directives + attribute SYNTHESIS_RETURN of result:variable is "LT" ; + begin + result := FALSE; + for i in 0 to sign loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + return result; + end; + + + -- compare two unsigned numbers of the same length + -- both arrays must have range (msb downto 0) + function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is + constant sign: INTEGER := A'left; + variable a_is_0, b_is_1, result : boolean; + + -- pragma map_to_operator LEQ_UNS_OP + -- pragma type_function UNSIGNED_RETURN_BOOLEAN + -- pragma return_port_name Z + -- pragma label_applies_to leq + + -- Exemplar synthesis directives + attribute SYNTHESIS_RETURN of result:variable is "LTE" ; + begin + result := TRUE; + for i in 0 to sign loop + a_is_0 := A(i) = '0'; + b_is_1 := B(i) = '1'; + result := (a_is_0 and b_is_1) or + (a_is_0 and result) or + (b_is_1 and result); + end loop; + return result; + end; + + + + + function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := L'length + 1; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := R'length + 1; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := L'length; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := R'length; + begin + return is_less(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label lt + end; + + + + + function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length), + CONV_UNSIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := L'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := R'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := L'length; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to leq + constant length: INTEGER := R'length; + begin + return is_less_or_equal(CONV_SIGNED(L, length), + CONV_SIGNED(R, length)); -- pragma label leq + end; + + + + + function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less(CONV_UNSIGNED(R, length), + CONV_UNSIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := L'length + 1; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := R'length + 1; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := L'length; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to gt + constant length: INTEGER := R'length; + begin + return is_less(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label gt + end; + + + + + function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length); + begin + return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length), + CONV_UNSIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := L'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := R'length + 1; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := L'length; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to geq + constant length: INTEGER := R'length; + begin + return is_less_or_equal(CONV_SIGNED(R, length), + CONV_SIGNED(L, length)); -- pragma label geq + end; + + + + + -- for internal use only. Assumes SIGNED arguments of equal length. + function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) + return BOOLEAN is + -- pragma label_applies_to eq + -- pragma built_in SYN_EQL + -- Exemplar synthesis directives + variable result : BOOLEAN ; + attribute SYNTHESIS_RETURN of result:variable is "EQ" ; + begin + for i in L'range loop + if L(i) /= R(i) then + result := FALSE ; + return result ; + end if; + end loop; + result := TRUE ; + return result ; + end; + + -- for internal use only. Assumes SIGNED arguments of equal length. + function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) + return BOOLEAN is + -- pragma label_applies_to neq + -- pragma built_in SYN_NEQ + -- Exemplar synthesis directives + variable result : BOOLEAN ; + attribute SYNTHESIS_RETURN of result:variable is "NEQ" ; + begin + for i in L'range loop + if L(i) /= R(i) then + result := TRUE ; + return result ; + end if; + end loop; + result := FALSE; + return result ; + end; + + + function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := L'length + 1; + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := R'length + 1; + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := L'length; + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to eq + constant length: INTEGER := R'length; + begin + return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + + + function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := max(L'length, R'length); + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := max(L'length + 1, R'length); + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := max(L'length, R'length + 1); + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := L'length + 1; + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := R'length + 1; + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := L'length; + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + + + function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is + -- pragma label_applies_to neq + constant length: INTEGER := R'length; + begin + return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ), + STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) ); + end; + +-- this is the Xilinx customized 'SHL(A,B: UNSIGNED) return UNSIGNED' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + + function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is + -- synopsys subpgm_id 358 + variable shiftval: integer; + constant result_msb: INTEGER := ARG'length-1; + variable result: UNSIGNED (result_msb downto 0); + alias aarg: unsigned(result_msb downto 0) is arg; + begin + -- synopsys synthesis_off + if has_x(count) then + result := (others => 'X'); + return result; + end if; + -- synopsys synthesis_on + shiftval:=conv_integer(count); + result := (others => '0'); + if shiftval <= result_msb then + result(result_msb downto shiftval) := + aarg(result_msb - shiftval downto 0); + end if; + return result; + end; + + + + --Function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is + ---- pragma label_applies_to shl + --constant control_msb: INTEGER := COUNT'length - 1; + --variable control: UNSIGNED (control_msb downto 0); + --constant result_msb: INTEGER := ARG'length-1; + --subtype rtype is UNSIGNED (result_msb downto 0); + --variable result, temp: rtype; + + -- -- Exemplar Synthesis Directive Attributes + -- attribute SYNTHESIS_RETURN of result:variable is "SLL" ; + --begin + --control := MAKE_BINARY(COUNT); + --if (control(0) = 'X') then + -- result := rtype'(others => 'X'); + -- return result; + --end if; + --result := ARG; + --for i in 0 to control_msb loop + -- if control(i) = '1' then + -- temp := rtype'(others => '0'); + -- if 2**i <= result_msb then + -- temp(result_msb downto 2**i) := + -- result(result_msb - 2**i downto 0); + -- end if; + -- result := temp; + -- end if; + --end loop; + --return result; + --end; + + function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is + -- pragma label_applies_to shl + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is SIGNED (result_msb downto 0); + variable result, temp: rtype; + + -- Exemplar Synthesis Directive Attributes + attribute SYNTHESIS_RETURN of result:variable is "SLL" ; + begin + control := MAKE_BINARY(COUNT); + if (control(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := ARG; + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => '0'); + if 2**i <= result_msb then + temp(result_msb downto 2**i) := + result(result_msb - 2**i downto 0); + end if; + result := temp; + end if; + end loop; + return result; + end; + + + function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is + -- pragma label_applies_to shr + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is UNSIGNED (result_msb downto 0); + variable result, temp: rtype; + + -- Exemplar Synthesis Directive Attributes + attribute SYNTHESIS_RETURN of result:variable is "SRL" ; + begin + control := MAKE_BINARY(COUNT); + if (control(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := ARG; + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => '0'); + if 2**i <= result_msb then + temp(result_msb - 2**i downto 0) := + result(result_msb downto 2**i); + end if; + result := temp; + end if; + end loop; + return result; + end; + + function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is + -- pragma label_applies_to shr + + constant control_msb: INTEGER := COUNT'length - 1; + variable control: UNSIGNED (control_msb downto 0); + constant result_msb: INTEGER := ARG'length-1; + subtype rtype is SIGNED (result_msb downto 0); + variable result, temp: rtype; + variable sign_bit: STD_ULOGIC; + -- Exemplar Synthesis Directive Attributes + attribute SYNTHESIS_RETURN of result:variable is "SRA" ; + begin + control := MAKE_BINARY(COUNT); + if (control(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := ARG; + sign_bit := ARG(ARG'left); + for i in 0 to control_msb loop + if control(i) = '1' then + temp := rtype'(others => sign_bit); + if 2**i <= result_msb then + temp(result_msb - 2**i downto 0) := + result(result_msb downto 2**i); + end if; + result := temp; + end if; + end loop; + return result; + end; + + + + + function CONV_INTEGER(ARG: INTEGER) return INTEGER is + begin + return ARG; + end; + +-- this is the Xilinx customized 'CONV_INTEGER(ARG: UNSIGNED) return UNSIGNED' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + + function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is + variable result: INTEGER; + variable tmp: STD_ULOGIC; + -- synopsys built_in SYN_UNSIGNED_TO_INTEGER + -- synopsys subpgm_id 366 + begin + -- synopsys synthesis_off + assert ARG'length <= 31 + report "ARG is too large in CONV_INTEGER" + severity FAILURE; + result := 0; + for i in ARG'range loop + result := result * 2; + tmp := tbl_BINARY(ARG(i)); + if tmp = '1' then + result := result + 1; + elsif tmp = 'X' then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + assert false + report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0." + severity WARNING; + return 0; + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + --function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is + --variable result: INTEGER; + --variable tmp: STD_ULOGIC; + ---- synopsys built_in SYN_UNSIGNED_TO_INTEGER + -- -- Exemplar synthesis directive : + -- attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + --begin + ---- synopsys synthesis_off + --assert ARG'length <= 31 + -- report "ARG is too large in CONV_INTEGER" + -- severity FAILURE; + --result := 0; + --for i in ARG'range loop + -- result := result * 2; + -- tmp := tbl_BINARY(ARG(i)); + -- if tmp = '1' then + -- result := result + 1; + -- elsif tmp = 'X' then + -- assert false + -- report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0." + -- severity WARNING; + -- end if; + --end loop; + --return result; + ---- synopsys synthesis_on + --end; + +-- this is the Xilinx customized 'CONV_INTEGER(ARG: SIGNED) return UNSIGNED' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + + function CONV_INTEGER(ARG: SIGNED) return INTEGER is + variable result: INTEGER; + variable tmp: STD_ULOGIC; + -- synopsys built_in SYN_SIGNED_TO_INTEGER + -- synopsys subpgm_id 367 + begin + -- synopsys synthesis_off + assert ARG'length <= 32 + report "ARG is too large in CONV_INTEGER" + severity FAILURE; + result := 0; + for i in ARG'range loop + if i /= ARG'left then + result := result * 2; + tmp := tbl_BINARY(ARG(i)); + if tmp = '1' then + result := result + 1; + elsif tmp = 'X' then + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + assert false + report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0." + severity WARNING; + return 0; + end if; + end if; + end loop; + tmp := MAKE_BINARY(ARG(ARG'left)); + if tmp = '1' then + if ARG'length = 32 then + result := (result - 2**30) - 2**30; + else + result := result - (2 ** (ARG'length-1)); + end if; + end if; + return result; + -- synopsys synthesis_on + end; + + + + --function CONV_INTEGER(ARG: SIGNED) return INTEGER is + --variable result: INTEGER; + --variable tmp: STD_ULOGIC; + ---- synopsys built_in SYN_SIGNED_TO_INTEGER + -- -- Exemplar synthesis directives : + -- attribute IS_SIGNED of ARG:constant is TRUE ; + -- attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + --begin + ---- synopsys synthesis_off + --assert ARG'length <= 32 + -- report "ARG is too large in CONV_INTEGER" + -- severity FAILURE; + --result := 0; + --for i in ARG'range loop + -- if i /= ARG'left then + -- result := result * 2; + -- tmp := tbl_BINARY(ARG(i)); + -- if tmp = '1' then + -- result := result + 1; + -- elsif tmp = 'X' then + -- assert false + -- report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0." + -- severity WARNING; + -- end if; + -- end if; + --end loop; + --tmp := MAKE_BINARY(ARG(ARG'left)); + --if tmp = '1' then + -- if ARG'length = 32 then + -- result := (result - 2**30) - 2**30; + -- else + -- result := result - (2 ** (ARG'length-1)); + -- end if; + --end if; + --return result; + ---- synopsys synthesis_on + --end; + + + function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is + variable tmp: STD_ULOGIC; + -- synopsys built_in SYN_FEED_THRU + -- Exemplar synthesis directives : + variable result : SMALL_INT ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + tmp := tbl_BINARY(ARG); + if tmp = '1' then + result := 1; + elsif tmp = 'X' then + assert false + report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0." + severity WARNING; + result := 0; + else + result := 0; + end if; + return result ; + -- synopsys synthesis_on + end; + + + -- convert an integer to a unsigned STD_ULOGIC_VECTOR + function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is + variable result: UNSIGNED(SIZE-1 downto 0); + variable temp: integer; + -- synopsys built_in SYN_INTEGER_TO_UNSIGNED + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp / 2; + else + temp := (temp - 1) / 2; -- simulate ASR + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + +-- this is the Xilinx customized '' version +-- I assume the deviation from standard version was to workaround legacy parser +-- issues. Using the Xilinx one, verific one commented out below. -muggli + function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is + variable msb: INTEGER := SIZE - 1; + constant rMsb: INTEGER := SIZE -1; + variable result: UNSIGNED (rMsb downto 0); + alias argDownto : UNSIGNED(ARG'length-1 downto 0) is arg; + -- synopsys built_in SYN_ZERO_EXTEND + -- synopsys subpgm_id 372 + begin + -- synopsys synthesis_off + if ARG'length = SIZE then + -- can't just return arg. Part of the job of this function is to + -- ensure that the index constraints are msb downto 0. + result:=arg; + elsif ARG'length > SIZE then + result := argDownto(size-1 downto 0); + else + result(arg'length-1 downto 0) := arg; + result(size-1 downto arg'length):=(others=>'0'); + msb:=arg'length-1; + end if; + for j in msb downto 0 loop + case result(j) is + when 'U'|'X'|'W'|'Z'|'-' => + assert false + report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." + severity warning; + result := (others => 'X'); + return result; + when 'L' => + result(j):='0'; + when 'H' => + result(j):='1'; + when '0' | '1' => + null; + end case; + end loop; + return result; + -- synopsys synthesis_on + end; + + + + --function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is + --constant msb: INTEGER := min(ARG'length, SIZE) - 1; + --subtype rtype is UNSIGNED (SIZE-1 downto 0); + --variable new_bounds: UNSIGNED (ARG'length-1 downto 0); + --variable result: rtype; + ---- synopsys built_in SYN_ZERO_EXTEND + -- -- Exemplar synthesis directives : + -- attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + --begin + ---- synopsys synthesis_off + --new_bounds := MAKE_BINARY(ARG); + --if (new_bounds(0) = 'X') then + -- result := rtype'(others => 'X'); + -- return result; + --end if; + --result := rtype'(others => '0'); + --result(msb downto 0) := new_bounds(msb downto 0); + --return result; + ---- synopsys synthesis_on + --end; + + + function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is UNSIGNED (SIZE-1 downto 0); + variable new_bounds: UNSIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is + subtype rtype is UNSIGNED (SIZE-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + result(0) := MAKE_BINARY(ARG); + if (result(0) = 'X') then + result := rtype'(others => 'X'); + end if; + return result; + -- synopsys synthesis_on + end; + + + -- convert an integer to a 2's complement STD_ULOGIC_VECTOR + function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is + variable result: SIGNED (SIZE-1 downto 0); + variable temp: integer; + -- synopsys built_in SYN_INTEGER_TO_SIGNED + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp / 2; + else + temp := (temp - 1) / 2; -- simulate ASR + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + + function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is SIGNED (SIZE-1 downto 0); + variable new_bounds : SIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => '0'); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is SIGNED (SIZE-1 downto 0); + variable new_bounds : SIGNED (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is + subtype rtype is SIGNED (SIZE-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + result(0) := MAKE_BINARY(ARG); + if (result(0) = 'X') then + result := rtype'(others => 'X'); + end if; + return result; + -- synopsys synthesis_on + end; + + + -- convert an integer to an STD_LOGIC_VECTOR + function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is + variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable temp: integer; + -- synopsys built_in SYN_INTEGER_TO_SIGNED + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp / 2; + else + temp := (temp - 1) / 2; -- simulate ASR + end if; + end loop; + return result; + -- synopsys synthesis_on + end; + + + function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => '0'); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is + subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + result := rtype'(others => '0'); + result(0) := MAKE_BINARY(ARG); + if (result(0) = 'X') then + result := rtype'(others => 'X'); + end if; + return result; + -- synopsys synthesis_on + end; + + function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) + return STD_LOGIC_VECTOR is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_ZERO_EXTEND + -- Exemplar synthesis directives : + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => '0'); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + + function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is + constant msb: INTEGER := min(ARG'length, SIZE) - 1; + subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0); + variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0); + variable result: rtype; + -- synopsys built_in SYN_SIGN_EXTEND + -- Exemplar synthesis directives : + attribute IS_SIGNED of ARG:constant is TRUE ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + -- synopsys synthesis_off + new_bounds := MAKE_BINARY(ARG); + if (new_bounds(0) = 'X') then + result := rtype'(others => 'X'); + return result; + end if; + result := rtype'(others => new_bounds(new_bounds'left)); + result(msb downto 0) := new_bounds(msb downto 0); + return result; + -- synopsys synthesis_on + end; + + +end std_logic_arith; diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_misc.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_misc.vhd new file mode 100644 index 0000000..602c217 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_misc.vhd @@ -0,0 +1,882 @@ +-------------------------------------------------------------------------- +-- +-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved. +-- +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +-- +-- Package name: std_logic_misc +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions for the Std_logic_1164 Package. +-- +-- Author: GWH +-- +-------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.all; + + +package std_logic_misc is + + -- output-strength types + + type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1, + strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1); + + +--synopsys synthesis_off + + type MINOMAX is array (1 to 3) of TIME; + + + --------------------------------------------------------------------- + -- + -- functions for mapping the STD_(U)LOGIC according to STRENGTH + -- + --------------------------------------------------------------------- + + function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC; + + function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC; + + --------------------------------------------------------------------- + -- + -- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR + -- + --------------------------------------------------------------------- + + -- STD_ULOGIC_VECTOR is the base type of STD_LOGIC_VECTOR in 2008 + -- So following function is redundant +--synopsys synthesis_on + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93; + + function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR; + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions +--synopsys synthesis_off + + attribute CLOSELY_RELATED_TCF of Drive: function is TRUE; + + --------------------------------------------------------------------- + -- + -- conversion functions for sensing various types + -- (the second argument allows the user to specify the value to + -- be returned when the network is undriven) + -- + --------------------------------------------------------------------- + + function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC; + + function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) + return STD_LOGIC_VECTOR_93; + function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) + return STD_ULOGIC_VECTOR; + +-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) +-- return STD_LOGIC_VECTOR_93; +-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) +-- return STD_ULOGIC_VECTOR; + +--synopsys synthesis_on + + + --------------------------------------------------------------------- + -- + -- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR + -- + -- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X, W --> vX if Xflag is TRUE + -- X, W --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- U --> vU if Uflag is TRUE + -- U --> 0 if Uflag is FALSE + -- - --> vDC if DCflag is TRUE + -- - --> 0 if DCflag is FALSE + -- + --------------------------------------------------------------------- + + function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR; + + function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR; + + + --------------------------------------------------------------------- + -- + -- Function: STD_ULOGICtoBIT + -- + -- Purpose: Conversion function from STD_(U)LOGIC to BIT + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X, W --> vX if Xflag is TRUE + -- X, W --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- U --> vU if Uflag is TRUE + -- U --> 0 if Uflag is FALSE + -- - --> vDC if DCflag is TRUE + -- - --> 0 if DCflag is FALSE + -- + --------------------------------------------------------------------- + + function STD_ULOGICtoBIT (V: STD_ULOGIC +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT; + + -------------------------------------------------------------------- + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01; + + function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + +--synopsys synthesis_off + + function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC; + function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC; + function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01; + + function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01; + function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC; + +--synopsys synthesis_on + +-- Synthesis Directive Attributes + attribute IS_SIGNED : BOOLEAN ; + attribute SYNTHESIS_RETURN : STRING ; +end; + + +package body std_logic_misc is + +--synopsys synthesis_off + + type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC; + + -------------------------------------------------------------------- + -- + -- Truth tables for output strength --> STD_ULOGIC lookup + -- + -------------------------------------------------------------------- + + -- truth table for output strength --> STD_ULOGIC lookup + constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE := + -- ------------------------------------------------------------------ + -- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output| + -- ------------------------------------------------------------------ + (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - | + + + + -------------------------------------------------------------------- + -- + -- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through) + -- + -------------------------------------------------------------------- + + -- truth table for output strength --> STD_ULOGIC lookup + constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE := + -- ------------------------------------------------------------------ + -- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output| + -- ------------------------------------------------------------------ + (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 | + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - | + + + + --------------------------------------------------------------------- + -- + -- functions for mapping the STD_(U)LOGIC according to STRENGTH + -- + --------------------------------------------------------------------- + + function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is + begin + return tbl_STRN_STD_ULOGIC(input, strn); + end strength_map; + + + function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is + begin + return tbl_STRN_STD_ULOGIC_Z(input, strn); + end strength_map_z; + + + --------------------------------------------------------------------- + -- + -- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR + -- + --------------------------------------------------------------------- + +--synopsys synthesis_on + function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR is + -- pragma built_in SYN_FEED_THRU + --synopsys synthesis_off + alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V; + --synopsys synthesis_on + -- Added Synthesis Directive + variable result : STD_ULOGIC_VECTOR(V'length-1 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + --synopsys synthesis_off + result := STD_ULOGIC_VECTOR(Value); + return result ; + --synopsys synthesis_on + end Drive; + + + function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93 is + -- pragma built_in SYN_FEED_THRU + --synopsys synthesis_off + alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V; + --synopsys synthesis_on + -- Added Synthesis Directive + variable result : STD_LOGIC_VECTOR_93(V'length-1 downto 0) ; + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin + --synopsys synthesis_off + result := STD_LOGIC_VECTOR_93(Value); + return result ; + --synopsys synthesis_on + end Drive; +--synopsys synthesis_off + + + --------------------------------------------------------------------- + -- + -- conversion functions for sensing various types + -- + -- (the second argument allows the user to specify the value to + -- be returned when the network is undriven) + -- + --------------------------------------------------------------------- + + function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) + return STD_LOGIC is + begin + if V = 'Z' then + return vZ; + else + return V; + end if; + end Sense; + + + function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) + return STD_LOGIC_VECTOR_93 is + alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V; + variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0); + begin + for i in Value'range loop + if ( Value(i) = 'Z' ) then + Result(i) := vZ; + else + Result(i) := Value(i); + end if; + end loop; + return Result; + end Sense; + + + function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) + return STD_ULOGIC_VECTOR is + alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V; + variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0); + begin + for i in Value'range loop + if ( Value(i) = 'Z' ) then + Result(i) := vZ; + else + Result(i) := Value(i); + end if; + end loop; + return Result; + end Sense; + + +-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) +-- return STD_LOGIC_VECTOR_93 is +-- alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V; +-- variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0); +-- begin +-- for i in Value'range loop +-- if ( Value(i) = 'Z' ) then +-- Result(i) := vZ; +-- else +-- Result(i) := Value(i); +-- end if; +-- end loop; +-- return Result; +-- end Sense; + + +-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) +-- return STD_ULOGIC_VECTOR is +-- alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V; +-- variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0); +-- begin +-- for i in Value'range loop +-- if ( Value(i) = 'Z' ) then +-- Result(i) := vZ; +-- else +-- Result(i) := Value(i); +-- end if; +-- end loop; +-- return Result; +-- end Sense; + + --------------------------------------------------------------------- + -- + -- Function: STD_LOGIC_VECTORtoBIT_VECTOR + -- + -- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X, W --> vX if Xflag is TRUE + -- X, W --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- U --> vU if Uflag is TRUE + -- U --> 0 if Uflag is FALSE + -- - --> vDC if DCflag is TRUE + -- - --> 0 if DCflag is FALSE + -- + --------------------------------------------------------------------- + +--synopsys synthesis_on + function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR is + -- pragma built_in SYN_FEED_THRU + variable Result: BIT_VECTOR (V'length-1 downto 0); + + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; +--synopsys synthesis_off + alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in Value'range loop + case Value(i) is + when '0' | 'L' => + Result(i) := '0'; + when '1' | 'H' => + Result(i) := '1'; + when 'X' | 'W' => + if ( Xflag ) then + Result(i) := vX; + else + Result(i) := '0'; + assert FALSE + report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0" + severity WARNING; + end if; + when others => + if ( Zflag ) then + Result(i) := vZ; + else + Result(i) := '0'; + assert FALSE + report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0" + severity WARNING; + end if; + end case; + end loop; + return Result; +--synopsys synthesis_on + end STD_LOGIC_VECTORtoBIT_VECTOR; + + + + + --------------------------------------------------------------------- + -- + -- Function: STD_ULOGIC_VECTORtoBIT_VECTOR + -- + -- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X, W --> vX if Xflag is TRUE + -- X, W --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- U --> vU if Uflag is TRUE + -- U --> 0 if Uflag is FALSE + -- - --> vDC if DCflag is TRUE + -- - --> 0 if DCflag is FALSE + -- + --------------------------------------------------------------------- + + function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR is + -- pragma built_in SYN_FEED_THRU + variable Result: BIT_VECTOR (V'length-1 downto 0); + + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; +--synopsys synthesis_off + alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in Value'range loop + case Value(i) is + when '0' | 'L' => + Result(i) := '0'; + when '1' | 'H' => + Result(i) := '1'; + when 'X' | 'W' => + if ( Xflag ) then + Result(i) := vX; + else + Result(i) := '0'; + assert FALSE + report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0" + severity WARNING; + end if; + when others => + if ( Zflag ) then + Result(i) := vZ; + else + Result(i) := '0'; + assert FALSE + report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0" + severity WARNING; + end if; + end case; + end loop; + return Result; +--synopsys synthesis_on + end STD_ULOGIC_VECTORtoBIT_VECTOR; + + + + + --------------------------------------------------------------------- + -- + -- Function: STD_ULOGICtoBIT + -- + -- Purpose: Conversion function from STD_ULOGIC to BIT + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X, W --> vX if Xflag is TRUE + -- X, W --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- U --> vU if Uflag is TRUE + -- U --> 0 if Uflag is FALSE + -- - --> vDC if DCflag is TRUE + -- - --> 0 if DCflag is FALSE + -- + --------------------------------------------------------------------- + + function STD_ULOGICtoBIT (V: STD_ULOGIC +--synopsys synthesis_off + ; vX, vZ, vU, vDC: BIT := '0'; + Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT is + -- pragma built_in SYN_FEED_THRU + variable Result: BIT; + + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; + begin +--synopsys synthesis_off + case V is + when '0' | 'L' => + Result := '0'; + when '1' | 'H' => + Result := '1'; + when 'X' | 'W' => + if ( Xflag ) then + Result := vX; + else + Result := '0'; + assert FALSE + report "STD_ULOGICtoBIT: X --> 0" + severity WARNING; + end if; + when others => + if ( Zflag ) then + Result := vZ; + else + Result := '0'; + assert FALSE + report "STD_ULOGICtoBIT: Z --> 0" + severity WARNING; + end if; + end case; + return Result; +--synopsys synthesis_on + end STD_ULOGICtoBIT; + + + -------------------------------------------------------------------------- + + -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ; + begin + result := '1'; + for i in ARG'range loop + result := result and ARG(i); + end loop; + return result; + end; + + function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + begin + return not AND_REDUCE(ARG); + end; + + function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ; + begin + result := '0'; + for i in ARG'range loop + result := result or ARG(i); + end loop; + return result; + end; + + function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + begin + return not OR_REDUCE(ARG); + end; + + function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ; + begin + result := '0'; + for i in ARG'range loop + result := result xor ARG(i); + end loop; + return result; + end; + + function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is + begin + return not XOR_REDUCE(ARG); + end; + + function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ; + begin + result := '1'; + for i in ARG'range loop + result := result and ARG(i); + end loop; + return result; + end; + + function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + begin + return not AND_REDUCE(ARG); + end; + + function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ; + begin + result := '0'; + for i in ARG'range loop + result := result or ARG(i); + end loop; + return result; + end; + + function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + begin + return not OR_REDUCE(ARG); + end; + + function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + variable result: STD_LOGIC; + -- Added Synthesis Directive + attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ; + begin + result := '0'; + for i in ARG'range loop + result := result xor ARG(i); + end loop; + return result; + end; + + function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is + begin + return not XOR_REDUCE(ARG); + end; + -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions + +--synopsys synthesis_off + + function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is + type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC; + + -- truth table for tristate "buf" function (Enable active Low) + constant tbl_BUF3S: TRISTATE_TABLE := + -- ---------------------------------------------------- + -- | Input U X 0 1 | Enable Strength | + -- ---------------------------------|-----------------| + ((('U', 'U', 'U', 'U'), --| U X01 | + ('U', 'X', 'X', 'X'), --| X X01 | + ('Z', 'Z', 'Z', 'Z'), --| 0 X01 | + ('U', 'X', '0', '1')), --| 1 X01 | + (('U', 'U', 'U', 'U'), --| U X0H | + ('U', 'X', 'X', 'X'), --| X X0H | + ('Z', 'Z', 'Z', 'Z'), --| 0 X0H | + ('U', 'X', '0', 'H')), --| 1 X0H | + (('U', 'U', 'U', 'U'), --| U XL1 | + ('U', 'X', 'X', 'X'), --| X XL1 | + ('Z', 'Z', 'Z', 'Z'), --| 0 XL1 | + ('U', 'X', 'L', '1')), --| 1 XL1 | + (('U', 'U', 'U', 'Z'), --| U X0Z | + ('U', 'X', 'X', 'Z'), --| X X0Z | + ('Z', 'Z', 'Z', 'Z'), --| 0 X0Z | + ('U', 'X', '0', 'Z')), --| 1 X0Z | + (('U', 'U', 'U', 'U'), --| U XZ1 | + ('U', 'X', 'X', 'X'), --| X XZ1 | + ('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 | + ('U', 'X', 'Z', '1')), --| 1 XZ1 | + (('U', 'U', 'U', 'U'), --| U WLH | + ('U', 'W', 'W', 'W'), --| X WLH | + ('Z', 'Z', 'Z', 'Z'), --| 0 WLH | + ('U', 'W', 'L', 'H')), --| 1 WLH | + (('U', 'U', 'U', 'U'), --| U WLZ | + ('U', 'W', 'W', 'Z'), --| X WLZ | + ('Z', 'Z', 'Z', 'Z'), --| 0 WLZ | + ('U', 'W', 'L', 'Z')), --| 1 WLZ | + (('U', 'U', 'U', 'U'), --| U WZH | + ('U', 'W', 'W', 'W'), --| X WZH | + ('Z', 'Z', 'Z', 'Z'), --| 0 WZH | + ('U', 'W', 'Z', 'H')), --| 1 WZH | + (('U', 'U', 'U', 'U'), --| U W0H | + ('U', 'W', 'W', 'W'), --| X W0H | + ('Z', 'Z', 'Z', 'Z'), --| 0 W0H | + ('U', 'W', '0', 'H')), --| 1 W0H | + (('U', 'U', 'U', 'U'), --| U WL1 | + ('U', 'W', 'W', 'W'), --| X WL1 | + ('Z', 'Z', 'Z', 'Z'), --| 0 WL1 | + ('U', 'W', 'L', '1')));--| 1 WL1 | + begin + return tbl_BUF3S(Strn, Enable, Input); + end fun_BUF3S; + + + function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is + type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC; + + -- truth table for tristate "buf" function (Enable active Low) + constant tbl_BUF3SL: TRISTATE_TABLE := + -- ---------------------------------------------------- + -- | Input U X 0 1 | Enable Strength | + -- ---------------------------------|-----------------| + ((('U', 'U', 'U', 'U'), --| U X01 | + ('U', 'X', 'X', 'X'), --| X X01 | + ('U', 'X', '0', '1'), --| 0 X01 | + ('Z', 'Z', 'Z', 'Z')), --| 1 X01 | + (('U', 'U', 'U', 'U'), --| U X0H | + ('U', 'X', 'X', 'X'), --| X X0H | + ('U', 'X', '0', 'H'), --| 0 X0H | + ('Z', 'Z', 'Z', 'Z')), --| 1 X0H | + (('U', 'U', 'U', 'U'), --| U XL1 | + ('U', 'X', 'X', 'X'), --| X XL1 | + ('U', 'X', 'L', '1'), --| 0 XL1 | + ('Z', 'Z', 'Z', 'Z')), --| 1 XL1 | + (('U', 'U', 'U', 'Z'), --| U X0Z | + ('U', 'X', 'X', 'Z'), --| X X0Z | + ('U', 'X', '0', 'Z'), --| 0 X0Z | + ('Z', 'Z', 'Z', 'Z')), --| 1 X0Z | + (('U', 'U', 'U', 'U'), --| U XZ1 | + ('U', 'X', 'X', 'X'), --| X XZ1 | + ('U', 'X', 'Z', '1'), --| 0 XZ1 | + ('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 | + (('U', 'U', 'U', 'U'), --| U WLH | + ('U', 'W', 'W', 'W'), --| X WLH | + ('U', 'W', 'L', 'H'), --| 0 WLH | + ('Z', 'Z', 'Z', 'Z')), --| 1 WLH | + (('U', 'U', 'U', 'U'), --| U WLZ | + ('U', 'W', 'W', 'Z'), --| X WLZ | + ('U', 'W', 'L', 'Z'), --| 0 WLZ | + ('Z', 'Z', 'Z', 'Z')), --| 1 WLZ | + (('U', 'U', 'U', 'U'), --| U WZH | + ('U', 'W', 'W', 'W'), --| X WZH | + ('U', 'W', 'Z', 'H'), --| 0 WZH | + ('Z', 'Z', 'Z', 'Z')), --| 1 WZH | + (('U', 'U', 'U', 'U'), --| U W0H | + ('U', 'W', 'W', 'W'), --| X W0H | + ('U', 'W', '0', 'H'), --| 0 W0H | + ('Z', 'Z', 'Z', 'Z')), --| 1 W0H | + (('U', 'U', 'U', 'U'), --| U WL1 | + ('U', 'W', 'W', 'W'), --| X WL1 | + ('U', 'W', 'L', '1'), --| 0 WL1 | + ('Z', 'Z', 'Z', 'Z')));--| 1 WL1 | + begin + return tbl_BUF3SL(Strn, Enable, Input); + end fun_BUF3SL; + + + function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is + type MUX_TABLE is array (UX01, UX01, UX01) of UX01; + + -- truth table for "MUX2x1" function + constant tbl_MUX2x1: MUX_TABLE := + -------------------------------------------- + --| In0 'U' 'X' '0' '1' | Sel In1 | + -------------------------------------------- + ((('U', 'U', 'U', 'U'), --| 'U' 'U' | + ('U', 'U', 'U', 'U'), --| 'X' 'U' | + ('U', 'X', '0', '1'), --| '0' 'U' | + ('U', 'U', 'U', 'U')), --| '1' 'U' | + (('U', 'X', 'U', 'U'), --| 'U' 'X' | + ('U', 'X', 'X', 'X'), --| 'X' 'X' | + ('U', 'X', '0', '1'), --| '0' 'X' | + ('X', 'X', 'X', 'X')), --| '1' 'X' | + (('U', 'U', '0', 'U'), --| 'U' '0' | + ('U', 'X', '0', 'X'), --| 'X' '0' | + ('U', 'X', '0', '1'), --| '0' '0' | + ('0', '0', '0', '0')), --| '1' '0' | + (('U', 'U', 'U', '1'), --| 'U' '1' | + ('U', 'X', 'X', '1'), --| 'X' '1' | + ('U', 'X', '0', '1'), --| '0' '1' | + ('1', '1', '1', '1')));--| '1' '1' | + begin + return tbl_MUX2x1(Input1, Sel, Input0); + end fun_MUX2x1; + + + function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is + type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01; + + ---------------------------------------------------------------------------- + -- The "tbl_MAJ23" truth table return 1 if the majority of three + -- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if + -- uninitialized. + ---------------------------------------------------------------------------- + constant tbl_MAJ23: MAJ23_TABLE := + -------------------------------------------- + --| In0 'U' 'X' '0' '1' | In1 In2 | + -------------------------------------------- + ((('U', 'U', 'U', 'U'), --| 'U' 'U' | + ('U', 'U', 'U', 'U'), --| 'X' 'U' | + ('U', 'U', '0', 'U'), --| '0' 'U' | + ('U', 'U', 'U', '1')), --| '1' 'U' | + (('U', 'U', 'U', 'U'), --| 'U' 'X' | + ('U', 'X', 'X', 'X'), --| 'X' 'X' | + ('U', 'X', '0', 'X'), --| '0' 'X' | + ('U', 'X', 'X', '1')), --| '1' 'X' | + (('U', 'U', '0', 'U'), --| 'U' '0' | + ('U', 'X', '0', 'X'), --| 'X' '0' | + ('0', '0', '0', '0'), --| '0' '0' | + ('U', 'X', '0', '1')), --| '1' '0' | + (('U', 'U', 'U', '1'), --| 'U' '1' | + ('U', 'X', 'X', '1'), --| 'X' '1' | + ('U', 'X', '0', '1'), --| '0' '1' | + ('1', '1', '1', '1')));--| '1' '1' | + + begin + return tbl_MAJ23(Input0, Input1, Input2); + end fun_MAJ23; + + + function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is + TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC; + + -- truth table for "WiredX" function + ------------------------------------------------------------------- + -- resolution function + ------------------------------------------------------------------- + CONSTANT resolution_table : stdlogic_table := ( + -- --------------------------------------------------------- + -- | U X 0 1 Z W L H - | | + -- --------------------------------------------------------- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | + ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | + ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | + ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | + ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | + ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | + ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - | + -- Added Synthesis Directive + variable result : STD_LOGIC ; + attribute SYNTHESIS_RETURN of result:variable is "WIRED_THREE_STATE" ; + begin + result := resolution_table(Input0, Input1); + return result ; + end fun_WiredX; + +--synopsys synthesis_on + +end; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_signed.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_signed.vhd new file mode 100644 index 0000000..ca7cf00 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_signed.vhd @@ -0,0 +1,389 @@ +-------------------------------------------------------------------------- +-- -- +-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. -- +-- All rights reserved. -- +-- -- +-- This source file may be used and distributed without restriction -- +-- provided that this copyright statement is not removed from the file -- +-- and that any derivative work contains this copyright notice. -- +-- -- +-- Package name: STD_LOGIC_SIGNED -- +-- -- +-- -- +-- Date: 09/11/91 KN -- +-- 10/08/92 AMT change std_ulogic to signed std_logic -- +-- 10/28/92 AMT added signed functions, -, ABS -- +-- -- +-- Purpose: -- +-- A set of signed arithemtic, conversion, -- +-- and comparision functions for STD_LOGIC_VECTOR. -- +-- -- +-- Note: Comparision of same length std_logic_vector is defined -- +-- in the LRM. The interpretation is for unsigned vectors -- +-- This package will "overload" that definition. -- +-- -- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +package STD_LOGIC_SIGNED is + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; + function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; + function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + + function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER; + +-- remove this since it is already in std_logic_arith +-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR; + + + attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_plus"; + attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_plus"; + attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_plus"; + attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_plus"; + attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_plus"; + + attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_minus"; + attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_minus"; + attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_minus"; + attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_minus"; + attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_minus"; + + attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus"; + attribute foreign of "-"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_unary_minus"; + attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_mult"; + + attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less"; + attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less"; + attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less"; + + attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less_or_equal"; + attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less_or_equal"; + attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less_or_equal"; + + attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater"; + attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater"; + attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater"; + + attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater_or_equal"; + attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater_or_equal"; + attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater_or_equal"; + + attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_equal"; + attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_equal"; + attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_equal"; + + attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_not_equal"; + attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_not_equal"; + attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_not_equal"; + + attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_signed_to_integer"; + + attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shl"; + attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shr"; + +end STD_LOGIC_SIGNED; + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +package body STD_LOGIC_SIGNED is + + + function maximum(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR (length-1 downto 0); + begin + result := SIGNED(L) + SIGNED(R); -- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := SIGNED(L) + R; -- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L + SIGNED(R); -- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := SIGNED(L) + R; -- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L + SIGNED(R); -- pragma label plus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR (length-1 downto 0); + begin + result := SIGNED(L) - SIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := SIGNED(L) - R; -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L - SIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := SIGNED(L) - R; -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L - SIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := + SIGNED(L); -- pragma label plus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := - SIGNED(L); -- pragma label minus + return std_logic_vector(result); + end; + + function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := ABS( SIGNED(L)); + return std_logic_vector(result); + end; + + function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to mult + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); + begin + result := SIGNED(L) * SIGNED(R); -- pragma label mult + return std_logic_vector(result); + end; + + function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := maximum(L'length, R'length); + begin + return SIGNED(L) < SIGNED(R); -- pragma label lt + end; + + function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + begin + return SIGNED(L) < R; -- pragma label lt + end; + + function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to lt + begin + return L < SIGNED(R); -- pragma label lt + end; + + function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to leq + begin + return SIGNED(L) <= SIGNED(R); -- pragma label leq + end; + + function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + begin + return SIGNED(L) <= R; -- pragma label leq + end; + + function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to leq + begin + return L <= SIGNED(R); -- pragma label leq + end; + + function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to gt + begin + return SIGNED(L) > SIGNED(R); -- pragma label gt + end; + + function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + begin + return SIGNED(L) > R; -- pragma label gt + end; + + function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to gt + begin + return L > SIGNED(R); -- pragma label gt + end; + + function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to geq + begin + return SIGNED(L) >= SIGNED(R); -- pragma label geq + end; + + function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + begin + return SIGNED(L) >= R; -- pragma label geq + end; + + function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to geq + begin + return L >= SIGNED(R); -- pragma label geq + end; + + function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return SIGNED(L) = SIGNED(R); + end; + + function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + begin + return SIGNED(L) = R; + end; + + function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return L = SIGNED(R); + end; + + function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return SIGNED(L) /= SIGNED(R); + end; + + function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + begin + return SIGNED(L) /= R; + end; + + function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return L /= SIGNED(R); + end; + + function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT))); + end; + + function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT))); + end; + + + +-- This function converts std_logic_vector to a signed integer value +-- using a conversion function in std_logic_arith + function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is + variable result : SIGNED(ARG'range); + begin + result := SIGNED(ARG); + return CONV_INTEGER(result); + end; +end STD_LOGIC_SIGNED; + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_unsigned.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_unsigned.vhd new file mode 100644 index 0000000..fa63bbe --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_unsigned.vhd @@ -0,0 +1,382 @@ +-------------------------------------------------------------------------- +-- -- +-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. -- +-- All rights reserved. -- +-- -- +-- This source file may be used and distributed without restriction -- +-- provided that this copyright statement is not removed from the file -- +-- and that any derivative work contains this copyright notice. -- +-- -- +-- Package name: STD_LOGIC_UNSIGNED -- +-- -- +-- -- +-- Date: 09/11/92 KN -- +-- 10/08/92 AMT -- +-- -- +-- Purpose: -- +-- A set of unsigned arithemtic, conversion, -- +-- and comparision functions for STD_LOGIC_VECTOR. -- +-- -- +-- Note: comparision of same length discrete arrays is defined -- +-- by the LRM. This package will "overload" those -- +-- definitions -- +-- -- +-------------------------------------------------------------------------- +-- Modifications : +-- Attributes added for Xilinx specific optimizations +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +package STD_LOGIC_UNSIGNED is + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; + function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; + function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; + function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; + function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + + function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; + function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; + function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; + function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; + + function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER; + + --attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_greater_stdv_stdv"; + + --attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_equal_stdv_stdv"; + + attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_plus"; + attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_plus"; + attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_plus"; + attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_plus"; + attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_plus"; + + attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_minus"; + attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_minus"; + attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_minus"; + attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_minus"; + attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_minus"; + + attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus"; + + attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_mult"; + + attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less"; + attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less"; + attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less"; + + attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less_or_equal"; + attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less_or_equal"; + attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less_or_equal"; + + attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater"; + attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater"; + attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater"; + + attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater_or_equal"; + attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater_or_equal"; + attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater_or_equal"; + + + attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_equal"; + attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_equal"; + attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_equal"; + + attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_not_equal"; + attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_not_equal"; + attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_not_equal"; + + attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_unsigned_to_integer"; + + attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shl"; + attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shr"; + +-- remove this since it is already in std_logic_arith +-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR; + +end STD_LOGIC_UNSIGNED; + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +package body STD_LOGIC_UNSIGNED is + + + function maximum(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR (length-1 downto 0); + begin + result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := UNSIGNED(L) + R;-- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L + UNSIGNED(R);-- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := UNSIGNED(L) + R;-- pragma label plus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to plus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L + UNSIGNED(R);-- pragma label plus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR (length-1 downto 0); + begin + result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := UNSIGNED(L) - R; -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L - UNSIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := UNSIGNED(L) - R; + return std_logic_vector(result); + end; + + function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to minus + variable result : STD_LOGIC_VECTOR (R'range); + begin + result := L - UNSIGNED(R); -- pragma label minus + return std_logic_vector(result); + end; + + function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + variable result : STD_LOGIC_VECTOR (L'range); + begin + result := + UNSIGNED(L); + return std_logic_vector(result); + end; + + function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + -- pragma label_applies_to mult + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); + begin + result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult + return std_logic_vector(result); + end; + + function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to lt + constant length: INTEGER := maximum(L'length, R'length); + begin + return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt + end; + + function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to lt + begin + return UNSIGNED(L) < R; -- pragma label lt + end; + + function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to lt + begin + return L < UNSIGNED(R); -- pragma label lt + end; + + function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to leq + begin + return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq + end; + + function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to leq + begin + return UNSIGNED(L) <= R; -- pragma label leq + end; + + function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to leq + begin + return L <= UNSIGNED(R); -- pragma label leq + end; + + function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to gt + begin + return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt + end; + + function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to gt + begin + return UNSIGNED(L) > R; -- pragma label gt + end; + + function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to gt + begin + return L > UNSIGNED(R); -- pragma label gt + end; + + function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to geq + begin + return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq + end; + + function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + -- pragma label_applies_to geq + begin + return UNSIGNED(L) >= R; -- pragma label geq + end; + + function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + -- pragma label_applies_to geq + begin + return L >= UNSIGNED(R); -- pragma label geq + end; + + function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) = UNSIGNED(R); + end; + + function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + begin + return UNSIGNED(L) = R; + end; + + function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return L = UNSIGNED(R); + end; + + function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return UNSIGNED(L) /= UNSIGNED(R); + end; + + function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is + begin + return UNSIGNED(L) /= R; + end; + + function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is + begin + return L /= UNSIGNED(R); + end; + + function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is + variable result : UNSIGNED(ARG'range); + begin + result := UNSIGNED(ARG); + return CONV_INTEGER(result); + end; + function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT))); + end; + + function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + begin + return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT))); + end; + + +-- remove this since it is already in std_logic_arith + --function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is + --variable result1 : UNSIGNED (SIZE-1 downto 0); + --variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0); + --begin + --result1 := CONV_UNSIGNED(ARG,SIZE); + --return std_logic_vector(result1); + --end; + + +end STD_LOGIC_UNSIGNED; + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/synopsys/types.vhd b/resources/dide-lsp/static/vhdl_std_lib/synopsys/types.vhd new file mode 100644 index 0000000..84d7a1c --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/synopsys/types.vhd @@ -0,0 +1,1152 @@ +---------------------------------------------------------------------------- +-- +-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved. +-- +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +-- +-- Package name: TYPES +-- +-- Purpose: This package defines the types, logic functions, +-- truth tables, definitions for wired signals, and +-- conversion functions for the Synopsys Standard Logic library. +-- +-- Author: JT, PH, GWH +-- +-- Modified with attributes for Synopsys synthesis. +-- +-- Also synthesis_off and synthesis_on pairs required because +-- synthesis does not fully support or gives warnings about: +-- 1) Multi-dimentional arrays +-- 2) aliases +-- 3) assert +-- +---------------------------------------------------------------------------- +-- Exemplar : Added Synthesis Directive Attributes for CORE +-- These attributes work like the Synopsys pragmas. The +-- attributes are declared in the "attributes" vhdl package +---------------------------------------------------------------------------- +--synopsys translate_off +library SYNOPSYS; +use SYNOPSYS.ATTRIBUTES.all; +--synopsys translate_on + + +package TYPES is + + --------------------------------------------------------------------- + -- + -- Definitions for Standard Logic types + -- + --------------------------------------------------------------------- + + -- multi-valued logic 7 states: + + type MVL7 is ('X', -- strong X (strong unknown) + '0', -- strong 0 (strong low) + '1', -- strong 1 (strong high) + 'Z', -- tristate X (high impedance) + 'W', -- weak X (weak unknown) + 'L', -- weak 0 (weak low) + 'H'); -- weak 1 (weak high) + + attribute ENUM_ENCODING : STRING; + attribute ENUM_ENCODING of MVL7 : type is "D 0 1 Z U 0 1"; + + -- Exemplar Synthesis encoding : + attribute LOGIC_TYPE_ENCODING : STRING ; + attribute LOGIC_TYPE_ENCODING of MVL7:type is ('X','0','1','Z','X','0','1') ; + + -- Declaration of Exemplar Synthesis Directive attributes + attribute IS_SIGNED : BOOLEAN ; + attribute SYNTHESIS_RETURN : STRING ; + + -- vector of MVL7 + + type MVL7_VECTOR is array (Natural range <>) of MVL7; + + + + + -- output-strength types + + type STRENGTH is (X01, X0H, XL1, X0Z, XZ1, WLH, WLZ, WZH, W0H, WL1); + + + + ----------------------------------------------------------------------- + -- + -- Internal types for table look up + -- + ---------------------------------------------------------------------- + +--synopsys synthesis_off + type MVL7_TAB1D is array (MVL7) of MVL7; -- one dimensional + + type MVL7_TABLE is array (MVL7, MVL7) of MVL7; -- two dimensional + + + + type STRN_MVL7_TABLE is array (MVL7,STRENGTH) of MVL7; + + type MUX_TABLE is array (MVL7 range 'X' to '1', + MVL7 range 'X' to '1', + MVL7 range 'X' to '1') of MVL7; + + type TRISTATE_TABLE is array (STRENGTH, + MVL7 range 'X' to '1', + MVL7 range 'X' to '1') of MVL7; + + type MINOMAX is array (1 to 3) of TIME; + + + + + ----------------------------------------------------------------------- + -- + -- Truth tables for output strength --> MVL7 lookup + -- + ----------------------------------------------------------------------- + + -- truth table for output strength --> MVL7 lookup + constant tbl_STRN_MVL7: STRN_MVL7_TABLE := + -- ------------------------------------------------------------------ + -- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output| + -- ------------------------------------------------------------------ + (('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1')); -- | H | + + + + ----------------------------------------------------------------------- + -- + -- Truth tables for strength --> MVL7 mapping ('Z' pass through) + -- + ----------------------------------------------------------------------- + + -- truth table for output strength --> MVL7 lookup + constant tbl_STRN_MVL7_Z: STRN_MVL7_TABLE := + -- ------------------------------------------------------------------ + -- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output| + -- ------------------------------------------------------------------ + (('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 | + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z | + ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W | + ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L | + ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1')); -- | H | + + + + ----------------------------------------------------------------------- + -- + -- Truth tables for logical operations + -- + ----------------------------------------------------------------------- + + + -- truth table for "and" function + constant tbl_AND: MVL7_TABLE := + -- ----------------------------------------------- + -- | X 0 1 Z W L H | | + -- ----------------------------------------------- + (('X', '0', 'X', 'X', 'X', '0', 'X'), -- | X | + ('0', '0', '0', '0', '0', '0', '0'), -- | 0 | + ('X', '0', '1', 'X', 'X', '0', '1'), -- | 1 | + ('X', '0', 'X', 'X', 'X', '0', 'X'), -- | Z | + ('X', '0', 'X', 'X', 'X', '0', 'X'), -- | W | + ('0', '0', '0', '0', '0', '0', '0'), -- | L | + ('X', '0', '1', 'X', 'X', '0', '1')); -- | H | + + + -- truth table for "or" function + constant tbl_OR: MVL7_TABLE := + -- ----------------------------------------------- + -- | X 0 1 Z W L H | | + -- ----------------------------------------------- + (('X', 'X', '1', 'X', 'X', 'X', '1'), -- | X | + ('X', '0', '1', 'X', 'X', '0', '1'), -- | 0 | + ('1', '1', '1', '1', '1', '1', '1'), -- | 1 | + ('X', 'X', '1', 'X', 'X', 'X', '1'), -- | Z | + ('X', 'X', '1', 'X', 'X', 'X', '1'), -- | W | + ('X', '0', '1', 'X', 'X', '0', '1'), -- | L | + ('1', '1', '1', '1', '1', '1', '1')); -- | H | + + + -- truth table for "xor" function + constant tbl_XOR: MVL7_TABLE := + -- ----------------------------------------------- + -- | X 0 1 Z W L H | | + -- ----------------------------------------------- + (('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | + ('X', '0', '1', 'X', 'X', '0', '1'), -- | 0 | + ('X', '1', '0', 'X', 'X', '1', '0'), -- | 1 | + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z | + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W | + ('X', '0', '1', 'X', 'X', '0', '1'), -- | L | + ('X', '1', '0', 'X', 'X', '1', '0')); -- | H | + + + -- truth table for "not" function + constant tbl_NOT: MVL7_TAB1D := + -- ------------------------------------- + -- | X 0 1 Z W L H | + -- ------------------------------------- + ('X', '1', '0', 'X', 'X', '1', '0'); + + + -- truth table for "buf" function + constant tbl_BUF: MVL7_TAB1D := + -- ------------------------------------- + -- | X 0 1 Z W L H | + -- ------------------------------------- + ('X', '0', '1', 'X', 'X', '0', '1'); + + + + -- truth table for tristate "buf" function (Enable active High) + constant tbl_BUF3S: TRISTATE_TABLE := + -- ---------------------------------------- + -- | X 0 1 | Enable Strength | + -- ---------------------------------------- + ((('X', 'X', 'X'), --| X X01 | + ('Z', 'Z', 'Z'), --| 0 X01 | + ('X', '0', '1')), --| 1 X01 | + + (('X', 'X', 'X'), --| X X0H | + ('Z', 'Z', 'Z'), --| 0 X0H | + ('X', '0', 'H')), --| 1 X0H | + + (('X', 'X', 'X'), --| X XL1 | + ('Z', 'Z', 'Z'), --| 0 XL1 | + ('X', 'L', '1')), --| 1 XL1 | + + (('X', 'X', 'Z'), --| X X0Z | + ('Z', 'Z', 'Z'), --| 0 X0Z | + ('X', '0', 'Z')), --| 1 X0Z | + + (('X', 'X', 'X'), --| X XZ1 | + ('Z', 'Z', 'Z'), --| 0 XZ1 | + ('X', 'Z', '1')), --| 1 XZ1 | + + (('W', 'W', 'W'), --| X WLH | + ('Z', 'Z', 'Z'), --| 0 WLH | + ('W', 'L', 'H')), --| 1 WLH | + + (('W', 'W', 'Z'), --| X WLZ | + ('Z', 'Z', 'Z'), --| 0 WLZ | + ('W', 'L', 'Z')), --| 1 WLZ | + + (('W', 'W', 'W'), --| X WZH | + ('Z', 'Z', 'Z'), --| 0 WZH | + ('W', 'Z', 'H')), --| 1 WZH | + + (('W', 'W', 'W'), --| X W0H | + ('Z', 'Z', 'Z'), --| 0 W0H | + ('W', '0', 'H')), --| 1 W0H | + + (('W', 'W', 'W'), --| X WL1 | + ('Z', 'Z', 'Z'), --| 0 WL1 | + ('W', 'L', '1')));--| 1 WL1 | + + + + + -- truth table for tristate "buf" function (Enable active Low) + constant tbl_BUF3SL: TRISTATE_TABLE := + -- ---------------------------------------- + -- | X 0 1 | Enable Strength | + -- ---------------------------------------- + ((('X', 'X', 'X'), --| X X01 | + ('X', '0', '1'), --| 0 X01 | + ('Z', 'Z', 'Z')), --| 1 X01 | + + (('X', 'X', 'X'), --| X X0H | + ('X', '0', 'H'), --| 0 X0H | + ('Z', 'Z', 'Z')), --| 1 X0H | + + (('X', 'X', 'X'), --| X XL1 | + ('X', 'L', '1'), --| 0 XL1 | + ('Z', 'Z', 'Z')), --| 1 XL1 | + + (('X', 'X', 'Z'), --| X X0Z | + ('X', '0', 'Z'), --| 0 X0Z | + ('Z', 'Z', 'Z')), --| 1 X0Z | + + (('X', 'X', 'X'), --| X XZ1 | + ('X', 'Z', '1'), --| 0 XZ1 | + ('Z', 'Z', 'Z')), --| 1 XZ1 | + + (('W', 'W', 'W'), --| X WLH | + ('W', 'L', 'H'), --| 0 WLH | + ('Z', 'Z', 'Z')), --| 1 WLH | + + (('W', 'W', 'Z'), --| X WLZ | + ('W', 'L', 'Z'), --| 0 WLZ | + ('Z', 'Z', 'Z')), --| 1 WLZ | + + (('W', 'W', 'W'), --| X WZH | + ('W', 'Z', 'H'), --| 0 WZH | + ('Z', 'Z', 'Z')), --| 1 WZH | + + (('W', 'W', 'W'), --| X W0H | + ('W', '0', 'H'), --| 0 W0H | + ('Z', 'Z', 'Z')), --| 1 W0H | + + (('W', 'W', 'W'), --| X WL1 | + ('W', 'L', '1'), --| 0 WL1 | + ('Z', 'Z', 'Z')));--| 1 WL1 | + + + + + -- truth table for "MUX2x1" function + constant tbl_MUX2x1: MUX_TABLE := + --------------------------------------- + --| In0 'X' '0' '1' | Sel In1 | + --------------------------------------- + ((('X', 'X', 'X'), --| 'X' 'X' | + ('X', '0', '1'), --| '0' 'X' | + ('X', 'X', 'X')), --| '1' 'X' | + (('X', '0', 'X'), --| 'X' '0' | + ('X', '0', '1'), --| '0' '0' | + ('0', '0', '0')), --| '1' '0' | + (('X', 'X', '1'), --| 'X' '1' | + ('X', '0', '1'), --| '0' '1' | + ('1', '1', '1')));--| '1' '1' | + + + + ---------------------------------------------------------------------- + -- + -- Truth tables for resolution functions + -- + ---------------------------------------------------------------------- + + + -- truth table for "WiredX" function + constant tbl_WIREDX: MVL7_TABLE := + -- ----------------------------------------------- + -- | X 0 1 Z W L H | | + -- ----------------------------------------------- + (('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | + ('X', '0', 'X', '0', '0', '0', '0'), -- | 0 | + ('X', 'X', '1', '1', '1', '1', '1'), -- | 1 | + ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z | + ('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W | + ('X', '0', '1', 'L', 'W', 'L', 'W'), -- | L | + ('X', '0', '1', 'H', 'W', 'W', 'H')); -- | H | + +--synopsys synthesis_on + + + ----------------------------------------------------------------------- + -- + -- logical functions for scalar type of MVL7 + -- + ----------------------------------------------------------------------- + + function "and" (L, R: MVL7) return MVL7; + + function "nand" (L, R: MVL7) return MVL7; + + function "or" (L, R: MVL7) return MVL7; + + function "nor" (L, R: MVL7) return MVL7; + + function "xor" (L, R: MVL7) return MVL7; + + function nxor (L, R: MVL7) return MVL7; + + function "not" (R: MVL7) return MVL7; + + function buf (R: MVL7) return MVL7; + + + + ----------------------------------------------------------------------- + -- + -- logical functions for composite type of MVL7_VECTOR + -- + ----------------------------------------------------------------------- + + function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function "xor" (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function nxor (L, R: MVL7_VECTOR) return MVL7_VECTOR; + + function "not" (R: MVL7_VECTOR) return MVL7_VECTOR; + + function buf (R: MVL7_VECTOR) return MVL7_VECTOR; + + + + ----------------------------------------------------------------------- + -- + -- resolution functions for wired signals and its attributes + -- + ----------------------------------------------------------------------- + + function WiredX (V: MVL7_VECTOR) return MVL7; + +--synopsys translate_off + attribute REFLEXIVE of WiredX: function is TRUE; + attribute RESULT_INITIAL_VALUE of WiredX: function is MVL7'POS('Z'); + attribute TABLE_NAME of WiredX: function is "TYPES.tbl_WIREDX"; +--synopsys translate_on + + + + + ----------------------------------------------------------------------- + -- + -- Definitions for wired signals (scalars and vectors) + -- + ----------------------------------------------------------------------- + + subtype DotX is WiredX MVL7; + + + type BusX is array (Natural range <>) of DotX; + + + + ----------------------------------------------------------------------- + -- + -- conversion functions for driving various types + -- + ----------------------------------------------------------------------- + + function Drive (V: MVL7_VECTOR) return BusX; + function Drive (V: BusX) return MVL7_VECTOR; + +--synopsys translate_off + attribute CLOSELY_RELATED_TCF of Drive: function is TRUE; +--synopsys translate_on + + + +--synopsys synthesis_off + ----------------------------------------------------------------------- + -- + -- conversion functions for sensing various types + -- (the second argument allows the user to specify the value to + -- be returned when the network is undriven) + -- + ----------------------------------------------------------------------- + + function Sense (V: MVL7; vZ: MVL7) return MVL7; + function Sense (V: MVL7_VECTOR; vZ: MVL7) return MVL7_VECTOR; + function Sense (V: BusX; vZ: MVL7) return MVL7_VECTOR; +--synopsys synthesis_on + + + ----------------------------------------------------------------------- + -- + -- Function: BVtoMVL7V + -- + -- Purpose: Conversion function from BIT_VECTOR to MVL7_VECTOR + -- + -- Mapping: 0 --> 0 + -- 1 --> 1 + -- + ----------------------------------------------------------------------- + + function BVtoMVL7V (V: BIT_VECTOR) return MVL7_VECTOR; + + + ----------------------------------------------------------------------- + -- + -- Function: MVL7VtoBV + -- + -- Purpose: Conversion function from MVL7_VECTOR to BIT_VECTOR + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X --> vX if Xflag is TRUE + -- X --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- + ----------------------------------------------------------------------- + + function MVL7VtoBV (V: MVL7_VECTOR +--synopsys synthesis_off + ; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR; + + + ----------------------------------------------------------------------- + -- + -- Function: BITtoMVL7 + -- + -- Purpose: Conversion function from BIT to MVL7 + -- + -- Mapping: 0 --> 0 + -- 1 --> 1 + -- + ----------------------------------------------------------------------- + + function BITtoMVL7 (V: BIT) return MVL7; + + + ----------------------------------------------------------------------- + -- + -- Function: MVL7toBIT + -- + -- Purpose: Conversion function from MVL7 to BIT + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X --> vX if Xflag is TRUE + -- X --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- + ----------------------------------------------------------------------- + + function MVL7toBIT (V: MVL7 +--synopsys synthesis_off + ; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT; + + + +--synopsys synthesis_off + ----------------------------------------------------------------------- + -- + -- Truth tables for unidirectional transistors + -- + ----------------------------------------------------------------------- + + + -- truth table for reduce function + constant tbl_REDUCE: MVL7_TAB1D := + -- ------------------------------------ + -- | X 0 1 Z W L H | + -- ------------------------------------ + ('W', 'L', 'H', 'Z', 'W', 'L', 'H'); + + constant tbl_NXFER: MVL7_TABLE := + ---------------------------------------------------------- + -- | Input 'X' '0' '1' 'Z' 'W' 'L' 'H' | Enable + ---------------------------------------------------------- + (('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'X' + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- '0' + ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- '1' + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'Z' + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'W' + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- 'L' + ('X', '0', '1', 'Z', 'W', 'L', 'H')); -- 'H' + + constant tbl_PXFER: MVL7_TABLE := + ---------------------------------------------------------- + -- | Input 'X' '0' '1' 'Z' 'W' 'L' 'H' | Enable + ---------------------------------------------------------- + (('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'X' + ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- '0' + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- '1' + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'Z' + ('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'W' + ('X', '0', '1', 'Z', 'W', 'L', 'H'), -- 'L' + ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z')); -- 'H' +--synopsys synthesis_on + +end TYPES; + + + + +package body TYPES is + + + ----------------------------------------------------------------------- + -- + -- logical functions for scalar type of MVL7 + -- + ----------------------------------------------------------------------- + + function "and" (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_AND +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "AND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_AND(L, R); + return result ; +--synopsys synthesis_on + end "and"; + + + + function "nand" (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_NAND +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NAND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_NOT(tbl_AND(L, R)); + return result ; +--synopsys synthesis_on + end "nand"; + + + + function "or" (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_OR +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "OR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_OR(L, R); + return result ; +--synopsys synthesis_on + end "or"; + + + + function "nor" (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_NOR +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_NOT(tbl_OR(L, R)); + return result ; +--synopsys synthesis_on + end "nor"; + + + + function "xor" (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_XOR +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "XOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_XOR(L, R); + return result ; +--synopsys synthesis_on + end "xor"; + + + function nxor (L, R: MVL7) return MVL7 is + -- pragma built_in SYN_XNOR +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "XNOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_NOT(tbl_XOR(L, R)); + return result ; +--synopsys synthesis_on + end nxor; + + + function "not" (R: MVL7) return MVL7 is + -- pragma built_in SYN_NOT +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NOT" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_NOT(R); + return result ; +--synopsys synthesis_on + end "not"; + + + function buf (R: MVL7) return MVL7 is + -- pragma built_in SYN_BUF +--synopsys synthesis_off + variable result : MVL7 ; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + result := tbl_BUF(R); + return result ; +--synopsys synthesis_on + end buf; + + + + ----------------------------------------------------------------------- + -- + -- logical functions for composite type of MVL7_VECTOR + -- + ----------------------------------------------------------------------- + + function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_AND +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "AND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := tbl_AND(LV (i), RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "and"; + + + function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_NAND +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NAND" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := tbl_NOT(tbl_AND(LV (i), RV (i))); + end loop; + return result; +--synopsys synthesis_on + end "nand"; + + + function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_OR +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "OR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := tbl_OR(LV (i), RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "or"; + + + function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_NOR +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := tbl_NOT(tbl_OR(LV (i), RV (i))); + end loop; + return result; +--synopsys synthesis_on + end "nor"; + + + function "xor" (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_XOR +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "XOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result (i) := tbl_XOR(LV (i), RV (i)); + end loop; + return result; +--synopsys synthesis_on + end "xor"; + + + function nxor (L, R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_XNOR +--synopsys synthesis_off + alias LV: MVL7_VECTOR (L'length-1 downto 0) is L; + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (L'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "XNOR" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + assert L'length = R'length; + for i in result'range loop + result(i) := tbl_NOT(tbl_XOR(LV(i), RV(i))); + end loop; + return result; +--synopsys synthesis_on + end nxor; + + + function "not" (R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_NOT +--synopsys synthesis_off + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (R'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "NOT" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + result (i) := tbl_NOT( RV(i) ); + end loop; + return result; +--synopsys synthesis_on + end "not"; + + + function buf (R: MVL7_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_BUF +--synopsys synthesis_off + alias RV: MVL7_VECTOR (R'length-1 downto 0) is R; + variable result: MVL7_VECTOR (R'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in result'range loop + result(i) := tbl_BUF( RV(i) ); + end loop; + return result; +--synopsys synthesis_on + end buf; + + + + + ----------------------------------------------------------------------- + -- + -- resolution functions for wired signals + -- + ----------------------------------------------------------------------- + + + function WiredX (V: MVL7_VECTOR) return MVL7 is + -- pragma resolution_method three_state + + variable result: MVL7; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "WIRED_THREE_STATE" ; + begin +--synopsys synthesis_off + result := 'Z'; + for i in V'range loop + result := tbl_WIREDX(result, V(i)); + exit when result = 'X'; + end loop; + return result; +--synopsys synthesis_on + end WiredX; + + + + + ----------------------------------------------------------------------- + -- + -- conversion functions for driving various types + -- + ----------------------------------------------------------------------- + + + + function Drive (V: BusX) return MVL7_VECTOR is + begin + return MVL7_VECTOR(V); + end Drive; + + + + + function Drive (V: MVL7_VECTOR) return BusX is + begin + return BusX(V); + end Drive; + + + ----------------------------------------------------------------------- + -- + -- conversion functions for sensing various types + -- + -- (the second argument allows the user to specify the value to + -- be returned when the network is undriven) + -- + ----------------------------------------------------------------------- +-- synopsys synthesis_off + + function Sense (V: MVL7; vZ: MVL7) return MVL7 is + begin + if V = 'Z' then + return vZ; + else + return V; + end if; + end Sense; + + + function Sense (V: MVL7_VECTOR; vZ: MVL7) return MVL7_VECTOR is + alias Value: MVL7_VECTOR (V'length-1 downto 0) is V; + variable Result: MVL7_VECTOR (V'length-1 downto 0); + begin + for i in Value'range loop + if ( Value(i) = 'Z' ) then + Result(i) := vZ; + else + Result(i) := Value(i); + end if; + end loop; + return Result; + end Sense; + + + function Sense (V: BusX; vZ: MVL7) return MVL7_VECTOR is + alias Value: BusX (V'length-1 downto 0) is V; + variable Result: MVL7_VECTOR (V'length-1 downto 0); + begin + for i in Value'range loop + if ( Value(i) = 'Z' ) then + Result(i) := vZ; + else + Result(i) := Value(i); + end if; + end loop; + return Result; + end Sense; + +-- synopsys synthesis_on + + ----------------------------------------------------------------------- + -- + -- Function: BVtoMVL7V + -- + -- Purpose: Conversion function from BIT_VECTOR to MVL7_VECTOR + -- + -- Mapping: 0 --> 0 + -- 1 --> 1 + -- + ----------------------------------------------------------------------- + + function BVtoMVL7V (V: BIT_VECTOR) return MVL7_VECTOR is + -- pragma built_in SYN_FEED_THRU +--synopsys synthesis_off + alias Value: BIT_VECTOR (V'length-1 downto 0) is V; + variable Result: MVL7_VECTOR (V'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in Value'range loop + if ( Value(i) = '0' ) then + Result(i) := '0'; + else + Result(i) := '1'; + end if; + end loop; + return Result; +--synopsys synthesis_on + end BVtoMVL7V; + + + + ----------------------------------------------------------------------- + -- + -- Function: MVL7VtoBV + -- + -- Purpose: Conversion function from MVL7_VECTOR to BIT_VECTOR + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X --> vX if Xflag is TRUE + -- X --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- + ----------------------------------------------------------------------- + + function MVL7VtoBV (V: MVL7_VECTOR +--synopsys synthesis_off + ; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT_VECTOR is + -- pragma built_in SYN_FEED_THRU +--synopsys synthesis_off + alias Value: MVL7_VECTOR (V'length-1 downto 0) is V; + variable Result: BIT_VECTOR (V'length-1 downto 0); + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; +--synopsys synthesis_on + begin +--synopsys synthesis_off + for i in Value'range loop + case Value(i) is + when '0' | 'L' => + Result(i) := '0'; + when '1' | 'H' => + Result(i) := '1'; + when 'X' | 'W' => + if ( Xflag ) then + Result(i) := vX; + else + Result(i) := '0'; + assert FALSE + report "MVL7VtoBV: X --> 0" + severity WARNING; + end if; + when others => + if ( Zflag ) then + Result(i) := vZ; + else + Result(i) := '0'; + assert FALSE + report "MVL7VtoBV: Z --> 0" + severity WARNING; + end if; + end case; + end loop; + return Result; +--synopsys synthesis_on + end MVL7VtoBV; + + + + ----------------------------------------------------------------------- + -- + -- Function: BITtoMVL7 + -- + -- Purpose: Conversion function from BIT to MVL7 + -- + -- Mapping: 0 --> 0 + -- 1 --> 1 + -- + ----------------------------------------------------------------------- + + function BITtoMVL7 (V: BIT) return MVL7 is + variable Result: MVL7; + -- pragma built_in SYN_FEED_THRU + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; + begin + if ( V = '0' ) then + Result := '0'; + else + Result := '1'; + end if; + return Result; + end BITtoMVL7; + + + + + ----------------------------------------------------------------------- + -- + -- Function: MVL7toBIT + -- + -- Purpose: Conversion function from MVL7 to BIT + -- + -- Mapping: 0, L --> 0 + -- 1, H --> 1 + -- X --> vX if Xflag is TRUE + -- X --> 0 if Xflag is FALSE + -- Z --> vZ if Zflag is TRUE + -- Z --> 0 if Zflag is FALSE + -- + ----------------------------------------------------------------------- + + function MVL7toBIT (V: MVL7 +--synopsys synthesis_off + ; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE +--synopsys synthesis_on + ) return BIT is + -- pragma built_in SYN_FEED_THRU + variable Result: BIT; + -- Set Exemplar Synthesis Directive for this function + attribute SYNTHESIS_RETURN of result:variable IS "FEED_THROUGH" ; + begin +--synopsys synthesis_off + case V is + when '0' | 'L' => + Result := '0'; + when '1' | 'H' => + Result := '1'; + when 'X' | 'W' => + if ( Xflag ) then + Result := vX; + else + Result := '0'; + assert FALSE + report "MVL7toBIT: X --> 0" + severity WARNING; + end if; + when others => + if ( Zflag ) then + Result := vZ; + else + Result := '0'; + assert FALSE + report "MVL7toBIT: Z --> 0" + severity WARNING; + end if; + end case; + return Result; +--synopsys synthesis_on + end MVL7toBIT; + +end TYPES; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/DSP48E1.vhd b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/DSP48E1.vhd new file mode 100644 index 0000000..429f41a --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/DSP48E1.vhd @@ -0,0 +1,1895 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Description : Xilinx Fast Functional Simulation Library Component +-- / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers +-- /___/ /\ Filename : DSP48E1.vhd +-- \ \ / \ Timestamp : Tue Mar 18 13:58:36 PDT 2008 +-- \___\/\___\ +-- +-- Revision: +-- 03/18/08 - Initial version. +-- 05/14/08 - IR472886 fix. +-- 05/19/08 - IR 473330 Fix for qa/qb_o_reg1 when AREG/BREG = 1 +-- 28/05/08 - CR 472154 Removed Vital GSR constructs +-- 07/12/08 - IR 472222 Removed SIM_MODE attribute +-- 07/18/08 - IR 477318 Overflow/Underflow generate statment issue +-- 07/31/08 - IR 478377 Fixed qcarryin_o_mux7 +-- 08/18/08 - IR 478378 Fixed mult sign extension +-- 09/22/08 - IR 490045 Fixed qad_o_mux output +-- 10/02/08 - IR 491365 fixed Vital timing constructs +-- 10/10/08 - IR 491951 Pattern Detect fix +-- 01/08/09 - CR 501854 -- Fixed invalid pdet comparison when there is a X in pattern. +-- 03/02/09 - CR 510304 Carryout should output "X" during multiply +-- 06/02/09 - CR 523600 Carryout "X"ed out before the register +-- 06/05/09 - CR 523917 Carryout is "X"ed one clock cycle ahead of previous DSP48E +-- 07/07/09 - CR 525163 DRC checks for USE_MULT/OPMODE combinations +-- 07/21/09 - CR 527637 Fixed incorrect error message for MREG +-- 08/31/10 - CR 574213 Carryout "X"ing mismatches between verilog and vhdl +-- 10/17/10 - CR 573535 Updated DRC check (carryinsel=100) since carrycascout is now always registered +-- 10/20/10 - CR 574337 Output X after a certain DRC violation +-- 06/23/11 - CR 612706 Removed Power Saving DRCs to Match UG +-- 09/30/11 - CR 619940 -- Enhanced DRC warning +-- 11/04/11 - CR 632559 -- Fixed issues caused by 619940 +-- 04/05/12 - PR 603477 Fast model version +-- 10/17/12 - 682802 - convert GSR H/L to 1/0 +-- End Revision +----- CELL DSP48E1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +entity DSP48E1 is + + generic( + + ACASCREG : integer := 1; + ADREG : integer := 1; + ALUMODEREG : integer := 1; + AREG : integer := 1; + AUTORESET_PATDET : string := "NO_RESET"; + A_INPUT : string := "DIRECT"; + BCASCREG : integer := 1; + BREG : integer := 1; + B_INPUT : string := "DIRECT"; + CARRYINREG : integer := 1; + CARRYINSELREG : integer := 1; + CREG : integer := 1; + DREG : integer := 1; + INMODEREG : integer := 1; + IS_ALUMODE_INVERTED : std_logic_vector (3 downto 0) := "0000"; + IS_CARRYIN_INVERTED : bit := '0'; + IS_CLK_INVERTED : bit := '0'; + IS_INMODE_INVERTED : std_logic_vector (4 downto 0) := "00000"; + IS_OPMODE_INVERTED : std_logic_vector (6 downto 0) := "0000000"; + MASK : bit_vector := X"3FFFFFFFFFFF"; + MREG : integer := 1; + OPMODEREG : integer := 1; + PATTERN : bit_vector := X"000000000000"; + PREG : integer := 1; + SEL_MASK : string := "MASK"; + SEL_PATTERN : string := "PATTERN"; + USE_DPORT : boolean := FALSE; + USE_MULT : string := "MULTIPLY"; + USE_PATTERN_DETECT : string := "NO_PATDET"; + USE_SIMD : string := "ONE48" + ); + + port( + ACOUT : out std_logic_vector(29 downto 0); + BCOUT : out std_logic_vector(17 downto 0); + CARRYCASCOUT : out std_ulogic; + CARRYOUT : out std_logic_vector(3 downto 0); + MULTSIGNOUT : out std_ulogic; + OVERFLOW : out std_ulogic; + P : out std_logic_vector(47 downto 0); + PATTERNBDETECT : out std_ulogic; + PATTERNDETECT : out std_ulogic; + PCOUT : out std_logic_vector(47 downto 0); + UNDERFLOW : out std_ulogic; + + A : in std_logic_vector(29 downto 0); + ACIN : in std_logic_vector(29 downto 0); + ALUMODE : in std_logic_vector(3 downto 0); + B : in std_logic_vector(17 downto 0); + BCIN : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYCASCIN : in std_ulogic; + CARRYIN : in std_ulogic; + CARRYINSEL : in std_logic_vector(2 downto 0); + CEA1 : in std_ulogic; + CEA2 : in std_ulogic; + CEAD : in std_ulogic; + CEALUMODE : in std_ulogic; + CEB1 : in std_ulogic; + CEB2 : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CECTRL : in std_ulogic; + CED : in std_ulogic; + CEINMODE : in std_ulogic; + CEM : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + D : in std_logic_vector(24 downto 0); + INMODE : in std_logic_vector(4 downto 0); + MULTSIGNIN : in std_ulogic; + OPMODE : in std_logic_vector(6 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTALLCARRYIN : in std_ulogic; + RSTALUMODE : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCTRL : in std_ulogic; + RSTD : in std_ulogic; + RSTINMODE : in std_ulogic; + RSTM : in std_ulogic; + RSTP : in std_ulogic + ); + +end DSP48E1; + +-- architecture body -- + +architecture DSP48E1_V of DSP48E1 is + + function find_x ( + lhs : in std_logic_vector (47 downto 0); + rhs : in std_logic_vector (47 downto 0) + ) return boolean is + variable test_bit : std_ulogic := '0'; + variable found_x : boolean := false; + variable i : integer := 0; + begin + + found_x := false; + + for i in 0 to 47 loop + test_bit := lhs(i); + if (test_bit /= '0' and test_bit /= '1') then + found_x := true; + end if; + end loop; + for i in 0 to 47 loop + test_bit := rhs(i); + if (test_bit /= '0' and test_bit /= '1') then + found_x := true; + end if; + end loop; + return found_x; + end; + + procedure invalid_opmode_preg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E1 instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg; + + procedure invalid_opmode_preg_msg_logic( OPMODE : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" to DSP48E1 instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg_logic; + + procedure invalid_opmode_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E1 instance ")); + Write ( Message, string'("requires attribute MREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_mreg_msg; + + procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E1 instance ")); + Write ( Message, string'("requires attribute MREG set to 0.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_no_mreg_msg; + + + + TYPE AluFuntionType is (INVALID_ALU, ADD_ALU, ADD_XY_NOTZ_ALU, NOT_XYZC_ALU, SUBTRACT_ALU, NOT_ALU, + AND_ALU, OR_ALU, XOR_ALU, NAND_ALU, NOR_ALU, + XNOR_ALU, X_AND_NOT_Z_ALU, NOT_X_OR_Z_ALU, X_OR_NOT_Z_ALU, + X_NOR_Z_ALU, NOT_X_AND_Z_ALU); + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant MAX_ACOUT : integer := 30; + constant MAX_BCOUT : integer := 18; + constant MAX_CARRYOUT : integer := 4; + constant MAX_P : integer := 48; + constant MAX_PCOUT : integer := 48; + + constant MAX_A : integer := 30; + constant MAX_ACIN : integer := 30; + constant MAX_ALUMODE : integer := 4; + constant MAX_A_MULT : integer := 25; + constant MAX_B : integer := 18; + constant MAX_B_MULT : integer := 18; + constant MAX_BCIN : integer := 18; + constant MAX_C : integer := 48; + constant MAX_D : integer := 25; + constant MAX_CARRYINSEL : integer := 3; + constant MAX_INMODE : integer := 5; + constant MAX_OPMODE : integer := 7; + constant MAX_PCIN : integer := 48; + + constant MAX_ALU_FULL : integer := 48; + constant MAX_ALU_HALF : integer := 24; + constant MAX_ALU_QUART : integer := 12; + + constant MAX_PREADD : integer := 25; + + constant MSB_ACOUT : integer := MAX_ACOUT - 1; + constant MSB_BCOUT : integer := MAX_BCOUT - 1; + constant MSB_CARRYOUT : integer := MAX_CARRYOUT - 1; + constant MSB_P : integer := MAX_P - 1; + constant MSB_PCOUT : integer := MAX_PCOUT - 1; + + + constant MSB_A : integer := MAX_A - 1; + constant MSB_ACIN : integer := MAX_ACIN - 1; + constant MSB_ALUMODE : integer := MAX_ALUMODE - 1; + constant MSB_A_MULT : integer := MAX_A_MULT - 1; + constant MSB_B : integer := MAX_B - 1; + constant MSB_B_MULT : integer := MAX_B_MULT - 1; + constant MSB_BCIN : integer := MAX_BCIN - 1; + constant MSB_C : integer := MAX_C - 1; + constant MSB_CARRYINSEL : integer := MAX_CARRYINSEL - 1; + constant MSB_OPMODE : integer := MAX_OPMODE - 1; + constant MSB_PCIN : integer := MAX_PCIN - 1; + + constant MSB_ALU_FULL : integer := MAX_ALU_FULL - 1; + constant MSB_ALU_HALF : integer := MAX_ALU_HALF - 1; + constant MSB_ALU_QUART : integer := MAX_ALU_QUART - 1; + + constant SHIFT_MUXZ : integer := 17; + + constant MSB_D : integer := MAX_D - 1; + constant MSB_INMODE : integer := MAX_INMODE - 1; + constant MSB_PREADD : integer := MAX_PREADD - 1; + + signal IS_ALUMODE_INVERTED_BIN : std_logic_vector (3 downto 0) := IS_ALUMODE_INVERTED; + signal IS_CARRYIN_INVERTED_BIN : std_ulogic := TO_X01(IS_CARRYIN_INVERTED); + signal IS_CLK_INVERTED_BIN : std_ulogic := TO_X01(IS_CLK_INVERTED); + signal IS_INMODE_INVERTED_BIN : std_logic_vector (4 downto 0) := IS_INMODE_INVERTED; + signal IS_OPMODE_INVERTED_BIN : std_logic_vector (6 downto 0) := IS_OPMODE_INVERTED; + + signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal ACIN_ipd : std_logic_vector(MSB_ACIN downto 0) := (others => '0'); + signal ALUMODE_ipd : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYCASCIN_ipd : std_ulogic := '0'; + signal CARRYIN_ipd : std_ulogic := '0'; + signal CARRYINSEL_ipd : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA1_ipd : std_ulogic := '0'; + signal CEA2_ipd : std_ulogic := '0'; + signal CEAD_ipd : std_ulogic := '0'; + signal CEALUMODE_ipd : std_ulogic := '0'; + signal CEB1_ipd : std_ulogic := '0'; + signal CEB2_ipd : std_ulogic := '0'; + signal CEC_ipd : std_ulogic := '0'; + signal CECARRYIN_ipd : std_ulogic := '0'; + signal CECTRL_ipd : std_ulogic := '0'; + signal CED_ipd : std_ulogic := '0'; + signal CEINMODE_ipd : std_ulogic := '0'; + signal CEM_ipd : std_ulogic := '0'; + signal CEP_ipd : std_ulogic := '0'; + signal CLK_ipd : std_ulogic := '0'; + signal D_ipd : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal INMODE_ipd : std_logic_vector(MSB_INMODE downto 0) := (others => '0'); +--signal GSR : std_ulogic := '0'; +--signal GSR_ipd : std_ulogic := '0'; + signal MULTSIGNIN_ipd : std_ulogic := '0'; + signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_ipd : std_ulogic := '0'; + signal RSTALLCARRYIN_ipd : std_ulogic := '0'; + signal RSTALUMODE_ipd : std_ulogic := '0'; + signal RSTB_ipd : std_ulogic := '0'; + signal RSTC_ipd : std_ulogic := '0'; + signal RSTCTRL_ipd : std_ulogic := '0'; + signal RSTD_ipd : std_ulogic := '0'; + signal RSTINMODE_ipd : std_ulogic := '0'; + signal RSTM_ipd : std_ulogic := '0'; + signal RSTP_ipd : std_ulogic := '0'; + + + signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal ACIN_dly : std_logic_vector(MSB_ACIN downto 0) := (others => '0'); + signal ALUMODE_dly : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYCASCIN_dly : std_ulogic := '0'; + signal CARRYIN_dly : std_ulogic := '0'; + signal CARRYINSEL_dly : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA1_dly : std_ulogic := '0'; + signal CEA2_dly : std_ulogic := '0'; + signal CEAD_dly : std_ulogic := '0'; + signal CEALUMODE_dly : std_ulogic := '0'; + signal CEB1_dly : std_ulogic := '0'; + signal CEB2_dly : std_ulogic := '0'; + signal CEC_dly : std_ulogic := '0'; + signal CECARRYIN_dly : std_ulogic := '0'; + signal CECTRL_dly : std_ulogic := '0'; + signal CED_dly : std_ulogic := '0'; + signal CEINMODE_dly : std_ulogic := '0'; + signal CEM_dly : std_ulogic := '0'; + signal CEP_dly : std_ulogic := '0'; + signal CLK_dly : std_ulogic := '0'; + signal D_dly : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal INMODE_dly : std_logic_vector(MSB_INMODE downto 0) := (others => '0'); + signal GSR_dly : std_ulogic := '0'; + signal MULTSIGNIN_dly : std_ulogic := '0'; + signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_dly : std_ulogic := '0'; + signal RSTALLCARRYIN_dly : std_ulogic := '0'; + signal RSTALUMODE_dly : std_ulogic := '0'; + signal RSTB_dly : std_ulogic := '0'; + signal RSTC_dly : std_ulogic := '0'; + signal RSTCTRL_dly : std_ulogic := '0'; + signal RSTD_dly : std_ulogic := '0'; + signal RSTINMODE_dly : std_ulogic := '0'; + signal RSTM_dly : std_ulogic := '0'; + signal RSTP_dly : std_ulogic := '0'; + + + signal ACOUT_zd : std_logic_vector(MSB_ACOUT downto 0) := (others => '0'); + signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + signal CARRYCASCOUT_zd : std_ulogic := '0'; + signal CARRYOUT_zd : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal OVERFLOW_zd : std_ulogic := '0'; + signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal PATTERNBDETECT_zd : std_ulogic := '0'; + signal PATTERNDETECT_zd : std_ulogic := '0'; + signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0'); + signal UNDERFLOW_zd : std_ulogic := '0'; + signal MULTSIGNOUT_zd : std_ulogic; + + --- Internal Signal Declarations + signal a_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qacout_o_mux : std_logic_vector(MSB_ACOUT downto 0) := (others => '0'); + + signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qbcout_o_mux : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + + signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0'); + +-- new D + signal d_o_mux : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal qd_o_mux : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal qd_o_reg1 : std_logic_vector(MSB_D downto 0) := (others => '0'); + +-- new INMODE + signal qinmode_o_mux : std_logic_vector(MSB_INMODE downto 0) := (others => '0'); + signal qinmode_o_reg : std_logic_vector(MSB_INMODE downto 0) := (others => '0'); + +-- new + signal d_portion : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal a_preaddsub : std_logic_vector(MSB_PREADD downto 0) := (others => '0'); + signal ad_addsub : std_logic_vector(MSB_A_MULT downto 0) := (others => '0'); + signal ad_mult : std_logic_vector(MSB_A_MULT downto 0) := (others => '0'); + signal qad_o_reg1 : std_logic_vector(MSB_A_MULT downto 0) := (others => '0'); + signal qad_o_mux : std_logic_vector(MSB_A_MULT downto 0) := (others => '0'); + + signal b_mult : std_logic_vector(MSB_B_MULT downto 0) := (others => '0'); + + signal mult_o_int : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + signal mult_o_reg : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + signal mult_o_mux : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + + signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + + signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal carryinsel_o_reg : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal carryinsel_o_mux : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + + signal qcarryin_o_reg0 : std_ulogic := '0'; + signal carryin_o_mux0 : std_ulogic := '0'; + signal qcarryin_o_reg7 : std_ulogic := '0'; + signal carryin_o_mux7 : std_ulogic := '0'; + + signal carryin_o_mux : std_ulogic := '0'; + + signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0'); + signal p_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal output_x_sig : std_ulogic := '0'; + + signal RST_META : std_ulogic := '0'; + + signal DefDelay : time := 10 ps; + + signal opmode_valid_flg : boolean := true; + signal alumode_valid_flg : boolean := true; + + signal AluFunction : AluFuntionType := INVALID_ALU; + + signal alumode_o_reg : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal alumode_o_mux : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + + signal carrycascout_o : std_ulogic := '0'; + signal carrycascout_o_reg : std_ulogic := '0'; + signal carrycascout_o_mux : std_ulogic := '0'; + signal carryout_o_hw : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_o : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_o_reg : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_o_mux : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_x_o : std_logic_vector(MSB_CARRYOUT downto 0) := (others => 'X'); + signal overflow_o : std_ulogic := '0'; + signal pdetb_o : std_ulogic := '0'; + signal pdetb_o_reg1 : std_ulogic := '0'; + signal pdetb_o_reg2 : std_ulogic := '0'; + signal pdet_o : std_ulogic := '0'; + signal pdet_o_reg1 : std_ulogic := '0'; + signal pdet_o_reg2 : std_ulogic := '0'; + signal underflow_o : std_ulogic := '0'; + + signal alu_o : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal pattern_qp : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal mask_qp : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal multsignout_o_reg : std_ulogic; + signal multsignout_o_mux : std_ulogic; + signal multsignout_o_opmode : std_ulogic; + + signal OPMODE_NUMBER : integer := -1; + + signal ping_opmode_drc_check : std_ulogic := '0'; + + signal y_mac_cascd : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal carryin_o_mux_tmp : std_ulogic := '0'; + signal the_auto_reset_patdet : boolean := true; + + signal the_pattern : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal the_mask : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal comux : std_logic_vector(MSB_ALU_FULL downto 0) := (others => '0'); + signal smux : std_logic_vector(MSB_ALU_FULL downto 0) := (others => '0'); + + signal s0 : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0'); + signal s1 : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0'); + signal s2 : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0'); + signal s3 : std_logic_vector((MAX_ALU_QUART + 1) downto 0) := (others => '0'); + + signal cout0 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout0_prt1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout0_prt2 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout1_prt1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout1_prt2 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout2 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout2_prt1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout2_prt2 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout3 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout3_prt1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout3_prt2 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout4 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout4_prt1 : std_logic_vector(1 downto 0) := (others => '0'); + signal cout4_prt2 : std_logic_vector(1 downto 0) := (others => '0'); + +-- signal cout0 : std_ulogic := '0'; +-- signal cout1 : std_ulogic := '0'; +-- signal cout2 : std_ulogic := '0'; +-- signal cout3 : std_ulogic := '0'; +-- signal cout4 : std_ulogic := '0'; + + signal co11_lsb : std_ulogic := '0'; + signal co23_lsb : std_ulogic := '0'; + signal co35_lsb : std_ulogic := '0'; + + signal C1 : std_ulogic := '0'; + signal C2 : std_ulogic := '0'; + signal C3 : std_ulogic := '0'; + +begin + + + A_dly <= A after 0 ps; + ACIN_dly <= ACIN after 0 ps; + ALUMODE_dly <= ALUMODE xor IS_ALUMODE_INVERTED_BIN after 0 ps; + B_dly <= B after 0 ps; + BCIN_dly <= BCIN after 0 ps; + C_dly <= C after 0 ps; + CARRYCASCIN_dly <= CARRYCASCIN after 0 ps; + CARRYIN_dly <= CARRYIN xor IS_CARRYIN_INVERTED_BIN after 0 ps; + CARRYINSEL_dly <= CARRYINSEL after 0 ps; + CEA1_dly <= CEA1 after 0 ps; + CEA2_dly <= CEA2 after 0 ps; + CEAD_dly <= CEAD after 0 ps; + CEALUMODE_dly <= CEALUMODE after 0 ps; + CEB1_dly <= CEB1 after 0 ps; + CEB2_dly <= CEB2 after 0 ps; + CEC_dly <= CEC after 0 ps; + CECARRYIN_dly <= CECARRYIN after 0 ps; + CECTRL_dly <= CECTRL after 0 ps; + CED_dly <= CED after 0 ps; + CEINMODE_dly <= CEINMODE after 0 ps; + CEM_dly <= CEM after 0 ps; + CEP_dly <= CEP after 0 ps; + CLK_dly <= CLK xor IS_CLK_INVERTED_BIN after 0 ps; + D_dly <= D after 0 ps; + INMODE_dly <= INMODE xor IS_INMODE_INVERTED_BIN after 0 ps; + MULTSIGNIN_dly <= MULTSIGNIN after 0 ps; + OPMODE_dly <= OPMODE xor IS_OPMODE_INVERTED_BIN after 0 ps; + PCIN_dly <= PCIN after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTALLCARRYIN_dly <= RSTALLCARRYIN after 0 ps; + RSTALUMODE_dly <= RSTALUMODE after 0 ps; + RSTB_dly <= RSTB after 0 ps; + RSTC_dly <= RSTC after 0 ps; + RSTCTRL_dly <= RSTCTRL after 0 ps; + RSTD_dly <= RSTD after 0 ps; + RSTINMODE_dly <= RSTINMODE after 0 ps; + RSTM_dly <= RSTM after 0 ps; + RSTP_dly <= RSTP after 0 ps; + GSR_dly <= TO_X01(GSR) after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + +----------- Checks for AREG ---------------------- + case AREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: Legal values for AREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for ACASCREG and (ACASCREG vs AREG) ---------------------- + + case AREG is + when 0 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E1 has to be set to 0 when attribute AREG = 0." + severity Failure; + end if; + when 1 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E1 has to be set to 1 when attribute AREG = 1." + severity Failure; + end if; + when 2 => if((AREG /= ACASCREG) and ((AREG-1) /= ACASCREG))then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E1 has to be set to either 2 or 1 when attribute AREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Checks for BREG ---------------------- + case BREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: Legal values for BREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for BCASCREG and (BCASCREG vs BREG) ---------------------- + + case BREG is + when 0 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E1 has to be set to 0 when attribute BREG = 0." + severity Failure; + end if; + when 1 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E1 has to be set to 1 when attribute BREG = 1." + severity Failure; + end if; + when 2 => if((BREG /= BCASCREG) and ((BREG-1) /= BCASCREG))then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E1 has to be set to either 2 or 1 when attribute BREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Check for AUTORESET_OVER_UNDER_FLOW ---------------------- + +-- case AUTORESET_OVER_UNDER_FLOW is +-- when true | false => null; +-- when others => +-- assert false +-- report "Attribute Syntax Error: Legal values for AUTORESET_OVER_UNDER_FLOW are true or fasle" +-- severity Failure; +-- end case; + +----------- Check for AUTORESET_PATDET ---------------------- + + if((AUTORESET_PATDET /="NO_RESET") and (AUTORESET_PATDET /="RESET_MATCH") and (AUTORESET_PATDET /="RESET_NOT_MATCH")) then + assert false + report "Attribute Syntax Error: Legal values for AUTORESET_PATDET are NO_RESET or RESET_MATCH or RESET_NOT_MATCH." + severity Failure; + end if; + +----------- Check for USE_MULT ---------------------- + + if((USE_MULT /="NONE") and (USE_MULT /="MULTIPLY") and (USE_MULT /="DYNAMIC")) then + assert false + report "Attribute Syntax Error: Legal values for USE_MULT are MULTIPLY, DYNAMIC or NONE." + severity Failure; + end if; + +----------- Check for USE_PATTERN_DETECT ---------------------- + + if((USE_PATTERN_DETECT /="PATDET") and (USE_PATTERN_DETECT /="NO_PATDET")) then + assert false + report "Attribute Syntax Error: Legal values for USE_PATTERN_DETECT are PATDET or NO_PATDET." + severity Failure; + end if; + +--********************************************************* +--*** ADDITIONAL DRC +--********************************************************* +-- CR 219407 -- (1) +-- if((AUTORESET_PATTERN_DETECT = TRUE) and (USE_PATTERN_DETECT = "NO_PATDET")) then +-- assert false +-- report "Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. " +-- severity Warning; +-- end if; + +--********************************************************* +--*** New Attribute DRC +--********************************************************* + + ----------- ADREG check + case ADREG is + when 0|1 => null; + when others => + assert false + report "Attribute Syntax Error: Legal values for ADREG are 0 or 1 " + severity Failure; + end case; + + ----------- DREG check + case DREG is + when 0|1 => null; + when others => + assert false + report "Attribute Syntax Error: Legal values for DREG are 0 or 1 " + severity Failure; + end case; + + ----------- INMODEREG check + case INMODEREG is + when 0|1 => null; + when others => + assert false + report "Attribute Syntax Error: Legal values for INMODEREG are 0 or 1 " + severity Failure; + end case; + + ----------- USE_DPORT check + case USE_DPORT is + when true | false => null; + when others => + assert false + report "Attribute Syntax Error: Legal values for USE_DPORT are true or false" + severity Failure; + end case; + +-- 612706 - following DRS were removed to match UG + ----------- Additional DRCs for Power Savings + +------------------------------------------------------------ + ping_opmode_drc_check <= '1' after 100010 ps; +------------------------------------------------------------ + + wait; + end process prcs_init; +--#################################################################### +--##### Input Register A with two levels of registers and a mux ### +--#################################################################### + prcs_a_in:process(A_dly, ACIN_dly) + begin + if(A_INPUT ="DIRECT") then + a_o_mux <= A_dly; + elsif(A_INPUT ="CASCADE") then + a_o_mux <= ACIN_dly; + else + assert false + report "Attribute Syntax Error: Legal values for A_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + end process prcs_a_in; +------------------------------------------------------------------ + prcs_qa_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (RSTA_dly = '0') then + case AREG is + when 1 => + if(CEA1_dly = '1') then + qa_o_reg1 <= a_o_mux; + end if; + if(CEA2_dly = '1') then + qa_o_reg2 <= a_o_mux; + end if; + when 2 => + if(CEA1_dly = '1') then + qa_o_reg1 <= a_o_mux; + end if; + if(CEA2_dly = '1') then + qa_o_reg2 <= qa_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qa_2lvl; +------------------------------------------------------------------ + prcs_qa_o_mux:process(a_o_mux, qa_o_reg2) + begin + case AREG is + when 0 => qa_o_mux <= a_o_mux; + when 1|2 => qa_o_mux <= qa_o_reg2; + when others => + assert false + report "Attribute Syntax Error: Legal values for AREG are 0 or 1 or 2" + severity Failure; + end case; + end process prcs_qa_o_mux; +------------------------------------------------------------------ + prcs_qacout_o_mux:process(qa_o_mux, qa_o_reg1) + begin + case ACASCREG is + when 1 => case AREG is + when 2 => qacout_o_mux <= qa_o_reg1; + when others => qacout_o_mux <= qa_o_mux; + end case; + when others => qacout_o_mux <= qa_o_mux; + end case; + + end process prcs_qacout_o_mux; + +-- new ----- +---------------Preadd ------------------------------------------------ + + a_preaddsub <= (others => '0') when (qinmode_o_mux(1) = '1') else + qa_o_reg1(24 downto 0) when (qinmode_o_mux(0) = '1') else + qa_o_mux(24 downto 0) when (qinmode_o_mux(0) = '0'); + +--#################################################################### +--##### Input Register B with two levels of registers and a mux ### +--#################################################################### + prcs_b_in:process(B_dly, BCIN_dly) + begin + if(B_INPUT ="DIRECT") then + b_o_mux <= B_dly; + elsif(B_INPUT ="CASCADE") then + b_o_mux <= BCIN_dly; + else + assert false + report "Attribute Syntax Error: Legal values for B_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + + end process prcs_b_in; +------------------------------------------------------------------ + prcs_qb_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (RSTB_dly = '0') then + case BREG is + when 1 => + if(CEB1_dly = '1') then + qb_o_reg1 <= b_o_mux; + end if; + if(CEB2_dly = '1') then + qb_o_reg2 <= b_o_mux; + end if; + when 2 => + if(CEB1_dly = '1') then + qb_o_reg1 <= b_o_mux; + end if; + if(CEB2_dly = '1') then + qb_o_reg2 <= qb_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qb_2lvl; +------------------------------------------------------------------ + prcs_qb_o_mux:process(b_o_mux, qb_o_reg2) + begin + case BREG is + when 0 => qb_o_mux <= b_o_mux; + when 1|2 => qb_o_mux <= qb_o_reg2; + when others => + assert false + report "Attribute Syntax Error: Legal values for BREG are 0 or 1 or 2 " + severity Failure; + end case; + + end process prcs_qb_o_mux; +------------------------------------------------------------------ + prcs_qbcout_o_mux:process(qb_o_mux, qb_o_reg1) + begin + case BCASCREG is + when 1 => case BREG is + when 2 => qbcout_o_mux <= qb_o_reg1; + when others => qbcout_o_mux <= qb_o_mux; + end case; + when others => qbcout_o_mux <= qb_o_mux; + end case; + end process prcs_qbcout_o_mux; + + b_mult <= qb_o_reg1 when qinmode_o_mux(4)='1' else qb_o_mux; + +--#################################################################### +--##### Input Register C with 0, 1, level of registers ##### +--#################################################################### + prcs_qc_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then + qc_o_reg <= C_dly; + end if; + end if; + end if; + end process prcs_qc_1lvl; +------------------------------------------------------------------ + prcs_qc_o_mux:process(C_dly, qc_o_reg) + begin + case CREG is + when 0 => qc_o_mux <= C_dly; + when 1 => qc_o_mux <= qc_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for CREG are 0 or 1" + severity Failure; + end case; + end process prcs_qc_o_mux; +-- new +--#################################################################### +--##### Input Register D with 0, 1, level of registers ##### +--#################################################################### + prcs_qd_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qd_o_reg1 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTD_dly = '1') then + qd_o_reg1 <= ( others => '0'); + elsif ((RSTD_dly = '0') and (CED_dly = '1')) then + qd_o_reg1 <= D_dly; + end if; + end if; + end if; + end process prcs_qd_1lvl; +------------------------------------------------------------------ + prcs_qd_o_mux:process(D_dly, qd_o_reg1) + begin + case DREG is + when 0 => qd_o_mux <= D_dly; + when 1 => qd_o_mux <= qd_o_reg1; + when others => + assert false + report "Attribute Syntax Error: Legal values for DREG are 0 or 1" + severity Failure; + end case; + end process prcs_qd_o_mux; +--#################################################################### +--##### Preaddsub AD register with 1 level deep of register ##### +--#################################################################### + d_portion <= (others => '0') when (qinmode_o_mux(2) = '0') else + qd_o_mux when (qinmode_o_mux(2) = '1'); + ad_addsub <= (a_preaddsub + d_portion) when (qinmode_o_mux(3) = '0') else + (d_portion - a_preaddsub) when (qinmode_o_mux(3) = '1'); + + prcs_qad_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qad_o_reg1 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTD_dly = '1') then + qad_o_reg1 <= ( others => '0'); + elsif ((RSTD_dly = '0') and (CEAD_dly = '1')) then + qad_o_reg1 <= ad_addsub; + end if; + end if; + end if; + end process prcs_qad_1lvl; +------------------------------------------------------------------ + prcs_qad_o_mux:process(ad_addsub, qad_o_reg1) + begin + case ADREG is + when 0 => qad_o_mux <= ad_addsub; + when 1 => qad_o_mux <= qad_o_reg1; + when others => + assert false + report "Attribute Syntax Error: Legal values for ADREG are 0 or 1" + severity Failure; + end case; + end process prcs_qad_o_mux; + + ad_mult <= qad_o_mux when (USE_DPORT = TRUE) else + a_preaddsub; + +--#################################################################### +--##### INMODE with 0, 1, level of registers ##### +--#################################################################### + prcs_qinmode_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qinmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTINMODE_dly = '1') then + qinmode_o_reg <= ( others => '0'); + elsif ((RSTINMODE_dly = '0') and (CEINMODE_dly = '1')) then + qinmode_o_reg <= INMODE_dly; + end if; + end if; + end if; + end process prcs_qinmode_1lvl; +------------------------------------------------------------------ + prcs_qinmode_o_mux:process(INMODE_dly, qinmode_o_reg) + begin + case INMODEREG is + when 0 => qinmode_o_mux <= INMODE_dly; + when 1 => qinmode_o_mux <= qinmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for INMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_qinmode_o_mux; + +--#################################################################### +--################### 25x18 Multiplier ###################### +--#################################################################### +-- +-- 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +-- SIMD=FOUR12 and SIMD=TWO24 +-- Made mult_o to be "X" +-- + + mult_o_int <= (others => '0') when ((USE_MULT = "NONE") OR (USE_SIMD = "TWO24") OR (USE_SIMD = "FOUR12")) else + ad_mult * b_mult; + +-- old +-- prcs_mult:process(qa_o_mux, qb_o_mux) +-- begin +-- if(USE_MULT /= "NONE") then +-- mult_o_int <= qa_o_mux(MSB_A_MULT downto 0) * qb_o_mux (MSB_B_MULT downto 0); +-- end if; +-- end process prcs_mult; +------------------------------------------------------------------ + prcs_mult_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then + mult_o_reg <= mult_o_int; + end if; + end if; + end if; + end process prcs_mult_reg; +------------------------------------------------------------------ + prcs_mult_mux:process(mult_o_reg, mult_o_int) + begin + case MREG is + when 0 => mult_o_mux <= mult_o_int; + when 1 => mult_o_mux <= mult_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for MREG are 0 or 1" + severity Failure; + end case; + end process prcs_mult_mux; + +--#################################################################### +--##### OpMode ##### +--#################################################################### + prcs_opmode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + end if; + end process prcs_opmode_reg; +------------------------------------------------------------------ + prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) + begin + case OPMODEREG is + when 0 => opmode_o_mux <= OPMODE_dly; + when 1 => opmode_o_mux <= opmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for OPMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_opmode_mux; + +--#################################################################### +--##### MUX_X ##### +--#################################################################### + + prcs_mux_x:process(qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, opmode_o_mux(1 downto 0) , output_x_sig) + begin +-- if(output_x_sig = '1') then +-- muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); +-- else + case opmode_o_mux(1 downto 0) is + when "00" => muxx_o_mux <= (others => '0'); + when "01" => muxx_o_mux((MSB_A_MULT + MSB_B_MULT +1) downto 0) <= mult_o_mux; + muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <= (others => mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1)); + when "10" => muxx_o_mux <= qp_o_mux; + when "11" => if((USE_MULT = "MULTIPLY") and ( + (AREG=0 and BREG=0 and MREG=0) or + (AREG=0 and BREG=0 and PREG=0) or + (MREG=0 and PREG=0))) + then +-- CR 574337 added the following line + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + assert false + report "OPMODE Input Warning : The OPMODE(1:0) to DSP48E1 is invalid when using attributes USE_MULT = MULTIPLY. Please set USE_MULT to either NONE or DYNAMIC." + severity Warning; + else + muxx_o_mux(MSB_P downto 0) <= (qa_o_mux & qb_o_mux); + end if; + + when others => null; + end case; +-- end if; + end process prcs_mux_x; + +--#################################################################### +--##### MUX_Y ##### +--#################################################################### +-- 478378 + prcs_mac_cascd:process(opmode_o_mux(6 downto 4) , MULTSIGNIN_dly) + begin + case opmode_o_mux(6 downto 4) is + when "100" => y_mac_cascd(MSB_P downto 0) <= ( others => MULTSIGNIN_dly); + when others => y_mac_cascd(MSB_P downto 0) <= ( others => '1'); + end case; + end process prcs_mac_cascd; + +-------------------------------------------------------------------------- + prcs_mux_y:process(qc_o_mux, opmode_o_mux(3 downto 2) , carryinsel_o_mux, y_mac_cascd, output_x_sig) + begin +-- if(output_x_sig = '1') then +-- muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); +-- else + case opmode_o_mux(3 downto 2) is + when "00" | "01" => muxy_o_mux <= ( others => '0'); + when "10" => muxy_o_mux <= y_mac_cascd; + when "11" => muxy_o_mux <= qc_o_mux; + when others => null; + end case; +-- end if; + end process prcs_mux_y; +--#################################################################### +--##### MUX_Z ##### +--#################################################################### + prcs_mux_z:process(qp_o_mux, qc_o_mux, PCIN_dly, opmode_o_mux(6 downto 4) , carryinsel_o_mux, output_x_sig) + begin +-- if(output_x_sig = '1') then +-- muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); +-- else + case opmode_o_mux(6 downto 4) is + when "000" => muxz_o_mux <= ( others => '0'); + when "001" => muxz_o_mux <= PCIN_dly; + when "010" => muxz_o_mux <= qp_o_mux; + when "011" => muxz_o_mux <= qc_o_mux; + when "100" => muxz_o_mux <= qp_o_mux; -- Used for MACC extend -- multsignin + when "101" => muxz_o_mux <= (others => PCIN_dly(MSB_PCIN)); + muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); + when "110" | "111" + => muxz_o_mux <= (others => qp_o_mux(MSB_P)); + muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); + when others => null; + end case; +-- end if; + end process prcs_mux_z; +--#################################################################### +--##### Alumode ##### +--#################################################################### + prcs_alumode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALUMODE_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif ((RSTALUMODE_dly = '0') and (CEALUMODE_dly = '1'))then + alumode_o_reg <= ALUMODE_dly; + end if; + end if; + end if; + end process prcs_alumode_reg; +------------------------------------------------------------------ + prcs_alumode_mux:process(alumode_o_reg, ALUMODE_dly) + begin + case ALUMODEREG is + when 0 => alumode_o_mux <= ALUMODE_dly; + when 1 => alumode_o_mux <= alumode_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for ALUMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_alumode_mux; + +--#################################################################### +--##### CarryInSel ##### +--#################################################################### + prcs_carryinsel_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + carryinsel_o_reg <= CARRYINSEL_dly; + end if; + end if; + end if; + end process prcs_carryinsel_reg; +------------------------------------------------------------------ + prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly) + begin + case CARRYINSELREG is + when 0 => carryinsel_o_mux <= CARRYINSEL_dly; + when 1 => carryinsel_o_mux <= carryinsel_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for CARRYINSELREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryinsel_mux; + +------------------------------------------------------------------ +-- CR 219047 (3) + prcs_carryinsel_drc:process(carryinsel_o_mux, MULTSIGNIN_dly, opmode_o_mux) + begin + if(carryinsel_o_mux = "010") then + if(not((MULTSIGNIN_dly = 'X') or ((opmode_o_mux = "1001000") and (MULTSIGNIN_dly /= 'X')) + or ((MULTSIGNIN_dly = '0') and (CARRYCASCIN_dly = '0')))) then + assert false +-- CR 619940 -- Enhanced DRC warning +-- CR 632559 fixed 619940 -- Enhanced DRC warning + report "DRC warning : CARRYCASCIN can only be used in the current DSP48E1 instance if the previous DSP48E1 is performing a two input ADD operation, or the current DSP48E1 is configured in the MAC extend opmode(6:0) equals 1001000.\n DRC warning note : The simulation model does not know the placement of the DSP48E1 slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the DSP48E1 slices and ensure that these warnings are not being breached\n" + severity Warning; + end if; + end if; + end process prcs_carryinsel_drc; + +-- CR 219047 (4) +-- prcs_carryinsel_mac_drc:process(carryinsel_o_mux) +-- begin +-- if((carryinsel_o_mux = "110") and (MULTCARRYINREG /= MREG)) then +-- assert false +-- report "Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E1 instance be set to the same value when using CARRYINSEL = 110 for multiply rounding. " +-- severity Warning; +-- end if; +-- end process prcs_carryinsel_mac_drc; + + +--#################################################################### +--##### CarryIn ##### +--#################################################################### + +------- input 0 + + prcs_carryin_reg0:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif((RSTALLCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then + qcarryin_o_reg0 <= CARRYIN_dly; + end if; + end if; + end if; + end process prcs_carryin_reg0; + + prcs_carryin_mux0:process(qcarryin_o_reg0, CARRYIN_dly) + begin + case CARRYINREG is + when 0 => carryin_o_mux0 <= CARRYIN_dly; + when 1 => carryin_o_mux0 <= qcarryin_o_reg0; + when others => + assert false + report "Attribute Syntax Error: Legal values for CARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux0; + +------------------------------------------------------------------ +------- input 7 + + prcs_carryin_reg7:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg7 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg7 <= '0'; +-- new + elsif((RSTALLCARRYIN_dly = '0') and (CEM_dly = '1')) then +-- IR 478377 +-- qcarryin_o_reg7 <= qa_o_mux(24) XNOR qb_o_mux(17); + qcarryin_o_reg7 <= ad_mult(24) XNOR qb_o_mux(17); + end if; + end if; + end if; + end process prcs_carryin_reg7; + +-- prcs_carryin_mux7:process(qa_o_mux(24), qb_o_mux(17), qcarryin_o_reg7) + prcs_carryin_mux7:process(ad_mult(24), qb_o_mux(17), qcarryin_o_reg7) + begin +-- new + case MREG is +-- IR 478377 +-- when 0 => carryin_o_mux7 <= qa_o_mux(24) XNOR qb_o_mux(17); + when 0 => carryin_o_mux7 <= ad_mult(24) XNOR qb_o_mux(17); + when 1 => carryin_o_mux7 <= qcarryin_o_reg7; + when others => + assert false + report "Attribute Syntax Error: Legal values for MREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux7; + + + prcs_carryin_mux:process(carryin_o_mux0, PCIN_dly(47), CARRYCASCIN_dly, carrycascout_o_mux, qp_o_mux(47), carryin_o_mux7, carryinsel_o_mux) + begin + case carryinsel_o_mux is + when "000" => carryin_o_mux_tmp <= carryin_o_mux0; + when "001" => carryin_o_mux_tmp <= NOT PCIN_dly(47); + when "010" => carryin_o_mux_tmp <= CARRYCASCIN_dly; + when "011" => carryin_o_mux_tmp <= PCIN_dly(47); + when "100" => carryin_o_mux_tmp <= carrycascout_o_mux; + when "101" => carryin_o_mux_tmp <= NOT qp_o_mux(47); + when "110" => carryin_o_mux_tmp <= carryin_o_mux7; + when "111" => carryin_o_mux_tmp <= qp_o_mux(47); + when others => null; + end case; + end process prcs_carryin_mux; + +-- disable carryin when performic logic operations + + carryin_o_mux <= '0' when (alumode_o_mux(3) = '1' OR alumode_o_mux(2) = '1') else + carryin_o_mux_tmp; +--#################################################################### +--##### NEW ALU ##### +--#################################################################### + prcs_co_s:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux) + variable co : std_logic_vector(MSB_ALU_FULL downto 0) := (others => '0'); + variable s : std_logic_vector(MSB_ALU_FULL downto 0) := (others => '0'); + begin + if(alumode_o_mux(0) = '1') then + co := ((muxx_o_mux and muxy_o_mux) or (not(muxz_o_mux) and muxy_o_mux) or (muxx_o_mux and (not muxz_o_mux))); + s := ((not muxz_o_mux) xor muxx_o_mux xor muxy_o_mux); + else + co := ((muxx_o_mux and muxy_o_mux) or (muxz_o_mux and muxy_o_mux) or (muxx_o_mux and muxz_o_mux)); + s := (muxz_o_mux xor muxx_o_mux xor muxy_o_mux); + end if; + + if(alumode_o_mux(2) = '1') then + comux <= (others => '0'); + else + comux <= co; + end if; + + if(alumode_o_mux(3) = '1') then + smux <= co; + else + smux <= s; + end if; + + end process prcs_co_s; + +-- FINAL ADDER + + s0 <= ('0' & comux(10 downto 0) & carryin_o_mux) + ('0' & smux(11 downto 0)); +-- cout0 <= comux(11) + s0(12); + cout0_prt1 <= ('0' & comux(11)); + cout0_prt2 <= ('0' & s0(12)); + cout0 <= cout0_prt1 + cout0_prt2; + + carryout_o_hw(0) <= not cout0(0) when (alumode_o_mux(0) and alumode_o_mux(1)) = '1' else cout0(0); + + C1 <= '0' when (USE_SIMD = "FOUR12") else s0(12); + co11_lsb <= '0' when (USE_SIMD = "FOUR12") else comux(11); + s1 <= ('0' & comux(22 downto 12) & co11_lsb) + ('0'&smux(23 downto 12)) + C1; +-- cout1 <= comux(23) + s1(12); + cout1_prt1 <= ('0' & comux(23)); + cout1_prt2 <= ('0' & s1(12)); + cout1 <= cout1_prt1 + cout1_prt2; + carryout_o_hw(1) <= not cout1(0) when (alumode_o_mux(0) and alumode_o_mux(1)) = '1' else cout1(0); + + C2 <= '0' when ((USE_SIMD = "TWO24") or (USE_SIMD = "FOUR12")) else s1(12); + co23_lsb <= '0' when ((USE_SIMD = "TWO24") or (USE_SIMD = "FOUR12")) else comux(23); + s2 <= ('0' & comux(34 downto 24) & co23_lsb) + ('0'&smux(35 downto 24)) + C2; +-- cout2 <= comux(35) + s2(12); + cout2_prt1 <= ('0' & comux(35)); + cout2_prt2 <= ('0' & s2(12)); + cout2 <= cout2_prt1 + cout2_prt2; + carryout_o_hw(2) <= not cout2(0) when (alumode_o_mux(0) and alumode_o_mux(1)) = '1' else cout2(0); + + C3 <= '0' when (USE_SIMD = "FOUR12") else s2(12); + co35_lsb <= '0' when (USE_SIMD = "FOUR12") else comux(35); + s3 <= ('0'&comux(47 downto 36) & co35_lsb) + ('0'&smux(47 downto 36)) + C3; + cout3(0) <= s3(12); + carryout_o_hw(3) <= not cout3(0) when (alumode_o_mux(0) and alumode_o_mux(1)) = '1' else cout3(0); + + carrycascout_o <= cout3(0); + cout4(0) <= s3(13); +-- carryout_o_hw(4) <= not cout4(0) when (alumode_o_mux(0) and alumode_o_mux(1)) = '1' else cout4(0); + + alu_o <= not (s3(11 downto 0) & s2(11 downto 0) & s1(11 downto 0) & s0(11 downto 0)) when alumode_o_mux(1) = '1' else + (s3(11 downto 0) & s2(11 downto 0) & s1(11 downto 0) & s0(11 downto 0)); +-- + +-- CR 523600 -- "X" carryout for multiply and logic operations + carryout_o(3) <= 'X' when ((opmode_o_mux(3 downto 0) = "0101") or (alumode_o_mux(3 downto 2) /= "00" )) else carryout_o_hw(3); + carryout_o(2) <= 'X' when ((opmode_o_mux(3 downto 0) = "0101") or (alumode_o_mux(3 downto 2) /= "00" )) else + carryout_o_hw(2) when (USE_SIMD = "FOUR12") else + 'X'; + carryout_o(1) <= 'X' when ((opmode_o_mux(3 downto 0) = "0101") or (alumode_o_mux(3 downto 2) /= "00" )) else + carryout_o_hw(1) when ((USE_SIMD = "TWO24") or (USE_SIMD = "FOUR12")) else + 'X'; + carryout_o(0) <= 'X' when ((opmode_o_mux(3 downto 0) = "0101") or (alumode_o_mux(3 downto 2) /= "00" )) else + carryout_o_hw(0) when (USE_SIMD = "FOUR12") else + 'X'; + + +--#################################################################### +--##### ALU ##### +--#################################################################### +-- prcs_alu:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux, opmode_o_mux, carryin_o_mux, output_x_sig) + +-- end process prcs_alu; +--#################################################################### +--##### AUTORESET_PATDET ##### +--#################################################################### + the_auto_reset_patdet <= ((AUTORESET_PATDET = "RESET_MATCH") and pdet_o_reg1 = '1') + OR + ((AUTORESET_PATDET = "RESET_NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')); +--#################################################################### +--##### CARRYOUT and CARRYCASCOUT ##### +--#################################################################### + prcs_carry_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1' or the_auto_reset_patdet) then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + carryout_o_reg <= carryout_o; + carrycascout_o_reg <= carrycascout_o; + end if; + end if; + end if; + end process prcs_carry_reg; +------------------------------------------------------------------ + prcs_carryout_mux:process(carryout_o, carryout_o_reg) + begin + case PREG is + when 0 => carryout_o_mux <= carryout_o; + when 1 => carryout_o_mux <= carryout_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carryout_mux; + +------------------------------------------------------------------ +-- CR 523917 +-- prcs_carryout_x_o:process(carryout_o_mux, opmode_o_mux(3 downto 0)) +-- begin +-- -- CR 510304 output X during mulltiply operation +-- if(opmode_o_mux(3 downto 0) = "0101") then +-- carryout_x_o <= (others => 'X'); +-- elsif(USE_SIMD = "ONE48") then +-- carryout_x_o(3) <= carryout_o_mux(3); + -- elsif(USE_SIMD = "TWO24") then +-- carryout_x_o(3) <= carryout_o_mux(3); +-- carryout_x_o(1) <= carryout_o_mux(1); +-- elsif(USE_SIMD = "FOUR12") then +-- carryout_x_o(3) <= carryout_o_mux(3); +-- carryout_x_o(2) <= carryout_o_mux(2); +-- carryout_x_o(1) <= carryout_o_mux(1); +-- carryout_x_o(0) <= carryout_o_mux(0); +-- end if; +-- end process prcs_carryout_x_o; + +------------------------------------------------------------------ + +-- CR 574213 + prcs_carryout_x_o:process(carryout_o_mux) + begin + carryout_x_o(3) <= carryout_o_mux(3); + + if(USE_SIMD = "FOUR12") then + carryout_x_o(2) <= carryout_o_mux(2); + else + carryout_x_o(2) <= 'X'; + end if; + + if((USE_SIMD = "FOUR12") or (USE_SIMD = "TWO24")) then + carryout_x_o(1) <= carryout_o_mux(1); + else + carryout_x_o(1) <= 'X'; + end if; + + if(USE_SIMD = "FOUR12") then + carryout_x_o(0) <= carryout_o_mux(0); + else + carryout_x_o(0) <= 'X'; + end if; + + end process prcs_carryout_x_o; + +------------------------------------------------------------------ + + prcs_carrycascout_mux:process(carrycascout_o, carrycascout_o_reg) + begin + case PREG is + when 0 => carrycascout_o_mux <= carrycascout_o; + when 1 => carrycascout_o_mux <= carrycascout_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carrycascout_mux; +------------------------------------------------------------------ +-- CR 219047 (2) + prcs_multsignout_o_opmode:process(mult_o_mux(MSB_A_MULT+MSB_B_MULT+1), opmode_o_mux(6 downto 4), MULTSIGNIN_dly) + begin +-- IR 478378 + if(opmode_o_mux(6 downto 4) = "100") then + multsignout_o_opmode <= MULTSIGNIN_dly; + else + multsignout_o_opmode <= mult_o_mux(MSB_A_MULT+MSB_B_MULT+1); + end if; + end process prcs_multsignout_o_opmode; + + prcs_multsignout_o_mux:process(multsignout_o_opmode, multsignout_o_reg) + begin + case PREG is + when 0 => multsignout_o_mux <= multsignout_o_opmode; +-- CR 232275 + when 1 => multsignout_o_mux <= multsignout_o_reg; + when others => null; +-- assert false +-- report "Attribute Syntax Error: Legal values for PREG are 0 or 1" +-- severity Failure; + end case; + + end process prcs_multsignout_o_mux; +--#################################################################### +--#################################################################### +--#################################################################### +--##### PCOUT and MULTSIGNOUT ##### +--#################################################################### + prcs_qp_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1' or the_auto_reset_patdet) then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= alu_o; + multsignout_o_reg <= mult_o_reg((MSB_A_MULT+MSB_B_MULT+1)); + end if; + end if; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(alu_o, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= alu_o; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: Legal values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### Pattern Detector ##### +--#################################################################### + +-- new + the_pattern <= To_StdLogicVector(PATTERN) when (SEL_PATTERN = "PATTERN") else + qc_o_mux; + + the_mask <= To_StdLogicVector(MASK) when (SEL_MASK = "MASK") else + qc_o_mux when (SEL_MASK = "C") else + To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) when (SEL_MASK = "ROUNDING_MODE1") else + To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) when (SEL_MASK = "ROUNDING_MODE2"); + + prcs_pdet:process(alu_o, the_mask, the_pattern, GSR_dly ) + variable x_found : boolean := false; + variable lhs : std_logic_vector(MSB_P downto 0) := (others => '0'); + variable rhs : std_logic_vector(MSB_P downto 0) := (others => '0'); + + begin + -- CR 501854 + + lhs := (alu_o or mask_qp); + rhs := (pattern_qp or mask_qp); + + x_found := find_x(lhs, rhs); + + if(((alu_o or the_mask) = (the_pattern or the_mask)) and (GSR_dly = '0') and (not x_found))then + pdet_o <= '1'; + else + pdet_o <= '0'; + end if; + + if(((alu_o or the_mask) = ((NOT the_pattern) or the_mask)) and (GSR_dly = '0') and (not x_found)) then + pdetb_o <= '1'; + else + pdetb_o <= '0'; + end if; + + end process prcs_pdet; + +--------------------------------------------------------------- + + prcs_pdet_reg:process(CLK_dly, GSR_dly) + variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0'; + begin + if(GSR_dly = '1') then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1' or the_auto_reset_patdet) then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + pdetb_reg2_var := pdetb_reg1_var; + pdetb_reg1_var := pdetb_o; + + pdet_reg2_var := pdet_reg1_var; + pdet_reg1_var := pdet_o; + + pdetb_o_reg1 <= pdetb_reg1_var; + pdetb_o_reg2 <= pdetb_reg2_var; + pdet_o_reg1 <= pdet_reg1_var; + pdet_o_reg2 <= pdet_reg2_var; + + end if; + end if; + end if; + end process prcs_pdet_reg; + +-- old prcs_sel_pattern_detect:process(alu_o, qc_o_mux) +-- old begin + +-- -- Select the pattern +-- if((SEL_PATTERN = "PATTERN") or (SEL_PATTERN = "pattern")) then +-- pattern_qp <= To_StdLogicVector(PATTERN); +-- elsif((SEL_PATTERN = "C") or (SEL_PATTERN = "c")) then +-- pattern_qp <= qc_o_mux; +-- else +-- assert false +-- report "Attribute Syntax Error: The attribute SEL_PATTERN on DSP48_ALU is incorrect. Legal values for this attribute are PATTERN or C" +-- severity Failure; +-- end if; +-- +-- -- Select the mask -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK +-- if((SEL_ROUNDING_MASK = "SEL_MASK") or (SEL_ROUNDING_MASK = "sel_mask")) then +-- if((SEL_MASK = "MASK") or (SEL_MASK = "mask")) then +-- mask_qp <= To_StdLogicVector(MASK); +-- elsif((SEL_MASK = "C") or (SEL_MASK = "c")) then +-- mask_qp <= qc_o_mux; +-- else +-- assert false +-- report "Attribute Syntax Error: The attribute SEL_MASK on DSP48_ALU is incorrect. Legal values for this attribute are MASK or C" +-- severity Failure; +-- end if; +-- elsif((SEL_ROUNDING_MASK = "MODE1") or (SEL_ROUNDING_MASK = "mode1")) then +-- mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) ; +-- mask_qp (0) <= '0'; +-- elsif((SEL_ROUNDING_MASK = "MODE2") or (SEL_ROUNDING_MASK = "mode2")) then +-- mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) ; +-- mask_qp (1 downto 0) <= (others => '0'); +-- else +-- assert false +-- report "Attribute Syntax Error: The attribute SEL_ROUNDING_MASK on DSP48_ALU is incorrect. Legal values for this attribute are SEL_MASK or MODE1 or MODE2." +-- severity Failure; +-- end if; +-- +-- end process prcs_sel_pattern_detect; + + +--------------------------------------------------------------- + +-- prcs_pdet:process(alu_o, mask_qp, pattern_qp, GSR_dly ) +-- begin +-- if(((alu_o or mask_qp) = (pattern_qp or mask_qp)) and (GSR_dly = '0'))then +-- pdet_o <= '1'; +-- else +-- pdet_o <= '0'; +-- end if; +-- +-- if(((alu_o or mask_qp) = ((NOT pattern_qp) or mask_qp)) and (GSR_dly = '0')) then +-- pdetb_o <= '1'; +-- else +-- pdetb_o <= '0'; +-- end if; +-- +-- end process prcs_pdet; + +--------------------------------------------------------------- + +-- prcs_pdet_reg:process(CLK_dly, GSR_dly) +-- variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0'; +-- begin +-- if(GSR_dly = '1') then +-- pdetb_o_reg1 <= '0'; +-- pdetb_o_reg2 <= '0'; +-- pdet_o_reg1 <= '0'; +-- pdet_o_reg2 <= '0'; +-- +-- pdetb_reg1_var := '0'; +-- pdetb_reg2_var := '0'; +-- pdet_reg1_var := '0'; +-- pdet_reg2_var := '0'; +-- elsif (GSR_dly = '0') then +-- if(rising_edge(CLK_dly)) then +-- if(RSTP_dly = '1' or the_auto_reset_patdet) then +-- pdetb_o_reg1 <= '0'; +-- pdetb_o_reg2 <= '0'; +-- pdet_o_reg1 <= '0'; +-- pdet_o_reg2 <= '0'; +-- +-- pdetb_reg1_var := '0'; +-- pdetb_reg2_var := '0'; +-- pdet_reg1_var := '0'; +-- pdet_reg2_var := '0'; +-- elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then +-- pdetb_reg2_var := pdetb_reg1_var; +-- pdetb_reg1_var := pdetb_o; +-- +-- pdet_reg2_var := pdet_reg1_var; +-- pdet_reg1_var := pdet_o; +-- +-- pdetb_o_reg1 <= pdetb_reg1_var; +-- pdetb_o_reg2 <= pdetb_reg2_var; +-- pdet_o_reg1 <= pdet_reg1_var; +-- pdet_o_reg2 <= pdet_reg2_var; +-- +-- end if; +-- end if; +-- end if; +-- end process prcs_pdet_reg; + +--#################################################################### +--##### Underflow / Overflow ##### +--#################################################################### + prcs_uflow_oflow:process(pdet_o_reg1 , pdet_o_reg2 , pdetb_o_reg1 , pdetb_o_reg2) + begin + if(GSR_dly = '1') then + overflow_o <= '0'; + underflow_o <= '0'; + elsif((USE_PATTERN_DETECT = "PATDET") or (PREG = 1))then + overflow_o <= pdet_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + underflow_o <= pdetb_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + else + overflow_o <= 'X'; + underflow_o <= 'X'; + end if; + + end process prcs_uflow_oflow; +-- skip for fast_model +--#################################################################### +--##### OPMODE DRC ##### +--#################################################################### + +-- end skip for fast_model +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qacout_o_mux, qbcout_o_mux, carryout_x_o, carrycascout_o_mux, + overflow_o, qp_o_mux, pdet_o, pdetb_o, + pdet_o_reg1, pdetb_o_reg1, + pdet_o_reg2, pdetb_o_reg2, + underflow_o, multsignout_o_mux, opmode_valid_flg, alumode_valid_flg) + begin + ACOUT_zd <= qacout_o_mux; + BCOUT_zd <= qbcout_o_mux; + OVERFLOW_zd <= overflow_o; + UNDERFLOW_zd <= underflow_o; + P_zd <= qp_o_mux; + PCOUT_zd <= qp_o_mux; + MULTSIGNOUT_zd <= multsignout_o_mux; + + if(the_auto_reset_patdet) then + CARRYCASCOUT_zd <= '0'; + CARRYOUT_zd <= (others => '0'); + else + CARRYCASCOUT_zd <= carrycascout_o_mux; + CARRYOUT_zd <= carryout_x_o; + end if; + +-- if((USE_PATTERN_DETECT = "NO_PATDET") or (not opmode_valid_flg) or (not alumode_valid_flg)) then +-- IR 491951 + if((not opmode_valid_flg) or (not alumode_valid_flg)) then + PATTERNBDETECT_zd <= 'X'; + PATTERNDETECT_zd <= 'X'; + elsif (PREG = 0) then + PATTERNBDETECT_zd <= pdetb_o; + PATTERNDETECT_zd <= pdet_o; + elsif(PREG = 1) then + PATTERNBDETECT_zd <= pdetb_o_reg1; + PATTERNDETECT_zd <= pdet_o_reg1; + end if; + + end process prcs_zero_delay_outputs; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ACOUT_zd, BCOUT_zd, CARRYCASCOUT_zd, CARRYOUT_zd, + OVERFLOW_zd, P_zd, PATTERNBDETECT_zd, PATTERNDETECT_zd, + PCOUT_zd, UNDERFLOW_zd, MULTSIGNOUT_zd) + begin + ACOUT <= ACOUT_zd after SYNC_PATH_DELAY; + BCOUT <= BCOUT_zd after SYNC_PATH_DELAY; + CARRYCASCOUT <= CARRYCASCOUT_zd after SYNC_PATH_DELAY; + CARRYOUT <= CARRYOUT_zd after SYNC_PATH_DELAY; + OVERFLOW <= OVERFLOW_zd after SYNC_PATH_DELAY; + P <= P_zd after SYNC_PATH_DELAY; + PATTERNBDETECT <= PATTERNBDETECT_zd after SYNC_PATH_DELAY; + PATTERNDETECT <= PATTERNDETECT_zd after SYNC_PATH_DELAY; + PCOUT <= PCOUT_zd after SYNC_PATH_DELAY; + UNDERFLOW <= UNDERFLOW_zd after SYNC_PATH_DELAY; + + MULTSIGNOUT <= MULTSIGNOUT_zd after SYNC_PATH_DELAY; + end process prcs_output; + + + +end DSP48E1_V; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/MMCME2_ADV.vhd b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/MMCME2_ADV.vhd new file mode 100644 index 0000000..7311de2 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/MMCME2_ADV.vhd @@ -0,0 +1,1938 @@ +-- Copyright (c) 1995/2010 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------/ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.i (O.xx) +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Phase Lock Loop Clock +-- /___/ /\ Filename : MMCME2_ADV.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 09/17/11 - Initial version. +-- End Revision + +----- CELL MMCME2_ADV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.NUMERIC_STD.all; +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity MMCME2_ADV is +generic ( + + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_MULT_F : real := 5.000; + CLKFBOUT_PHASE : real := 0.000; + CLKFBOUT_USE_FINE_PS : boolean := FALSE; + CLKIN1_PERIOD : real := 0.000; + CLKIN2_PERIOD : real := 0.000; + CLKOUT0_DIVIDE_F : real := 1.000; + CLKOUT0_DUTY_CYCLE : real := 0.500; + CLKOUT0_PHASE : real := 0.000; + CLKOUT0_USE_FINE_PS : boolean := FALSE; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.500; + CLKOUT1_PHASE : real := 0.000; + CLKOUT1_USE_FINE_PS : boolean := FALSE; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.500; + CLKOUT2_PHASE : real := 0.000; + CLKOUT2_USE_FINE_PS : boolean := FALSE; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.500; + CLKOUT3_PHASE : real := 0.000; + CLKOUT3_USE_FINE_PS : boolean := FALSE; + CLKOUT4_CASCADE : boolean := FALSE; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.500; + CLKOUT4_PHASE : real := 0.000; + CLKOUT4_USE_FINE_PS : boolean := FALSE; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.500; + CLKOUT5_PHASE : real := 0.000; + CLKOUT5_USE_FINE_PS : boolean := FALSE; + CLKOUT6_DIVIDE : integer := 1; + CLKOUT6_DUTY_CYCLE : real := 0.500; + CLKOUT6_PHASE : real := 0.000; + CLKOUT6_USE_FINE_PS : boolean := FALSE; + COMPENSATION : string := "ZHOLD"; + DIVCLK_DIVIDE : integer := 1; + IS_CLKINSEL_INVERTED : bit := '0'; + IS_PSEN_INVERTED : bit := '0'; + IS_PSINCDEC_INVERTED : bit := '0'; + IS_PWRDWN_INVERTED : bit := '0'; + IS_RST_INVERTED : bit := '0'; + REF_JITTER1 : real := 0.0; + REF_JITTER2 : real := 0.0; + SS_EN : string := "FALSE"; + SS_MODE : string := "CENTER_HIGH"; + SS_MOD_PERIOD : integer := 10000; + STARTUP_WAIT : boolean := FALSE + ); +port ( + CLKFBOUT : out std_ulogic := '0'; + CLKFBOUTB : out std_ulogic := '0'; + CLKFBSTOPPED : out std_ulogic := '0'; + CLKINSTOPPED : out std_ulogic := '0'; + CLKOUT0 : out std_ulogic := '0'; + CLKOUT0B : out std_ulogic := '0'; + CLKOUT1 : out std_ulogic := '0'; + CLKOUT1B : out std_ulogic := '0'; + CLKOUT2 : out std_ulogic := '0'; + CLKOUT2B : out std_ulogic := '0'; + CLKOUT3 : out std_ulogic := '0'; + CLKOUT3B : out std_ulogic := '0'; + CLKOUT4 : out std_ulogic := '0'; + CLKOUT5 : out std_ulogic := '0'; + CLKOUT6 : out std_ulogic := '0'; + DO : out std_logic_vector (15 downto 0); + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + CLKFBIN : in std_ulogic; + CLKIN1 : in std_ulogic; + CLKIN2 : in std_ulogic; + CLKINSEL : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + PSCLK : in std_ulogic; + PSEN : in std_ulogic; + PSINCDEC : in std_ulogic; + PWRDWN : in std_ulogic; + RST : in std_ulogic + ); +end MMCME2_ADV; + + +-- Architecture body -- + +architecture MMCME2_ADV_V of MMCME2_ADV is + + function real2int( real_in : in real) return integer is + variable int_value : integer; + variable int_value1 : integer; + variable tmps : time := 1 ps; + variable tmps1 : real; + + begin + if (real_in < 1.00000 and real_in > -1.00000) then + int_value1 := 0; + else + tmps := real_in * 1 ns; + int_value := tmps / 1 ns; + tmps1 := real (int_value); + if ( tmps1 > real_in) then + int_value1 := int_value - 1 ; + else + int_value1 := int_value; + end if; + end if; + return int_value1; + end real2int; + + function clkout_duty_chk (CLKOUT_DIVIDE : in integer; + CLKOUT_DUTY_CYCLE : in real; + CLKOUT_DUTY_CYCLE_N : in string) + return std_ulogic is + constant O_MAX_HT_LT_real : real := 64.0; + variable CLKOUT_DIVIDE_real : real; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MIN_rnd : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable clk_duty_tmp_int : integer; + variable duty_cycle_valid : std_ulogic; + variable tmp_duty_value : real; + variable tmp_j : real; + variable Message : line; + variable step_round_tmp : integer; + variable step_round_tmp1 : real; + + begin + CLKOUT_DIVIDE_real := real(CLKOUT_DIVIDE); + step_round_tmp := 1000 /CLKOUT_DIVIDE; + step_round_tmp1 := real(step_round_tmp); + if (CLKOUT_DIVIDE_real > O_MAX_HT_LT_real) then + CLK_DUTY_CYCLE_MIN := (CLKOUT_DIVIDE_real - O_MAX_HT_LT_real)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MAX := (O_MAX_HT_LT_real + 0.5)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MIN_rnd := CLK_DUTY_CYCLE_MIN; + else + if (CLKOUT_DIVIDE = 1) then + CLK_DUTY_CYCLE_MIN_rnd := 0.0; + CLK_DUTY_CYCLE_MIN := 0.0; + else + CLK_DUTY_CYCLE_MIN_rnd := step_round_tmp1 / 1000.00; + CLK_DUTY_CYCLE_MIN := 1.0 / CLKOUT_DIVIDE_real; + end if; + CLK_DUTY_CYCLE_MAX := 1.0; + end if; + + if ((CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX) or (CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd)) then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" is set to ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" and is not in the allowed range ")); + Write ( Message, CLK_DUTY_CYCLE_MIN); + Write ( Message, string'(" to ")); + Write ( Message, CLK_DUTY_CYCLE_MAX); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + CLK_DUTY_CYCLE_STEP := 0.5 / CLKOUT_DIVIDE_real; + tmp_j := 0.0; + duty_cycle_valid := '0'; + clk_duty_tmp_int := 0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if (abs(tmp_duty_value - CLKOUT_DUTY_CYCLE) < 0.001 and (tmp_duty_value <= CLK_DUTY_CYCLE_MAX)) then + duty_cycle_valid := '1'; + end if; + tmp_j := tmp_j + 1.0; + end loop; + + if (duty_cycle_valid /= '1') then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" = ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" which is not an allowed value. Allowed value s are: ")); + Write ( Message, LF ); + tmp_j := 0.0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if ( (tmp_duty_value <= CLK_DUTY_CYCLE_MAX) and (tmp_duty_value < 1.0)) then + Write ( Message, tmp_duty_value); + Write ( Message, LF ); + end if; + tmp_j := tmp_j + 1.0; + end loop; + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + return duty_cycle_valid; + end function clkout_duty_chk; + + constant VCOCLK_FREQ_MAX : real := 1600.0; + constant VCOCLK_FREQ_MIN : real := 600.0; + constant CLKIN_FREQ_MAX : real := 1066.0; + constant CLKIN_FREQ_MIN : real := 10.0; + constant CLKPFD_FREQ_MAX : real := 550.0; + constant CLKPFD_FREQ_MIN : real := 10.0; + constant VCOCLK_FREQ_TARGET : real := 1000.0; + constant O_MAX_HT_LT : integer := 64; + constant REF_CLK_JITTER_MAX : time := 1000 ps; + constant REF_CLK_JITTER_SCALE : real := 0.1; + constant MAX_FEEDBACK_DELAY : time := 10 ns; + constant MAX_FEEDBACK_DELAY_SCALE : real := 1.0; + constant M_MAX : real := 64.000; + constant M_MIN : real := 2.000; + constant D_MAX : integer := 106; + constant D_MIN : integer := 1; + + signal pwrdwn_in1 : std_ulogic := '0'; + signal rst_input : std_ulogic := '0'; + signal init_done : std_ulogic := '0'; + signal clkpll_r : std_ulogic := '0'; + signal locked_out_tmp : std_ulogic := '0'; + signal clkfbm1_f_div : real := 1.0; + signal clkfb_div_fint : integer := 0; + signal clkfb_div_frac : real := 0.0; + signal clkfb_frac_en : std_ulogic := '0'; + signal clkfb_div_frac_int : integer := 0; + signal clkfb_div_f_int : integer := 0; + signal clkfb_val : integer := 0; + signal clkfb_val1 : integer := 0; + signal clkfb_val11 : integer := 0; + signal clkfb_val2 : integer := 0; + signal clk0_div_fint : integer := 0; + signal clk0_div_frac : real := 0.0; + signal clk0_frac_en : std_ulogic := '0'; + signal clk0_div_frac_int : integer := 0; + signal clk0_div_f_int : integer := 0; + signal clk0_val : integer := 0; + signal clk0_val1 : integer := 0; + signal clk0_val11 : integer := 0; + signal clk1_val11 : integer := 0; + signal clk2_val11 : integer := 0; + signal clk3_val11 : integer := 0; + signal clk4_val11 : integer := 0; + signal clk5_val11 : integer := 0; + signal clk6_val11 : integer := 0; + signal clk0_val2 : integer := 0; + signal clk1_val2 : integer := 0; + signal clk2_val2 : integer := 0; + signal clk3_val2 : integer := 0; + signal clk4_val2 : integer := 0; + signal clk5_val2 : integer := 0; + signal clk6_val2 : integer := 0; + signal clk1_val : integer := 0; + signal clk1_val1 : integer := 0; + signal clk2_val : integer := 0; + signal clk2_val1 : integer := 0; + signal clk3_val : integer := 0; + signal clk3_val1 : integer := 0; + signal clk4_val : integer := 0; + signal clk4_val1 : integer := 0; + signal clk5_val : integer := 0; + signal clk5_val1 : integer := 0; + signal clk6_val : integer := 0; + signal clk6_val1 : integer := 0; + signal chk_ok : std_ulogic := '0'; + constant period_vco_target : time := 1000 ps / VCOCLK_FREQ_TARGET; + constant fb_delay_max : time := MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + signal pll_lock_time : integer := 0; + signal clkfb_out : std_ulogic := '0'; + signal clkout0_out : std_ulogic := '0'; + signal clkout1_out : std_ulogic := '0'; + signal clkout2_out : std_ulogic := '0'; + signal clkout3_out : std_ulogic := '0'; + signal clkout4_out : std_ulogic := '0'; + signal clkout5_out : std_ulogic := '0'; + signal clkout6_out : std_ulogic := '0'; + signal p_fb : time := 0 ps; + signal p_fb_h : time := 0 ps; + signal p_fb_r : time := 0 ps; + signal p_fb_r1 : time := 0 ps; + signal p_fb_d : time := 0 ps; + signal p_c0_dr : time := 0 ps; + signal p_c1_dr : time := 0 ps; + signal p_c2_dr : time := 0 ps; + signal p_c3_dr : time := 0 ps; + signal p_c4_dr : time := 0 ps; + signal p_c5_dr : time := 0 ps; + signal p_c6_dr : time := 0 ps; + signal p_c0_h : time := 0 ps; + signal p_c0_r : time := 0 ps; + signal p_c0_d : time := 0 ps; + signal p_c0_r1 : time := 0 ps; + signal p_c1_r1 : time := 0 ps; + signal p_c2_r1 : time := 0 ps; + signal p_c3_r1 : time := 0 ps; + signal p_c4_r1 : time := 0 ps; + signal p_c5_r1 : time := 0 ps; + signal p_c6_r1 : time := 0 ps; + signal p_c1_h : time := 0 ps; + signal p_c1_r : time := 0 ps; + signal p_c1_d : time := 0 ps; + signal p_c2_h : time := 0 ps; + signal p_c2_r : time := 0 ps; + signal p_c2_d : time := 0 ps; + signal p_c3_h : time := 0 ps; + signal p_c3_r : time := 0 ps; + signal p_c3_d : time := 0 ps; + signal p_c4_h : time := 0 ps; + signal p_c4_r : time := 0 ps; + signal p_c4_d : time := 0 ps; + signal p_c5_h : time := 0 ps; + signal p_c5_r : time := 0 ps; + signal p_c5_d : time := 0 ps; + signal p_c6_h : time := 0 ps; + signal p_c6_r : time := 0 ps; + signal p_c6_d : time := 0 ps; + signal period_fb : time := 0 ps; + signal clk0_gen : std_ulogic := '0'; + signal clk1_gen : std_ulogic := '0'; + signal clk2_gen : std_ulogic := '0'; + signal clk3_gen : std_ulogic := '0'; + signal clk4_gen : std_ulogic := '0'; + signal clk5_gen : std_ulogic := '0'; + signal clk6_gen : std_ulogic := '0'; + signal clkfb_gen : std_ulogic := '0'; + signal clk0_gen_f : std_ulogic := '0'; + signal clk1_gen_f : std_ulogic := '0'; + signal clk2_gen_f : std_ulogic := '0'; + signal clk3_gen_f : std_ulogic := '0'; + signal clk4_gen_f : std_ulogic := '0'; + signal clk5_gen_f : std_ulogic := '0'; + signal clk6_gen_f : std_ulogic := '0'; + signal clkfb_gen_f : std_ulogic := '0'; + signal sample_en : std_ulogic := '1'; + signal clk0_out : std_ulogic := '0'; + signal clk1_out : std_ulogic := '0'; + signal clk2_out : std_ulogic := '0'; + signal clk3_out : std_ulogic := '0'; + signal clk4_out : std_ulogic := '0'; + signal clk5_out : std_ulogic := '0'; + signal clk6_out : std_ulogic := '0'; + signal clkfbm1_out : std_ulogic := '0'; + signal fb_delay_found_tmp : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + type real_array_usr is array (4 downto 0) of time; + signal clkin_period : real_array_usr := (others => 0 ps); + signal clkout_mux : std_logic_vector (7 downto 0) ; + signal lock_period_time : integer := 0; + signal clkout_en_time : integer := 0; + signal locked_en_time : integer := 0; + signal lock_cnt_max : integer := 0; + signal pwron_int : std_ulogic := '0'; + signal rst_in : std_ulogic := '0'; + signal pll_locked_tmp1 : std_ulogic := '0'; + signal pll_locked_tmp2 : std_ulogic := '0'; + signal lock_period : std_ulogic := '0'; + signal pll_locked_tm : std_ulogic := '0'; + signal clkin_edge : time := 0 ps; + signal fb_delay : time := 0 ps; + signal clkvco_delay : time := 0 ps; + signal clkin_lock_cnt : integer := 0; + signal clkfbm1_dly : time := 0 ps; + signal clkout_en0_tmp : std_ulogic := '0'; + signal clkout_en : std_ulogic := '0'; + signal clkout_en1 : std_ulogic := '0'; + signal locked_out : std_ulogic := '0'; + signal period_avg : time := 0 ps; + signal delay_edge : time := 0 ps; + signal clkin_period_tmp_t : integer := 0; + signal period_vco : time := 0 ps; + signal clk0ps_en : std_ulogic := '0'; + signal clk1ps_en : std_ulogic := '0'; + signal clk2ps_en : std_ulogic := '0'; + signal clk3ps_en : std_ulogic := '0'; + signal clk4ps_en : std_ulogic := '0'; + signal clk5ps_en : std_ulogic := '0'; + signal clk6ps_en : std_ulogic := '0'; + signal clkfbm1ps_en : std_ulogic := '0'; + signal clk0_cnt : integer := 0; + signal clk1_cnt : integer := 0; + signal clk2_cnt : integer := 0; + signal clk3_cnt : integer := 0; + signal clk4_cnt : integer := 0; + signal clk5_cnt : integer := 0; + signal clk6_cnt : integer := 0; + signal clkfb_cnt : integer := 0; + signal clkfb_tst : std_ulogic := '0'; + signal clkfb_in : std_ulogic := '0'; + signal clkin1_in : std_ulogic := '0'; + signal clkin1_in_dly : std_ulogic := '0'; + signal clkin2_in : std_ulogic := '0'; + signal clkinsel_in : std_ulogic := '0'; + signal clkinsel_tmp : std_ulogic := '0'; + signal rst_input_r : std_ulogic := '0'; + signal pwrdwn_in : std_ulogic := '0'; + signal IS_CLKINSEL_INVERTED_BIN : std_ulogic := TO_X01(IS_CLKINSEL_INVERTED); + signal IS_PWRDWN_INVERTED_BIN : std_ulogic := TO_X01(IS_PWRDWN_INVERTED); + signal IS_RST_INVERTED_BIN : std_ulogic := TO_X01(IS_RST_INVERTED); + + begin + + clkin1_in <= CLKIN1; + clkin2_in <= CLKIN2; + clkfb_in <= CLKFBIN; + clkinsel_in <= '1' when (CLKINSEL xor IS_CLKINSEL_INVERTED_BIN) /= '0' else '0'; + rst_input_r <= RST xor IS_RST_INVERTED_BIN; + pwrdwn_in <= PWRDWN xor IS_PWRDWN_INVERTED_BIN; + LOCKED <= locked_out_tmp; + CLKOUT0 <= clkout0_out; + CLKOUT1 <= clkout1_out; + CLKOUT2 <= clkout2_out; + CLKOUT3 <= clkout3_out; + CLKOUT4 <= clkout4_out; + CLKOUT5 <= clkout5_out; + CLKOUT6 <= clkout6_out; + CLKFBOUT <= clkfb_out; + CLKFBOUTB <= not clkfb_out; + CLKOUT0B <= not clkout0_out; + CLKOUT1B <= not clkout1_out; + CLKOUT2B <= not clkout2_out; + CLKOUT3B <= not clkout3_out; + DO <= "0000000000000000"; + + INIPROC : process + variable Message : line; + variable con_line : line; + variable tmpvalue : real; + variable chk_ok : std_ulogic; + variable tmp_string : string(1 to 18); + variable skipspace : character; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable O_MAX_HT_LT_real : real; + variable duty_cycle_valid : std_ulogic; + variable CLKOUT0_DIVIDE_real : real; + variable CLKOUT1_DIVIDE_real : real; + variable CLKOUT2_DIVIDE_real : real; + variable CLKOUT3_DIVIDE_real : real; + variable CLKOUT4_DIVIDE_real : real; + variable CLKOUT5_DIVIDE_real : real; + variable CLKOUT6_DIVIDE_real : real; + variable tmp_j : real; + variable tmp_duty_value : real; + variable clk_nocnt_i : std_ulogic; + variable clk_edge_i : std_ulogic; + variable clkfbm1_f_div_v : real := 1.0; + variable clkfb_div_fint_v : integer := 1; + variable clkfb_div_fint_v_tmp : integer := 1; + variable clkfb_div_fint_v1 : real := 1.0; + variable clkfb_div_frac_v : real := 0.0; + variable clkfb_div_frac_int_v : integer := 0; + variable clk0_div_fint_v : integer := 1; + variable clk0_div_fint_v_tmp : integer := 1; + variable clk0_div_fint_v1 : real := 1.0; + variable clk0_div_frac_v : real := 0.0; + variable clk0_div_frac_int_v : integer := 0; + variable clk0_frac_v : integer := 0; + variable clkfb_fps_eni : integer; + variable clk0_fps_eni : integer; + variable clk1_fps_eni : integer; + variable clk2_fps_eni : integer; + variable clk3_fps_eni : integer; + variable clk4_fps_eni : integer; + variable clk5_fps_eni : integer; + variable clk6_fps_eni : integer; + variable clkout_en_time_i : integer; + variable clkfb_frac_v : integer := 0; + variable clkfb_frac_en_v : std_ulogic := '0'; + variable clk0_frac_en_v : std_ulogic := '0'; + variable clkfb_div_f_int_v : integer := 0; + variable clk0_div_f_int_v : integer := 0; + variable clkfb_div_fint_odd_v : integer := 0; + variable clkout_en_time_i1 : integer := 0; + variable clk0_val1_tmp : integer := 0; + variable clk1_val1_tmp : integer := 0; + variable clk2_val1_tmp : integer := 0; + variable clk3_val1_tmp : integer := 0; + variable clk4_val1_tmp : integer := 0; + variable clk5_val1_tmp : integer := 0; + variable clk6_val1_tmp : integer := 0; + begin + if((COMPENSATION /= "ZHOLD") and (COMPENSATION /= "zhold") and + (COMPENSATION /= "BUF_IN") and (COMPENSATION /= "buf_in") and + (COMPENSATION /= "EXTERNAL") and (COMPENSATION /= "external") and + (COMPENSATION /= "INTERNAL") and (COMPENSATION /= "internal")) +then + assert FALSE report " Attribute Syntax Error : The Attribute COMPENSATION must be set to ZHOLD or BUF_IN or EXTERNAL or INTERNAL." severity error; end if; + + if((BANDWIDTH /= "HIGH") and (BANDWIDTH /= "high") and + (BANDWIDTH /= "LOW") and (BANDWIDTH /= "low") and + (BANDWIDTH /= "OPTIMIZED") and (BANDWIDTH /= "optimized")) then assert FALSE report "Attribute Syntax Error : BANDWIDTH is not HIGH, LOW, OPTIMIZED." severity error; + end if; + + if (CLKFBOUT_USE_FINE_PS /= FALSE and CLKFBOUT_USE_FINE_PS /= false + and CLKFBOUT_USE_FINE_PS /= TRUE and CLKFBOUT_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT0_USE_FINE_PS /= FALSE and CLKOUT0_USE_FINE_PS /= false + and CLKOUT0_USE_FINE_PS /= TRUE and CLKOUT0_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT1_USE_FINE_PS /= FALSE and CLKOUT1_USE_FINE_PS /= false + and CLKOUT1_USE_FINE_PS /= TRUE and CLKOUT1_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT2_USE_FINE_PS /= FALSE and CLKOUT2_USE_FINE_PS /= false + and CLKOUT2_USE_FINE_PS /= TRUE and CLKOUT2_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT3_USE_FINE_PS /= FALSE and CLKOUT3_USE_FINE_PS /= false + and CLKOUT3_USE_FINE_PS /= TRUE and CLKOUT3_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT4_USE_FINE_PS /= FALSE and CLKOUT4_USE_FINE_PS /= false + and CLKOUT4_USE_FINE_PS /= TRUE and CLKOUT4_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT5_USE_FINE_PS /= FALSE and CLKOUT5_USE_FINE_PS /= false + and CLKOUT5_USE_FINE_PS /= TRUE and CLKOUT5_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + if (CLKOUT6_USE_FINE_PS /= FALSE and CLKOUT6_USE_FINE_PS /= false + and CLKOUT6_USE_FINE_PS /= TRUE and CLKOUT6_USE_FINE_PS /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS must be set to FALSE or TRUE." severity error; + end if; + + + + if (CLKOUT4_CASCADE /= FALSE and CLKOUT4_CASCADE /= false + and CLKOUT4_CASCADE /= TRUE and CLKOUT4_CASCADE /= true) then + assert FALSE report " Attribute Syntax Error : The Attribute CLKOUT4_CASCADE must be set to FALSE or TRUE." severity error; + end if; + + if((STARTUP_WAIT /= FALSE) and (STARTUP_WAIT /= false) + and (STARTUP_WAIT /= TRUE) and (STARTUP_WAIT /= true)) then + assert FALSE report "Error : STARTUP_WAIT must be set to FALSE, TRUE." severity error; + end if; + + clkfbm1_f_div_v := CLKFBOUT_MULT_F; + clkfbm1_f_div <= CLKFBOUT_MULT_F; + clkfb_div_fint_v := real2int(clkfbm1_f_div_v); + clkfb_div_fint <= clkfb_div_fint_v; + clkfb_div_fint_v_tmp := clkfb_div_fint_v / 2; + clkfb_div_fint_odd_v := clkfb_div_fint_v - 2 * clkfb_div_fint_v_tmp; + clkfb_div_fint_v1 := real(clkfb_div_fint_v); + clkfb_div_frac_v := clkfbm1_f_div_v - clkfb_div_fint_v1; + clkfb_div_frac <= clkfb_div_frac_v; + if (clkfb_div_frac_v > 0.000) then + clkfb_frac_en <= '1'; + clkfb_frac_en_v := '1'; + else + clkfb_frac_en <= '0'; + clkfb_frac_en_v := '0'; + end if; + clkfb_div_frac_int_v := real2int(clkfb_div_frac_v * 8.0); + clkfb_div_frac_int <= clkfb_div_frac_int_v; + clkfb_div_f_int_v := clkfb_div_fint_v * 8 + clkfb_div_frac_int_v; + clkfb_div_f_int <= clkfb_div_f_int_v; + clkfb_val <= DIVCLK_DIVIDE * 8; + clkfb_val2 <= DIVCLK_DIVIDE * 8 * 2 - 1; + clkfb_val1 <= 8; + clkfb_val11 <= 7; + + clk0_div_fint_v := real2int(CLKOUT0_DIVIDE_F); + clk0_div_fint_v1 := real(clk0_div_fint_v); + clk0_div_fint <= clk0_div_fint_v; + clk0_div_frac_v := CLKOUT0_DIVIDE_F - clk0_div_fint_v1; + clk0_div_frac <= clk0_div_frac_v; + if (clk0_div_frac_v > 0.000 and clk0_div_fint_v >= 2) then + clk0_frac_en <= '1'; + clk0_frac_en_v := '1'; + else + clk0_frac_en <= '0'; + clk0_frac_en_v := '0'; + end if; + clk0_div_frac_int_v := real2int(clk0_div_frac_v * 8.0); + clk0_div_frac_int <= clk0_div_frac_int_v; + clk0_div_f_int_v := clk0_div_fint_v * 8 + clk0_div_frac_int_v; + clk0_div_f_int <= clk0_div_f_int_v; + if (clkfb_frac_en_v = '1') then + if (clk0_frac_en_v = '1') then + clk0_val <= clk0_div_f_int_v * 8 * DIVCLK_DIVIDE; + clk0_val2 <= clk0_div_f_int_v * 8 * DIVCLK_DIVIDE * 2 - 1; + clk0_val1_tmp := clkfb_div_f_int_v * clk0_div_f_int_v; + else + clk0_val <= DIVCLK_DIVIDE * 8 * clk0_div_fint_v; + clk0_val2 <= DIVCLK_DIVIDE * 8 * clk0_div_fint_v * 2 - 1; + clk0_val1_tmp := clkfb_div_f_int_v; + end if; + else + if (clk0_frac_en_v = '1') then + clk0_val <= clk0_div_f_int_v * 8 * DIVCLK_DIVIDE; + clk0_val2 <= clk0_div_f_int_v * 8 * DIVCLK_DIVIDE * 2 -1; + clk0_val1_tmp := clkfb_div_f_int_v * clk0_div_f_int_v; + else + clk0_val <= DIVCLK_DIVIDE * clk0_div_fint_v; + clk0_val2 <= DIVCLK_DIVIDE * clk0_div_fint_v * 2 - 1; + clk0_val1_tmp := clkfb_div_fint_v; + end if; + end if; + clk0_val1 <= clk0_val1_tmp; + if ( clk0_val1_tmp > 1) then + clk0_val11 <= clk0_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk1_val <= DIVCLK_DIVIDE * 8 * CLKOUT1_DIVIDE; + clk1_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT1_DIVIDE * 2 - 1; + clk1_val1_tmp := clkfb_div_f_int_v; + else + clk1_val <= DIVCLK_DIVIDE * CLKOUT1_DIVIDE; + clk1_val2 <= DIVCLK_DIVIDE * CLKOUT1_DIVIDE * 2 - 1; + clk1_val1_tmp := clkfb_div_fint_v; + end if; + clk1_val1 <= clk1_val1_tmp; + if ( clk1_val1_tmp > 1) then + clk1_val11 <= clk1_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk2_val <= DIVCLK_DIVIDE * 8 * CLKOUT2_DIVIDE; + clk2_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT2_DIVIDE * 2 - 1; + clk2_val1_tmp := clkfb_div_f_int_v; + else + clk2_val <= DIVCLK_DIVIDE * CLKOUT2_DIVIDE; + clk2_val2 <= DIVCLK_DIVIDE * CLKOUT2_DIVIDE * 2 - 1; + clk2_val1_tmp := clkfb_div_fint_v; + end if; + clk2_val1 <= clk2_val1_tmp; + if ( clk2_val1_tmp > 1) then + clk2_val11 <= clk2_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk3_val <= DIVCLK_DIVIDE * 8 * CLKOUT3_DIVIDE; + clk3_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT3_DIVIDE * 2 - 1; + clk3_val1_tmp := clkfb_div_f_int_v; + else + clk3_val <= DIVCLK_DIVIDE * CLKOUT3_DIVIDE; + clk3_val2 <= DIVCLK_DIVIDE * CLKOUT3_DIVIDE * 2 - 1; + clk3_val1_tmp := clkfb_div_fint_v; + end if; + clk3_val1 <= clk3_val1_tmp; + if ( clk3_val1_tmp > 1) then + clk3_val11 <= clk3_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk4_val <= DIVCLK_DIVIDE * 8 * CLKOUT4_DIVIDE; + clk4_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT4_DIVIDE * 2 - 1; + clk4_val1_tmp := clkfb_div_f_int_v; + else + clk4_val <= DIVCLK_DIVIDE * CLKOUT4_DIVIDE; + clk4_val2 <= DIVCLK_DIVIDE * CLKOUT4_DIVIDE * 2 - 1; + clk4_val1_tmp := clkfb_div_fint_v; + end if; + clk4_val1 <= clk4_val1_tmp; + if ( clk4_val1_tmp > 1) then + clk4_val11 <= clk4_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk5_val <= DIVCLK_DIVIDE * 8 * CLKOUT5_DIVIDE; + clk5_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT5_DIVIDE * 2 - 1; + clk5_val1_tmp := clkfb_div_f_int_v; + else + clk5_val <= DIVCLK_DIVIDE * CLKOUT5_DIVIDE; + clk5_val2 <= DIVCLK_DIVIDE * CLKOUT5_DIVIDE * 2 - 1; + clk5_val1_tmp := clkfb_div_fint_v; + end if; + clk5_val1 <= clk5_val1_tmp; + if ( clk5_val1_tmp > 1) then + clk5_val11 <= clk5_val1_tmp - 1; + end if; + if (clkfb_frac_en_v = '1') then + clk6_val <= DIVCLK_DIVIDE * 8 * CLKOUT6_DIVIDE; + clk6_val2 <= DIVCLK_DIVIDE * 8 * CLKOUT6_DIVIDE * 2 - 1; + clk6_val1_tmp := clkfb_div_f_int_v; + else + clk6_val <= DIVCLK_DIVIDE * CLKOUT6_DIVIDE; + clk6_val2 <= DIVCLK_DIVIDE * CLKOUT6_DIVIDE * 2 - 1; + clk6_val1_tmp := clkfb_div_fint_v; + end if; + clk6_val1 <= clk6_val1_tmp; + if ( clk6_val1_tmp > 1) then + clk6_val11 <= clk6_val1_tmp - 1; + end if; + if (CLKOUT0_DIVIDE_F < 0.000 or CLKOUT0_DIVIDE_F > 128.000) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DIVIDE_F is not in range 1.000 to 128.000." severity error; + end if; + + if (CLKOUT0_DIVIDE_F > 1.0000 and CLKOUT0_DIVIDE_F < 2.0000) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DIVIDE_F is in range of greater than 1.0000 and less than 2.0000, which is not allowed." severity error; + end if; + + if ((CLKOUT0_PHASE < -360.0) or (CLKOUT0_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if (clk0_frac_en_v = '0') then + if ((CLKOUT0_DUTY_CYCLE < 0.001) or (CLKOUT0_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + else + if (CLKOUT0_DUTY_CYCLE > 0.5 or CLKOUT0_DUTY_CYCLE < 0.5) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part." severity error; + end if; + end if; + + case CLKOUT1_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT1_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT1_PHASE < -360.0) or (CLKOUT1_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT1_DUTY_CYCLE < 0.001) or (CLKOUT1_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT2_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT2_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT2_PHASE < -360.0) or (CLKOUT2_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE is not in range -360.0 to 360.0" severity error; + end if; + if ((CLKOUT2_DUTY_CYCLE < 0.001) or (CLKOUT2_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT3_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT3_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT3_PHASE < -360.0) or (CLKOUT3_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT3_DUTY_CYCLE < 0.001) or (CLKOUT3_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT4_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT4_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT4_PHASE < -360.0) or (CLKOUT4_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT4_DUTY_CYCLE < 0.001) or (CLKOUT4_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT5_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT5_DIVIDE is not in range 1...128." severity error; + end case; + if ((CLKOUT5_PHASE < -360.0) or (CLKOUT5_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_PHASE is not in range 360.0 to 360.0" severity error; + end if; + if ((CLKOUT5_DUTY_CYCLE < 0.001) or (CLKOUT5_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT6_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT6_DIVIDE is not in range 1 to 128." severity error; + end case; + if ((CLKOUT6_PHASE < -360.0) or (CLKOUT6_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT6_PHASE is not in range 360.0 to 360.0" severity error; + end if; + if ((CLKOUT6_DUTY_CYCLE < 0.001) or (CLKOUT6_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT6_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + end if; + + if (CLKFBOUT_MULT_F < 2.000 or CLKFBOUT_MULT_F > 64.000) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_MULT is not in range 2.000 to 64.000 ." severity error; + end if; + + if ( CLKFBOUT_PHASE < -360.0 or CLKFBOUT_PHASE > 360.0 ) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + case DIVCLK_DIVIDE is + when 1 to 106 => NULL; + when others => assert FALSE report "Attribute Syntax Error : DIVCLK_DIVIDE is not in range 1 to 106." severity error; + end case; + + if ((REF_JITTER1 < 0.0) or (REF_JITTER1 > 0.999)) then + assert FALSE report "Attribute Syntax Error : REF_JITTER1 is not in range 0.0 ... 1.0." severity error; + end if; + + if ((REF_JITTER2 < 0.0) or (REF_JITTER2 > 0.999)) then + assert FALSE report "Attribute Syntax Error : REF_JITTER2 is not in range 0.0 ... 1.0." severity error; + end if; + + O_MAX_HT_LT_real := real(O_MAX_HT_LT); + CLKOUT0_DIVIDE_real := CLKOUT0_DIVIDE_F; + CLKOUT1_DIVIDE_real := real(CLKOUT1_DIVIDE); + CLKOUT2_DIVIDE_real := real(CLKOUT2_DIVIDE); + CLKOUT3_DIVIDE_real := real(CLKOUT3_DIVIDE); + CLKOUT4_DIVIDE_real := real(CLKOUT4_DIVIDE); + CLKOUT5_DIVIDE_real := real(CLKOUT5_DIVIDE); + CLKOUT6_DIVIDE_real := real(CLKOUT6_DIVIDE); + + if (clk0_frac_en_v = '0') then + if (clk0_div_fint_v /= 0) then + chk_ok := clkout_duty_chk (clk0_div_fint_v, CLKOUT0_DUTY_CYCLE, "CLKOUT0_DUTY_CYCLE"); + end if; + end if; + if (CLKOUT5_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, "CLKOUT5_DUTY_CYCLE"); + end if; + if (CLKOUT1_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, "CLKOUT1_DUTY_CYCLE"); + end if; + if (CLKOUT2_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, "CLKOUT2_DUTY_CYCLE"); + end if; + if (CLKOUT3_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, "CLKOUT3_DUTY_CYCLE"); + end if; + if (CLKOUT4_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, "CLKOUT4_DUTY_CYCLE"); + end if; + if (CLKOUT6_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, "CLKOUT6_DUTY_CYCLE"); + end if; + pll_lock_time <= 12; + lock_period_time <= 16; + clkout_en_time_i1 := 10 + 12; + clkout_en_time <= clkout_en_time_i1; + locked_en_time <= clkout_en_time_i1 + 20; + lock_cnt_max <= clkout_en_time_i1 + 20 + 16; + init_done <= '1'; + wait; + end process INIPROC; + + clkinsel_p : process + variable period_clkin : real; + variable clkvco_freq_init_chk : real := 0.0; + variable Message : line; + variable tmpreal1 : real; + variable tmpreal2 : real; + variable first_check : boolean := true; + variable clkin_chk_t1 : real; + variable clkin_chk_t1_tmp1 : real; + variable clkin_chk_t1_tmp2 : real; + variable clkin_chk_t1_tmpi : time; + variable clkin_chk_t1_tmpi1 : integer; + variable clkin_chk_t2 : real; + variable clkin_chk_t2_tmp1 : real; + variable clkin_chk_t2_tmp2 : real; + variable clkin_chk_t2_tmpi : time; + variable clkin_chk_t2_tmpi1 : integer; + begin + + if (first_check = true or rising_edge(clkinsel_in) or falling_edge(clkinsel_in)) then + + if (NOW > 1 ps and rst_in = '0' and (clkinsel_tmp = '0' or clkinsel_tmp += '1')) then + assert false report + "Input Error : MMCME2_ADV input clock can only be switched when RST=1. CLKINSEL is changed when RST low, which should be changed at RST high." + severity error; + end if; + if (NOW = 0 ps) then + wait for 1 ps; + end if; + + clkin_chk_t1_tmp1 := 1000.0 / CLKIN_FREQ_MIN; + clkin_chk_t1_tmp2 := 1000.0 * clkin_chk_t1_tmp1; + clkin_chk_t1_tmpi := clkin_chk_t1_tmp2 * 1 ps; + clkin_chk_t1_tmpi1 := clkin_chk_t1_tmpi / 1 ps; + clkin_chk_t1 := real(clkin_chk_t1_tmpi1) / 1000.0; + + clkin_chk_t2_tmp1 := 1000.0 / CLKIN_FREQ_MAX; + clkin_chk_t2_tmp2 := 1000.0 * clkin_chk_t2_tmp1; + clkin_chk_t2_tmpi := clkin_chk_t2_tmp2 * 1 ps; + clkin_chk_t2_tmpi1 := clkin_chk_t2_tmpi / 1 ps; + clkin_chk_t2 := real(clkin_chk_t2_tmpi1) / 1000.0; + + if (((CLKIN1_PERIOD < clkin_chk_t2) or (CLKIN1_PERIOD > clkin_chk_t1)) and (CLKINSEL /= '0')) then + Write ( Message, string'(" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to ")); + Write ( Message, CLKIN1_PERIOD); + Write ( Message, string'(" ns and out the allowed range ")); + Write ( Message, clkin_chk_t2); + Write ( Message, string'(" ns to ")); + Write ( Message, clkin_chk_t1); + Write ( Message, string'(" ns" )); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + if (((CLKIN2_PERIOD < clkin_chk_t2) or (CLKIN2_PERIOD > clkin_chk_t1)) and (CLKINSEL = '0')) then + Write ( Message, string'(" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to ")); + Write ( Message, CLKIN2_PERIOD); + Write ( Message, string'(" ns and out the allowed range ")); + Write ( Message, clkin_chk_t2); + Write ( Message, string'(" ns to ")); + Write ( Message, clkin_chk_t1); + Write ( Message, string'(" ns")); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + if ( clkinsel_in /= '0') then + period_clkin := CLKIN1_PERIOD; + else + period_clkin := CLKIN2_PERIOD; + end if; + + tmpreal1 := CLKFBOUT_MULT_F; + tmpreal2 := real(DIVCLK_DIVIDE); + if (period_clkin > 0.000) then + clkvco_freq_init_chk := (1000.0 * tmpreal1) / ( period_clkin * tmpreal2); + + if ((clkvco_freq_init_chk > VCOCLK_FREQ_MAX) or (clkvco_freq_init_chk +< VCOCLK_FREQ_MIN)) then + Write ( Message, string'(" Attribute Syntax Error : The calculation of VCO frequency=")); + Write ( Message, clkvco_freq_init_chk); + Write ( Message, string'(" Mhz. This exceeds the permitted VCO frequency range of ")); + Write ( Message, VCOCLK_FREQ_MIN); + Write ( Message, string'(" MHz to ")); + Write ( Message, VCOCLK_FREQ_MAX); + if (clkinsel_in /= '0') then + Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN1_PERIOD).")); else + Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN2_PERIOD).")); end if; + Write ( Message, string'(" Please adjust the attributes to the permitted VCO frequency range.")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + first_check := false; + end if; + wait on clkinsel_in, clkpll_r; + end process; + + clkpll_r <= clkin1_in when clkinsel_in = '1' else clkin2_in; + pwrdwn_in1 <= '1' when (pwrdwn_in = '1' or pwron_int = '1') else '0'; + rst_input <= '1' when (rst_input_r = '1' or pwrdwn_in1 = '1') else '0'; + + + RST_SYNC_P : process (clkpll_r, rst_input) + begin + if (rst_input = '1') then + rst_in <= '1'; + elsif (rising_edge (clkpll_r)) then + rst_in <= rst_input; + end if; + end process; + + pwron_int_p : process + begin + pwron_int <= '1'; + wait for 100 ns; + pwron_int <= '0'; + wait; + end process; + + CLOCK_PERIOD_P : process (clkpll_r, rst_in) + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_in = '1' ) then + clkin_period(0) <= period_vco_target; + clkin_period(1) <= period_vco_target; + clkin_period(2) <= period_vco_target; + clkin_period(3) <= period_vco_target; + clkin_period(4) <= period_vco_target; + clkin_lock_cnt <= 0; + pll_locked_tm <= '0'; + lock_period <= '0'; + pll_locked_tmp1 <= '0'; + clkout_en0_tmp <= '0'; + clkin_edge_previous := 0 ps; + sample_en <= '1'; + elsif (rising_edge(clkpll_r)) then + if (sample_en = '1') then + clkin_edge_current := NOW; + if (clkin_edge_previous /= 0 ps ) then + clkin_period(4) <= clkin_period(3); + clkin_period(3) <= clkin_period(2); + clkin_period(2) <= clkin_period(1); + clkin_period(1) <= clkin_period(0); + clkin_period(0) <= clkin_edge_current - clkin_edge_previous; + end if; + + clkin_edge_previous := clkin_edge_current; + + if ( (clkin_lock_cnt < lock_cnt_max) and fb_delay_found = '1' ) then + clkin_lock_cnt <= clkin_lock_cnt + 1; + end if; + if ( clkin_lock_cnt >= pll_lock_time) then + pll_locked_tm <= '1'; + end if; + if ( clkin_lock_cnt = lock_period_time ) then + lock_period <= '1'; + end if; + + if (clkin_lock_cnt >= clkout_en_time and pll_locked_tm = '1') then + clkout_en0_tmp <= '1'; + end if; + + if (clkin_lock_cnt >= locked_en_time and clkout_en = '1') then + pll_locked_tmp1 <= '1'; + end if; + + if (pll_locked_tmp2 = '1' and pll_locked_tmp1 = '1') then + sample_en <= '0'; + end if; + end if; + end if; + end process; + + locked_out <= '1' when (pll_locked_tmp1 = '1' and pll_locked_tmp2 = '1') else '0'; + pll_locked_tmp2 <= (clk0ps_en and clk1ps_en and clk2ps_en and clk3ps_en + and clk4ps_en and clk5ps_en and clk6ps_en and clkfbm1ps_en); + + pchk_p : process(pll_locked_tmp1) + variable pchk_tmp1 : time; + variable pchk_tmp2 : time; + begin + if (rising_edge(pll_locked_tmp1)) then + if (clkinsel_in = '0') then + pchk_tmp1 := CLKIN2_PERIOD * 1100 ps; + pchk_tmp2 := CLKIN2_PERIOD * 900 ps; + if (period_avg > pchk_tmp1 or period_avg < pchk_tmp2) then + assert false report "Warning : input CLKIN2 period and attribute CLKIN2_PERIOD are not same." severity warning ; + end if; + else + pchk_tmp1 := CLKIN1_PERIOD * 1100 ps; + pchk_tmp2 := CLKIN1_PERIOD * 900 ps; + if (period_avg > pchk_tmp1 or period_avg < pchk_tmp2) then + assert false report "Warning : input CLKIN1 period and attribute CLKIN1_PERIOD are not same." severity warning ; + end if; + end if; + end if; + end process; + + locked_out_tmp_p : process + begin + if (rising_edge(rst_in)) then + wait for 1 ns; + locked_out_tmp <= '0'; + else + if (rst_in = '0') then + locked_out_tmp <= locked_out; + else + locked_out_tmp <= '0'; + end if; + end if; + wait on rst_in, locked_out; + end process; + + + clkout_en1_p : process (clkout_en0_tmp , rst_in) + begin + if (rst_in = '1') then + clkout_en1 <= '0'; + else + clkout_en1 <= transport clkout_en0_tmp after clkvco_delay; + end if; + end process; + + clkout_en_p : process (clkout_en1, rst_in) + begin + if (rst_in = '1') then + clkout_en <= '0'; + else + clkout_en <= clkout_en1; + end if; + end process; + + CLK_PERIOD_AVG_P : process (clkin_period(0), clkin_period(1), clkin_period(2), + clkin_period(3), clkin_period(4), period_avg) + variable period_avg_tmp : time := 0 ps; + variable clkin_period_tmp0 : time := 0 ps; + variable clkin_period_tmp1 : time := 0 ps; + variable clkin_period_tmp_t : time := 0 ps; + begin + clkin_period_tmp0 := clkin_period(0); + clkin_period_tmp1 := clkin_period(1); + if (clkin_period_tmp0 > clkin_period_tmp1) then + clkin_period_tmp_t := clkin_period_tmp0 - clkin_period_tmp1; + else + clkin_period_tmp_t := clkin_period_tmp1 - clkin_period_tmp0; + end if; + + if (clkin_period_tmp0 /= period_avg and (clkin_period_tmp0 < 1.5 * period_avg or clkin_period_tmp_t <= 300 ps)) then + period_avg_tmp := (clkin_period(0) + clkin_period(1) + clkin_period(2) + + clkin_period(3) + clkin_period(4))/5.0; + period_avg <= period_avg_tmp; + end if; + end process; + + process (period_avg, lock_period, rst_in) + variable p_c0 : time; + variable p_c0i : integer; + variable p_c0_dr : integer; + variable p_c0_dri : time; + variable p_c0_dri1 : integer; + variable p_c0_dri2 : integer; + variable p_c1 : time; + variable p_c1i : integer; + variable p_c1_dr : integer; + variable p_c1_dri : time; + variable p_c1_dri1 : integer; + variable p_c1_dri2 : integer; + variable p_c2 : time; + variable p_c2i : integer; + variable p_c2_dr : integer; + variable p_c2_dri : time; + variable p_c2_dri1 : integer; + variable p_c2_dri2 : integer; + variable p_c3 : time; + variable p_c3i : integer; + variable p_c3_dr : integer; + variable p_c3_dri : time; + variable p_c3_dri1 : integer; + variable p_c3_dri2 : integer; + variable p_c4 : time; + variable p_c4i : integer; + variable p_c4_dr : integer; + variable p_c4_dri : time; + variable p_c4_dri1 : integer; + variable p_c4_dri2 : integer; + variable p_c5 : time; + variable p_c5i : integer; + variable p_c5_dr : integer; + variable p_c5_dri : time; + variable p_c5_dri1 : integer; + variable p_c5_dri2 : integer; + variable p_c6 : time; + variable p_c6i : integer; + variable p_c6_dr : integer; + variable p_c6_dri : time; + variable p_c6_dri1 : integer; + variable p_c6_dri2 : integer; + variable period_fbi : integer; + variable period_fb_tmp : time; + variable fb_delayi : integer; + variable clkvco_delay_tmp : time; + variable clkvco_delayi : integer; + variable fb_delaym : integer; + variable dly_tmp : time; + variable dly_tmpi : integer; + variable clkfbm1_dly_tmp : time; + variable period_vco_tmp : time; + begin + if (rst_in = '1') then + p_fb <= 0 ps; + p_fb_h <= 0 ps; + p_fb_r <= 0 ps; + p_fb_r1 <= 0 ps; + p_fb_d <= 0 ps; + p_c0 := 0 ps; + p_c0_h <= 0 ps; + p_c0_r <= 0 ps; + p_c0_r1 <= 0 ps; + p_c0_d <= 0 ps; + p_c1 := 0 ps; + p_c1_h <= 0 ps; + p_c1_r <= 0 ps; + p_c1_r1 <= 0 ps; + p_c1_d <= 0 ps; + p_c2 := 0 ps; + p_c2_h <= 0 ps; + p_c2_r <= 0 ps; + p_c2_r1 <= 0 ps; + p_c2_d <= 0 ps; + p_c3 := 0 ps; + p_c3_h <= 0 ps; + p_c3_r <= 0 ps; + p_c3_r1 <= 0 ps; + p_c3_d <= 0 ps; + p_c4 := 0 ps; + p_c4_h <= 0 ps; + p_c4_r <= 0 ps; + p_c4_r1 <= 0 ps; + p_c4_d <= 0 ps; + p_c5 := 0 ps; + p_c5_h <= 0 ps; + p_c5_r <= 0 ps; + p_c5_r1 <= 0 ps; + p_c5_d <= 0 ps; + p_c6 := 0 ps; + p_c6_h <= 0 ps; + p_c6_r <= 0 ps; + p_c6_r1 <= 0 ps; + p_c6_d <= 0 ps; + clkvco_delay <= 0 ps; + dly_tmp := 0 ps; + period_fb <= 0 ps; + period_vco <= 0 ps; + clkfbm1_dly <= 0 ps; + p_c0_dr := 0; + p_c1_dr := 0 ; + p_c2_dr := 0; + p_c3_dr := 0; + p_c4_dr := 0; + p_c5_dr := 0; + p_c6_dr := 0; + else + if (period_avg > 0 ps and lock_period = '1') then + fb_delayi := fb_delay / 1 ps; + period_fb_tmp := period_avg * DIVCLK_DIVIDE; + period_fbi := period_fb_tmp / 1 ps; + period_fb <= period_fb_tmp; + period_vco_tmp := period_fb_tmp / CLKFBOUT_MULT_F; + period_vco <= period_vco_tmp; + clkfbm1_dly_tmp := ((CLKFBOUT_PHASE * period_fb_tmp) / 360.0); + clkfbm1_dly <= clkfbm1_dly_tmp; + dly_tmp := fb_delay + clkfbm1_dly_tmp; + dly_tmpi := dly_tmp / 1 ps; + if (dly_tmp = 0 ps) then + clkvco_delay_tmp := 0 ps; + elsif ( dly_tmp <= period_fb_tmp ) then + clkvco_delay_tmp := period_fb_tmp - dly_tmp; + else + clkvco_delay_tmp := period_fb_tmp - ((dly_tmpi mod( period_fbi)) * 1 ps) ; + end if; + clkvco_delay <= clkvco_delay_tmp; + clkvco_delayi := clkvco_delay_tmp / 1 ps; + p_fb <= period_fb_tmp; + p_fb_h <= period_fb_tmp / 2; + p_fb_r <= period_fb_tmp - period_fb_tmp / 2; + p_fb_r1 <= period_fb_tmp - period_fb_tmp / 2 - 1 ps; + fb_delaym := fb_delayi mod (period_fbi); + if ( fb_delay <= period_fb_tmp) then + p_fb_d <= period_fb_tmp - fb_delay; + else + p_fb_d <= period_fb_tmp - fb_delaym * 1 ps; + end if; + p_c0 := (period_fb_tmp * CLKOUT0_DIVIDE_F) / CLKFBOUT_MULT_F; + p_c0i := p_c0 / 1 ps; + p_c0_h <= p_c0 * CLKOUT0_DUTY_CYCLE; + p_c0_r <= p_c0 - p_c0 * CLKOUT0_DUTY_CYCLE; + p_c0_r1 <= p_c0 - p_c0 * CLKOUT0_DUTY_CYCLE - 1 ps; + p_c0_dri := ((CLKOUT0_PHASE * p_c0) / 360.0); + p_c0_dri1 := (p_c0_dri / 1 ps); + p_c0_dri2 := (clkvco_delayi mod p_c0i); + p_c0_dr := p_c0_dri1 + p_c0_dri2; + if (p_c0_dr < 0 ) then + p_c0_d <= p_c0 + (p_c0_dr mod p_c0i) * 1 ps; + else + p_c0_d <= (p_c0_dr mod p_c0i ) * 1 ps; + end if; + + + p_c1 := (period_fb_tmp * CLKOUT1_DIVIDE) / CLKFBOUT_MULT_F; + p_c1i := p_c1 / 1 ps; + p_c1_h <= p_c1 * CLKOUT1_DUTY_CYCLE; + p_c1_r <= p_c1 - p_c1 * CLKOUT1_DUTY_CYCLE; + p_c1_r1 <= p_c1 - p_c1 * CLKOUT1_DUTY_CYCLE - 1 ps; + p_c1_dri := ((CLKOUT1_PHASE * p_c1) / 360.0); + p_c1_dri1 := (p_c1_dri / 1 ps); + p_c1_dri2 := (clkvco_delayi mod p_c1i); + p_c1_dr := p_c1_dri1 + p_c1_dri2; + if (p_c1_dr < 0 ) then + p_c1_d <= p_c1 + (p_c1_dr mod p_c1i) * 1 ps; + else + p_c1_d <= (p_c1_dr mod p_c1i ) * 1 ps; + end if; + + p_c2 := (period_fb_tmp * CLKOUT2_DIVIDE) / CLKFBOUT_MULT_F; + p_c2i := p_c2 / 1 ps; + p_c2_h <= p_c2 * CLKOUT2_DUTY_CYCLE; + p_c2_r <= p_c2 - p_c2 * CLKOUT2_DUTY_CYCLE; + p_c2_r1 <= p_c2 - p_c2 * CLKOUT2_DUTY_CYCLE - 1 ps; + p_c2_dri := ((CLKOUT2_PHASE * p_c2) / 360.0); + p_c2_dri1 := (p_c2_dri / 1 ps); + p_c2_dri2 := (clkvco_delayi mod p_c2i); + p_c2_dr := p_c2_dri1 + p_c2_dri2; + if (p_c2_dr < 0 ) then + p_c2_d <= p_c2 + (p_c2_dr mod p_c2i) * 1 ps; + else + p_c2_d <= (p_c2_dr mod p_c2i ) * 1 ps; + end if; + + p_c3 := (period_fb_tmp * CLKOUT3_DIVIDE) / CLKFBOUT_MULT_F; + p_c3i := p_c3 / 1 ps; + p_c3_h <= p_c3 * CLKOUT3_DUTY_CYCLE; + p_c3_r <= p_c3 - p_c3 * CLKOUT3_DUTY_CYCLE; + p_c3_r1 <= p_c3 - p_c3 * CLKOUT3_DUTY_CYCLE - 1 ps; + p_c3_dri := ((CLKOUT3_PHASE * p_c3) / 360.0); + p_c3_dri1 := (p_c3_dri / 1 ps); + p_c3_dri2 := (clkvco_delayi mod p_c3i); + p_c3_dr := p_c3_dri1 + p_c3_dri2; + if (p_c3_dr < 0 ) then + p_c3_d <= p_c3 + (p_c3_dr mod p_c3i) * 1 ps; + else + p_c3_d <= (p_c3_dr mod p_c3i ) * 1 ps; + end if; + + p_c4 := (period_fb_tmp * CLKOUT4_DIVIDE) / CLKFBOUT_MULT_F; + p_c4i := p_c4 / 1 ps; + p_c4_h <= p_c4 * CLKOUT4_DUTY_CYCLE; + p_c4_r <= p_c4 - p_c4 * CLKOUT4_DUTY_CYCLE; + p_c4_r1 <= p_c4 - p_c4 * CLKOUT4_DUTY_CYCLE - 1 ps; + p_c4_dri := ((CLKOUT4_PHASE * p_c4) / 360.0); + p_c4_dri1 := (p_c4_dri / 1 ps); + p_c4_dri2 := (clkvco_delayi mod p_c4i); + p_c4_dr := p_c4_dri1 + p_c4_dri2; + if (p_c4_dr < 0 ) then + p_c4_d <= p_c4 + (p_c4_dr mod p_c4i) * 1 ps; + else + p_c4_d <= (p_c4_dr mod p_c4i ) * 1 ps; + end if; + + p_c5 := (period_fb_tmp * CLKOUT5_DIVIDE) / CLKFBOUT_MULT_F; + p_c5i := p_c5 / 1 ps; + p_c5_h <= p_c5 * CLKOUT5_DUTY_CYCLE; + p_c5_r <= p_c5 - p_c5 * CLKOUT5_DUTY_CYCLE; + p_c5_r1 <= p_c5 - p_c5 * CLKOUT5_DUTY_CYCLE - 1 ps; + p_c5_dri := ((CLKOUT5_PHASE * p_c5) / 360.0); + p_c5_dri1 := (p_c5_dri / 1 ps); + p_c5_dri2 := (clkvco_delayi mod p_c5i); + p_c5_dr := p_c5_dri1 + p_c5_dri2; + if (p_c5_dr < 0 ) then + p_c5_d <= p_c5 + (p_c5_dr mod p_c5i) * 1 ps; + else + p_c5_d <= (p_c5_dr mod p_c5i ) * 1 ps; + end if; + + p_c6 := (period_fb_tmp * CLKOUT6_DIVIDE) / CLKFBOUT_MULT_F; + p_c6i := p_c6 / 1 ps; + p_c6_h <= p_c6 * CLKOUT6_DUTY_CYCLE; + p_c6_r <= p_c6 - p_c6 * CLKOUT6_DUTY_CYCLE; + p_c6_r1 <= p_c6 - p_c6 * CLKOUT6_DUTY_CYCLE - 1 ps; + p_c6_dri := ((CLKOUT6_PHASE * p_c6) / 360.0); + p_c6_dri1 := (p_c6_dri / 1 ps); + p_c6_dri2 := (clkvco_delayi mod p_c6i); + p_c6_dr := p_c6_dri1 + p_c6_dri2; + if (p_c6_dr < 0 ) then + p_c6_d <= p_c6 + (p_c6_dr mod p_c6i) * 1 ps; + else + p_c6_d <= (p_c6_dr mod p_c6i ) * 1 ps; + end if; + end if; + end if; + end process; + + process (clkout_en, rst_in) begin + if (rst_in = '1') then + clk0ps_en <= '0'; + clk1ps_en <= '0'; + clk2ps_en <= '0'; + clk3ps_en <= '0'; + clk4ps_en <= '0'; + clk5ps_en <= '0'; + clk6ps_en <= '0'; + clkfbm1ps_en <= '0'; + elsif (rising_edge(clkout_en)) then + clk0ps_en <= '1' after p_c0_d; + clk1ps_en <= '1' after p_c1_d; + clk2ps_en <= '1' after p_c2_d; + clk3ps_en <= '1' after p_c3_d; + clk4ps_en <= '1' after p_c4_d; + clk5ps_en <= '1' after p_c5_d; + clk6ps_en <= '1' after p_c6_d; + clkfbm1ps_en <= '1' after p_fb_d; + end if; + end process; + + process (clkpll_r, rst_in) begin + if (rst_in = '1') then + clk0_cnt <= 0; + clk1_cnt <= 0; + clk2_cnt <= 0; + clk3_cnt <= 0; + clk4_cnt <= 0; + clk5_cnt <= 0; + clk6_cnt <= 0; + clkfb_cnt <= 0; + clk0_gen <= '0'; + clk1_gen <= '0'; + clk2_gen <= '0'; + clk3_gen <= '0'; + clk4_gen <= '0'; + clk5_gen <= '0'; + clk6_gen <= '0'; + clkfb_gen <= '0'; + elsif (rising_edge (clkpll_r)) then + if (clkout_en0_tmp = '1' ) then + if (clk0_cnt < clk0_val2 ) then + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 0; + end if; + + if (clk0_cnt >= clk0_val ) then + clk0_gen <= '0'; + else + clk0_gen <= '1'; + end if; + else + clk0_cnt <= 0; + clk0_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk1_cnt < clk1_val2 ) then + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 0; + end if; + + if (clk1_cnt >= clk1_val ) then + clk1_gen <= '0'; + else + clk1_gen <= '1'; + end if; + else + clk1_cnt <= 0; + clk1_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk2_cnt < clk2_val2 ) then + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 0; + end if; + + if (clk2_cnt >= clk2_val ) then + clk2_gen <= '0'; + else + clk2_gen <= '1'; + end if; + else + clk2_cnt <= 0; + clk2_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk3_cnt < clk3_val2) then + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 0; + end if; + + if (clk3_cnt >= clk3_val ) then + clk3_gen <= '0'; + else + clk3_gen <= '1'; + end if; + else + clk3_cnt <= 0; + clk3_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk4_cnt < clk4_val2 ) then + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 0; + end if; + + if (clk4_cnt >= clk4_val ) then + clk4_gen <= '0'; + else + clk4_gen <= '1'; + end if; + else + clk4_cnt <= 0; + clk4_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk5_cnt < clk5_val2) then + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 0; + end if; + + if (clk5_cnt >= clk5_val ) then + clk5_gen <= '0'; + else + clk5_gen <= '1'; + end if; + else + clk5_cnt <= 0; + clk5_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk6_cnt < clk6_val2) then + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 0; + end if; + + if (clk6_cnt >= clk6_val ) then + clk6_gen <= '0'; + else + clk6_gen <= '1'; + end if; + else + clk6_cnt <= 0; + clk6_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clkfb_cnt < clkfb_val2 ) then + clkfb_cnt <= clkfb_cnt + 1; + else + clkfb_cnt <= 0; + end if; + + if (clkfb_cnt >= clkfb_val) then + clkfb_gen <= '0'; + else + clkfb_gen <= '1'; + end if; + else + clkfb_cnt <= 0; + clkfb_gen <= '0'; + end if; + end if; + end process; + + process (clk0_gen, rst_in) begin + if (rst_in = '1') then + clk0_gen_f <= '0'; + else + clk0_gen_f <= clk0_gen after p_c0_d; + end if; + end process; + + process (clk1_gen, rst_in) begin + if (rst_in = '1') then + clk1_gen_f <= '0'; + else + clk1_gen_f <= clk1_gen after p_c1_d; + end if; + end process; + + process (clk2_gen, rst_in) begin + if (rst_in = '1') then + clk2_gen_f <= '0'; + else + clk2_gen_f <= clk2_gen after p_c2_d; + end if; + end process; + + process (clk3_gen, rst_in) begin + if (rst_in = '1') then + clk3_gen_f <= '0'; + else + clk3_gen_f <= clk3_gen after p_c3_d; + end if; + end process; + + process (clk4_gen, rst_in) begin + if (rst_in = '1') then + clk4_gen_f <= '0'; + else + clk4_gen_f <= clk4_gen after p_c4_d; + end if; + end process; + + process (clk5_gen, rst_in) begin + if (rst_in = '1') then + clk5_gen_f <= '0'; + else + clk5_gen_f <= clk5_gen after p_c5_d; + end if; + end process; + + process (clk6_gen, rst_in) begin + if (rst_in = '1') then + clk6_gen_f <= '0'; + else + clk6_gen_f <= clk6_gen after p_c6_d; + end if; + end process; + + process (clkfb_gen, rst_in) begin + if (rst_in = '1') then + clkfb_gen_f <= '0'; + else + clkfb_gen_f <= clkfb_gen after p_fb_d; + end if; + end process; + + process begin + if (rst_in = '1') then + clk0_out <= '0'; + elsif (rising_edge(clk0_gen_f) or falling_edge(clk0_gen_f)) then + if (clk0ps_en = '1' ) then + if ( clk0_val1 = 1) then + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r1; + else + for i0 in 1 to clk0_val11 loop + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r; + end loop; + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r1; + end if; + else + clk0_out <= '0'; + end if; + end if; + wait on clk0_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk1_out <= '0'; + elsif (rising_edge(clk1_gen_f) or falling_edge(clk1_gen_f)) then + if (clk1ps_en = '1' ) then + if ( clk1_val1 = 1) then + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r1; + else + for i1 in 1 to clk1_val11 loop + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r; + end loop; + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r1; + end if; + else + clk1_out <= '0'; + end if; + end if; + wait on clk1_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk2_out <= '0'; + elsif (rising_edge(clk2_gen_f) or falling_edge(clk2_gen_f)) then + if (clk2ps_en = '1' ) then + if ( clk2_val1 = 1) then + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r1; + else + for i2 in 1 to clk2_val11 loop + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r; + end loop; + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r1; + end if; + else + clk2_out <= '0'; + end if; + end if; + wait on clk2_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk3_out <= '0'; + elsif (rising_edge(clk3_gen_f) or falling_edge(clk3_gen_f)) then + if (clk3ps_en = '1' ) then + if ( clk3_val1 = 1) then + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r1; + else + for i3 in 1 to clk3_val11 loop + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r; + end loop; + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r1; + end if; + else + clk3_out <= '0'; + end if; + end if; + wait on clk3_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk4_out <= '0'; + elsif (rising_edge(clk4_gen_f) or falling_edge(clk4_gen_f)) then + if (clk4ps_en = '1' ) then + if ( clk4_val1 = 1) then + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r1; + else + for i4 in 1 to clk4_val11 loop + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r; + end loop; + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r1; + end if; + else + clk4_out <= '0'; + end if; + end if; + wait on clk4_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk5_out <= '0'; + elsif (rising_edge(clk5_gen_f) or falling_edge(clk5_gen_f)) then + if (clk5ps_en = '1' ) then + if ( clk5_val1 = 1) then + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r1; + else + for i5 in 1 to clk5_val11 loop + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r; + end loop; + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r1; + end if; + else + clk5_out <= '0'; + end if; + end if; + wait on clk5_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk6_out <= '0'; + elsif (rising_edge(clk6_gen_f) or falling_edge(clk6_gen_f)) then + if (clk6ps_en = '1' ) then + if ( clk6_val1 = 1) then + clk6_out <= '1'; + wait for p_c6_h; + clk6_out <= '0'; + wait for p_c6_r1; + else + for i6 in 1 to clk6_val11 loop + clk6_out <= '1'; + wait for p_c6_h; + clk6_out <= '0'; + wait for p_c6_r; + end loop; + clk6_out <= '1'; + wait for p_c6_h; + clk6_out <= '0'; + wait for p_c6_r1; + end if; + else + clk6_out <= '0'; + end if; + end if; + wait on clk6_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clkfbm1_out <= '0'; + elsif (rising_edge(clkfb_gen_f) or falling_edge(clkfb_gen_f)) then + if (clkfbm1ps_en = '1' ) then + if (clkfb_val1 = 1) then + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r1; + else + for ib in 1 to clkfb_val11 loop + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r; + end loop; + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r1; + end if; + else + clkfbm1_out <= '0'; + end if; + end if; + wait on clkfb_gen_f, rst_in; + end process; + + clkout0_out <= transport clk0_out when fb_delay_found = '1' else clkfb_tst; + clkout1_out <= transport clk1_out when fb_delay_found = '1' else clkfb_tst; + clkout2_out <= transport clk2_out when fb_delay_found = '1' else clkfb_tst; + clkout3_out <= transport clk3_out when fb_delay_found = '1' else clkfb_tst; + clkout4_out <= transport clk4_out when fb_delay_found = '1' else clkfb_tst; + clkout5_out <= transport clk5_out when fb_delay_found = '1' else clkfb_tst; + clkout6_out <= transport clk6_out when fb_delay_found = '1' else clkfb_tst; + clkfb_out <= transport clkfbm1_out when fb_delay_found = '1' else clkfb_tst; + + CLKFB_TST_P : process (clkpll_r, rst_in) + begin + if (rst_in = '1') then + clkfb_tst <= '0'; + elsif (rising_edge(clkpll_r)) then + if (fb_delay_found_tmp = '0' and pwron_int = '0') then + clkfb_tst <= '1'; + else + clkfb_tst <= '0'; + end if; + end if; + end process; + + FB_DELAY_CAL_P0 : process (clkfb_tst, rst_in) + begin + if (rst_in = '1') then + delay_edge <= 0 ps; + elsif (rising_edge(clkfb_tst)) then + delay_edge <= NOW; + end if; + end process; + + FB_DELAY_CAL_P : process (clkfb_in, rst_in) + variable delay_edge1 : time := 0 ps; + variable fb_delay_tmp : time := 0 ps; + variable Message : line; + begin + if (rst_in = '1') then + fb_delay <= 0 ps; + fb_delay_found_tmp <= '0'; + delay_edge1 := 0 ps; + fb_delay_tmp := 0 ps; + elsif (clkfb_in'event and clkfb_in = '1') then + if (fb_delay_found_tmp = '0') then + if (delay_edge /= 0 ps) then + delay_edge1 := NOW; + fb_delay_tmp := delay_edge1 - delay_edge; + else + fb_delay_tmp := 0 ps; + end if; + fb_delay <= fb_delay_tmp; + fb_delay_found_tmp <= '1'; + if (rst_in = '0' and (fb_delay_tmp > fb_delay_max)) then + Write ( Message, string'(" Warning : The feedback delay is ")); + Write ( Message, fb_delay_tmp); + Write ( Message, string'(". It is over the maximun value ")); + Write ( Message, fb_delay_max); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + end if; + end process; + + fb_delay_found_P : process(fb_delay_found_tmp, clkvco_delay, rst_in) + begin + if (rst_in = '1') then + fb_delay_found <= '0'; + elsif (clkvco_delay = 0 ps) then + fb_delay_found <= fb_delay_found_tmp after 1 ns; + else + fb_delay_found <= fb_delay_found_tmp after clkvco_delay; + end if; + end process; + +end MMCME2_ADV_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/PLLE2_ADV.vhd b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/PLLE2_ADV.vhd new file mode 100644 index 0000000..b070548 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/PLLE2_ADV.vhd @@ -0,0 +1,1601 @@ +-- Copyright (c) 1995/2010 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------/ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.i (O.xx) +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Phase Lock Loop Clock +-- /___/ /\ Filename : PLLE2_ADV.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 10/17/11 - Initial version. +-- End Revision + +----- CELL PLLE2_ADV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.NUMERIC_STD.all; +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity PLLE2_ADV is +generic ( + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_MULT : integer := 5; + CLKFBOUT_PHASE : real := 0.0; + CLKIN1_PERIOD : real := 0.0; + CLKIN2_PERIOD : real := 0.0; + CLKOUT0_DIVIDE : integer := 1; + CLKOUT0_DUTY_CYCLE : real := 0.5; + CLKOUT0_PHASE : real := 0.0; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.5; + CLKOUT1_PHASE : real := 0.0; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.5; + CLKOUT2_PHASE : real := 0.0; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.5; + CLKOUT3_PHASE : real := 0.0; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.5; + CLKOUT4_PHASE : real := 0.0; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.5; + CLKOUT5_PHASE : real := 0.0; + COMPENSATION : string := "ZHOLD"; + DIVCLK_DIVIDE : integer := 1; + IS_CLKINSEL_INVERTED : bit := '0'; + IS_PWRDWN_INVERTED : bit := '0'; + IS_RST_INVERTED : bit := '0'; + REF_JITTER1 : real := 0.0; + REF_JITTER2 : real := 0.0; + STARTUP_WAIT : string := "FALSE" + ); +port ( + CLKFBOUT : out std_ulogic := '0'; + CLKOUT0 : out std_ulogic := '0'; + CLKOUT1 : out std_ulogic := '0'; + CLKOUT2 : out std_ulogic := '0'; + CLKOUT3 : out std_ulogic := '0'; + CLKOUT4 : out std_ulogic := '0'; + CLKOUT5 : out std_ulogic := '0'; + DO : out std_logic_vector (15 downto 0); + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFBIN : in std_ulogic; + CLKIN1 : in std_ulogic; + CLKIN2 : in std_ulogic; + CLKINSEL : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + PWRDWN : in std_ulogic; + RST : in std_ulogic + ); +end PLLE2_ADV; + + +-- Architecture body -- + +architecture PLLE2_ADV_V of PLLE2_ADV is + + function real2int( real_in : in real) return integer is + variable int_value : integer; + variable int_value1 : integer; + variable tmps : time := 1 ps; + variable tmps1 : real; + + begin + if (real_in < 1.00000 and real_in > -1.00000) then + int_value1 := 0; + else + tmps := real_in * 1 ns; + int_value := tmps / 1 ns; + tmps1 := real (int_value); + if ( tmps1 > real_in) then + int_value1 := int_value - 1 ; + else + int_value1 := int_value; + end if; + end if; + return int_value1; + end real2int; + + function clkout_duty_chk (CLKOUT_DIVIDE : in integer; + CLKOUT_DUTY_CYCLE : in real; + CLKOUT_DUTY_CYCLE_N : in string) + return std_ulogic is + constant O_MAX_HT_LT_real : real := 64.0; + variable CLKOUT_DIVIDE_real : real; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MIN_rnd : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable clk_duty_tmp_int : integer; + variable duty_cycle_valid : std_ulogic; + variable tmp_duty_value : real; + variable tmp_j : real; + variable Message : line; + variable step_round_tmp : integer; + variable step_round_tmp1 : real; + + begin + CLKOUT_DIVIDE_real := real(CLKOUT_DIVIDE); + step_round_tmp := 1000 /CLKOUT_DIVIDE; + step_round_tmp1 := real(step_round_tmp); + if (CLKOUT_DIVIDE_real > O_MAX_HT_LT_real) then + CLK_DUTY_CYCLE_MIN := (CLKOUT_DIVIDE_real - O_MAX_HT_LT_real)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MAX := (O_MAX_HT_LT_real + 0.5)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MIN_rnd := CLK_DUTY_CYCLE_MIN; + else + if (CLKOUT_DIVIDE = 1) then + CLK_DUTY_CYCLE_MIN_rnd := 0.0; + CLK_DUTY_CYCLE_MIN := 0.0; + else + CLK_DUTY_CYCLE_MIN_rnd := step_round_tmp1 / 1000.00; + CLK_DUTY_CYCLE_MIN := 1.0 / CLKOUT_DIVIDE_real; + end if; + CLK_DUTY_CYCLE_MAX := 1.0; + end if; + + if ((CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX) or (CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd)) then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" is set to ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" and is not in the allowed range ")); + Write ( Message, CLK_DUTY_CYCLE_MIN); + Write ( Message, string'(" to ")); + Write ( Message, CLK_DUTY_CYCLE_MAX); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + CLK_DUTY_CYCLE_STEP := 0.5 / CLKOUT_DIVIDE_real; + tmp_j := 0.0; + duty_cycle_valid := '0'; + clk_duty_tmp_int := 0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if (abs(tmp_duty_value - CLKOUT_DUTY_CYCLE) < 0.001 and (tmp_duty_value <= CLK_DUTY_CYCLE_MAX)) then + duty_cycle_valid := '1'; + end if; + tmp_j := tmp_j + 1.0; + end loop; + + if (duty_cycle_valid /= '1') then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" = ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" which is not an allowed value. Allowed value s are: ")); + Write ( Message, LF ); + tmp_j := 0.0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if ( (tmp_duty_value <= CLK_DUTY_CYCLE_MAX) and (tmp_duty_value < 1.0)) then + Write ( Message, tmp_duty_value); + Write ( Message, LF ); + end if; + tmp_j := tmp_j + 1.0; + end loop; + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + return duty_cycle_valid; + end function clkout_duty_chk; + + constant VCOCLK_FREQ_MAX : real := 2133.0; + constant VCOCLK_FREQ_MIN : real := 800.0; + constant CLKIN_FREQ_MAX : real := 1066.0; + constant CLKIN_FREQ_MIN : real := 19.0; + constant CLKPFD_FREQ_MAX : real := 550.0; + constant CLKPFD_FREQ_MIN : real := 19.0; + constant VCOCLK_FREQ_TARGET : real := 1200.0; + constant O_MAX_HT_LT : integer := 64; + constant REF_CLK_JITTER_MAX : time := 1000 ps; + constant REF_CLK_JITTER_SCALE : real := 0.1; + constant MAX_FEEDBACK_DELAY : time := 10 ns; + constant MAX_FEEDBACK_DELAY_SCALE : real := 1.0; + constant M_MAX : real := 64.000; + constant M_MIN : real := 2.000; + constant D_MAX : integer := 80; + constant D_MIN : integer := 1; + + signal pwrdwn_in1 : std_ulogic := '0'; + signal rst_input : std_ulogic := '0'; + signal init_done : std_ulogic := '0'; + signal clkpll_r : std_ulogic := '0'; + signal locked_out_tmp : std_ulogic := '0'; + signal clkfb_div_fint : integer := 0; + signal clkfb_val : integer := 0; + signal clkfb_val1 : integer := 0; + signal clkfb_val11 : integer := 0; + signal clkfb_val2 : integer := 0; + signal clk0_val : integer := 0; + signal clk0_val1 : integer := 0; + signal clk0_val11 : integer := 0; + signal clk1_val11 : integer := 0; + signal clk2_val11 : integer := 0; + signal clk3_val11 : integer := 0; + signal clk4_val11 : integer := 0; + signal clk5_val11 : integer := 0; + signal clk0_val2 : integer := 0; + signal clk1_val2 : integer := 0; + signal clk2_val2 : integer := 0; + signal clk3_val2 : integer := 0; + signal clk4_val2 : integer := 0; + signal clk5_val2 : integer := 0; + signal clk1_val : integer := 0; + signal clk1_val1 : integer := 0; + signal clk2_val : integer := 0; + signal clk2_val1 : integer := 0; + signal clk3_val : integer := 0; + signal clk3_val1 : integer := 0; + signal clk4_val : integer := 0; + signal clk4_val1 : integer := 0; + signal clk5_val : integer := 0; + signal clk5_val1 : integer := 0; + signal chk_ok : std_ulogic := '0'; + constant period_vco_target : time := 1000 ps / VCOCLK_FREQ_TARGET; + constant fb_delay_max : time := MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + signal pll_lock_time : integer := 0; + signal clkfb_out : std_ulogic := '0'; + signal clkout0_out : std_ulogic := '0'; + signal clkout1_out : std_ulogic := '0'; + signal clkout2_out : std_ulogic := '0'; + signal clkout3_out : std_ulogic := '0'; + signal clkout4_out : std_ulogic := '0'; + signal clkout5_out : std_ulogic := '0'; + signal p_fb : time := 0 ps; + signal p_fb_h : time := 0 ps; + signal p_fb_r : time := 0 ps; + signal p_fb_r1 : time := 0 ps; + signal p_fb_d : time := 0 ps; + signal p_c0_dr : time := 0 ps; + signal p_c1_dr : time := 0 ps; + signal p_c2_dr : time := 0 ps; + signal p_c3_dr : time := 0 ps; + signal p_c4_dr : time := 0 ps; + signal p_c5_dr : time := 0 ps; + signal p_c6_dr : time := 0 ps; + signal p_c0_h : time := 0 ps; + signal p_c0_r : time := 0 ps; + signal p_c0_d : time := 0 ps; + signal p_c0_r1 : time := 0 ps; + signal p_c1_r1 : time := 0 ps; + signal p_c2_r1 : time := 0 ps; + signal p_c3_r1 : time := 0 ps; + signal p_c4_r1 : time := 0 ps; + signal p_c5_r1 : time := 0 ps; + signal p_c6_r1 : time := 0 ps; + signal p_c1_h : time := 0 ps; + signal p_c1_r : time := 0 ps; + signal p_c1_d : time := 0 ps; + signal p_c2_h : time := 0 ps; + signal p_c2_r : time := 0 ps; + signal p_c2_d : time := 0 ps; + signal p_c3_h : time := 0 ps; + signal p_c3_r : time := 0 ps; + signal p_c3_d : time := 0 ps; + signal p_c4_h : time := 0 ps; + signal p_c4_r : time := 0 ps; + signal p_c4_d : time := 0 ps; + signal p_c5_h : time := 0 ps; + signal p_c5_r : time := 0 ps; + signal p_c5_d : time := 0 ps; + signal period_fb : time := 0 ps; + signal clk0_gen : std_ulogic := '0'; + signal clk1_gen : std_ulogic := '0'; + signal clk2_gen : std_ulogic := '0'; + signal clk3_gen : std_ulogic := '0'; + signal clk4_gen : std_ulogic := '0'; + signal clk5_gen : std_ulogic := '0'; + signal clkfb_gen : std_ulogic := '0'; + signal clk0_gen_f : std_ulogic := '0'; + signal clk1_gen_f : std_ulogic := '0'; + signal clk2_gen_f : std_ulogic := '0'; + signal clk3_gen_f : std_ulogic := '0'; + signal clk4_gen_f : std_ulogic := '0'; + signal clk5_gen_f : std_ulogic := '0'; + signal clkfb_gen_f : std_ulogic := '0'; + signal sample_en : std_ulogic := '1'; + signal clk0_out : std_ulogic := '0'; + signal clk1_out : std_ulogic := '0'; + signal clk2_out : std_ulogic := '0'; + signal clk3_out : std_ulogic := '0'; + signal clk4_out : std_ulogic := '0'; + signal clk5_out : std_ulogic := '0'; + signal clkfbm1_out : std_ulogic := '0'; + signal fb_delay_found_tmp : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + type real_array_usr is array (4 downto 0) of time; + signal clkin_period : real_array_usr := (others => 0 ps); + signal clkout_mux : std_logic_vector (7 downto 0) ; + signal lock_period_time : integer := 0; + signal clkout_en_time : integer := 0; + signal locked_en_time : integer := 0; + signal lock_cnt_max : integer := 0; + signal pwron_int : std_ulogic := '0'; + signal rst_in : std_ulogic := '0'; + signal pll_locked_tmp1 : std_ulogic := '0'; + signal pll_locked_tmp2 : std_ulogic := '0'; + signal lock_period : std_ulogic := '0'; + signal pll_locked_tm : std_ulogic := '0'; + signal clkin_edge : time := 0 ps; + signal fb_delay : time := 0 ps; + signal clkvco_delay : time := 0 ps; + signal clkin_lock_cnt : integer := 0; + signal clkfbm1_dly : time := 0 ps; + signal clkout_en0_tmp : std_ulogic := '0'; + signal clkout_en : std_ulogic := '0'; + signal clkout_en1 : std_ulogic := '0'; + signal locked_out : std_ulogic := '0'; + signal period_avg : time := 0 ps; + signal delay_edge : time := 0 ps; + signal clkin_period_tmp_t : integer := 0; + signal period_vco : time := 0 ps; + signal clk0ps_en : std_ulogic := '0'; + signal clk1ps_en : std_ulogic := '0'; + signal clk2ps_en : std_ulogic := '0'; + signal clk3ps_en : std_ulogic := '0'; + signal clk4ps_en : std_ulogic := '0'; + signal clk5ps_en : std_ulogic := '0'; + signal clkfbm1ps_en : std_ulogic := '0'; + signal clk0_cnt : integer := 0; + signal clk1_cnt : integer := 0; + signal clk2_cnt : integer := 0; + signal clk3_cnt : integer := 0; + signal clk4_cnt : integer := 0; + signal clk5_cnt : integer := 0; + signal clkfb_cnt : integer := 0; + signal clkfb_tst : std_ulogic := '0'; + signal clkfb_in : std_ulogic := '0'; + signal clkin1_in : std_ulogic := '0'; + signal clkin1_in_dly : std_ulogic := '0'; + signal clkin2_in : std_ulogic := '0'; + signal clkinsel_in : std_ulogic := '0'; + signal clkinsel_tmp : std_ulogic := '0'; + signal rst_input_r : std_ulogic := '0'; + signal pwrdwn_in : std_ulogic := '0'; + signal IS_CLKINSEL_INVERTED_BIN : std_ulogic := TO_X01(IS_CLKINSEL_INVERTED); + signal IS_PWRDWN_INVERTED_BIN : std_ulogic := TO_X01(IS_PWRDWN_INVERTED); + signal IS_RST_INVERTED_BIN : std_ulogic := TO_X01(IS_RST_INVERTED); + + begin + + clkin1_in <= CLKIN1; + clkin2_in <= CLKIN2; + clkfb_in <= CLKFBIN; + clkinsel_in <= '1' when (CLKINSEL xor IS_CLKINSEL_INVERTED_BIN) /= '0' else '0'; + rst_input_r <= RST xor IS_RST_INVERTED_BIN; + pwrdwn_in <= PWRDWN xor IS_PWRDWN_INVERTED_BIN; + LOCKED <= locked_out_tmp; + CLKOUT0 <= clkout0_out; + CLKOUT1 <= clkout1_out; + CLKOUT2 <= clkout2_out; + CLKOUT3 <= clkout3_out; + CLKOUT4 <= clkout4_out; + CLKOUT5 <= clkout5_out; + CLKFBOUT <= clkfb_out; + DO <= "0000000000000000"; + + INIPROC : process + variable Message : line; + variable con_line : line; + variable tmpvalue : real; + variable chk_ok : std_ulogic; + variable tmp_string : string(1 to 18); + variable skipspace : character; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable O_MAX_HT_LT_real : real; + variable duty_cycle_valid : std_ulogic; + variable CLKOUT0_DIVIDE_real : real; + variable CLKOUT1_DIVIDE_real : real; + variable CLKOUT2_DIVIDE_real : real; + variable CLKOUT3_DIVIDE_real : real; + variable CLKOUT4_DIVIDE_real : real; + variable CLKOUT5_DIVIDE_real : real; + variable tmp_j : real; + variable tmp_duty_value : real; + variable clk_nocnt_i : std_ulogic; + variable clk_edge_i : std_ulogic; + variable clkfbm1_f_div_v : real := 1.0; + variable clkfb_div_fint_v : integer := 1; + variable clkfb_div_fint_v_tmp : integer := 1; + variable clkfb_div_fint_v1 : real := 1.0; + variable clkout_en_time_i : integer; + variable clkout_en_time_i1 : integer := 0; + variable clk0_val1_tmp : integer := 0; + variable clk1_val1_tmp : integer := 0; + variable clk2_val1_tmp : integer := 0; + variable clk3_val1_tmp : integer := 0; + variable clk4_val1_tmp : integer := 0; + variable clk5_val1_tmp : integer := 0; + begin + if((COMPENSATION /= "ZHOLD") and (COMPENSATION /= "zhold") and + (COMPENSATION /= "BUF_IN") and (COMPENSATION /= "buf_in") and + (COMPENSATION /= "EXTERNAL") and (COMPENSATION /= "external") and + (COMPENSATION /= "INTERNAL") and (COMPENSATION /= "internal")) +then + assert FALSE report " Attribute Syntax Error : The Attribute COMPENSATION must be set to ZHOLD or BUF_IN or EXTERNAL or INTERNAL." severity error; end if; + + if((BANDWIDTH /= "HIGH") and (BANDWIDTH /= "high") and + (BANDWIDTH /= "LOW") and (BANDWIDTH /= "low") and + (BANDWIDTH /= "OPTIMIZED") and (BANDWIDTH /= "optimized")) then assert FALSE report "Attribute Syntax Error : BANDWIDTH is not HIGH, LOW, OPTIMIZED." severity error; + end if; + + if((STARTUP_WAIT /= "FALSE") and (STARTUP_WAIT /= "false") and + (STARTUP_WAIT /= "TRUE") and (STARTUP_WAIT /= "true")) then + assert FALSE report "Error : STARTUP_WAIT must be set to string FALSE or TRUE." severity error; + end if; + + clkfb_div_fint_v := CLKFBOUT_MULT; + clkfb_div_fint <= clkfb_div_fint_v; + clkfb_val <= DIVCLK_DIVIDE * 8; + clkfb_val2 <= DIVCLK_DIVIDE * 8 * 2 - 1; + clkfb_val1 <= 8; + clkfb_val11 <= 7; + + clk0_val <= DIVCLK_DIVIDE * CLKOUT0_DIVIDE; + clk0_val2 <= DIVCLK_DIVIDE * CLKOUT0_DIVIDE * 2 - 1; + clk0_val1_tmp := clkfb_div_fint_v; + clk0_val1 <= clkfb_div_fint_v; + if ( clk0_val1_tmp > 1) then + clk0_val11 <= clk0_val1_tmp - 1; + end if; + clk1_val <= DIVCLK_DIVIDE * CLKOUT1_DIVIDE; + clk1_val2 <= DIVCLK_DIVIDE * CLKOUT1_DIVIDE * 2 - 1; + clk1_val1_tmp := clkfb_div_fint_v; + clk1_val1 <= clk1_val1_tmp; + if ( clk1_val1_tmp > 1) then + clk1_val11 <= clk1_val1_tmp - 1; + end if; + clk2_val <= DIVCLK_DIVIDE * CLKOUT2_DIVIDE; + clk2_val2 <= DIVCLK_DIVIDE * CLKOUT2_DIVIDE * 2 - 1; + clk2_val1_tmp := clkfb_div_fint_v; + clk2_val1 <= clk2_val1_tmp; + if ( clk2_val1_tmp > 1) then + clk2_val11 <= clk2_val1_tmp - 1; + end if; + clk3_val <= DIVCLK_DIVIDE * CLKOUT3_DIVIDE; + clk3_val2 <= DIVCLK_DIVIDE * CLKOUT3_DIVIDE * 2 - 1; + clk3_val1_tmp := clkfb_div_fint_v; + clk3_val1 <= clk3_val1_tmp; + if ( clk3_val1_tmp > 1) then + clk3_val11 <= clk3_val1_tmp - 1; + end if; + clk4_val <= DIVCLK_DIVIDE * CLKOUT4_DIVIDE; + clk4_val2 <= DIVCLK_DIVIDE * CLKOUT4_DIVIDE * 2 - 1; + clk4_val1_tmp := clkfb_div_fint_v; + clk4_val1 <= clk4_val1_tmp; + if ( clk4_val1_tmp > 1) then + clk4_val11 <= clk4_val1_tmp - 1; + end if; + clk5_val <= DIVCLK_DIVIDE * CLKOUT5_DIVIDE; + clk5_val2 <= DIVCLK_DIVIDE * CLKOUT5_DIVIDE * 2 - 1; + clk5_val1_tmp := clkfb_div_fint_v; + clk5_val1 <= clk5_val1_tmp; + if ( clk5_val1_tmp > 1) then + clk5_val11 <= clk5_val1_tmp - 1; + end if; + if (CLKOUT0_DIVIDE < 0 or CLKOUT0_DIVIDE > 128) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DIVIDE is not in range 1.000 to 128.000." severity error; + end if; + + if ((CLKOUT0_PHASE < -360.0) or (CLKOUT0_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT0_DUTY_CYCLE < 0.001) or (CLKOUT0_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT1_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT1_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT1_PHASE < -360.0) or (CLKOUT1_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT1_DUTY_CYCLE < 0.001) or (CLKOUT1_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT2_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT2_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT2_PHASE < -360.0) or (CLKOUT2_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE is not in range -360.0 to 360.0" severity error; + end if; + if ((CLKOUT2_DUTY_CYCLE < 0.001) or (CLKOUT2_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT3_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT3_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT3_PHASE < -360.0) or (CLKOUT3_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT3_DUTY_CYCLE < 0.001) or (CLKOUT3_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT4_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT4_DIVIDE is not in range 1 to 128." severity error; + end case; + + if ((CLKOUT4_PHASE < -360.0) or (CLKOUT4_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT4_DUTY_CYCLE < 0.001) or (CLKOUT4_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + case CLKOUT5_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT5_DIVIDE is not in range 1...128." severity error; + end case; + if ((CLKOUT5_PHASE < -360.0) or (CLKOUT5_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_PHASE is not in range 360.0 to 360.0" severity error; + end if; + if ((CLKOUT5_DUTY_CYCLE < 0.001) or (CLKOUT5_DUTY_CYCLE > 0.999)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_DUTY_CYCLE is not real in range 0.001 to 0.999 pecentage."severity error; + end if; + + if (CLKFBOUT_MULT < 2 or CLKFBOUT_MULT > 64) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_MULT is not in range 2 to 64." severity error; + end if; + + if ( CLKFBOUT_PHASE < -360.0 or CLKFBOUT_PHASE > 360.0 ) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + case DIVCLK_DIVIDE is + when 1 to 56 => NULL; + when others => assert FALSE report "Attribute Syntax Error : DIVCLK_DIVIDE is not in range 1 to 56." severity error; + end case; + + if ((REF_JITTER1 < 0.0) or (REF_JITTER1 > 0.999)) then + assert FALSE report "Attribute Syntax Error : REF_JITTER1 is not in range 0.0 ... 1.0." severity error; + end if; + + if ((REF_JITTER2 < 0.0) or (REF_JITTER2 > 0.999)) then + assert FALSE report "Attribute Syntax Error : REF_JITTER2 is not in range 0.0 ... 1.0." severity error; + end if; + + O_MAX_HT_LT_real := real(O_MAX_HT_LT); + CLKOUT0_DIVIDE_real := real(CLKOUT0_DIVIDE); + CLKOUT1_DIVIDE_real := real(CLKOUT1_DIVIDE); + CLKOUT2_DIVIDE_real := real(CLKOUT2_DIVIDE); + CLKOUT3_DIVIDE_real := real(CLKOUT3_DIVIDE); + CLKOUT4_DIVIDE_real := real(CLKOUT4_DIVIDE); + CLKOUT5_DIVIDE_real := real(CLKOUT5_DIVIDE); + + if (CLKOUT0_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, "CLKOUT0_DUTY_CYCLE"); + end if; + if (CLKOUT5_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, "CLKOUT5_DUTY_CYCLE"); + end if; + if (CLKOUT1_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, "CLKOUT1_DUTY_CYCLE"); + end if; + if (CLKOUT2_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, "CLKOUT2_DUTY_CYCLE"); + end if; + if (CLKOUT3_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, "CLKOUT3_DUTY_CYCLE"); + end if; + if (CLKOUT4_DIVIDE /= 0) then + chk_ok := clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, "CLKOUT4_DUTY_CYCLE"); + end if; + pll_lock_time <= 12; + lock_period_time <= 16; + clkout_en_time_i1 := 10 + 12; + clkout_en_time <= clkout_en_time_i1; + locked_en_time <= clkout_en_time_i1 + 20; + lock_cnt_max <= clkout_en_time_i1 + 20 + 16; + init_done <= '1'; + wait; + end process INIPROC; + + clkinsel_p : process + variable period_clkin : real; + variable clkvco_freq_init_chk : real := 0.0; + variable Message : line; + variable tmpreal1 : real; + variable tmpreal2 : real; + variable first_check : boolean := true; + variable clkin_chk_t1 : real; + variable clkin_chk_t1_tmp1 : real; + variable clkin_chk_t1_tmp2 : real; + variable clkin_chk_t1_tmpi : time; + variable clkin_chk_t1_tmpi1 : integer; + variable clkin_chk_t2 : real; + variable clkin_chk_t2_tmp1 : real; + variable clkin_chk_t2_tmp2 : real; + variable clkin_chk_t2_tmpi : time; + variable clkin_chk_t2_tmpi1 : integer; + begin + + if (first_check = true or rising_edge(clkinsel_in) or falling_edge(clkinsel_in)) then + + if (NOW > 1 ps and rst_in = '0' and (clkinsel_tmp = '0' or clkinsel_tmp += '1')) then + assert false report + "Input Error : PLLE2_ADV input clock can only be switched when RST=1. CLKINSEL is changed when RST low, which should be changed at RST high." + severity error; + end if; + if (NOW = 0 ps) then + wait for 1 ps; + end if; + + clkin_chk_t1_tmp1 := 1000.0 / CLKIN_FREQ_MIN; + clkin_chk_t1_tmp2 := 1000.0 * clkin_chk_t1_tmp1; + clkin_chk_t1_tmpi := clkin_chk_t1_tmp2 * 1 ps; + clkin_chk_t1_tmpi1 := clkin_chk_t1_tmpi / 1 ps; + clkin_chk_t1 := real(clkin_chk_t1_tmpi1) / 1000.0; + + clkin_chk_t2_tmp1 := 1000.0 / CLKIN_FREQ_MAX; + clkin_chk_t2_tmp2 := 1000.0 * clkin_chk_t2_tmp1; + clkin_chk_t2_tmpi := clkin_chk_t2_tmp2 * 1 ps; + clkin_chk_t2_tmpi1 := clkin_chk_t2_tmpi / 1 ps; + clkin_chk_t2 := real(clkin_chk_t2_tmpi1) / 1000.0; + + if (((CLKIN1_PERIOD < clkin_chk_t2) or (CLKIN1_PERIOD > clkin_chk_t1)) and (CLKINSEL /= '0')) then + Write ( Message, string'(" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to ")); + Write ( Message, CLKIN1_PERIOD); + Write ( Message, string'(" ns and out the allowed range ")); + Write ( Message, clkin_chk_t2); + Write ( Message, string'(" ns to ")); + Write ( Message, clkin_chk_t1); + Write ( Message, string'(" ns" )); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + if (((CLKIN2_PERIOD < clkin_chk_t2) or (CLKIN2_PERIOD > clkin_chk_t1)) and (CLKINSEL = '0')) then + Write ( Message, string'(" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to ")); + Write ( Message, CLKIN2_PERIOD); + Write ( Message, string'(" ns and out the allowed range ")); + Write ( Message, clkin_chk_t2); + Write ( Message, string'(" ns to ")); + Write ( Message, clkin_chk_t1); + Write ( Message, string'(" ns")); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + if ( clkinsel_in /= '0') then + period_clkin := CLKIN1_PERIOD; + else + period_clkin := CLKIN2_PERIOD; + end if; + + tmpreal1 := real(CLKFBOUT_MULT); + tmpreal2 := real(DIVCLK_DIVIDE); + if (period_clkin > 0.000) then + clkvco_freq_init_chk := (1000.0 * tmpreal1) / ( period_clkin * tmpreal2); + + if ((clkvco_freq_init_chk > VCOCLK_FREQ_MAX) or (clkvco_freq_init_chk +< VCOCLK_FREQ_MIN)) then + Write ( Message, string'(" Attribute Syntax Error : The calculation of VCO frequency=")); + Write ( Message, clkvco_freq_init_chk); + Write ( Message, string'(" Mhz. This exceeds the permitted VCO frequency range of ")); + Write ( Message, VCOCLK_FREQ_MIN); + Write ( Message, string'(" MHz to ")); + Write ( Message, VCOCLK_FREQ_MAX); + if (clkinsel_in /= '0') then + Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN1_PERIOD).")); else + Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN2_PERIOD).")); end if; + Write ( Message, string'(" Please adjust the attributes to the permitted VCO frequency range.")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + first_check := false; + end if; + wait on clkinsel_in, clkpll_r; + end process; + + clkpll_r <= clkin1_in when clkinsel_in = '1' else clkin2_in; + pwrdwn_in1 <= '1' when (pwrdwn_in = '1' or pwron_int = '1') else '0'; + rst_input <= '1' when (rst_input_r = '1' or pwrdwn_in1 = '1') else '0'; + + + RST_SYNC_P : process (clkpll_r, rst_input) + begin + if (rst_input = '1') then + rst_in <= '1'; + elsif (rising_edge (clkpll_r)) then + rst_in <= rst_input; + end if; + end process; + + pwron_int_p : process + begin + pwron_int <= '1'; + wait for 100 ns; + pwron_int <= '0'; + wait; + end process; + + CLOCK_PERIOD_P : process (clkpll_r, rst_in) + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_in = '1' ) then + clkin_period(0) <= period_vco_target; + clkin_period(1) <= period_vco_target; + clkin_period(2) <= period_vco_target; + clkin_period(3) <= period_vco_target; + clkin_period(4) <= period_vco_target; + clkin_lock_cnt <= 0; + pll_locked_tm <= '0'; + lock_period <= '0'; + pll_locked_tmp1 <= '0'; + clkout_en0_tmp <= '0'; + clkin_edge_previous := 0 ps; + sample_en <= '1'; + elsif (rising_edge(clkpll_r)) then + if (sample_en = '1') then + clkin_edge_current := NOW; + if (clkin_edge_previous /= 0 ps ) then + clkin_period(4) <= clkin_period(3); + clkin_period(3) <= clkin_period(2); + clkin_period(2) <= clkin_period(1); + clkin_period(1) <= clkin_period(0); + clkin_period(0) <= clkin_edge_current - clkin_edge_previous; + end if; + + clkin_edge_previous := clkin_edge_current; + + if ( (clkin_lock_cnt < lock_cnt_max) and fb_delay_found = '1' ) then + clkin_lock_cnt <= clkin_lock_cnt + 1; + end if; + if ( clkin_lock_cnt >= pll_lock_time) then + pll_locked_tm <= '1'; + end if; + if ( clkin_lock_cnt = lock_period_time ) then + lock_period <= '1'; + end if; + + if (clkin_lock_cnt >= clkout_en_time and pll_locked_tm = '1') then + clkout_en0_tmp <= '1'; + end if; + + if (clkin_lock_cnt >= locked_en_time and clkout_en = '1') then + pll_locked_tmp1 <= '1'; + end if; + + if (pll_locked_tmp2 = '1' and pll_locked_tmp1 = '1') then + sample_en <= '0'; + end if; + end if; + end if; + end process; + + locked_out <= '1' when (pll_locked_tmp1 = '1' and pll_locked_tmp2 = '1') else '0'; + pll_locked_tmp2 <= (clk0ps_en and clk1ps_en and clk2ps_en and clk3ps_en + and clk4ps_en and clk5ps_en and clkfbm1ps_en); + + pchk_p : process(pll_locked_tmp1) + variable pchk_tmp1 : time; + variable pchk_tmp2 : time; + begin + if (rising_edge(pll_locked_tmp1)) then + if (clkinsel_in = '0') then + pchk_tmp1 := CLKIN2_PERIOD * 1100 ps; + pchk_tmp2 := CLKIN2_PERIOD * 900 ps; + if (period_avg > pchk_tmp1 or period_avg < pchk_tmp2) then + assert false report "Error : input CLKIN2 period and attribute CLKIN2_PERIOD are not same." severity error ; + end if; + else + pchk_tmp1 := CLKIN1_PERIOD * 1100 ps; + pchk_tmp2 := CLKIN1_PERIOD * 900 ps; + if (period_avg > pchk_tmp1 or period_avg < pchk_tmp2) then + assert false report "Error : input CLKIN1 period and attribute CLKIN1_PERIOD are not same." severity error ; + end if; + end if; + end if; + end process; + + locked_out_tmp_p : process + begin + if (rising_edge(rst_in)) then + wait for 1 ns; + locked_out_tmp <= '0'; + else + if (rst_in = '0') then + locked_out_tmp <= locked_out; + else + locked_out_tmp <= '0'; + end if; + end if; + wait on rst_in, locked_out; + end process; + + + clkout_en1_p : process (clkout_en0_tmp , rst_in) + begin + if (rst_in = '1') then + clkout_en1 <= '0'; + else + clkout_en1 <= transport clkout_en0_tmp after clkvco_delay; + end if; + end process; + + clkout_en_p : process (clkout_en1, rst_in) + begin + if (rst_in = '1') then + clkout_en <= '0'; + else + clkout_en <= clkout_en1; + end if; + end process; + + CLK_PERIOD_AVG_P : process (clkin_period(0), clkin_period(1), clkin_period(2), + clkin_period(3), clkin_period(4), period_avg) + variable period_avg_tmp : time := 0 ps; + variable clkin_period_tmp0 : time := 0 ps; + variable clkin_period_tmp1 : time := 0 ps; + variable clkin_period_tmp_t : time := 0 ps; + begin + clkin_period_tmp0 := clkin_period(0); + clkin_period_tmp1 := clkin_period(1); + if (clkin_period_tmp0 > clkin_period_tmp1) then + clkin_period_tmp_t := clkin_period_tmp0 - clkin_period_tmp1; + else + clkin_period_tmp_t := clkin_period_tmp1 - clkin_period_tmp0; + end if; + + if (clkin_period_tmp0 /= period_avg and (clkin_period_tmp0 < 1.5 * period_avg or clkin_period_tmp_t <= 300 ps)) then + period_avg_tmp := (clkin_period(0) + clkin_period(1) + clkin_period(2) + + clkin_period(3) + clkin_period(4))/5.0; + period_avg <= period_avg_tmp; + end if; + end process; + + process (period_avg, lock_period, rst_in) + variable p_c0 : time; + variable p_c0i : integer; + variable p_c0_dr : integer; + variable p_c0_dri : time; + variable p_c0_dri1 : integer; + variable p_c0_dri2 : integer; + variable p_c1 : time; + variable p_c1i : integer; + variable p_c1_dr : integer; + variable p_c1_dri : time; + variable p_c1_dri1 : integer; + variable p_c1_dri2 : integer; + variable p_c2 : time; + variable p_c2i : integer; + variable p_c2_dr : integer; + variable p_c2_dri : time; + variable p_c2_dri1 : integer; + variable p_c2_dri2 : integer; + variable p_c3 : time; + variable p_c3i : integer; + variable p_c3_dr : integer; + variable p_c3_dri : time; + variable p_c3_dri1 : integer; + variable p_c3_dri2 : integer; + variable p_c4 : time; + variable p_c4i : integer; + variable p_c4_dr : integer; + variable p_c4_dri : time; + variable p_c4_dri1 : integer; + variable p_c4_dri2 : integer; + variable p_c5 : time; + variable p_c5i : integer; + variable p_c5_dr : integer; + variable p_c5_dri : time; + variable p_c5_dri1 : integer; + variable p_c5_dri2 : integer; + variable period_fbi : integer; + variable period_fb_tmp : time; + variable fb_delayi : integer; + variable clkvco_delay_tmp : time; + variable clkvco_delayi : integer; + variable fb_delaym : integer; + variable dly_tmp : time; + variable dly_tmpi : integer; + variable clkfbm1_dly_tmp : time; + variable period_vco_tmp : time; + begin + if (rst_in = '1') then + p_fb <= 0 ps; + p_fb_h <= 0 ps; + p_fb_r <= 0 ps; + p_fb_r1 <= 0 ps; + p_fb_d <= 0 ps; + p_c0 := 0 ps; + p_c0_h <= 0 ps; + p_c0_r <= 0 ps; + p_c0_r1 <= 0 ps; + p_c0_d <= 0 ps; + p_c1 := 0 ps; + p_c1_h <= 0 ps; + p_c1_r <= 0 ps; + p_c1_r1 <= 0 ps; + p_c1_d <= 0 ps; + p_c2 := 0 ps; + p_c2_h <= 0 ps; + p_c2_r <= 0 ps; + p_c2_r1 <= 0 ps; + p_c2_d <= 0 ps; + p_c3 := 0 ps; + p_c3_h <= 0 ps; + p_c3_r <= 0 ps; + p_c3_r1 <= 0 ps; + p_c3_d <= 0 ps; + p_c4 := 0 ps; + p_c4_h <= 0 ps; + p_c4_r <= 0 ps; + p_c4_r1 <= 0 ps; + p_c4_d <= 0 ps; + p_c5 := 0 ps; + p_c5_h <= 0 ps; + p_c5_r <= 0 ps; + p_c5_r1 <= 0 ps; + p_c5_d <= 0 ps; + clkvco_delay <= 0 ps; + dly_tmp := 0 ps; + period_fb <= 0 ps; + period_vco <= 0 ps; + clkfbm1_dly <= 0 ps; + p_c0_dr := 0; + p_c1_dr := 0 ; + p_c2_dr := 0; + p_c3_dr := 0; + p_c4_dr := 0; + p_c5_dr := 0; + else + if (period_avg > 0 ps and lock_period = '1') then + fb_delayi := fb_delay / 1 ps; + period_fb_tmp := period_avg * DIVCLK_DIVIDE; + period_fbi := period_fb_tmp / 1 ps; + period_fb <= period_fb_tmp; + period_vco_tmp := period_fb_tmp / CLKFBOUT_MULT; + period_vco <= period_vco_tmp; + clkfbm1_dly_tmp := ((CLKFBOUT_PHASE * period_fb_tmp) / 360.0); + clkfbm1_dly <= clkfbm1_dly_tmp; + dly_tmp := fb_delay + clkfbm1_dly_tmp; + dly_tmpi := dly_tmp / 1 ps; + if (dly_tmp = 0 ps) then + clkvco_delay_tmp := 0 ps; + elsif ( dly_tmp <= period_fb_tmp ) then + clkvco_delay_tmp := period_fb_tmp - dly_tmp; + else + clkvco_delay_tmp := period_fb_tmp - ((dly_tmpi mod( period_fbi)) * 1 ps) ; + end if; + clkvco_delay <= clkvco_delay_tmp; + clkvco_delayi := clkvco_delay_tmp / 1 ps; + p_fb <= period_fb_tmp; + p_fb_h <= period_fb_tmp / 2; + p_fb_r <= period_fb_tmp - period_fb_tmp / 2; + p_fb_r1 <= period_fb_tmp - period_fb_tmp / 2 - 1 ps; + fb_delaym := fb_delayi mod (period_fbi); + if ( fb_delay <= period_fb_tmp) then + p_fb_d <= period_fb_tmp - fb_delay; + else + p_fb_d <= period_fb_tmp - fb_delaym * 1 ps; + end if; + p_c0 := (period_fb_tmp * CLKOUT0_DIVIDE) / CLKFBOUT_MULT; + p_c0i := p_c0 / 1 ps; + p_c0_h <= p_c0 * CLKOUT0_DUTY_CYCLE; + p_c0_r <= p_c0 - p_c0 * CLKOUT0_DUTY_CYCLE; + p_c0_r1 <= p_c0 - p_c0 * CLKOUT0_DUTY_CYCLE - 1 ps; + p_c0_dri := ((CLKOUT0_PHASE * p_c0) / 360.0); + p_c0_dri1 := (p_c0_dri / 1 ps); + p_c0_dri2 := (clkvco_delayi mod p_c0i); + p_c0_dr := p_c0_dri1 + p_c0_dri2; + if (p_c0_dr < 0 ) then + p_c0_d <= p_c0 + (p_c0_dr mod p_c0i) * 1 ps; + else + p_c0_d <= (p_c0_dr mod p_c0i ) * 1 ps; + end if; + + + p_c1 := (period_fb_tmp * CLKOUT1_DIVIDE) / CLKFBOUT_MULT; + p_c1i := p_c1 / 1 ps; + p_c1_h <= p_c1 * CLKOUT1_DUTY_CYCLE; + p_c1_r <= p_c1 - p_c1 * CLKOUT1_DUTY_CYCLE; + p_c1_r1 <= p_c1 - p_c1 * CLKOUT1_DUTY_CYCLE - 1 ps; + p_c1_dri := ((CLKOUT1_PHASE * p_c1) / 360.0); + p_c1_dri1 := (p_c1_dri / 1 ps); + p_c1_dri2 := (clkvco_delayi mod p_c1i); + p_c1_dr := p_c1_dri1 + p_c1_dri2; + if (p_c1_dr < 0 ) then + p_c1_d <= p_c1 + (p_c1_dr mod p_c1i) * 1 ps; + else + p_c1_d <= (p_c1_dr mod p_c1i ) * 1 ps; + end if; + + p_c2 := (period_fb_tmp * CLKOUT2_DIVIDE) / CLKFBOUT_MULT; + p_c2i := p_c2 / 1 ps; + p_c2_h <= p_c2 * CLKOUT2_DUTY_CYCLE; + p_c2_r <= p_c2 - p_c2 * CLKOUT2_DUTY_CYCLE; + p_c2_r1 <= p_c2 - p_c2 * CLKOUT2_DUTY_CYCLE - 1 ps; + p_c2_dri := ((CLKOUT2_PHASE * p_c2) / 360.0); + p_c2_dri1 := (p_c2_dri / 1 ps); + p_c2_dri2 := (clkvco_delayi mod p_c2i); + p_c2_dr := p_c2_dri1 + p_c2_dri2; + if (p_c2_dr < 0 ) then + p_c2_d <= p_c2 + (p_c2_dr mod p_c2i) * 1 ps; + else + p_c2_d <= (p_c2_dr mod p_c2i ) * 1 ps; + end if; + + p_c3 := (period_fb_tmp * CLKOUT3_DIVIDE) / CLKFBOUT_MULT; + p_c3i := p_c3 / 1 ps; + p_c3_h <= p_c3 * CLKOUT3_DUTY_CYCLE; + p_c3_r <= p_c3 - p_c3 * CLKOUT3_DUTY_CYCLE; + p_c3_r1 <= p_c3 - p_c3 * CLKOUT3_DUTY_CYCLE - 1 ps; + p_c3_dri := ((CLKOUT3_PHASE * p_c3) / 360.0); + p_c3_dri1 := (p_c3_dri / 1 ps); + p_c3_dri2 := (clkvco_delayi mod p_c3i); + p_c3_dr := p_c3_dri1 + p_c3_dri2; + if (p_c3_dr < 0 ) then + p_c3_d <= p_c3 + (p_c3_dr mod p_c3i) * 1 ps; + else + p_c3_d <= (p_c3_dr mod p_c3i ) * 1 ps; + end if; + + p_c4 := (period_fb_tmp * CLKOUT4_DIVIDE) / CLKFBOUT_MULT; + p_c4i := p_c4 / 1 ps; + p_c4_h <= p_c4 * CLKOUT4_DUTY_CYCLE; + p_c4_r <= p_c4 - p_c4 * CLKOUT4_DUTY_CYCLE; + p_c4_r1 <= p_c4 - p_c4 * CLKOUT4_DUTY_CYCLE - 1 ps; + p_c4_dri := ((CLKOUT4_PHASE * p_c4) / 360.0); + p_c4_dri1 := (p_c4_dri / 1 ps); + p_c4_dri2 := (clkvco_delayi mod p_c4i); + p_c4_dr := p_c4_dri1 + p_c4_dri2; + if (p_c4_dr < 0 ) then + p_c4_d <= p_c4 + (p_c4_dr mod p_c4i) * 1 ps; + else + p_c4_d <= (p_c4_dr mod p_c4i ) * 1 ps; + end if; + + p_c5 := (period_fb_tmp * CLKOUT5_DIVIDE) / CLKFBOUT_MULT; + p_c5i := p_c5 / 1 ps; + p_c5_h <= p_c5 * CLKOUT5_DUTY_CYCLE; + p_c5_r <= p_c5 - p_c5 * CLKOUT5_DUTY_CYCLE; + p_c5_r1 <= p_c5 - p_c5 * CLKOUT5_DUTY_CYCLE - 1 ps; + p_c5_dri := ((CLKOUT5_PHASE * p_c5) / 360.0); + p_c5_dri1 := (p_c5_dri / 1 ps); + p_c5_dri2 := (clkvco_delayi mod p_c5i); + p_c5_dr := p_c5_dri1 + p_c5_dri2; + if (p_c5_dr < 0 ) then + p_c5_d <= p_c5 + (p_c5_dr mod p_c5i) * 1 ps; + else + p_c5_d <= (p_c5_dr mod p_c5i ) * 1 ps; + end if; + + end if; + end if; + end process; + + process (clkout_en, rst_in) begin + if (rst_in = '1') then + clk0ps_en <= '0'; + clk1ps_en <= '0'; + clk2ps_en <= '0'; + clk3ps_en <= '0'; + clk4ps_en <= '0'; + clk5ps_en <= '0'; + clkfbm1ps_en <= '0'; + elsif (rising_edge(clkout_en)) then + clk0ps_en <= '1' after p_c0_d; + clk1ps_en <= '1' after p_c1_d; + clk2ps_en <= '1' after p_c2_d; + clk3ps_en <= '1' after p_c3_d; + clk4ps_en <= '1' after p_c4_d; + clk5ps_en <= '1' after p_c5_d; + clkfbm1ps_en <= '1' after p_fb_d; + end if; + end process; + + process (clkpll_r, rst_in) begin + if (rst_in = '1') then + clk0_cnt <= 0; + clk1_cnt <= 0; + clk2_cnt <= 0; + clk3_cnt <= 0; + clk4_cnt <= 0; + clk5_cnt <= 0; + clkfb_cnt <= 0; + clk0_gen <= '0'; + clk1_gen <= '0'; + clk2_gen <= '0'; + clk3_gen <= '0'; + clk4_gen <= '0'; + clk5_gen <= '0'; + clkfb_gen <= '0'; + elsif (rising_edge (clkpll_r)) then + if (clkout_en0_tmp = '1' ) then + if (clk0_cnt < clk0_val2 ) then + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 0; + end if; + + if (clk0_cnt >= clk0_val ) then + clk0_gen <= '0'; + else + clk0_gen <= '1'; + end if; + else + clk0_cnt <= 0; + clk0_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk1_cnt < clk1_val2 ) then + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 0; + end if; + + if (clk1_cnt >= clk1_val ) then + clk1_gen <= '0'; + else + clk1_gen <= '1'; + end if; + else + clk1_cnt <= 0; + clk1_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk2_cnt < clk2_val2 ) then + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 0; + end if; + + if (clk2_cnt >= clk2_val ) then + clk2_gen <= '0'; + else + clk2_gen <= '1'; + end if; + else + clk2_cnt <= 0; + clk2_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk3_cnt < clk3_val2) then + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 0; + end if; + + if (clk3_cnt >= clk3_val ) then + clk3_gen <= '0'; + else + clk3_gen <= '1'; + end if; + else + clk3_cnt <= 0; + clk3_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk4_cnt < clk4_val2 ) then + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 0; + end if; + + if (clk4_cnt >= clk4_val ) then + clk4_gen <= '0'; + else + clk4_gen <= '1'; + end if; + else + clk4_cnt <= 0; + clk4_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clk5_cnt < clk5_val2) then + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 0; + end if; + + if (clk5_cnt >= clk5_val ) then + clk5_gen <= '0'; + else + clk5_gen <= '1'; + end if; + else + clk5_cnt <= 0; + clk5_gen <= '0'; + end if; + + if (clkout_en0_tmp = '1' ) then + if (clkfb_cnt < clkfb_val2 ) then + clkfb_cnt <= clkfb_cnt + 1; + else + clkfb_cnt <= 0; + end if; + + if (clkfb_cnt >= clkfb_val) then + clkfb_gen <= '0'; + else + clkfb_gen <= '1'; + end if; + else + clkfb_cnt <= 0; + clkfb_gen <= '0'; + end if; + end if; + end process; + + process (clk0_gen, rst_in) begin + if (rst_in = '1') then + clk0_gen_f <= '0'; + else + clk0_gen_f <= clk0_gen after p_c0_d; + end if; + end process; + + process (clk1_gen, rst_in) begin + if (rst_in = '1') then + clk1_gen_f <= '0'; + else + clk1_gen_f <= clk1_gen after p_c1_d; + end if; + end process; + + process (clk2_gen, rst_in) begin + if (rst_in = '1') then + clk2_gen_f <= '0'; + else + clk2_gen_f <= clk2_gen after p_c2_d; + end if; + end process; + + process (clk3_gen, rst_in) begin + if (rst_in = '1') then + clk3_gen_f <= '0'; + else + clk3_gen_f <= clk3_gen after p_c3_d; + end if; + end process; + + process (clk4_gen, rst_in) begin + if (rst_in = '1') then + clk4_gen_f <= '0'; + else + clk4_gen_f <= clk4_gen after p_c4_d; + end if; + end process; + + process (clk5_gen, rst_in) begin + if (rst_in = '1') then + clk5_gen_f <= '0'; + else + clk5_gen_f <= clk5_gen after p_c5_d; + end if; + end process; + + process (clkfb_gen, rst_in) begin + if (rst_in = '1') then + clkfb_gen_f <= '0'; + else + clkfb_gen_f <= clkfb_gen after p_fb_d; + end if; + end process; + + process begin + if (rst_in = '1') then + clk0_out <= '0'; + elsif (rising_edge(clk0_gen_f) or falling_edge(clk0_gen_f)) then + if (clk0ps_en = '1' ) then + if ( clk0_val1 = 1) then + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r1; + else + for i0 in 1 to clk0_val11 loop + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r; + end loop; + clk0_out <= '1'; + wait for p_c0_h; + clk0_out <= '0'; + wait for p_c0_r1; + end if; + else + clk0_out <= '0'; + end if; + end if; + wait on clk0_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk1_out <= '0'; + elsif (rising_edge(clk1_gen_f) or falling_edge(clk1_gen_f)) then + if (clk1ps_en = '1' ) then + if ( clk1_val1 = 1) then + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r1; + else + for i1 in 1 to clk1_val11 loop + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r; + end loop; + clk1_out <= '1'; + wait for p_c1_h; + clk1_out <= '0'; + wait for p_c1_r1; + end if; + else + clk1_out <= '0'; + end if; + end if; + wait on clk1_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk2_out <= '0'; + elsif (rising_edge(clk2_gen_f) or falling_edge(clk2_gen_f)) then + if (clk2ps_en = '1' ) then + if ( clk2_val1 = 1) then + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r1; + else + for i2 in 1 to clk2_val11 loop + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r; + end loop; + clk2_out <= '1'; + wait for p_c2_h; + clk2_out <= '0'; + wait for p_c2_r1; + end if; + else + clk2_out <= '0'; + end if; + end if; + wait on clk2_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk3_out <= '0'; + elsif (rising_edge(clk3_gen_f) or falling_edge(clk3_gen_f)) then + if (clk3ps_en = '1' ) then + if ( clk3_val1 = 1) then + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r1; + else + for i3 in 1 to clk3_val11 loop + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r; + end loop; + clk3_out <= '1'; + wait for p_c3_h; + clk3_out <= '0'; + wait for p_c3_r1; + end if; + else + clk3_out <= '0'; + end if; + end if; + wait on clk3_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk4_out <= '0'; + elsif (rising_edge(clk4_gen_f) or falling_edge(clk4_gen_f)) then + if (clk4ps_en = '1' ) then + if ( clk4_val1 = 1) then + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r1; + else + for i4 in 1 to clk4_val11 loop + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r; + end loop; + clk4_out <= '1'; + wait for p_c4_h; + clk4_out <= '0'; + wait for p_c4_r1; + end if; + else + clk4_out <= '0'; + end if; + end if; + wait on clk4_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clk5_out <= '0'; + elsif (rising_edge(clk5_gen_f) or falling_edge(clk5_gen_f)) then + if (clk5ps_en = '1' ) then + if ( clk5_val1 = 1) then + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r1; + else + for i5 in 1 to clk5_val11 loop + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r; + end loop; + clk5_out <= '1'; + wait for p_c5_h; + clk5_out <= '0'; + wait for p_c5_r1; + end if; + else + clk5_out <= '0'; + end if; + end if; + wait on clk5_gen_f, rst_in; + end process; + + process begin + if (rst_in = '1') then + clkfbm1_out <= '0'; + elsif (rising_edge(clkfb_gen_f) or falling_edge(clkfb_gen_f)) then + if (clkfbm1ps_en = '1' ) then + if (clkfb_val1 = 1) then + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r1; + else + for ib in 1 to clkfb_val11 loop + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r; + end loop; + clkfbm1_out <= '1'; + wait for p_fb_h; + clkfbm1_out <= '0'; + wait for p_fb_r1; + end if; + else + clkfbm1_out <= '0'; + end if; + end if; + wait on clkfb_gen_f, rst_in; + end process; + + clkout0_out <= transport clk0_out when fb_delay_found = '1' else clkfb_tst; + clkout1_out <= transport clk1_out when fb_delay_found = '1' else clkfb_tst; + clkout2_out <= transport clk2_out when fb_delay_found = '1' else clkfb_tst; + clkout3_out <= transport clk3_out when fb_delay_found = '1' else clkfb_tst; + clkout4_out <= transport clk4_out when fb_delay_found = '1' else clkfb_tst; + clkout5_out <= transport clk5_out when fb_delay_found = '1' else clkfb_tst; + clkfb_out <= transport clkfbm1_out when fb_delay_found = '1' else clkfb_tst; + + CLKFB_TST_P : process (clkpll_r, rst_in) + begin + if (rst_in = '1') then + clkfb_tst <= '0'; + elsif (rising_edge(clkpll_r)) then + if (fb_delay_found_tmp = '0' and pwron_int = '0') then + clkfb_tst <= '1'; + else + clkfb_tst <= '0'; + end if; + end if; + end process; + + FB_DELAY_CAL_P0 : process (clkfb_tst, rst_in) + begin + if (rst_in = '1') then + delay_edge <= 0 ps; + elsif (rising_edge(clkfb_tst)) then + delay_edge <= NOW; + end if; + end process; + + FB_DELAY_CAL_P : process (clkfb_in, rst_in) + variable delay_edge1 : time := 0 ps; + variable fb_delay_tmp : time := 0 ps; + variable Message : line; + begin + if (rst_in = '1') then + fb_delay <= 0 ps; + fb_delay_found_tmp <= '0'; + delay_edge1 := 0 ps; + fb_delay_tmp := 0 ps; + elsif (clkfb_in'event and clkfb_in = '1') then + if (fb_delay_found_tmp = '0') then + if (delay_edge /= 0 ps) then + delay_edge1 := NOW; + fb_delay_tmp := delay_edge1 - delay_edge; + else + fb_delay_tmp := 0 ps; + end if; + fb_delay <= fb_delay_tmp; + fb_delay_found_tmp <= '1'; + if (rst_in = '0' and (fb_delay_tmp > fb_delay_max)) then + Write ( Message, string'(" Warning : The feedback delay is ")); + Write ( Message, fb_delay_tmp); + Write ( Message, string'(". It is over the maximun value ")); + Write ( Message, fb_delay_max); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + end if; + end process; + + fb_delay_found_P : process(fb_delay_found_tmp, clkvco_delay, rst_in) + begin + if (rst_in = '1') then + fb_delay_found <= '0'; + elsif (clkvco_delay = 0 ps) then + fb_delay_found <= fb_delay_found_tmp after 1 ns; + else + fb_delay_found <= fb_delay_found_tmp after clkvco_delay; + end if; + end process; + +end PLLE2_ADV_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/vhdl_analyze_order b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/vhdl_analyze_order new file mode 100644 index 0000000..230a93d --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/vhdl_analyze_order @@ -0,0 +1,3 @@ +DSP48E1.vhd +MMCME2_ADV.vhd +PLLE2_ADV.vhd diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTHE2_CHANNEL.vhd b/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTHE2_CHANNEL.vhd new file mode 100644 index 0000000..6c33e83 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTHE2_CHANNEL.vhd @@ -0,0 +1,3959 @@ +------------------------------------------------------- +-- Copyright (c) 2011 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.4 +-- \ \ Description : +-- / / +-- /___/ /\ Filename : GTHE2_CHANNEL.vhd +-- \ \ / \ +-- \__ \/\__ \ +-- +-- Revision: 1.0 +-- 04/13/11 - 605801 - Initial version +-- 05/24/11 - 610034 - Secureip model added +-- 09/22/11 - 624065 - YML update +-- 10/17/12 - 682802 - convert GSR H/L to 1/0 +-- 11/08/12 - 686590 - YML default attribute changes +-- 01/23/13 - Added DRP monitor (CR 695630). +-- 06/19/14 - PR785721 - IS_*INVERTED update from std_ulogic to bit +------------------------------------------------------- + + +----- CELL GTHE2_CHANNEL ----- + +library IEEE; +use IEEE.STD_LOGIC_arith.all; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.vpkg.all; + +library secureip; +use secureip.all; + + entity GTHE2_CHANNEL is + generic ( + ACJTAG_DEBUG_MODE : bit := '0'; + ACJTAG_MODE : bit := '0'; + ACJTAG_RESET : bit := '0'; + ADAPT_CFG0 : bit_vector := X"00C10"; + ALIGN_COMMA_DOUBLE : string := "FALSE"; + ALIGN_COMMA_ENABLE : bit_vector := "0001111111"; + ALIGN_COMMA_WORD : integer := 1; + ALIGN_MCOMMA_DET : string := "TRUE"; + ALIGN_MCOMMA_VALUE : bit_vector := "1010000011"; + ALIGN_PCOMMA_DET : string := "TRUE"; + ALIGN_PCOMMA_VALUE : bit_vector := "0101111100"; + A_RXOSCALRESET : bit := '0'; + CBCC_DATA_SOURCE_SEL : string := "DECODED"; + CFOK_CFG : bit_vector := X"24800040E80"; + CFOK_CFG2 : bit_vector := "100000"; + CFOK_CFG3 : bit_vector := "100000"; + CHAN_BOND_KEEP_ALIGN : string := "FALSE"; + CHAN_BOND_MAX_SKEW : integer := 7; + CHAN_BOND_SEQ_1_1 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_2 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_ENABLE : bit_vector := "1111"; + CHAN_BOND_SEQ_2_1 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_ENABLE : bit_vector := "1111"; + CHAN_BOND_SEQ_2_USE : string := "FALSE"; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : string := "TRUE"; + CLK_COR_KEEP_IDLE : string := "FALSE"; + CLK_COR_MAX_LAT : integer := 20; + CLK_COR_MIN_LAT : integer := 18; + CLK_COR_PRECEDENCE : string := "TRUE"; + CLK_COR_REPEAT_WAIT : integer := 0; + CLK_COR_SEQ_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE : bit_vector := "1111"; + CLK_COR_SEQ_2_1 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_2 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_3 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_4 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_ENABLE : bit_vector := "1111"; + CLK_COR_SEQ_2_USE : string := "FALSE"; + CLK_COR_SEQ_LEN : integer := 1; + CPLL_CFG : bit_vector := X"00BC07DC"; + CPLL_FBDIV : integer := 4; + CPLL_FBDIV_45 : integer := 5; + CPLL_INIT_CFG : bit_vector := X"00001E"; + CPLL_LOCK_CFG : bit_vector := X"01E8"; + CPLL_REFCLK_DIV : integer := 1; + DEC_MCOMMA_DETECT : string := "TRUE"; + DEC_PCOMMA_DETECT : string := "TRUE"; + DEC_VALID_COMMA_ONLY : string := "TRUE"; + DMONITOR_CFG : bit_vector := X"000A00"; + ES_CLK_PHASE_SEL : bit := '0'; + ES_CONTROL : bit_vector := "000000"; + ES_ERRDET_EN : string := "FALSE"; + ES_EYE_SCAN_EN : string := "TRUE"; + ES_HORZ_OFFSET : bit_vector := X"000"; + ES_PMA_CFG : bit_vector := "0000000000"; + ES_PRESCALE : bit_vector := "00000"; + ES_QUALIFIER : bit_vector := X"00000000000000000000"; + ES_QUAL_MASK : bit_vector := X"00000000000000000000"; + ES_SDATA_MASK : bit_vector := X"00000000000000000000"; + ES_VERT_OFFSET : bit_vector := "000000000"; + FTS_DESKEW_SEQ_ENABLE : bit_vector := "1111"; + FTS_LANE_DESKEW_CFG : bit_vector := "1111"; + FTS_LANE_DESKEW_EN : string := "FALSE"; + GEARBOX_MODE : bit_vector := "000"; + IS_CLKRSVD0_INVERTED : bit := '0'; + IS_CLKRSVD1_INVERTED : bit := '0'; + IS_CPLLLOCKDETCLK_INVERTED : bit := '0'; + IS_DMONITORCLK_INVERTED : bit := '0'; + IS_DRPCLK_INVERTED : bit := '0'; + IS_GTGREFCLK_INVERTED : bit := '0'; + IS_RXUSRCLK2_INVERTED : bit := '0'; + IS_RXUSRCLK_INVERTED : bit := '0'; + IS_SIGVALIDCLK_INVERTED : bit := '0'; + IS_TXPHDLYTSTCLK_INVERTED : bit := '0'; + IS_TXUSRCLK2_INVERTED : bit := '0'; + IS_TXUSRCLK_INVERTED : bit := '0'; + LOOPBACK_CFG : bit := '0'; + OUTREFCLK_SEL_INV : bit_vector := "11"; + PCS_PCIE_EN : string := "FALSE"; + PCS_RSVD_ATTR : bit_vector := X"000000000000"; + PD_TRANS_TIME_FROM_P2 : bit_vector := X"03C"; + PD_TRANS_TIME_NONE_P2 : bit_vector := X"19"; + PD_TRANS_TIME_TO_P2 : bit_vector := X"64"; + PMA_RSV : bit_vector := "00000000000000000000000010000000"; + PMA_RSV2 : bit_vector := "00011100000000000000000000001010"; + PMA_RSV3 : bit_vector := "00"; + PMA_RSV4 : bit_vector := "000000000001000"; + PMA_RSV5 : bit_vector := "0000"; + RESET_POWERSAVE_DISABLE : bit := '0'; + RXBUFRESET_TIME : bit_vector := "00001"; + RXBUF_ADDR_MODE : string := "FULL"; + RXBUF_EIDLE_HI_CNT : bit_vector := "1000"; + RXBUF_EIDLE_LO_CNT : bit_vector := "0000"; + RXBUF_EN : string := "TRUE"; + RXBUF_RESET_ON_CB_CHANGE : string := "TRUE"; + RXBUF_RESET_ON_COMMAALIGN : string := "FALSE"; + RXBUF_RESET_ON_EIDLE : string := "FALSE"; + RXBUF_RESET_ON_RATE_CHANGE : string := "TRUE"; + RXBUF_THRESH_OVFLW : integer := 61; + RXBUF_THRESH_OVRD : string := "FALSE"; + RXBUF_THRESH_UNDFLW : integer := 4; + RXCDRFREQRESET_TIME : bit_vector := "00001"; + RXCDRPHRESET_TIME : bit_vector := "00001"; + RXCDR_CFG : bit_vector := X"0002007FE2000C208001A"; + RXCDR_FR_RESET_ON_EIDLE : bit := '0'; + RXCDR_HOLD_DURING_EIDLE : bit := '0'; + RXCDR_LOCK_CFG : bit_vector := "001001"; + RXCDR_PH_RESET_ON_EIDLE : bit := '0'; + RXDFELPMRESET_TIME : bit_vector := "0001111"; + RXDLY_CFG : bit_vector := X"001F"; + RXDLY_LCFG : bit_vector := X"030"; + RXDLY_TAP_CFG : bit_vector := X"0000"; + RXGEARBOX_EN : string := "FALSE"; + RXISCANRESET_TIME : bit_vector := "00001"; + RXLPM_HF_CFG : bit_vector := "00001000000000"; + RXLPM_LF_CFG : bit_vector := "001001000000000000"; + RXOOB_CFG : bit_vector := "0000110"; + RXOOB_CLK_CFG : string := "PMA"; + RXOSCALRESET_TIME : bit_vector := "00011"; + RXOSCALRESET_TIMEOUT : bit_vector := "00000"; + RXOUT_DIV : integer := 2; + RXPCSRESET_TIME : bit_vector := "00001"; + RXPHDLY_CFG : bit_vector := X"084020"; + RXPH_CFG : bit_vector := X"C00002"; + RXPH_MONITOR_SEL : bit_vector := "00000"; + RXPI_CFG0 : bit_vector := "00"; + RXPI_CFG1 : bit_vector := "00"; + RXPI_CFG2 : bit_vector := "00"; + RXPI_CFG3 : bit_vector := "00"; + RXPI_CFG4 : bit := '0'; + RXPI_CFG5 : bit := '0'; + RXPI_CFG6 : bit_vector := "100"; + RXPMARESET_TIME : bit_vector := "00011"; + RXPRBS_ERR_LOOPBACK : bit := '0'; + RXSLIDE_AUTO_WAIT : integer := 7; + RXSLIDE_MODE : string := "OFF"; + RXSYNC_MULTILANE : bit := '0'; + RXSYNC_OVRD : bit := '0'; + RXSYNC_SKIP_DA : bit := '0'; + RX_BIAS_CFG : bit_vector := "000011000000000000010000"; + RX_BUFFER_CFG : bit_vector := "000000"; + RX_CLK25_DIV : integer := 7; + RX_CLKMUX_PD : bit := '1'; + RX_CM_SEL : bit_vector := "11"; + RX_CM_TRIM : bit_vector := "0100"; + RX_DATA_WIDTH : integer := 20; + RX_DDI_SEL : bit_vector := "000000"; + RX_DEBUG_CFG : bit_vector := "00000000000000"; + RX_DEFER_RESET_BUF_EN : string := "TRUE"; + RX_DFELPM_CFG0 : bit_vector := "0110"; + RX_DFELPM_CFG1 : bit := '0'; + RX_DFELPM_KLKH_AGC_STUP_EN : bit := '1'; + RX_DFE_AGC_CFG0 : bit_vector := "00"; + RX_DFE_AGC_CFG1 : bit_vector := "010"; + RX_DFE_AGC_CFG2 : bit_vector := "0000"; + RX_DFE_AGC_OVRDEN : bit := '1'; + RX_DFE_GAIN_CFG : bit_vector := X"0020C0"; + RX_DFE_H2_CFG : bit_vector := "000000000000"; + RX_DFE_H3_CFG : bit_vector := "000001000000"; + RX_DFE_H4_CFG : bit_vector := "00011100000"; + RX_DFE_H5_CFG : bit_vector := "00011100000"; + RX_DFE_H6_CFG : bit_vector := "00000100000"; + RX_DFE_H7_CFG : bit_vector := "00000100000"; + RX_DFE_KL_CFG : bit_vector := "000000000000000000000001100010000"; + RX_DFE_KL_LPM_KH_CFG0 : bit_vector := "01"; + RX_DFE_KL_LPM_KH_CFG1 : bit_vector := "010"; + RX_DFE_KL_LPM_KH_CFG2 : bit_vector := "0010"; + RX_DFE_KL_LPM_KH_OVRDEN : bit := '1'; + RX_DFE_KL_LPM_KL_CFG0 : bit_vector := "10"; + RX_DFE_KL_LPM_KL_CFG1 : bit_vector := "010"; + RX_DFE_KL_LPM_KL_CFG2 : bit_vector := "0010"; + RX_DFE_KL_LPM_KL_OVRDEN : bit := '1'; + RX_DFE_LPM_CFG : bit_vector := X"0080"; + RX_DFE_LPM_HOLD_DURING_EIDLE : bit := '0'; + RX_DFE_ST_CFG : bit_vector := X"00E100000C003F"; + RX_DFE_UT_CFG : bit_vector := "00011100000000000"; + RX_DFE_VP_CFG : bit_vector := "00011101010100011"; + RX_DISPERR_SEQ_MATCH : string := "TRUE"; + RX_INT_DATAWIDTH : integer := 0; + RX_OS_CFG : bit_vector := "0000010000000"; + RX_SIG_VALID_DLY : integer := 10; + RX_XCLK_SEL : string := "RXREC"; + SAS_MAX_COM : integer := 64; + SAS_MIN_COM : integer := 36; + SATA_BURST_SEQ_LEN : bit_vector := "1111"; + SATA_BURST_VAL : bit_vector := "100"; + SATA_CPLL_CFG : string := "VCO_3000MHZ"; + SATA_EIDLE_VAL : bit_vector := "100"; + SATA_MAX_BURST : integer := 8; + SATA_MAX_INIT : integer := 21; + SATA_MAX_WAKE : integer := 7; + SATA_MIN_BURST : integer := 4; + SATA_MIN_INIT : integer := 12; + SATA_MIN_WAKE : integer := 4; + SHOW_REALIGN_COMMA : string := "TRUE"; + SIM_CPLLREFCLK_SEL : bit_vector := "001"; + SIM_RECEIVER_DETECT_PASS : string := "TRUE"; + SIM_RESET_SPEEDUP : string := "TRUE"; + SIM_TX_EIDLE_DRIVE_LEVEL : string := "X"; + SIM_VERSION : string := "1.1"; + TERM_RCAL_CFG : bit_vector := "100001000010000"; + TERM_RCAL_OVRD : bit_vector := "000"; + TRANS_TIME_RATE : bit_vector := X"0E"; + TST_RSV : bit_vector := X"00000000"; + TXBUF_EN : string := "TRUE"; + TXBUF_RESET_ON_RATE_CHANGE : string := "FALSE"; + TXDLY_CFG : bit_vector := X"001F"; + TXDLY_LCFG : bit_vector := X"030"; + TXDLY_TAP_CFG : bit_vector := X"0000"; + TXGEARBOX_EN : string := "FALSE"; + TXOOB_CFG : bit := '0'; + TXOUT_DIV : integer := 2; + TXPCSRESET_TIME : bit_vector := "00001"; + TXPHDLY_CFG : bit_vector := X"084020"; + TXPH_CFG : bit_vector := X"0780"; + TXPH_MONITOR_SEL : bit_vector := "00000"; + TXPI_CFG0 : bit_vector := "00"; + TXPI_CFG1 : bit_vector := "00"; + TXPI_CFG2 : bit_vector := "00"; + TXPI_CFG3 : bit := '0'; + TXPI_CFG4 : bit := '0'; + TXPI_CFG5 : bit_vector := "100"; + TXPI_GREY_SEL : bit := '0'; + TXPI_INVSTROBE_SEL : bit := '0'; + TXPI_PPMCLK_SEL : string := "TXUSRCLK2"; + TXPI_PPM_CFG : bit_vector := "00000000"; + TXPI_SYNFREQ_PPM : bit_vector := "000"; + TXPMARESET_TIME : bit_vector := "00001"; + TXSYNC_MULTILANE : bit := '0'; + TXSYNC_OVRD : bit := '0'; + TXSYNC_SKIP_DA : bit := '0'; + TX_CLK25_DIV : integer := 7; + TX_CLKMUX_PD : bit := '1'; + TX_DATA_WIDTH : integer := 20; + TX_DEEMPH0 : bit_vector := "000000"; + TX_DEEMPH1 : bit_vector := "000000"; + TX_DRIVE_MODE : string := "DIRECT"; + TX_EIDLE_ASSERT_DELAY : bit_vector := "110"; + TX_EIDLE_DEASSERT_DELAY : bit_vector := "100"; + TX_INT_DATAWIDTH : integer := 0; + TX_LOOPBACK_DRIVE_HIZ : string := "FALSE"; + TX_MAINCURSOR_SEL : bit := '0'; + TX_MARGIN_FULL_0 : bit_vector := "1001110"; + TX_MARGIN_FULL_1 : bit_vector := "1001001"; + TX_MARGIN_FULL_2 : bit_vector := "1000101"; + TX_MARGIN_FULL_3 : bit_vector := "1000010"; + TX_MARGIN_FULL_4 : bit_vector := "1000000"; + TX_MARGIN_LOW_0 : bit_vector := "1000110"; + TX_MARGIN_LOW_1 : bit_vector := "1000100"; + TX_MARGIN_LOW_2 : bit_vector := "1000010"; + TX_MARGIN_LOW_3 : bit_vector := "1000000"; + TX_MARGIN_LOW_4 : bit_vector := "1000000"; + TX_QPI_STATUS_EN : bit := '0'; + TX_RXDETECT_CFG : bit_vector := X"1832"; + TX_RXDETECT_PRECHARGE_TIME : bit_vector := X"00000"; + TX_RXDETECT_REF : bit_vector := "100"; + TX_XCLK_SEL : string := "TXUSR"; + UCODEER_CLR : bit := '0'; + USE_PCS_CLK_PHASE_SEL : bit := '0' + ); + + port ( + CPLLFBCLKLOST : out std_ulogic; + CPLLLOCK : out std_ulogic; + CPLLREFCLKLOST : out std_ulogic; + DMONITOROUT : out std_logic_vector(14 downto 0); + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_ulogic; + EYESCANDATAERROR : out std_ulogic; + GTHTXN : out std_ulogic; + GTHTXP : out std_ulogic; + GTREFCLKMONITOR : out std_ulogic; + PCSRSVDOUT : out std_logic_vector(15 downto 0); + PHYSTATUS : out std_ulogic; + RSOSINTDONE : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED : out std_ulogic; + RXBYTEREALIGN : out std_ulogic; + RXCDRLOCK : out std_ulogic; + RXCHANBONDSEQ : out std_ulogic; + RXCHANISALIGNED : out std_ulogic; + RXCHANREALIGN : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCHBONDO : out std_logic_vector(4 downto 0); + RXCLKCORCNT : out std_logic_vector(1 downto 0); + RXCOMINITDET : out std_ulogic; + RXCOMMADET : out std_ulogic; + RXCOMSASDET : out std_ulogic; + RXCOMWAKEDET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDATAVALID : out std_logic_vector(1 downto 0); + RXDFESLIDETAPSTARTED : out std_ulogic; + RXDFESLIDETAPSTROBEDONE : out std_ulogic; + RXDFESLIDETAPSTROBESTARTED : out std_ulogic; + RXDFESTADAPTDONE : out std_ulogic; + RXDISPERR : out std_logic_vector(7 downto 0); + RXDLYSRESETDONE : out std_ulogic; + RXELECIDLE : out std_ulogic; + RXHEADER : out std_logic_vector(5 downto 0); + RXHEADERVALID : out std_logic_vector(1 downto 0); + RXMONITOROUT : out std_logic_vector(6 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXOSINTSTARTED : out std_ulogic; + RXOSINTSTROBEDONE : out std_ulogic; + RXOSINTSTROBESTARTED : out std_ulogic; + RXOUTCLK : out std_ulogic; + RXOUTCLKFABRIC : out std_ulogic; + RXOUTCLKPCS : out std_ulogic; + RXPHALIGNDONE : out std_ulogic; + RXPHMONITOR : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR : out std_logic_vector(4 downto 0); + RXPMARESETDONE : out std_ulogic; + RXPRBSERR : out std_ulogic; + RXQPISENN : out std_ulogic; + RXQPISENP : out std_ulogic; + RXRATEDONE : out std_ulogic; + RXRESETDONE : out std_ulogic; + RXSTARTOFSEQ : out std_logic_vector(1 downto 0); + RXSTATUS : out std_logic_vector(2 downto 0); + RXSYNCDONE : out std_ulogic; + RXSYNCOUT : out std_ulogic; + RXVALID : out std_ulogic; + TXBUFSTATUS : out std_logic_vector(1 downto 0); + TXCOMFINISH : out std_ulogic; + TXDLYSRESETDONE : out std_ulogic; + TXGEARBOXREADY : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXOUTCLKFABRIC : out std_ulogic; + TXOUTCLKPCS : out std_ulogic; + TXPHALIGNDONE : out std_ulogic; + TXPHINITDONE : out std_ulogic; + TXPMARESETDONE : out std_ulogic; + TXQPISENN : out std_ulogic; + TXQPISENP : out std_ulogic; + TXRATEDONE : out std_ulogic; + TXRESETDONE : out std_ulogic; + TXSYNCDONE : out std_ulogic; + TXSYNCOUT : out std_ulogic; + CFGRESET : in std_ulogic; + CLKRSVD0 : in std_ulogic; + CLKRSVD1 : in std_ulogic; + CPLLLOCKDETCLK : in std_ulogic; + CPLLLOCKEN : in std_ulogic; + CPLLPD : in std_ulogic; + CPLLREFCLKSEL : in std_logic_vector(2 downto 0); + CPLLRESET : in std_ulogic; + DMONFIFORESET : in std_ulogic; + DMONITORCLK : in std_ulogic; + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_ulogic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_ulogic; + DRPWE : in std_ulogic; + EYESCANMODE : in std_ulogic; + EYESCANRESET : in std_ulogic; + EYESCANTRIGGER : in std_ulogic; + GTGREFCLK : in std_ulogic; + GTHRXN : in std_ulogic; + GTHRXP : in std_ulogic; + GTNORTHREFCLK0 : in std_ulogic; + GTNORTHREFCLK1 : in std_ulogic; + GTREFCLK0 : in std_ulogic; + GTREFCLK1 : in std_ulogic; + GTRESETSEL : in std_ulogic; + GTRSVD : in std_logic_vector(15 downto 0); + GTRXRESET : in std_ulogic; + GTSOUTHREFCLK0 : in std_ulogic; + GTSOUTHREFCLK1 : in std_ulogic; + GTTXRESET : in std_ulogic; + LOOPBACK : in std_logic_vector(2 downto 0); + PCSRSVDIN : in std_logic_vector(15 downto 0); + PCSRSVDIN2 : in std_logic_vector(4 downto 0); + PMARSVDIN : in std_logic_vector(4 downto 0); + QPLLCLK : in std_ulogic; + QPLLREFCLK : in std_ulogic; + RESETOVRD : in std_ulogic; + RX8B10BEN : in std_ulogic; + RXADAPTSELTEST : in std_logic_vector(13 downto 0); + RXBUFRESET : in std_ulogic; + RXCDRFREQRESET : in std_ulogic; + RXCDRHOLD : in std_ulogic; + RXCDROVRDEN : in std_ulogic; + RXCDRRESET : in std_ulogic; + RXCDRRESETRSV : in std_ulogic; + RXCHBONDEN : in std_ulogic; + RXCHBONDI : in std_logic_vector(4 downto 0); + RXCHBONDLEVEL : in std_logic_vector(2 downto 0); + RXCHBONDMASTER : in std_ulogic; + RXCHBONDSLAVE : in std_ulogic; + RXCOMMADETEN : in std_ulogic; + RXDDIEN : in std_ulogic; + RXDFEAGCHOLD : in std_ulogic; + RXDFEAGCOVRDEN : in std_ulogic; + RXDFEAGCTRL : in std_logic_vector(4 downto 0); + RXDFECM1EN : in std_ulogic; + RXDFELFHOLD : in std_ulogic; + RXDFELFOVRDEN : in std_ulogic; + RXDFELPMRESET : in std_ulogic; + RXDFESLIDETAP : in std_logic_vector(4 downto 0); + RXDFESLIDETAPADAPTEN : in std_ulogic; + RXDFESLIDETAPHOLD : in std_ulogic; + RXDFESLIDETAPID : in std_logic_vector(5 downto 0); + RXDFESLIDETAPINITOVRDEN : in std_ulogic; + RXDFESLIDETAPONLYADAPTEN : in std_ulogic; + RXDFESLIDETAPOVRDEN : in std_ulogic; + RXDFESLIDETAPSTROBE : in std_ulogic; + RXDFETAP2HOLD : in std_ulogic; + RXDFETAP2OVRDEN : in std_ulogic; + RXDFETAP3HOLD : in std_ulogic; + RXDFETAP3OVRDEN : in std_ulogic; + RXDFETAP4HOLD : in std_ulogic; + RXDFETAP4OVRDEN : in std_ulogic; + RXDFETAP5HOLD : in std_ulogic; + RXDFETAP5OVRDEN : in std_ulogic; + RXDFETAP6HOLD : in std_ulogic; + RXDFETAP6OVRDEN : in std_ulogic; + RXDFETAP7HOLD : in std_ulogic; + RXDFETAP7OVRDEN : in std_ulogic; + RXDFEUTHOLD : in std_ulogic; + RXDFEUTOVRDEN : in std_ulogic; + RXDFEVPHOLD : in std_ulogic; + RXDFEVPOVRDEN : in std_ulogic; + RXDFEVSEN : in std_ulogic; + RXDFEXYDEN : in std_ulogic; + RXDLYBYPASS : in std_ulogic; + RXDLYEN : in std_ulogic; + RXDLYOVRDEN : in std_ulogic; + RXDLYSRESET : in std_ulogic; + RXELECIDLEMODE : in std_logic_vector(1 downto 0); + RXGEARBOXSLIP : in std_ulogic; + RXLPMEN : in std_ulogic; + RXLPMHFHOLD : in std_ulogic; + RXLPMHFOVRDEN : in std_ulogic; + RXLPMLFHOLD : in std_ulogic; + RXLPMLFKLOVRDEN : in std_ulogic; + RXMCOMMAALIGNEN : in std_ulogic; + RXMONITORSEL : in std_logic_vector(1 downto 0); + RXOOBRESET : in std_ulogic; + RXOSCALRESET : in std_ulogic; + RXOSHOLD : in std_ulogic; + RXOSINTCFG : in std_logic_vector(3 downto 0); + RXOSINTEN : in std_ulogic; + RXOSINTHOLD : in std_ulogic; + RXOSINTID0 : in std_logic_vector(3 downto 0); + RXOSINTNTRLEN : in std_ulogic; + RXOSINTOVRDEN : in std_ulogic; + RXOSINTSTROBE : in std_ulogic; + RXOSINTTESTOVRDEN : in std_ulogic; + RXOSOVRDEN : in std_ulogic; + RXOUTCLKSEL : in std_logic_vector(2 downto 0); + RXPCOMMAALIGNEN : in std_ulogic; + RXPCSRESET : in std_ulogic; + RXPD : in std_logic_vector(1 downto 0); + RXPHALIGN : in std_ulogic; + RXPHALIGNEN : in std_ulogic; + RXPHDLYPD : in std_ulogic; + RXPHDLYRESET : in std_ulogic; + RXPHOVRDEN : in std_ulogic; + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXPRBSCNTRESET : in std_ulogic; + RXPRBSSEL : in std_logic_vector(2 downto 0); + RXQPIEN : in std_ulogic; + RXRATE : in std_logic_vector(2 downto 0); + RXRATEMODE : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNCALLIN : in std_ulogic; + RXSYNCIN : in std_ulogic; + RXSYNCMODE : in std_ulogic; + RXSYSCLKSEL : in std_logic_vector(1 downto 0); + RXUSERRDY : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + SETERRSTATUS : in std_ulogic; + SIGVALIDCLK : in std_ulogic; + TSTIN : in std_logic_vector(19 downto 0); + TX8B10BBYPASS : in std_logic_vector(7 downto 0); + TX8B10BEN : in std_ulogic; + TXBUFDIFFCTRL : in std_logic_vector(2 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCOMINIT : in std_ulogic; + TXCOMSAS : in std_ulogic; + TXCOMWAKE : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDEEMPH : in std_ulogic; + TXDETECTRX : in std_ulogic; + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXDIFFPD : in std_ulogic; + TXDLYBYPASS : in std_ulogic; + TXDLYEN : in std_ulogic; + TXDLYHOLD : in std_ulogic; + TXDLYOVRDEN : in std_ulogic; + TXDLYSRESET : in std_ulogic; + TXDLYUPDOWN : in std_ulogic; + TXELECIDLE : in std_ulogic; + TXHEADER : in std_logic_vector(2 downto 0); + TXINHIBIT : in std_ulogic; + TXMAINCURSOR : in std_logic_vector(6 downto 0); + TXMARGIN : in std_logic_vector(2 downto 0); + TXOUTCLKSEL : in std_logic_vector(2 downto 0); + TXPCSRESET : in std_ulogic; + TXPD : in std_logic_vector(1 downto 0); + TXPDELECIDLEMODE : in std_ulogic; + TXPHALIGN : in std_ulogic; + TXPHALIGNEN : in std_ulogic; + TXPHDLYPD : in std_ulogic; + TXPHDLYRESET : in std_ulogic; + TXPHDLYTSTCLK : in std_ulogic; + TXPHINIT : in std_ulogic; + TXPHOVRDEN : in std_ulogic; + TXPIPPMEN : in std_ulogic; + TXPIPPMOVRDEN : in std_ulogic; + TXPIPPMPD : in std_ulogic; + TXPIPPMSEL : in std_ulogic; + TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0); + TXPISOPD : in std_ulogic; + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPOSTCURSORINV : in std_ulogic; + TXPRBSFORCEERR : in std_ulogic; + TXPRBSSEL : in std_logic_vector(2 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0); + TXPRECURSORINV : in std_ulogic; + TXQPIBIASEN : in std_ulogic; + TXQPISTRONGPDOWN : in std_ulogic; + TXQPIWEAKPUP : in std_ulogic; + TXRATE : in std_logic_vector(2 downto 0); + TXRATEMODE : in std_ulogic; + TXSEQUENCE : in std_logic_vector(6 downto 0); + TXSTARTSEQ : in std_ulogic; + TXSWING : in std_ulogic; + TXSYNCALLIN : in std_ulogic; + TXSYNCIN : in std_ulogic; + TXSYNCMODE : in std_ulogic; + TXSYSCLKSEL : in std_logic_vector(1 downto 0); + TXUSERRDY : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); + end GTHE2_CHANNEL; + + architecture GTHE2_CHANNEL_FAST_V of GTHE2_CHANNEL is + component GTHE2_CHANNEL_FAST_WRAP + generic ( + ACJTAG_DEBUG_MODE : string; + ACJTAG_MODE : string; + ACJTAG_RESET : string; + ADAPT_CFG0 : string; + ALIGN_COMMA_DOUBLE : string; + ALIGN_COMMA_ENABLE : string; + ALIGN_COMMA_WORD : integer; + ALIGN_MCOMMA_DET : string; + ALIGN_MCOMMA_VALUE : string; + ALIGN_PCOMMA_DET : string; + ALIGN_PCOMMA_VALUE : string; + A_RXOSCALRESET : string; + CBCC_DATA_SOURCE_SEL : string; + CFOK_CFG : string; + CFOK_CFG2 : string; + CFOK_CFG3 : string; + CHAN_BOND_KEEP_ALIGN : string; + CHAN_BOND_MAX_SKEW : integer; + CHAN_BOND_SEQ_1_1 : string; + CHAN_BOND_SEQ_1_2 : string; + CHAN_BOND_SEQ_1_3 : string; + CHAN_BOND_SEQ_1_4 : string; + CHAN_BOND_SEQ_1_ENABLE : string; + CHAN_BOND_SEQ_2_1 : string; + CHAN_BOND_SEQ_2_2 : string; + CHAN_BOND_SEQ_2_3 : string; + CHAN_BOND_SEQ_2_4 : string; + CHAN_BOND_SEQ_2_ENABLE : string; + CHAN_BOND_SEQ_2_USE : string; + CHAN_BOND_SEQ_LEN : integer; + CLK_CORRECT_USE : string; + CLK_COR_KEEP_IDLE : string; + CLK_COR_MAX_LAT : integer; + CLK_COR_MIN_LAT : integer; + CLK_COR_PRECEDENCE : string; + CLK_COR_REPEAT_WAIT : integer; + CLK_COR_SEQ_1_1 : string; + CLK_COR_SEQ_1_2 : string; + CLK_COR_SEQ_1_3 : string; + CLK_COR_SEQ_1_4 : string; + CLK_COR_SEQ_1_ENABLE : string; + CLK_COR_SEQ_2_1 : string; + CLK_COR_SEQ_2_2 : string; + CLK_COR_SEQ_2_3 : string; + CLK_COR_SEQ_2_4 : string; + CLK_COR_SEQ_2_ENABLE : string; + CLK_COR_SEQ_2_USE : string; + CLK_COR_SEQ_LEN : integer; + CPLL_CFG : string; + CPLL_FBDIV : integer; + CPLL_FBDIV_45 : integer; + CPLL_INIT_CFG : string; + CPLL_LOCK_CFG : string; + CPLL_REFCLK_DIV : integer; + DEC_MCOMMA_DETECT : string; + DEC_PCOMMA_DETECT : string; + DEC_VALID_COMMA_ONLY : string; + DMONITOR_CFG : string; + ES_CLK_PHASE_SEL : string; + ES_CONTROL : string; + ES_ERRDET_EN : string; + ES_EYE_SCAN_EN : string; + ES_HORZ_OFFSET : string; + ES_PMA_CFG : string; + ES_PRESCALE : string; + ES_QUALIFIER : string; + ES_QUAL_MASK : string; + ES_SDATA_MASK : string; + ES_VERT_OFFSET : string; + FTS_DESKEW_SEQ_ENABLE : string; + FTS_LANE_DESKEW_CFG : string; + FTS_LANE_DESKEW_EN : string; + GEARBOX_MODE : string; + LOOPBACK_CFG : string; + OUTREFCLK_SEL_INV : string; + PCS_PCIE_EN : string; + PCS_RSVD_ATTR : string; + PD_TRANS_TIME_FROM_P2 : string; + PD_TRANS_TIME_NONE_P2 : string; + PD_TRANS_TIME_TO_P2 : string; + PMA_RSV : string; + PMA_RSV2 : string; + PMA_RSV3 : string; + PMA_RSV4 : string; + PMA_RSV5 : string; + RESET_POWERSAVE_DISABLE : string; + RXBUFRESET_TIME : string; + RXBUF_ADDR_MODE : string; + RXBUF_EIDLE_HI_CNT : string; + RXBUF_EIDLE_LO_CNT : string; + RXBUF_EN : string; + RXBUF_RESET_ON_CB_CHANGE : string; + RXBUF_RESET_ON_COMMAALIGN : string; + RXBUF_RESET_ON_EIDLE : string; + RXBUF_RESET_ON_RATE_CHANGE : string; + RXBUF_THRESH_OVFLW : integer; + RXBUF_THRESH_OVRD : string; + RXBUF_THRESH_UNDFLW : integer; + RXCDRFREQRESET_TIME : string; + RXCDRPHRESET_TIME : string; + RXCDR_CFG : string; + RXCDR_FR_RESET_ON_EIDLE : string; + RXCDR_HOLD_DURING_EIDLE : string; + RXCDR_LOCK_CFG : string; + RXCDR_PH_RESET_ON_EIDLE : string; + RXDFELPMRESET_TIME : string; + RXDLY_CFG : string; + RXDLY_LCFG : string; + RXDLY_TAP_CFG : string; + RXGEARBOX_EN : string; + RXISCANRESET_TIME : string; + RXLPM_HF_CFG : string; + RXLPM_LF_CFG : string; + RXOOB_CFG : string; + RXOOB_CLK_CFG : string; + RXOSCALRESET_TIME : string; + RXOSCALRESET_TIMEOUT : string; + RXOUT_DIV : integer; + RXPCSRESET_TIME : string; + RXPHDLY_CFG : string; + RXPH_CFG : string; + RXPH_MONITOR_SEL : string; + RXPI_CFG0 : string; + RXPI_CFG1 : string; + RXPI_CFG2 : string; + RXPI_CFG3 : string; + RXPI_CFG4 : string; + RXPI_CFG5 : string; + RXPI_CFG6 : string; + RXPMARESET_TIME : string; + RXPRBS_ERR_LOOPBACK : string; + RXSLIDE_AUTO_WAIT : integer; + RXSLIDE_MODE : string; + RXSYNC_MULTILANE : string; + RXSYNC_OVRD : string; + RXSYNC_SKIP_DA : string; + RX_BIAS_CFG : string; + RX_BUFFER_CFG : string; + RX_CLK25_DIV : integer; + RX_CLKMUX_PD : string; + RX_CM_SEL : string; + RX_CM_TRIM : string; + RX_DATA_WIDTH : integer; + RX_DDI_SEL : string; + RX_DEBUG_CFG : string; + RX_DEFER_RESET_BUF_EN : string; + RX_DFELPM_CFG0 : string; + RX_DFELPM_CFG1 : string; + RX_DFELPM_KLKH_AGC_STUP_EN : string; + RX_DFE_AGC_CFG0 : string; + RX_DFE_AGC_CFG1 : string; + RX_DFE_AGC_CFG2 : string; + RX_DFE_AGC_OVRDEN : string; + RX_DFE_GAIN_CFG : string; + RX_DFE_H2_CFG : string; + RX_DFE_H3_CFG : string; + RX_DFE_H4_CFG : string; + RX_DFE_H5_CFG : string; + RX_DFE_H6_CFG : string; + RX_DFE_H7_CFG : string; + RX_DFE_KL_CFG : string; + RX_DFE_KL_LPM_KH_CFG0 : string; + RX_DFE_KL_LPM_KH_CFG1 : string; + RX_DFE_KL_LPM_KH_CFG2 : string; + RX_DFE_KL_LPM_KH_OVRDEN : string; + RX_DFE_KL_LPM_KL_CFG0 : string; + RX_DFE_KL_LPM_KL_CFG1 : string; + RX_DFE_KL_LPM_KL_CFG2 : string; + RX_DFE_KL_LPM_KL_OVRDEN : string; + RX_DFE_LPM_CFG : string; + RX_DFE_LPM_HOLD_DURING_EIDLE : string; + RX_DFE_ST_CFG : string; + RX_DFE_UT_CFG : string; + RX_DFE_VP_CFG : string; + RX_DISPERR_SEQ_MATCH : string; + RX_INT_DATAWIDTH : integer; + RX_OS_CFG : string; + RX_SIG_VALID_DLY : integer; + RX_XCLK_SEL : string; + SAS_MAX_COM : integer; + SAS_MIN_COM : integer; + SATA_BURST_SEQ_LEN : string; + SATA_BURST_VAL : string; + SATA_CPLL_CFG : string; + SATA_EIDLE_VAL : string; + SATA_MAX_BURST : integer; + SATA_MAX_INIT : integer; + SATA_MAX_WAKE : integer; + SATA_MIN_BURST : integer; + SATA_MIN_INIT : integer; + SATA_MIN_WAKE : integer; + SHOW_REALIGN_COMMA : string; + SIM_CPLLREFCLK_SEL : string; + SIM_RECEIVER_DETECT_PASS : string; + SIM_RESET_SPEEDUP : string; + SIM_TX_EIDLE_DRIVE_LEVEL : string; + SIM_VERSION : string; + TERM_RCAL_CFG : string; + TERM_RCAL_OVRD : string; + TRANS_TIME_RATE : string; + TST_RSV : string; + TXBUF_EN : string; + TXBUF_RESET_ON_RATE_CHANGE : string; + TXDLY_CFG : string; + TXDLY_LCFG : string; + TXDLY_TAP_CFG : string; + TXGEARBOX_EN : string; + TXOOB_CFG : string; + TXOUT_DIV : integer; + TXPCSRESET_TIME : string; + TXPHDLY_CFG : string; + TXPH_CFG : string; + TXPH_MONITOR_SEL : string; + TXPI_CFG0 : string; + TXPI_CFG1 : string; + TXPI_CFG2 : string; + TXPI_CFG3 : string; + TXPI_CFG4 : string; + TXPI_CFG5 : string; + TXPI_GREY_SEL : string; + TXPI_INVSTROBE_SEL : string; + TXPI_PPMCLK_SEL : string; + TXPI_PPM_CFG : string; + TXPI_SYNFREQ_PPM : string; + TXPMARESET_TIME : string; + TXSYNC_MULTILANE : string; + TXSYNC_OVRD : string; + TXSYNC_SKIP_DA : string; + TX_CLK25_DIV : integer; + TX_CLKMUX_PD : string; + TX_DATA_WIDTH : integer; + TX_DEEMPH0 : string; + TX_DEEMPH1 : string; + TX_DRIVE_MODE : string; + TX_EIDLE_ASSERT_DELAY : string; + TX_EIDLE_DEASSERT_DELAY : string; + TX_INT_DATAWIDTH : integer; + TX_LOOPBACK_DRIVE_HIZ : string; + TX_MAINCURSOR_SEL : string; + TX_MARGIN_FULL_0 : string; + TX_MARGIN_FULL_1 : string; + TX_MARGIN_FULL_2 : string; + TX_MARGIN_FULL_3 : string; + TX_MARGIN_FULL_4 : string; + TX_MARGIN_LOW_0 : string; + TX_MARGIN_LOW_1 : string; + TX_MARGIN_LOW_2 : string; + TX_MARGIN_LOW_3 : string; + TX_MARGIN_LOW_4 : string; + TX_QPI_STATUS_EN : string; + TX_RXDETECT_CFG : string; + TX_RXDETECT_PRECHARGE_TIME : string; + TX_RXDETECT_REF : string; + TX_XCLK_SEL : string; + UCODEER_CLR : string; + USE_PCS_CLK_PHASE_SEL : string + ); + + port ( + CPLLFBCLKLOST : out std_ulogic; + CPLLLOCK : out std_ulogic; + CPLLREFCLKLOST : out std_ulogic; + DMONITOROUT : out std_logic_vector(14 downto 0); + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_ulogic; + EYESCANDATAERROR : out std_ulogic; + GTHTXN : out std_ulogic; + GTHTXP : out std_ulogic; + GTREFCLKMONITOR : out std_ulogic; + PCSRSVDOUT : out std_logic_vector(15 downto 0); + PHYSTATUS : out std_ulogic; + RSOSINTDONE : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED : out std_ulogic; + RXBYTEREALIGN : out std_ulogic; + RXCDRLOCK : out std_ulogic; + RXCHANBONDSEQ : out std_ulogic; + RXCHANISALIGNED : out std_ulogic; + RXCHANREALIGN : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCHBONDO : out std_logic_vector(4 downto 0); + RXCLKCORCNT : out std_logic_vector(1 downto 0); + RXCOMINITDET : out std_ulogic; + RXCOMMADET : out std_ulogic; + RXCOMSASDET : out std_ulogic; + RXCOMWAKEDET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDATAVALID : out std_logic_vector(1 downto 0); + RXDFESLIDETAPSTARTED : out std_ulogic; + RXDFESLIDETAPSTROBEDONE : out std_ulogic; + RXDFESLIDETAPSTROBESTARTED : out std_ulogic; + RXDFESTADAPTDONE : out std_ulogic; + RXDISPERR : out std_logic_vector(7 downto 0); + RXDLYSRESETDONE : out std_ulogic; + RXELECIDLE : out std_ulogic; + RXHEADER : out std_logic_vector(5 downto 0); + RXHEADERVALID : out std_logic_vector(1 downto 0); + RXMONITOROUT : out std_logic_vector(6 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXOSINTSTARTED : out std_ulogic; + RXOSINTSTROBEDONE : out std_ulogic; + RXOSINTSTROBESTARTED : out std_ulogic; + RXOUTCLK : out std_ulogic; + RXOUTCLKFABRIC : out std_ulogic; + RXOUTCLKPCS : out std_ulogic; + RXPHALIGNDONE : out std_ulogic; + RXPHMONITOR : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR : out std_logic_vector(4 downto 0); + RXPMARESETDONE : out std_ulogic; + RXPRBSERR : out std_ulogic; + RXQPISENN : out std_ulogic; + RXQPISENP : out std_ulogic; + RXRATEDONE : out std_ulogic; + RXRESETDONE : out std_ulogic; + RXSTARTOFSEQ : out std_logic_vector(1 downto 0); + RXSTATUS : out std_logic_vector(2 downto 0); + RXSYNCDONE : out std_ulogic; + RXSYNCOUT : out std_ulogic; + RXVALID : out std_ulogic; + TXBUFSTATUS : out std_logic_vector(1 downto 0); + TXCOMFINISH : out std_ulogic; + TXDLYSRESETDONE : out std_ulogic; + TXGEARBOXREADY : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXOUTCLKFABRIC : out std_ulogic; + TXOUTCLKPCS : out std_ulogic; + TXPHALIGNDONE : out std_ulogic; + TXPHINITDONE : out std_ulogic; + TXPMARESETDONE : out std_ulogic; + TXQPISENN : out std_ulogic; + TXQPISENP : out std_ulogic; + TXRATEDONE : out std_ulogic; + TXRESETDONE : out std_ulogic; + TXSYNCDONE : out std_ulogic; + TXSYNCOUT : out std_ulogic; + + GSR : in std_ulogic; + CFGRESET : in std_ulogic; + CLKRSVD0 : in std_ulogic; + CLKRSVD1 : in std_ulogic; + CPLLLOCKDETCLK : in std_ulogic; + CPLLLOCKEN : in std_ulogic; + CPLLPD : in std_ulogic; + CPLLREFCLKSEL : in std_logic_vector(2 downto 0); + CPLLRESET : in std_ulogic; + DMONFIFORESET : in std_ulogic; + DMONITORCLK : in std_ulogic; + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_ulogic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_ulogic; + DRPWE : in std_ulogic; + EYESCANMODE : in std_ulogic; + EYESCANRESET : in std_ulogic; + EYESCANTRIGGER : in std_ulogic; + GTGREFCLK : in std_ulogic; + GTHRXN : in std_ulogic; + GTHRXP : in std_ulogic; + GTNORTHREFCLK0 : in std_ulogic; + GTNORTHREFCLK1 : in std_ulogic; + GTREFCLK0 : in std_ulogic; + GTREFCLK1 : in std_ulogic; + GTRESETSEL : in std_ulogic; + GTRSVD : in std_logic_vector(15 downto 0); + GTRXRESET : in std_ulogic; + GTSOUTHREFCLK0 : in std_ulogic; + GTSOUTHREFCLK1 : in std_ulogic; + GTTXRESET : in std_ulogic; + LOOPBACK : in std_logic_vector(2 downto 0); + PCSRSVDIN : in std_logic_vector(15 downto 0); + PCSRSVDIN2 : in std_logic_vector(4 downto 0); + PMARSVDIN : in std_logic_vector(4 downto 0); + QPLLCLK : in std_ulogic; + QPLLREFCLK : in std_ulogic; + RESETOVRD : in std_ulogic; + RX8B10BEN : in std_ulogic; + RXADAPTSELTEST : in std_logic_vector(13 downto 0); + RXBUFRESET : in std_ulogic; + RXCDRFREQRESET : in std_ulogic; + RXCDRHOLD : in std_ulogic; + RXCDROVRDEN : in std_ulogic; + RXCDRRESET : in std_ulogic; + RXCDRRESETRSV : in std_ulogic; + RXCHBONDEN : in std_ulogic; + RXCHBONDI : in std_logic_vector(4 downto 0); + RXCHBONDLEVEL : in std_logic_vector(2 downto 0); + RXCHBONDMASTER : in std_ulogic; + RXCHBONDSLAVE : in std_ulogic; + RXCOMMADETEN : in std_ulogic; + RXDDIEN : in std_ulogic; + RXDFEAGCHOLD : in std_ulogic; + RXDFEAGCOVRDEN : in std_ulogic; + RXDFEAGCTRL : in std_logic_vector(4 downto 0); + RXDFECM1EN : in std_ulogic; + RXDFELFHOLD : in std_ulogic; + RXDFELFOVRDEN : in std_ulogic; + RXDFELPMRESET : in std_ulogic; + RXDFESLIDETAP : in std_logic_vector(4 downto 0); + RXDFESLIDETAPADAPTEN : in std_ulogic; + RXDFESLIDETAPHOLD : in std_ulogic; + RXDFESLIDETAPID : in std_logic_vector(5 downto 0); + RXDFESLIDETAPINITOVRDEN : in std_ulogic; + RXDFESLIDETAPONLYADAPTEN : in std_ulogic; + RXDFESLIDETAPOVRDEN : in std_ulogic; + RXDFESLIDETAPSTROBE : in std_ulogic; + RXDFETAP2HOLD : in std_ulogic; + RXDFETAP2OVRDEN : in std_ulogic; + RXDFETAP3HOLD : in std_ulogic; + RXDFETAP3OVRDEN : in std_ulogic; + RXDFETAP4HOLD : in std_ulogic; + RXDFETAP4OVRDEN : in std_ulogic; + RXDFETAP5HOLD : in std_ulogic; + RXDFETAP5OVRDEN : in std_ulogic; + RXDFETAP6HOLD : in std_ulogic; + RXDFETAP6OVRDEN : in std_ulogic; + RXDFETAP7HOLD : in std_ulogic; + RXDFETAP7OVRDEN : in std_ulogic; + RXDFEUTHOLD : in std_ulogic; + RXDFEUTOVRDEN : in std_ulogic; + RXDFEVPHOLD : in std_ulogic; + RXDFEVPOVRDEN : in std_ulogic; + RXDFEVSEN : in std_ulogic; + RXDFEXYDEN : in std_ulogic; + RXDLYBYPASS : in std_ulogic; + RXDLYEN : in std_ulogic; + RXDLYOVRDEN : in std_ulogic; + RXDLYSRESET : in std_ulogic; + RXELECIDLEMODE : in std_logic_vector(1 downto 0); + RXGEARBOXSLIP : in std_ulogic; + RXLPMEN : in std_ulogic; + RXLPMHFHOLD : in std_ulogic; + RXLPMHFOVRDEN : in std_ulogic; + RXLPMLFHOLD : in std_ulogic; + RXLPMLFKLOVRDEN : in std_ulogic; + RXMCOMMAALIGNEN : in std_ulogic; + RXMONITORSEL : in std_logic_vector(1 downto 0); + RXOOBRESET : in std_ulogic; + RXOSCALRESET : in std_ulogic; + RXOSHOLD : in std_ulogic; + RXOSINTCFG : in std_logic_vector(3 downto 0); + RXOSINTEN : in std_ulogic; + RXOSINTHOLD : in std_ulogic; + RXOSINTID0 : in std_logic_vector(3 downto 0); + RXOSINTNTRLEN : in std_ulogic; + RXOSINTOVRDEN : in std_ulogic; + RXOSINTSTROBE : in std_ulogic; + RXOSINTTESTOVRDEN : in std_ulogic; + RXOSOVRDEN : in std_ulogic; + RXOUTCLKSEL : in std_logic_vector(2 downto 0); + RXPCOMMAALIGNEN : in std_ulogic; + RXPCSRESET : in std_ulogic; + RXPD : in std_logic_vector(1 downto 0); + RXPHALIGN : in std_ulogic; + RXPHALIGNEN : in std_ulogic; + RXPHDLYPD : in std_ulogic; + RXPHDLYRESET : in std_ulogic; + RXPHOVRDEN : in std_ulogic; + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXPRBSCNTRESET : in std_ulogic; + RXPRBSSEL : in std_logic_vector(2 downto 0); + RXQPIEN : in std_ulogic; + RXRATE : in std_logic_vector(2 downto 0); + RXRATEMODE : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNCALLIN : in std_ulogic; + RXSYNCIN : in std_ulogic; + RXSYNCMODE : in std_ulogic; + RXSYSCLKSEL : in std_logic_vector(1 downto 0); + RXUSERRDY : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + SETERRSTATUS : in std_ulogic; + SIGVALIDCLK : in std_ulogic; + TSTIN : in std_logic_vector(19 downto 0); + TX8B10BBYPASS : in std_logic_vector(7 downto 0); + TX8B10BEN : in std_ulogic; + TXBUFDIFFCTRL : in std_logic_vector(2 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCOMINIT : in std_ulogic; + TXCOMSAS : in std_ulogic; + TXCOMWAKE : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDEEMPH : in std_ulogic; + TXDETECTRX : in std_ulogic; + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXDIFFPD : in std_ulogic; + TXDLYBYPASS : in std_ulogic; + TXDLYEN : in std_ulogic; + TXDLYHOLD : in std_ulogic; + TXDLYOVRDEN : in std_ulogic; + TXDLYSRESET : in std_ulogic; + TXDLYUPDOWN : in std_ulogic; + TXELECIDLE : in std_ulogic; + TXHEADER : in std_logic_vector(2 downto 0); + TXINHIBIT : in std_ulogic; + TXMAINCURSOR : in std_logic_vector(6 downto 0); + TXMARGIN : in std_logic_vector(2 downto 0); + TXOUTCLKSEL : in std_logic_vector(2 downto 0); + TXPCSRESET : in std_ulogic; + TXPD : in std_logic_vector(1 downto 0); + TXPDELECIDLEMODE : in std_ulogic; + TXPHALIGN : in std_ulogic; + TXPHALIGNEN : in std_ulogic; + TXPHDLYPD : in std_ulogic; + TXPHDLYRESET : in std_ulogic; + TXPHDLYTSTCLK : in std_ulogic; + TXPHINIT : in std_ulogic; + TXPHOVRDEN : in std_ulogic; + TXPIPPMEN : in std_ulogic; + TXPIPPMOVRDEN : in std_ulogic; + TXPIPPMPD : in std_ulogic; + TXPIPPMSEL : in std_ulogic; + TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0); + TXPISOPD : in std_ulogic; + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPOSTCURSORINV : in std_ulogic; + TXPRBSFORCEERR : in std_ulogic; + TXPRBSSEL : in std_logic_vector(2 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0); + TXPRECURSORINV : in std_ulogic; + TXQPIBIASEN : in std_ulogic; + TXQPISTRONGPDOWN : in std_ulogic; + TXQPIWEAKPUP : in std_ulogic; + TXRATE : in std_logic_vector(2 downto 0); + TXRATEMODE : in std_ulogic; + TXSEQUENCE : in std_logic_vector(6 downto 0); + TXSTARTSEQ : in std_ulogic; + TXSWING : in std_ulogic; + TXSYNCALLIN : in std_ulogic; + TXSYNCIN : in std_ulogic; + TXSYNCMODE : in std_ulogic; + TXSYSCLKSEL : in std_logic_vector(1 downto 0); + TXUSERRDY : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant INCLK_DELAY : time := 0 ps; + constant OUTCLK_DELAY : time := 0 ps; + + function SUL_TO_STR (sul : std_ulogic) + return string is + begin + if sul = '0' then + return "0"; + else + return "1"; + end if; + end SUL_TO_STR; + + function boolean_to_string(bool: boolean) + return string is + begin + if bool then + return "TRUE"; + else + return "FALSE"; + end if; + end boolean_to_string; + + function getstrlength(in_vec : std_logic_vector) + return integer is + variable string_length : integer; + begin + if ((in_vec'length mod 4) = 0) then + string_length := in_vec'length/4; + elsif ((in_vec'length mod 4) > 0) then + string_length := in_vec'length/4 + 1; + end if; + return string_length; + end getstrlength; + + -- Convert bit_vector to std_logic_vector + constant ACJTAG_DEBUG_MODE_BINARY : std_ulogic := To_StduLogic(ACJTAG_DEBUG_MODE); + constant ACJTAG_MODE_BINARY : std_ulogic := To_StduLogic(ACJTAG_MODE); + constant ACJTAG_RESET_BINARY : std_ulogic := To_StduLogic(ACJTAG_RESET); + constant ADAPT_CFG0_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(ADAPT_CFG0)(19 downto 0); + constant ALIGN_COMMA_ENABLE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_COMMA_ENABLE)(9 downto 0); + constant ALIGN_MCOMMA_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_MCOMMA_VALUE)(9 downto 0); + constant ALIGN_PCOMMA_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_PCOMMA_VALUE)(9 downto 0); + constant A_RXOSCALRESET_BINARY : std_ulogic := To_StduLogic(A_RXOSCALRESET); + constant CFOK_CFG2_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(CFOK_CFG2)(5 downto 0); + constant CFOK_CFG3_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(CFOK_CFG3)(5 downto 0); + constant CFOK_CFG_BINARY : std_logic_vector(41 downto 0) := To_StdLogicVector(CFOK_CFG)(41 downto 0); + constant CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1)(9 downto 0); + constant CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2)(9 downto 0); + constant CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3)(9 downto 0); + constant CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4)(9 downto 0); + constant CHAN_BOND_SEQ_1_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE)(3 downto 0); + constant CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1)(9 downto 0); + constant CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2)(9 downto 0); + constant CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3)(9 downto 0); + constant CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4)(9 downto 0); + constant CHAN_BOND_SEQ_2_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE)(3 downto 0); + constant CLK_COR_SEQ_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1)(9 downto 0); + constant CLK_COR_SEQ_1_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2)(9 downto 0); + constant CLK_COR_SEQ_1_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3)(9 downto 0); + constant CLK_COR_SEQ_1_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4)(9 downto 0); + constant CLK_COR_SEQ_1_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE)(3 downto 0); + constant CLK_COR_SEQ_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1)(9 downto 0); + constant CLK_COR_SEQ_2_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2)(9 downto 0); + constant CLK_COR_SEQ_2_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3)(9 downto 0); + constant CLK_COR_SEQ_2_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4)(9 downto 0); + constant CLK_COR_SEQ_2_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE)(3 downto 0); + constant CPLL_CFG_BINARY : std_logic_vector(28 downto 0) := To_StdLogicVector(CPLL_CFG)(28 downto 0); + constant CPLL_INIT_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CPLL_INIT_CFG)(23 downto 0); + constant CPLL_LOCK_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(CPLL_LOCK_CFG)(15 downto 0); + constant DMONITOR_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(DMONITOR_CFG)(23 downto 0); + constant ES_CLK_PHASE_SEL_BINARY : std_ulogic := To_StduLogic(ES_CLK_PHASE_SEL); + constant ES_CONTROL_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(ES_CONTROL)(5 downto 0); + constant ES_HORZ_OFFSET_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(ES_HORZ_OFFSET)(11 downto 0); + constant ES_PMA_CFG_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ES_PMA_CFG)(9 downto 0); + constant ES_PRESCALE_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(ES_PRESCALE)(4 downto 0); + constant ES_QUALIFIER_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_QUALIFIER)(79 downto 0); + constant ES_QUAL_MASK_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_QUAL_MASK)(79 downto 0); + constant ES_SDATA_MASK_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_SDATA_MASK)(79 downto 0); + constant ES_VERT_OFFSET_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(ES_VERT_OFFSET)(8 downto 0); + constant FTS_DESKEW_SEQ_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(FTS_DESKEW_SEQ_ENABLE)(3 downto 0); + constant FTS_LANE_DESKEW_CFG_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(FTS_LANE_DESKEW_CFG)(3 downto 0); + constant GEARBOX_MODE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_MODE)(2 downto 0); + constant LOOPBACK_CFG_BINARY : std_ulogic := To_StduLogic(LOOPBACK_CFG); + constant OUTREFCLK_SEL_INV_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(OUTREFCLK_SEL_INV)(1 downto 0); + constant PCS_RSVD_ATTR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(PCS_RSVD_ATTR)(47 downto 0); + constant PD_TRANS_TIME_FROM_P2_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PD_TRANS_TIME_FROM_P2)(11 downto 0); + constant PD_TRANS_TIME_NONE_P2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PD_TRANS_TIME_NONE_P2)(7 downto 0); + constant PD_TRANS_TIME_TO_P2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PD_TRANS_TIME_TO_P2)(7 downto 0); + constant PMA_RSV2_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PMA_RSV2)(31 downto 0); + constant PMA_RSV3_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PMA_RSV3)(1 downto 0); + constant PMA_RSV4_BINARY : std_logic_vector(14 downto 0) := To_StdLogicVector(PMA_RSV4)(14 downto 0); + constant PMA_RSV5_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(PMA_RSV5)(3 downto 0); + constant PMA_RSV_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PMA_RSV)(31 downto 0); + constant RESET_POWERSAVE_DISABLE_BINARY : std_ulogic := To_StduLogic(RESET_POWERSAVE_DISABLE); + constant RXBUFRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXBUFRESET_TIME)(4 downto 0); + constant RXBUF_EIDLE_HI_CNT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXBUF_EIDLE_HI_CNT)(3 downto 0); + constant RXBUF_EIDLE_LO_CNT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXBUF_EIDLE_LO_CNT)(3 downto 0); + constant RXCDRFREQRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXCDRFREQRESET_TIME)(4 downto 0); + constant RXCDRPHRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXCDRPHRESET_TIME)(4 downto 0); + constant RXCDR_CFG_BINARY : std_logic_vector(82 downto 0) := To_StdLogicVector(RXCDR_CFG)(82 downto 0); + constant RXCDR_FR_RESET_ON_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_FR_RESET_ON_EIDLE); + constant RXCDR_HOLD_DURING_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_HOLD_DURING_EIDLE); + constant RXCDR_LOCK_CFG_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCDR_LOCK_CFG)(5 downto 0); + constant RXCDR_PH_RESET_ON_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_PH_RESET_ON_EIDLE); + constant RXDFELPMRESET_TIME_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(RXDFELPMRESET_TIME)(6 downto 0); + constant RXDLY_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RXDLY_CFG)(15 downto 0); + constant RXDLY_LCFG_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(RXDLY_LCFG)(8 downto 0); + constant RXDLY_TAP_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RXDLY_TAP_CFG)(15 downto 0); + constant RXISCANRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXISCANRESET_TIME)(4 downto 0); + constant RXLPM_HF_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(RXLPM_HF_CFG)(13 downto 0); + constant RXLPM_LF_CFG_BINARY : std_logic_vector(17 downto 0) := To_StdLogicVector(RXLPM_LF_CFG)(17 downto 0); + constant RXOOB_CFG_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(RXOOB_CFG)(6 downto 0); + constant RXOSCALRESET_TIMEOUT_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXOSCALRESET_TIMEOUT)(4 downto 0); + constant RXOSCALRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXOSCALRESET_TIME)(4 downto 0); + constant RXPCSRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPCSRESET_TIME)(4 downto 0); + constant RXPHDLY_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(RXPHDLY_CFG)(23 downto 0); + constant RXPH_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(RXPH_CFG)(23 downto 0); + constant RXPH_MONITOR_SEL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPH_MONITOR_SEL)(4 downto 0); + constant RXPI_CFG0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXPI_CFG0)(1 downto 0); + constant RXPI_CFG1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXPI_CFG1)(1 downto 0); + constant RXPI_CFG2_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXPI_CFG2)(1 downto 0); + constant RXPI_CFG3_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXPI_CFG3)(1 downto 0); + constant RXPI_CFG4_BINARY : std_ulogic := To_StduLogic(RXPI_CFG4); + constant RXPI_CFG5_BINARY : std_ulogic := To_StduLogic(RXPI_CFG5); + constant RXPI_CFG6_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXPI_CFG6)(2 downto 0); + constant RXPMARESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPMARESET_TIME)(4 downto 0); + constant RXPRBS_ERR_LOOPBACK_BINARY : std_ulogic := To_StduLogic(RXPRBS_ERR_LOOPBACK); + constant RXSYNC_MULTILANE_BINARY : std_ulogic := To_StduLogic(RXSYNC_MULTILANE); + constant RXSYNC_OVRD_BINARY : std_ulogic := To_StduLogic(RXSYNC_OVRD); + constant RXSYNC_SKIP_DA_BINARY : std_ulogic := To_StduLogic(RXSYNC_SKIP_DA); + constant RX_BIAS_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(RX_BIAS_CFG)(23 downto 0); + constant RX_BUFFER_CFG_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RX_BUFFER_CFG)(5 downto 0); + constant RX_CLKMUX_PD_BINARY : std_ulogic := To_StduLogic(RX_CLKMUX_PD); + constant RX_CM_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_CM_SEL)(1 downto 0); + constant RX_CM_TRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_CM_TRIM)(3 downto 0); + constant RX_DDI_SEL_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RX_DDI_SEL)(5 downto 0); + constant RX_DEBUG_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(RX_DEBUG_CFG)(13 downto 0); + constant RX_DFELPM_CFG0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_DFELPM_CFG0)(3 downto 0); + constant RX_DFELPM_CFG1_BINARY : std_ulogic := To_StduLogic(RX_DFELPM_CFG1); + constant RX_DFELPM_KLKH_AGC_STUP_EN_BINARY : std_ulogic := To_StduLogic(RX_DFELPM_KLKH_AGC_STUP_EN); + constant RX_DFE_AGC_CFG0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_DFE_AGC_CFG0)(1 downto 0); + constant RX_DFE_AGC_CFG1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RX_DFE_AGC_CFG1)(2 downto 0); + constant RX_DFE_AGC_CFG2_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_DFE_AGC_CFG2)(3 downto 0); + constant RX_DFE_AGC_OVRDEN_BINARY : std_ulogic := To_StduLogic(RX_DFE_AGC_OVRDEN); + constant RX_DFE_GAIN_CFG_BINARY : std_logic_vector(22 downto 0) := To_StdLogicVector(RX_DFE_GAIN_CFG)(22 downto 0); + constant RX_DFE_H2_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_DFE_H2_CFG)(11 downto 0); + constant RX_DFE_H3_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_DFE_H3_CFG)(11 downto 0); + constant RX_DFE_H4_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H4_CFG)(10 downto 0); + constant RX_DFE_H5_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H5_CFG)(10 downto 0); + constant RX_DFE_H6_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H6_CFG)(10 downto 0); + constant RX_DFE_H7_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H7_CFG)(10 downto 0); + constant RX_DFE_KL_CFG_BINARY : std_logic_vector(32 downto 0) := To_StdLogicVector(RX_DFE_KL_CFG)(32 downto 0); + constant RX_DFE_KL_LPM_KH_CFG0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KH_CFG0)(1 downto 0); + constant RX_DFE_KL_LPM_KH_CFG1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KH_CFG1)(2 downto 0); + constant RX_DFE_KL_LPM_KH_CFG2_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KH_CFG2)(3 downto 0); + constant RX_DFE_KL_LPM_KH_OVRDEN_BINARY : std_ulogic := To_StduLogic(RX_DFE_KL_LPM_KH_OVRDEN); + constant RX_DFE_KL_LPM_KL_CFG0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KL_CFG0)(1 downto 0); + constant RX_DFE_KL_LPM_KL_CFG1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KL_CFG1)(2 downto 0); + constant RX_DFE_KL_LPM_KL_CFG2_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_DFE_KL_LPM_KL_CFG2)(3 downto 0); + constant RX_DFE_KL_LPM_KL_OVRDEN_BINARY : std_ulogic := To_StduLogic(RX_DFE_KL_LPM_KL_OVRDEN); + constant RX_DFE_LPM_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RX_DFE_LPM_CFG)(15 downto 0); + constant RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY : std_ulogic := To_StduLogic(RX_DFE_LPM_HOLD_DURING_EIDLE); + constant RX_DFE_ST_CFG_BINARY : std_logic_vector(53 downto 0) := To_StdLogicVector(RX_DFE_ST_CFG)(53 downto 0); + constant RX_DFE_UT_CFG_BINARY : std_logic_vector(16 downto 0) := To_StdLogicVector(RX_DFE_UT_CFG)(16 downto 0); + constant RX_DFE_VP_CFG_BINARY : std_logic_vector(16 downto 0) := To_StdLogicVector(RX_DFE_VP_CFG)(16 downto 0); + constant RX_OS_CFG_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RX_OS_CFG)(12 downto 0); + constant SATA_BURST_SEQ_LEN_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(SATA_BURST_SEQ_LEN)(3 downto 0); + constant SATA_BURST_VAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL)(2 downto 0); + constant SATA_EIDLE_VAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_EIDLE_VAL)(2 downto 0); + constant SIM_CPLLREFCLK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SIM_CPLLREFCLK_SEL)(2 downto 0); + constant TERM_RCAL_CFG_BINARY : std_logic_vector(14 downto 0) := To_StdLogicVector(TERM_RCAL_CFG)(14 downto 0); + constant TERM_RCAL_OVRD_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TERM_RCAL_OVRD)(2 downto 0); + constant TRANS_TIME_RATE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_RATE)(7 downto 0); + constant TST_RSV_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(TST_RSV)(31 downto 0); + constant TXDLY_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXDLY_CFG)(15 downto 0); + constant TXDLY_LCFG_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(TXDLY_LCFG)(8 downto 0); + constant TXDLY_TAP_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXDLY_TAP_CFG)(15 downto 0); + constant TXOOB_CFG_BINARY : std_ulogic := To_StduLogic(TXOOB_CFG); + constant TXPCSRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPCSRESET_TIME)(4 downto 0); + constant TXPHDLY_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(TXPHDLY_CFG)(23 downto 0); + constant TXPH_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXPH_CFG)(15 downto 0); + constant TXPH_MONITOR_SEL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPH_MONITOR_SEL)(4 downto 0); + constant TXPI_CFG0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXPI_CFG0)(1 downto 0); + constant TXPI_CFG1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXPI_CFG1)(1 downto 0); + constant TXPI_CFG2_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXPI_CFG2)(1 downto 0); + constant TXPI_CFG3_BINARY : std_ulogic := To_StduLogic(TXPI_CFG3); + constant TXPI_CFG4_BINARY : std_ulogic := To_StduLogic(TXPI_CFG4); + constant TXPI_CFG5_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPI_CFG5)(2 downto 0); + constant TXPI_GREY_SEL_BINARY : std_ulogic := To_StduLogic(TXPI_GREY_SEL); + constant TXPI_INVSTROBE_SEL_BINARY : std_ulogic := To_StduLogic(TXPI_INVSTROBE_SEL); + constant TXPI_PPM_CFG_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TXPI_PPM_CFG)(7 downto 0); + constant TXPI_SYNFREQ_PPM_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPI_SYNFREQ_PPM)(2 downto 0); + constant TXPMARESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPMARESET_TIME)(4 downto 0); + constant TXSYNC_MULTILANE_BINARY : std_ulogic := To_StduLogic(TXSYNC_MULTILANE); + constant TXSYNC_OVRD_BINARY : std_ulogic := To_StduLogic(TXSYNC_OVRD); + constant TXSYNC_SKIP_DA_BINARY : std_ulogic := To_StduLogic(TXSYNC_SKIP_DA); + constant TX_CLKMUX_PD_BINARY : std_ulogic := To_StduLogic(TX_CLKMUX_PD); + constant TX_DEEMPH0_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(TX_DEEMPH0)(5 downto 0); + constant TX_DEEMPH1_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(TX_DEEMPH1)(5 downto 0); + constant TX_EIDLE_ASSERT_DELAY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_EIDLE_ASSERT_DELAY)(2 downto 0); + constant TX_EIDLE_DEASSERT_DELAY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_EIDLE_DEASSERT_DELAY)(2 downto 0); + constant TX_MAINCURSOR_SEL_BINARY : std_ulogic := To_StduLogic(TX_MAINCURSOR_SEL); + constant TX_MARGIN_FULL_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_0)(6 downto 0); + constant TX_MARGIN_FULL_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_1)(6 downto 0); + constant TX_MARGIN_FULL_2_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_2)(6 downto 0); + constant TX_MARGIN_FULL_3_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_3)(6 downto 0); + constant TX_MARGIN_FULL_4_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_4)(6 downto 0); + constant TX_MARGIN_LOW_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_0)(6 downto 0); + constant TX_MARGIN_LOW_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_1)(6 downto 0); + constant TX_MARGIN_LOW_2_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_2)(6 downto 0); + constant TX_MARGIN_LOW_3_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_3)(6 downto 0); + constant TX_MARGIN_LOW_4_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_4)(6 downto 0); + constant TX_QPI_STATUS_EN_BINARY : std_ulogic := To_StduLogic(TX_QPI_STATUS_EN); + constant TX_RXDETECT_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_RXDETECT_CFG)(13 downto 0); + constant TX_RXDETECT_PRECHARGE_TIME_BINARY : std_logic_vector(16 downto 0) := To_StdLogicVector(TX_RXDETECT_PRECHARGE_TIME)(16 downto 0); + constant TX_RXDETECT_REF_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_RXDETECT_REF)(2 downto 0); + constant UCODEER_CLR_BINARY : std_ulogic := To_StduLogic(UCODEER_CLR); + constant USE_PCS_CLK_PHASE_SEL_BINARY : std_ulogic := To_StduLogic(USE_PCS_CLK_PHASE_SEL); + + -- Get String Length + constant ADAPT_CFG0_STRLEN : integer := getstrlength(ADAPT_CFG0_BINARY); + constant CFOK_CFG_STRLEN : integer := getstrlength(CFOK_CFG_BINARY); + constant CPLL_CFG_STRLEN : integer := getstrlength(CPLL_CFG_BINARY); + constant CPLL_INIT_CFG_STRLEN : integer := getstrlength(CPLL_INIT_CFG_BINARY); + constant CPLL_LOCK_CFG_STRLEN : integer := getstrlength(CPLL_LOCK_CFG_BINARY); + constant DMONITOR_CFG_STRLEN : integer := getstrlength(DMONITOR_CFG_BINARY); + constant ES_HORZ_OFFSET_STRLEN : integer := getstrlength(ES_HORZ_OFFSET_BINARY); + constant ES_QUALIFIER_STRLEN : integer := getstrlength(ES_QUALIFIER_BINARY); + constant ES_QUAL_MASK_STRLEN : integer := getstrlength(ES_QUAL_MASK_BINARY); + constant ES_SDATA_MASK_STRLEN : integer := getstrlength(ES_SDATA_MASK_BINARY); + constant PCS_RSVD_ATTR_STRLEN : integer := getstrlength(PCS_RSVD_ATTR_BINARY); + constant PD_TRANS_TIME_FROM_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_FROM_P2_BINARY); + constant PD_TRANS_TIME_NONE_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_NONE_P2_BINARY); + constant PD_TRANS_TIME_TO_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_TO_P2_BINARY); + constant RXCDR_CFG_STRLEN : integer := getstrlength(RXCDR_CFG_BINARY); + constant RXDLY_CFG_STRLEN : integer := getstrlength(RXDLY_CFG_BINARY); + constant RXDLY_LCFG_STRLEN : integer := getstrlength(RXDLY_LCFG_BINARY); + constant RXDLY_TAP_CFG_STRLEN : integer := getstrlength(RXDLY_TAP_CFG_BINARY); + constant RXPHDLY_CFG_STRLEN : integer := getstrlength(RXPHDLY_CFG_BINARY); + constant RXPH_CFG_STRLEN : integer := getstrlength(RXPH_CFG_BINARY); + constant RX_DFE_GAIN_CFG_STRLEN : integer := getstrlength(RX_DFE_GAIN_CFG_BINARY); + constant RX_DFE_LPM_CFG_STRLEN : integer := getstrlength(RX_DFE_LPM_CFG_BINARY); + constant RX_DFE_ST_CFG_STRLEN : integer := getstrlength(RX_DFE_ST_CFG_BINARY); + constant TRANS_TIME_RATE_STRLEN : integer := getstrlength(TRANS_TIME_RATE_BINARY); + constant TST_RSV_STRLEN : integer := getstrlength(TST_RSV_BINARY); + constant TXDLY_CFG_STRLEN : integer := getstrlength(TXDLY_CFG_BINARY); + constant TXDLY_LCFG_STRLEN : integer := getstrlength(TXDLY_LCFG_BINARY); + constant TXDLY_TAP_CFG_STRLEN : integer := getstrlength(TXDLY_TAP_CFG_BINARY); + constant TXPHDLY_CFG_STRLEN : integer := getstrlength(TXPHDLY_CFG_BINARY); + constant TXPH_CFG_STRLEN : integer := getstrlength(TXPH_CFG_BINARY); + constant TX_RXDETECT_CFG_STRLEN : integer := getstrlength(TX_RXDETECT_CFG_BINARY); + constant TX_RXDETECT_PRECHARGE_TIME_STRLEN : integer := getstrlength(TX_RXDETECT_PRECHARGE_TIME_BINARY); + + -- Convert std_logic_vector to string + constant ACJTAG_DEBUG_MODE_STRING : string := SUL_TO_STR(ACJTAG_DEBUG_MODE_BINARY); + constant ACJTAG_MODE_STRING : string := SUL_TO_STR(ACJTAG_MODE_BINARY); + constant ACJTAG_RESET_STRING : string := SUL_TO_STR(ACJTAG_RESET_BINARY); + constant ADAPT_CFG0_STRING : string := SLV_TO_HEX(ADAPT_CFG0_BINARY, ADAPT_CFG0_STRLEN); + constant ALIGN_COMMA_ENABLE_STRING : string := SLV_TO_STR(ALIGN_COMMA_ENABLE_BINARY); + constant ALIGN_MCOMMA_VALUE_STRING : string := SLV_TO_STR(ALIGN_MCOMMA_VALUE_BINARY); + constant ALIGN_PCOMMA_VALUE_STRING : string := SLV_TO_STR(ALIGN_PCOMMA_VALUE_BINARY); + constant A_RXOSCALRESET_STRING : string := SUL_TO_STR(A_RXOSCALRESET_BINARY); + constant CFOK_CFG2_STRING : string := SLV_TO_STR(CFOK_CFG2_BINARY); + constant CFOK_CFG3_STRING : string := SLV_TO_STR(CFOK_CFG3_BINARY); + constant CFOK_CFG_STRING : string := SLV_TO_HEX(CFOK_CFG_BINARY, CFOK_CFG_STRLEN); + constant CHAN_BOND_SEQ_1_1_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_1_BINARY); + constant CHAN_BOND_SEQ_1_2_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_2_BINARY); + constant CHAN_BOND_SEQ_1_3_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_3_BINARY); + constant CHAN_BOND_SEQ_1_4_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_4_BINARY); + constant CHAN_BOND_SEQ_1_ENABLE_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_ENABLE_BINARY); + constant CHAN_BOND_SEQ_2_1_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_1_BINARY); + constant CHAN_BOND_SEQ_2_2_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_2_BINARY); + constant CHAN_BOND_SEQ_2_3_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_3_BINARY); + constant CHAN_BOND_SEQ_2_4_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_4_BINARY); + constant CHAN_BOND_SEQ_2_ENABLE_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_ENABLE_BINARY); + constant CLK_COR_SEQ_1_1_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_1_BINARY); + constant CLK_COR_SEQ_1_2_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_2_BINARY); + constant CLK_COR_SEQ_1_3_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_3_BINARY); + constant CLK_COR_SEQ_1_4_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_4_BINARY); + constant CLK_COR_SEQ_1_ENABLE_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_ENABLE_BINARY); + constant CLK_COR_SEQ_2_1_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_1_BINARY); + constant CLK_COR_SEQ_2_2_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_2_BINARY); + constant CLK_COR_SEQ_2_3_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_3_BINARY); + constant CLK_COR_SEQ_2_4_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_4_BINARY); + constant CLK_COR_SEQ_2_ENABLE_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_ENABLE_BINARY); + constant CPLL_CFG_STRING : string := SLV_TO_HEX(CPLL_CFG_BINARY, CPLL_CFG_STRLEN); + constant CPLL_INIT_CFG_STRING : string := SLV_TO_HEX(CPLL_INIT_CFG_BINARY, CPLL_INIT_CFG_STRLEN); + constant CPLL_LOCK_CFG_STRING : string := SLV_TO_HEX(CPLL_LOCK_CFG_BINARY, CPLL_LOCK_CFG_STRLEN); + constant DMONITOR_CFG_STRING : string := SLV_TO_HEX(DMONITOR_CFG_BINARY, DMONITOR_CFG_STRLEN); + constant ES_CLK_PHASE_SEL_STRING : string := SUL_TO_STR(ES_CLK_PHASE_SEL_BINARY); + constant ES_CONTROL_STRING : string := SLV_TO_STR(ES_CONTROL_BINARY); + constant ES_HORZ_OFFSET_STRING : string := SLV_TO_HEX(ES_HORZ_OFFSET_BINARY, ES_HORZ_OFFSET_STRLEN); + constant ES_PMA_CFG_STRING : string := SLV_TO_STR(ES_PMA_CFG_BINARY); + constant ES_PRESCALE_STRING : string := SLV_TO_STR(ES_PRESCALE_BINARY); + constant ES_QUALIFIER_STRING : string := SLV_TO_HEX(ES_QUALIFIER_BINARY, ES_QUALIFIER_STRLEN); + constant ES_QUAL_MASK_STRING : string := SLV_TO_HEX(ES_QUAL_MASK_BINARY, ES_QUAL_MASK_STRLEN); + constant ES_SDATA_MASK_STRING : string := SLV_TO_HEX(ES_SDATA_MASK_BINARY, ES_SDATA_MASK_STRLEN); + constant ES_VERT_OFFSET_STRING : string := SLV_TO_STR(ES_VERT_OFFSET_BINARY); + constant FTS_DESKEW_SEQ_ENABLE_STRING : string := SLV_TO_STR(FTS_DESKEW_SEQ_ENABLE_BINARY); + constant FTS_LANE_DESKEW_CFG_STRING : string := SLV_TO_STR(FTS_LANE_DESKEW_CFG_BINARY); + constant GEARBOX_MODE_STRING : string := SLV_TO_STR(GEARBOX_MODE_BINARY); + constant LOOPBACK_CFG_STRING : string := SUL_TO_STR(LOOPBACK_CFG_BINARY); + constant OUTREFCLK_SEL_INV_STRING : string := SLV_TO_STR(OUTREFCLK_SEL_INV_BINARY); + constant PCS_RSVD_ATTR_STRING : string := SLV_TO_HEX(PCS_RSVD_ATTR_BINARY, PCS_RSVD_ATTR_STRLEN); + constant PD_TRANS_TIME_FROM_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_FROM_P2_BINARY, PD_TRANS_TIME_FROM_P2_STRLEN); + constant PD_TRANS_TIME_NONE_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_NONE_P2_BINARY, PD_TRANS_TIME_NONE_P2_STRLEN); + constant PD_TRANS_TIME_TO_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_TO_P2_BINARY, PD_TRANS_TIME_TO_P2_STRLEN); + constant PMA_RSV2_STRING : string := SLV_TO_STR(PMA_RSV2_BINARY); + constant PMA_RSV3_STRING : string := SLV_TO_STR(PMA_RSV3_BINARY); + constant PMA_RSV4_STRING : string := SLV_TO_STR(PMA_RSV4_BINARY); + constant PMA_RSV5_STRING : string := SLV_TO_STR(PMA_RSV5_BINARY); + constant PMA_RSV_STRING : string := SLV_TO_STR(PMA_RSV_BINARY); + constant RESET_POWERSAVE_DISABLE_STRING : string := SUL_TO_STR(RESET_POWERSAVE_DISABLE_BINARY); + constant RXBUFRESET_TIME_STRING : string := SLV_TO_STR(RXBUFRESET_TIME_BINARY); + constant RXBUF_EIDLE_HI_CNT_STRING : string := SLV_TO_STR(RXBUF_EIDLE_HI_CNT_BINARY); + constant RXBUF_EIDLE_LO_CNT_STRING : string := SLV_TO_STR(RXBUF_EIDLE_LO_CNT_BINARY); + constant RXCDRFREQRESET_TIME_STRING : string := SLV_TO_STR(RXCDRFREQRESET_TIME_BINARY); + constant RXCDRPHRESET_TIME_STRING : string := SLV_TO_STR(RXCDRPHRESET_TIME_BINARY); + constant RXCDR_CFG_STRING : string := SLV_TO_HEX(RXCDR_CFG_BINARY, RXCDR_CFG_STRLEN); + constant RXCDR_FR_RESET_ON_EIDLE_STRING : string := SUL_TO_STR(RXCDR_FR_RESET_ON_EIDLE_BINARY); + constant RXCDR_HOLD_DURING_EIDLE_STRING : string := SUL_TO_STR(RXCDR_HOLD_DURING_EIDLE_BINARY); + constant RXCDR_LOCK_CFG_STRING : string := SLV_TO_STR(RXCDR_LOCK_CFG_BINARY); + constant RXCDR_PH_RESET_ON_EIDLE_STRING : string := SUL_TO_STR(RXCDR_PH_RESET_ON_EIDLE_BINARY); + constant RXDFELPMRESET_TIME_STRING : string := SLV_TO_STR(RXDFELPMRESET_TIME_BINARY); + constant RXDLY_CFG_STRING : string := SLV_TO_HEX(RXDLY_CFG_BINARY, RXDLY_CFG_STRLEN); + constant RXDLY_LCFG_STRING : string := SLV_TO_HEX(RXDLY_LCFG_BINARY, RXDLY_LCFG_STRLEN); + constant RXDLY_TAP_CFG_STRING : string := SLV_TO_HEX(RXDLY_TAP_CFG_BINARY, RXDLY_TAP_CFG_STRLEN); + constant RXISCANRESET_TIME_STRING : string := SLV_TO_STR(RXISCANRESET_TIME_BINARY); + constant RXLPM_HF_CFG_STRING : string := SLV_TO_STR(RXLPM_HF_CFG_BINARY); + constant RXLPM_LF_CFG_STRING : string := SLV_TO_STR(RXLPM_LF_CFG_BINARY); + constant RXOOB_CFG_STRING : string := SLV_TO_STR(RXOOB_CFG_BINARY); + constant RXOSCALRESET_TIMEOUT_STRING : string := SLV_TO_STR(RXOSCALRESET_TIMEOUT_BINARY); + constant RXOSCALRESET_TIME_STRING : string := SLV_TO_STR(RXOSCALRESET_TIME_BINARY); + constant RXPCSRESET_TIME_STRING : string := SLV_TO_STR(RXPCSRESET_TIME_BINARY); + constant RXPHDLY_CFG_STRING : string := SLV_TO_HEX(RXPHDLY_CFG_BINARY, RXPHDLY_CFG_STRLEN); + constant RXPH_CFG_STRING : string := SLV_TO_HEX(RXPH_CFG_BINARY, RXPH_CFG_STRLEN); + constant RXPH_MONITOR_SEL_STRING : string := SLV_TO_STR(RXPH_MONITOR_SEL_BINARY); + constant RXPI_CFG0_STRING : string := SLV_TO_STR(RXPI_CFG0_BINARY); + constant RXPI_CFG1_STRING : string := SLV_TO_STR(RXPI_CFG1_BINARY); + constant RXPI_CFG2_STRING : string := SLV_TO_STR(RXPI_CFG2_BINARY); + constant RXPI_CFG3_STRING : string := SLV_TO_STR(RXPI_CFG3_BINARY); + constant RXPI_CFG4_STRING : string := SUL_TO_STR(RXPI_CFG4_BINARY); + constant RXPI_CFG5_STRING : string := SUL_TO_STR(RXPI_CFG5_BINARY); + constant RXPI_CFG6_STRING : string := SLV_TO_STR(RXPI_CFG6_BINARY); + constant RXPMARESET_TIME_STRING : string := SLV_TO_STR(RXPMARESET_TIME_BINARY); + constant RXPRBS_ERR_LOOPBACK_STRING : string := SUL_TO_STR(RXPRBS_ERR_LOOPBACK_BINARY); + constant RXSYNC_MULTILANE_STRING : string := SUL_TO_STR(RXSYNC_MULTILANE_BINARY); + constant RXSYNC_OVRD_STRING : string := SUL_TO_STR(RXSYNC_OVRD_BINARY); + constant RXSYNC_SKIP_DA_STRING : string := SUL_TO_STR(RXSYNC_SKIP_DA_BINARY); + constant RX_BIAS_CFG_STRING : string := SLV_TO_STR(RX_BIAS_CFG_BINARY); + constant RX_BUFFER_CFG_STRING : string := SLV_TO_STR(RX_BUFFER_CFG_BINARY); + constant RX_CLKMUX_PD_STRING : string := SUL_TO_STR(RX_CLKMUX_PD_BINARY); + constant RX_CM_SEL_STRING : string := SLV_TO_STR(RX_CM_SEL_BINARY); + constant RX_CM_TRIM_STRING : string := SLV_TO_STR(RX_CM_TRIM_BINARY); + constant RX_DDI_SEL_STRING : string := SLV_TO_STR(RX_DDI_SEL_BINARY); + constant RX_DEBUG_CFG_STRING : string := SLV_TO_STR(RX_DEBUG_CFG_BINARY); + constant RX_DFELPM_CFG0_STRING : string := SLV_TO_STR(RX_DFELPM_CFG0_BINARY); + constant RX_DFELPM_CFG1_STRING : string := SUL_TO_STR(RX_DFELPM_CFG1_BINARY); + constant RX_DFELPM_KLKH_AGC_STUP_EN_STRING : string := SUL_TO_STR(RX_DFELPM_KLKH_AGC_STUP_EN_BINARY); + constant RX_DFE_AGC_CFG0_STRING : string := SLV_TO_STR(RX_DFE_AGC_CFG0_BINARY); + constant RX_DFE_AGC_CFG1_STRING : string := SLV_TO_STR(RX_DFE_AGC_CFG1_BINARY); + constant RX_DFE_AGC_CFG2_STRING : string := SLV_TO_STR(RX_DFE_AGC_CFG2_BINARY); + constant RX_DFE_AGC_OVRDEN_STRING : string := SUL_TO_STR(RX_DFE_AGC_OVRDEN_BINARY); + constant RX_DFE_GAIN_CFG_STRING : string := SLV_TO_HEX(RX_DFE_GAIN_CFG_BINARY, RX_DFE_GAIN_CFG_STRLEN); + constant RX_DFE_H2_CFG_STRING : string := SLV_TO_STR(RX_DFE_H2_CFG_BINARY); + constant RX_DFE_H3_CFG_STRING : string := SLV_TO_STR(RX_DFE_H3_CFG_BINARY); + constant RX_DFE_H4_CFG_STRING : string := SLV_TO_STR(RX_DFE_H4_CFG_BINARY); + constant RX_DFE_H5_CFG_STRING : string := SLV_TO_STR(RX_DFE_H5_CFG_BINARY); + constant RX_DFE_H6_CFG_STRING : string := SLV_TO_STR(RX_DFE_H6_CFG_BINARY); + constant RX_DFE_H7_CFG_STRING : string := SLV_TO_STR(RX_DFE_H7_CFG_BINARY); + constant RX_DFE_KL_CFG_STRING : string := SLV_TO_STR(RX_DFE_KL_CFG_BINARY); + constant RX_DFE_KL_LPM_KH_CFG0_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KH_CFG0_BINARY); + constant RX_DFE_KL_LPM_KH_CFG1_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KH_CFG1_BINARY); + constant RX_DFE_KL_LPM_KH_CFG2_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KH_CFG2_BINARY); + constant RX_DFE_KL_LPM_KH_OVRDEN_STRING : string := SUL_TO_STR(RX_DFE_KL_LPM_KH_OVRDEN_BINARY); + constant RX_DFE_KL_LPM_KL_CFG0_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KL_CFG0_BINARY); + constant RX_DFE_KL_LPM_KL_CFG1_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KL_CFG1_BINARY); + constant RX_DFE_KL_LPM_KL_CFG2_STRING : string := SLV_TO_STR(RX_DFE_KL_LPM_KL_CFG2_BINARY); + constant RX_DFE_KL_LPM_KL_OVRDEN_STRING : string := SUL_TO_STR(RX_DFE_KL_LPM_KL_OVRDEN_BINARY); + constant RX_DFE_LPM_CFG_STRING : string := SLV_TO_HEX(RX_DFE_LPM_CFG_BINARY, RX_DFE_LPM_CFG_STRLEN); + constant RX_DFE_LPM_HOLD_DURING_EIDLE_STRING : string := SUL_TO_STR(RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY); + constant RX_DFE_ST_CFG_STRING : string := SLV_TO_HEX(RX_DFE_ST_CFG_BINARY, RX_DFE_ST_CFG_STRLEN); + constant RX_DFE_UT_CFG_STRING : string := SLV_TO_STR(RX_DFE_UT_CFG_BINARY); + constant RX_DFE_VP_CFG_STRING : string := SLV_TO_STR(RX_DFE_VP_CFG_BINARY); + constant RX_OS_CFG_STRING : string := SLV_TO_STR(RX_OS_CFG_BINARY); + constant SATA_BURST_SEQ_LEN_STRING : string := SLV_TO_STR(SATA_BURST_SEQ_LEN_BINARY); + constant SATA_BURST_VAL_STRING : string := SLV_TO_STR(SATA_BURST_VAL_BINARY); + constant SATA_EIDLE_VAL_STRING : string := SLV_TO_STR(SATA_EIDLE_VAL_BINARY); + constant SIM_CPLLREFCLK_SEL_STRING : string := SLV_TO_STR(SIM_CPLLREFCLK_SEL_BINARY); + constant TERM_RCAL_CFG_STRING : string := SLV_TO_STR(TERM_RCAL_CFG_BINARY); + constant TERM_RCAL_OVRD_STRING : string := SLV_TO_STR(TERM_RCAL_OVRD_BINARY); + constant TRANS_TIME_RATE_STRING : string := SLV_TO_HEX(TRANS_TIME_RATE_BINARY, TRANS_TIME_RATE_STRLEN); + constant TST_RSV_STRING : string := SLV_TO_HEX(TST_RSV_BINARY, TST_RSV_STRLEN); + constant TXDLY_CFG_STRING : string := SLV_TO_HEX(TXDLY_CFG_BINARY, TXDLY_CFG_STRLEN); + constant TXDLY_LCFG_STRING : string := SLV_TO_HEX(TXDLY_LCFG_BINARY, TXDLY_LCFG_STRLEN); + constant TXDLY_TAP_CFG_STRING : string := SLV_TO_HEX(TXDLY_TAP_CFG_BINARY, TXDLY_TAP_CFG_STRLEN); + constant TXOOB_CFG_STRING : string := SUL_TO_STR(TXOOB_CFG_BINARY); + constant TXPCSRESET_TIME_STRING : string := SLV_TO_STR(TXPCSRESET_TIME_BINARY); + constant TXPHDLY_CFG_STRING : string := SLV_TO_HEX(TXPHDLY_CFG_BINARY, TXPHDLY_CFG_STRLEN); + constant TXPH_CFG_STRING : string := SLV_TO_HEX(TXPH_CFG_BINARY, TXPH_CFG_STRLEN); + constant TXPH_MONITOR_SEL_STRING : string := SLV_TO_STR(TXPH_MONITOR_SEL_BINARY); + constant TXPI_CFG0_STRING : string := SLV_TO_STR(TXPI_CFG0_BINARY); + constant TXPI_CFG1_STRING : string := SLV_TO_STR(TXPI_CFG1_BINARY); + constant TXPI_CFG2_STRING : string := SLV_TO_STR(TXPI_CFG2_BINARY); + constant TXPI_CFG3_STRING : string := SUL_TO_STR(TXPI_CFG3_BINARY); + constant TXPI_CFG4_STRING : string := SUL_TO_STR(TXPI_CFG4_BINARY); + constant TXPI_CFG5_STRING : string := SLV_TO_STR(TXPI_CFG5_BINARY); + constant TXPI_GREY_SEL_STRING : string := SUL_TO_STR(TXPI_GREY_SEL_BINARY); + constant TXPI_INVSTROBE_SEL_STRING : string := SUL_TO_STR(TXPI_INVSTROBE_SEL_BINARY); + constant TXPI_PPM_CFG_STRING : string := SLV_TO_STR(TXPI_PPM_CFG_BINARY); + constant TXPI_SYNFREQ_PPM_STRING : string := SLV_TO_STR(TXPI_SYNFREQ_PPM_BINARY); + constant TXPMARESET_TIME_STRING : string := SLV_TO_STR(TXPMARESET_TIME_BINARY); + constant TXSYNC_MULTILANE_STRING : string := SUL_TO_STR(TXSYNC_MULTILANE_BINARY); + constant TXSYNC_OVRD_STRING : string := SUL_TO_STR(TXSYNC_OVRD_BINARY); + constant TXSYNC_SKIP_DA_STRING : string := SUL_TO_STR(TXSYNC_SKIP_DA_BINARY); + constant TX_CLKMUX_PD_STRING : string := SUL_TO_STR(TX_CLKMUX_PD_BINARY); + constant TX_DEEMPH0_STRING : string := SLV_TO_STR(TX_DEEMPH0_BINARY); + constant TX_DEEMPH1_STRING : string := SLV_TO_STR(TX_DEEMPH1_BINARY); + constant TX_EIDLE_ASSERT_DELAY_STRING : string := SLV_TO_STR(TX_EIDLE_ASSERT_DELAY_BINARY); + constant TX_EIDLE_DEASSERT_DELAY_STRING : string := SLV_TO_STR(TX_EIDLE_DEASSERT_DELAY_BINARY); + constant TX_MAINCURSOR_SEL_STRING : string := SUL_TO_STR(TX_MAINCURSOR_SEL_BINARY); + constant TX_MARGIN_FULL_0_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_0_BINARY); + constant TX_MARGIN_FULL_1_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_1_BINARY); + constant TX_MARGIN_FULL_2_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_2_BINARY); + constant TX_MARGIN_FULL_3_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_3_BINARY); + constant TX_MARGIN_FULL_4_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_4_BINARY); + constant TX_MARGIN_LOW_0_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_0_BINARY); + constant TX_MARGIN_LOW_1_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_1_BINARY); + constant TX_MARGIN_LOW_2_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_2_BINARY); + constant TX_MARGIN_LOW_3_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_3_BINARY); + constant TX_MARGIN_LOW_4_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_4_BINARY); + constant TX_QPI_STATUS_EN_STRING : string := SUL_TO_STR(TX_QPI_STATUS_EN_BINARY); + constant TX_RXDETECT_CFG_STRING : string := SLV_TO_HEX(TX_RXDETECT_CFG_BINARY, TX_RXDETECT_CFG_STRLEN); + constant TX_RXDETECT_PRECHARGE_TIME_STRING : string := SLV_TO_HEX(TX_RXDETECT_PRECHARGE_TIME_BINARY, TX_RXDETECT_PRECHARGE_TIME_STRLEN); + constant TX_RXDETECT_REF_STRING : string := SLV_TO_STR(TX_RXDETECT_REF_BINARY); + constant UCODEER_CLR_STRING : string := SUL_TO_STR(UCODEER_CLR_BINARY); + constant USE_PCS_CLK_PHASE_SEL_STRING : string := SUL_TO_STR(USE_PCS_CLK_PHASE_SEL_BINARY); + + signal IS_CLKRSVD0_INVERTED_BIN : std_ulogic; + signal IS_CLKRSVD1_INVERTED_BIN : std_ulogic; + signal IS_CPLLLOCKDETCLK_INVERTED_BIN : std_ulogic; + signal IS_DMONITORCLK_INVERTED_BIN : std_ulogic; + signal IS_DRPCLK_INVERTED_BIN : std_ulogic; + signal IS_GTGREFCLK_INVERTED_BIN : std_ulogic; + signal IS_RXUSRCLK2_INVERTED_BIN : std_ulogic; + signal IS_RXUSRCLK_INVERTED_BIN : std_ulogic; + signal IS_SIGVALIDCLK_INVERTED_BIN : std_ulogic; + signal IS_TXPHDLYTSTCLK_INVERTED_BIN : std_ulogic; + signal IS_TXUSRCLK2_INVERTED_BIN : std_ulogic; + signal IS_TXUSRCLK_INVERTED_BIN : std_ulogic; + + signal ALIGN_COMMA_DOUBLE_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_BINARY : std_logic_vector(2 downto 0); + signal ALIGN_MCOMMA_DET_BINARY : std_ulogic; + signal ALIGN_PCOMMA_DET_BINARY : std_ulogic; + signal CBCC_DATA_SOURCE_SEL_BINARY : std_ulogic; + signal CHAN_BOND_KEEP_ALIGN_BINARY : std_ulogic; + signal CHAN_BOND_MAX_SKEW_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CLK_CORRECT_USE_BINARY : std_ulogic; + signal CLK_COR_KEEP_IDLE_BINARY : std_ulogic; + signal CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_PRECEDENCE_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; + signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CPLL_FBDIV_45_BINARY : std_ulogic; + signal CPLL_FBDIV_BINARY : std_logic_vector(6 downto 0); + signal CPLL_REFCLK_DIV_BINARY : std_logic_vector(4 downto 0); + signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; + signal ES_ERRDET_EN_BINARY : std_ulogic; + signal ES_EYE_SCAN_EN_BINARY : std_ulogic; + signal FTS_LANE_DESKEW_EN_BINARY : std_ulogic; + signal PCS_PCIE_EN_BINARY : std_ulogic; + signal RXBUF_ADDR_MODE_BINARY : std_ulogic; + signal RXBUF_EN_BINARY : std_ulogic; + signal RXBUF_RESET_ON_CB_CHANGE_BINARY : std_ulogic; + signal RXBUF_RESET_ON_COMMAALIGN_BINARY : std_ulogic; + signal RXBUF_RESET_ON_EIDLE_BINARY : std_ulogic; + signal RXBUF_RESET_ON_RATE_CHANGE_BINARY : std_ulogic; + signal RXBUF_THRESH_OVFLW_BINARY : std_logic_vector(5 downto 0); + signal RXBUF_THRESH_OVRD_BINARY : std_ulogic; + signal RXBUF_THRESH_UNDFLW_BINARY : std_logic_vector(5 downto 0); + signal RXGEARBOX_EN_BINARY : std_ulogic; + signal RXOOB_CLK_CFG_BINARY : std_ulogic; + signal RXOUT_DIV_BINARY : std_logic_vector(2 downto 0); + signal RXSLIDE_AUTO_WAIT_BINARY : std_logic_vector(3 downto 0); + signal RXSLIDE_MODE_BINARY : std_logic_vector(1 downto 0); + signal RX_CLK25_DIV_BINARY : std_logic_vector(4 downto 0); + signal RX_DATA_WIDTH_BINARY : std_logic_vector(2 downto 0); + signal RX_DEFER_RESET_BUF_EN_BINARY : std_ulogic; + signal RX_DISPERR_SEQ_MATCH_BINARY : std_ulogic; + signal RX_INT_DATAWIDTH_BINARY : std_ulogic; + signal RX_SIG_VALID_DLY_BINARY : std_logic_vector(4 downto 0); + signal RX_XCLK_SEL_BINARY : std_ulogic; + signal SAS_MAX_COM_BINARY : std_logic_vector(6 downto 0); + signal SAS_MIN_COM_BINARY : std_logic_vector(5 downto 0); + signal SATA_CPLL_CFG_BINARY : std_logic_vector(1 downto 0); + signal SATA_MAX_BURST_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_BURST_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_BINARY : std_logic_vector(5 downto 0); + signal SHOW_REALIGN_COMMA_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS_BINARY : std_ulogic; + signal SIM_RESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_TX_EIDLE_DRIVE_LEVEL_BINARY : std_ulogic; + signal SIM_VERSION_BINARY : std_ulogic; + signal TXBUF_EN_BINARY : std_ulogic; + signal TXBUF_RESET_ON_RATE_CHANGE_BINARY : std_ulogic; + signal TXGEARBOX_EN_BINARY : std_ulogic; + signal TXOUT_DIV_BINARY : std_logic_vector(2 downto 0); + signal TXPI_PPMCLK_SEL_BINARY : std_ulogic; + signal TX_CLK25_DIV_BINARY : std_logic_vector(4 downto 0); + signal TX_DATA_WIDTH_BINARY : std_logic_vector(2 downto 0); + signal TX_DRIVE_MODE_BINARY : std_logic_vector(4 downto 0); + signal TX_INT_DATAWIDTH_BINARY : std_ulogic; + signal TX_LOOPBACK_DRIVE_HIZ_BINARY : std_ulogic; + signal TX_XCLK_SEL_BINARY : std_ulogic; + + signal CPLLFBCLKLOST_out : std_ulogic; + signal CPLLLOCK_out : std_ulogic; + signal CPLLREFCLKLOST_out : std_ulogic; + signal DMONITOROUT_out : std_logic_vector(14 downto 0); + signal DRPDO_out : std_logic_vector(15 downto 0); + signal DRPRDY_out : std_ulogic; + signal EYESCANDATAERROR_out : std_ulogic; + signal GTHTXN_out : std_ulogic; + signal GTHTXP_out : std_ulogic; + signal GTREFCLKMONITOR_out : std_ulogic; + signal PCSRSVDOUT_out : std_logic_vector(15 downto 0); + signal PHYSTATUS_out : std_ulogic; + signal RSOSINTDONE_out : std_ulogic; + signal RXBUFSTATUS_out : std_logic_vector(2 downto 0); + signal RXBYTEISALIGNED_out : std_ulogic; + signal RXBYTEREALIGN_out : std_ulogic; + signal RXCDRLOCK_out : std_ulogic; + signal RXCHANBONDSEQ_out : std_ulogic; + signal RXCHANISALIGNED_out : std_ulogic; + signal RXCHANREALIGN_out : std_ulogic; + signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); + signal RXCHARISK_out : std_logic_vector(7 downto 0); + signal RXCHBONDO_out : std_logic_vector(4 downto 0); + signal RXCLKCORCNT_out : std_logic_vector(1 downto 0); + signal RXCOMINITDET_out : std_ulogic; + signal RXCOMMADET_out : std_ulogic; + signal RXCOMSASDET_out : std_ulogic; + signal RXCOMWAKEDET_out : std_ulogic; + signal RXDATAVALID_out : std_logic_vector(1 downto 0); + signal RXDATA_out : std_logic_vector(63 downto 0); + signal RXDFESLIDETAPSTARTED_out : std_ulogic; + signal RXDFESLIDETAPSTROBEDONE_out : std_ulogic; + signal RXDFESLIDETAPSTROBESTARTED_out : std_ulogic; + signal RXDFESTADAPTDONE_out : std_ulogic; + signal RXDISPERR_out : std_logic_vector(7 downto 0); + signal RXDLYSRESETDONE_out : std_ulogic; + signal RXELECIDLE_out : std_ulogic; + signal RXHEADERVALID_out : std_logic_vector(1 downto 0); + signal RXHEADER_out : std_logic_vector(5 downto 0); + signal RXMONITOROUT_out : std_logic_vector(6 downto 0); + signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); + signal RXOSINTSTARTED_out : std_ulogic; + signal RXOSINTSTROBEDONE_out : std_ulogic; + signal RXOSINTSTROBESTARTED_out : std_ulogic; + signal RXOUTCLKFABRIC_out : std_ulogic; + signal RXOUTCLKPCS_out : std_ulogic; + signal RXOUTCLK_out : std_ulogic; + signal RXPHALIGNDONE_out : std_ulogic; + signal RXPHMONITOR_out : std_logic_vector(4 downto 0); + signal RXPHSLIPMONITOR_out : std_logic_vector(4 downto 0); + signal RXPMARESETDONE_out : std_ulogic; + signal RXPRBSERR_out : std_ulogic; + signal RXQPISENN_out : std_ulogic; + signal RXQPISENP_out : std_ulogic; + signal RXRATEDONE_out : std_ulogic; + signal RXRESETDONE_out : std_ulogic; + signal RXSTARTOFSEQ_out : std_logic_vector(1 downto 0); + signal RXSTATUS_out : std_logic_vector(2 downto 0); + signal RXSYNCDONE_out : std_ulogic; + signal RXSYNCOUT_out : std_ulogic; + signal RXVALID_out : std_ulogic; + signal TXBUFSTATUS_out : std_logic_vector(1 downto 0); + signal TXCOMFINISH_out : std_ulogic; + signal TXDLYSRESETDONE_out : std_ulogic; + signal TXGEARBOXREADY_out : std_ulogic; + signal TXOUTCLKFABRIC_out : std_ulogic; + signal TXOUTCLKPCS_out : std_ulogic; + signal TXOUTCLK_out : std_ulogic; + signal TXPHALIGNDONE_out : std_ulogic; + signal TXPHINITDONE_out : std_ulogic; + signal TXPMARESETDONE_out : std_ulogic; + signal TXQPISENN_out : std_ulogic; + signal TXQPISENP_out : std_ulogic; + signal TXRATEDONE_out : std_ulogic; + signal TXRESETDONE_out : std_ulogic; + signal TXSYNCDONE_out : std_ulogic; + signal TXSYNCOUT_out : std_ulogic; + + signal CPLLFBCLKLOST_outdelay : std_ulogic; + signal CPLLLOCK_outdelay : std_ulogic; + signal CPLLREFCLKLOST_outdelay : std_ulogic; + signal DMONITOROUT_outdelay : std_logic_vector(14 downto 0); + signal DRPDO_outdelay : std_logic_vector(15 downto 0); + signal DRPRDY_outdelay : std_ulogic; + signal EYESCANDATAERROR_outdelay : std_ulogic; + signal GTHTXN_outdelay : std_ulogic; + signal GTHTXP_outdelay : std_ulogic; + signal GTREFCLKMONITOR_outdelay : std_ulogic; + signal PCSRSVDOUT_outdelay : std_logic_vector(15 downto 0); + signal PHYSTATUS_outdelay : std_ulogic; + signal RSOSINTDONE_outdelay : std_ulogic; + signal RXBUFSTATUS_outdelay : std_logic_vector(2 downto 0); + signal RXBYTEISALIGNED_outdelay : std_ulogic; + signal RXBYTEREALIGN_outdelay : std_ulogic; + signal RXCDRLOCK_outdelay : std_ulogic; + signal RXCHANBONDSEQ_outdelay : std_ulogic; + signal RXCHANISALIGNED_outdelay : std_ulogic; + signal RXCHANREALIGN_outdelay : std_ulogic; + signal RXCHARISCOMMA_outdelay : std_logic_vector(7 downto 0); + signal RXCHARISK_outdelay : std_logic_vector(7 downto 0); + signal RXCHBONDO_outdelay : std_logic_vector(4 downto 0); + signal RXCLKCORCNT_outdelay : std_logic_vector(1 downto 0); + signal RXCOMINITDET_outdelay : std_ulogic; + signal RXCOMMADET_outdelay : std_ulogic; + signal RXCOMSASDET_outdelay : std_ulogic; + signal RXCOMWAKEDET_outdelay : std_ulogic; + signal RXDATAVALID_outdelay : std_logic_vector(1 downto 0); + signal RXDATA_outdelay : std_logic_vector(63 downto 0); + signal RXDFESLIDETAPSTARTED_outdelay : std_ulogic; + signal RXDFESLIDETAPSTROBEDONE_outdelay : std_ulogic; + signal RXDFESLIDETAPSTROBESTARTED_outdelay : std_ulogic; + signal RXDFESTADAPTDONE_outdelay : std_ulogic; + signal RXDISPERR_outdelay : std_logic_vector(7 downto 0); + signal RXDLYSRESETDONE_outdelay : std_ulogic; + signal RXELECIDLE_outdelay : std_ulogic; + signal RXHEADERVALID_outdelay : std_logic_vector(1 downto 0); + signal RXHEADER_outdelay : std_logic_vector(5 downto 0); + signal RXMONITOROUT_outdelay : std_logic_vector(6 downto 0); + signal RXNOTINTABLE_outdelay : std_logic_vector(7 downto 0); + signal RXOSINTSTARTED_outdelay : std_ulogic; + signal RXOSINTSTROBEDONE_outdelay : std_ulogic; + signal RXOSINTSTROBESTARTED_outdelay : std_ulogic; + signal RXOUTCLKFABRIC_outdelay : std_ulogic; + signal RXOUTCLKPCS_outdelay : std_ulogic; + signal RXOUTCLK_outdelay : std_ulogic; + signal RXPHALIGNDONE_outdelay : std_ulogic; + signal RXPHMONITOR_outdelay : std_logic_vector(4 downto 0); + signal RXPHSLIPMONITOR_outdelay : std_logic_vector(4 downto 0); + signal RXPMARESETDONE_outdelay : std_ulogic; + signal RXPRBSERR_outdelay : std_ulogic; + signal RXQPISENN_outdelay : std_ulogic; + signal RXQPISENP_outdelay : std_ulogic; + signal RXRATEDONE_outdelay : std_ulogic; + signal RXRESETDONE_outdelay : std_ulogic; + signal RXSTARTOFSEQ_outdelay : std_logic_vector(1 downto 0); + signal RXSTATUS_outdelay : std_logic_vector(2 downto 0); + signal RXSYNCDONE_outdelay : std_ulogic; + signal RXSYNCOUT_outdelay : std_ulogic; + signal RXVALID_outdelay : std_ulogic; + signal TXBUFSTATUS_outdelay : std_logic_vector(1 downto 0); + signal TXCOMFINISH_outdelay : std_ulogic; + signal TXDLYSRESETDONE_outdelay : std_ulogic; + signal TXGEARBOXREADY_outdelay : std_ulogic; + signal TXOUTCLKFABRIC_outdelay : std_ulogic; + signal TXOUTCLKPCS_outdelay : std_ulogic; + signal TXOUTCLK_outdelay : std_ulogic; + signal TXPHALIGNDONE_outdelay : std_ulogic; + signal TXPHINITDONE_outdelay : std_ulogic; + signal TXPMARESETDONE_outdelay : std_ulogic; + signal TXQPISENN_outdelay : std_ulogic; + signal TXQPISENP_outdelay : std_ulogic; + signal TXRATEDONE_outdelay : std_ulogic; + signal TXRESETDONE_outdelay : std_ulogic; + signal TXSYNCDONE_outdelay : std_ulogic; + signal TXSYNCOUT_outdelay : std_ulogic; + + signal CFGRESET_ipd : std_ulogic; + signal CLKRSVD0_ipd : std_ulogic; + signal CLKRSVD1_ipd : std_ulogic; + signal CPLLLOCKDETCLK_ipd : std_ulogic; + signal CPLLLOCKEN_ipd : std_ulogic; + signal CPLLPD_ipd : std_ulogic; + signal CPLLREFCLKSEL_ipd : std_logic_vector(2 downto 0); + signal CPLLRESET_ipd : std_ulogic; + signal DMONFIFORESET_ipd : std_ulogic; + signal DMONITORCLK_ipd : std_ulogic; + signal DRPADDR_ipd : std_logic_vector(8 downto 0); + signal DRPCLK_ipd : std_ulogic; + signal DRPDI_ipd : std_logic_vector(15 downto 0); + signal DRPEN_ipd : std_ulogic; + signal DRPWE_ipd : std_ulogic; + signal EYESCANMODE_ipd : std_ulogic; + signal EYESCANRESET_ipd : std_ulogic; + signal EYESCANTRIGGER_ipd : std_ulogic; + signal GTGREFCLK_ipd : std_ulogic; + signal GTHRXN_ipd : std_ulogic; + signal GTHRXP_ipd : std_ulogic; + signal GTNORTHREFCLK0_ipd : std_ulogic; + signal GTNORTHREFCLK1_ipd : std_ulogic; + signal GTREFCLK0_ipd : std_ulogic; + signal GTREFCLK1_ipd : std_ulogic; + signal GTRESETSEL_ipd : std_ulogic; + signal GTRSVD_ipd : std_logic_vector(15 downto 0); + signal GTRXRESET_ipd : std_ulogic; + signal GTSOUTHREFCLK0_ipd : std_ulogic; + signal GTSOUTHREFCLK1_ipd : std_ulogic; + signal GTTXRESET_ipd : std_ulogic; + signal LOOPBACK_ipd : std_logic_vector(2 downto 0); + signal PCSRSVDIN2_ipd : std_logic_vector(4 downto 0); + signal PCSRSVDIN_ipd : std_logic_vector(15 downto 0); + signal PMARSVDIN_ipd : std_logic_vector(4 downto 0); + signal QPLLCLK_ipd : std_ulogic; + signal QPLLREFCLK_ipd : std_ulogic; + signal RESETOVRD_ipd : std_ulogic; + signal RX8B10BEN_ipd : std_ulogic; + signal RXADAPTSELTEST_ipd : std_logic_vector(13 downto 0); + signal RXBUFRESET_ipd : std_ulogic; + signal RXCDRFREQRESET_ipd : std_ulogic; + signal RXCDRHOLD_ipd : std_ulogic; + signal RXCDROVRDEN_ipd : std_ulogic; + signal RXCDRRESETRSV_ipd : std_ulogic; + signal RXCDRRESET_ipd : std_ulogic; + signal RXCHBONDEN_ipd : std_ulogic; + signal RXCHBONDI_ipd : std_logic_vector(4 downto 0); + signal RXCHBONDLEVEL_ipd : std_logic_vector(2 downto 0); + signal RXCHBONDMASTER_ipd : std_ulogic; + signal RXCHBONDSLAVE_ipd : std_ulogic; + signal RXCOMMADETEN_ipd : std_ulogic; + signal RXDDIEN_ipd : std_ulogic; + signal RXDFEAGCHOLD_ipd : std_ulogic; + signal RXDFEAGCOVRDEN_ipd : std_ulogic; + signal RXDFEAGCTRL_ipd : std_logic_vector(4 downto 0); + signal RXDFECM1EN_ipd : std_ulogic; + signal RXDFELFHOLD_ipd : std_ulogic; + signal RXDFELFOVRDEN_ipd : std_ulogic; + signal RXDFELPMRESET_ipd : std_ulogic; + signal RXDFESLIDETAPADAPTEN_ipd : std_ulogic; + signal RXDFESLIDETAPHOLD_ipd : std_ulogic; + signal RXDFESLIDETAPID_ipd : std_logic_vector(5 downto 0); + signal RXDFESLIDETAPINITOVRDEN_ipd : std_ulogic; + signal RXDFESLIDETAPONLYADAPTEN_ipd : std_ulogic; + signal RXDFESLIDETAPOVRDEN_ipd : std_ulogic; + signal RXDFESLIDETAPSTROBE_ipd : std_ulogic; + signal RXDFESLIDETAP_ipd : std_logic_vector(4 downto 0); + signal RXDFETAP2HOLD_ipd : std_ulogic; + signal RXDFETAP2OVRDEN_ipd : std_ulogic; + signal RXDFETAP3HOLD_ipd : std_ulogic; + signal RXDFETAP3OVRDEN_ipd : std_ulogic; + signal RXDFETAP4HOLD_ipd : std_ulogic; + signal RXDFETAP4OVRDEN_ipd : std_ulogic; + signal RXDFETAP5HOLD_ipd : std_ulogic; + signal RXDFETAP5OVRDEN_ipd : std_ulogic; + signal RXDFETAP6HOLD_ipd : std_ulogic; + signal RXDFETAP6OVRDEN_ipd : std_ulogic; + signal RXDFETAP7HOLD_ipd : std_ulogic; + signal RXDFETAP7OVRDEN_ipd : std_ulogic; + signal RXDFEUTHOLD_ipd : std_ulogic; + signal RXDFEUTOVRDEN_ipd : std_ulogic; + signal RXDFEVPHOLD_ipd : std_ulogic; + signal RXDFEVPOVRDEN_ipd : std_ulogic; + signal RXDFEVSEN_ipd : std_ulogic; + signal RXDFEXYDEN_ipd : std_ulogic; + signal RXDLYBYPASS_ipd : std_ulogic; + signal RXDLYEN_ipd : std_ulogic; + signal RXDLYOVRDEN_ipd : std_ulogic; + signal RXDLYSRESET_ipd : std_ulogic; + signal RXELECIDLEMODE_ipd : std_logic_vector(1 downto 0); + signal RXGEARBOXSLIP_ipd : std_ulogic; + signal RXLPMEN_ipd : std_ulogic; + signal RXLPMHFHOLD_ipd : std_ulogic; + signal RXLPMHFOVRDEN_ipd : std_ulogic; + signal RXLPMLFHOLD_ipd : std_ulogic; + signal RXLPMLFKLOVRDEN_ipd : std_ulogic; + signal RXMCOMMAALIGNEN_ipd : std_ulogic; + signal RXMONITORSEL_ipd : std_logic_vector(1 downto 0); + signal RXOOBRESET_ipd : std_ulogic; + signal RXOSCALRESET_ipd : std_ulogic; + signal RXOSHOLD_ipd : std_ulogic; + signal RXOSINTCFG_ipd : std_logic_vector(3 downto 0); + signal RXOSINTEN_ipd : std_ulogic; + signal RXOSINTHOLD_ipd : std_ulogic; + signal RXOSINTID0_ipd : std_logic_vector(3 downto 0); + signal RXOSINTNTRLEN_ipd : std_ulogic; + signal RXOSINTOVRDEN_ipd : std_ulogic; + signal RXOSINTSTROBE_ipd : std_ulogic; + signal RXOSINTTESTOVRDEN_ipd : std_ulogic; + signal RXOSOVRDEN_ipd : std_ulogic; + signal RXOUTCLKSEL_ipd : std_logic_vector(2 downto 0); + signal RXPCOMMAALIGNEN_ipd : std_ulogic; + signal RXPCSRESET_ipd : std_ulogic; + signal RXPD_ipd : std_logic_vector(1 downto 0); + signal RXPHALIGNEN_ipd : std_ulogic; + signal RXPHALIGN_ipd : std_ulogic; + signal RXPHDLYPD_ipd : std_ulogic; + signal RXPHDLYRESET_ipd : std_ulogic; + signal RXPHOVRDEN_ipd : std_ulogic; + signal RXPMARESET_ipd : std_ulogic; + signal RXPOLARITY_ipd : std_ulogic; + signal RXPRBSCNTRESET_ipd : std_ulogic; + signal RXPRBSSEL_ipd : std_logic_vector(2 downto 0); + signal RXQPIEN_ipd : std_ulogic; + signal RXRATEMODE_ipd : std_ulogic; + signal RXRATE_ipd : std_logic_vector(2 downto 0); + signal RXSLIDE_ipd : std_ulogic; + signal RXSYNCALLIN_ipd : std_ulogic; + signal RXSYNCIN_ipd : std_ulogic; + signal RXSYNCMODE_ipd : std_ulogic; + signal RXSYSCLKSEL_ipd : std_logic_vector(1 downto 0); + signal RXUSERRDY_ipd : std_ulogic; + signal RXUSRCLK2_ipd : std_ulogic; + signal RXUSRCLK_ipd : std_ulogic; + signal SETERRSTATUS_ipd : std_ulogic; + signal SIGVALIDCLK_ipd : std_ulogic; + signal TSTIN_ipd : std_logic_vector(19 downto 0); + signal TX8B10BBYPASS_ipd : std_logic_vector(7 downto 0); + signal TX8B10BEN_ipd : std_ulogic; + signal TXBUFDIFFCTRL_ipd : std_logic_vector(2 downto 0); + signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); + signal TXCHARISK_ipd : std_logic_vector(7 downto 0); + signal TXCOMINIT_ipd : std_ulogic; + signal TXCOMSAS_ipd : std_ulogic; + signal TXCOMWAKE_ipd : std_ulogic; + signal TXDATA_ipd : std_logic_vector(63 downto 0); + signal TXDEEMPH_ipd : std_ulogic; + signal TXDETECTRX_ipd : std_ulogic; + signal TXDIFFCTRL_ipd : std_logic_vector(3 downto 0); + signal TXDIFFPD_ipd : std_ulogic; + signal TXDLYBYPASS_ipd : std_ulogic; + signal TXDLYEN_ipd : std_ulogic; + signal TXDLYHOLD_ipd : std_ulogic; + signal TXDLYOVRDEN_ipd : std_ulogic; + signal TXDLYSRESET_ipd : std_ulogic; + signal TXDLYUPDOWN_ipd : std_ulogic; + signal TXELECIDLE_ipd : std_ulogic; + signal TXHEADER_ipd : std_logic_vector(2 downto 0); + signal TXINHIBIT_ipd : std_ulogic; + signal TXMAINCURSOR_ipd : std_logic_vector(6 downto 0); + signal TXMARGIN_ipd : std_logic_vector(2 downto 0); + signal TXOUTCLKSEL_ipd : std_logic_vector(2 downto 0); + signal TXPCSRESET_ipd : std_ulogic; + signal TXPDELECIDLEMODE_ipd : std_ulogic; + signal TXPD_ipd : std_logic_vector(1 downto 0); + signal TXPHALIGNEN_ipd : std_ulogic; + signal TXPHALIGN_ipd : std_ulogic; + signal TXPHDLYPD_ipd : std_ulogic; + signal TXPHDLYRESET_ipd : std_ulogic; + signal TXPHDLYTSTCLK_ipd : std_ulogic; + signal TXPHINIT_ipd : std_ulogic; + signal TXPHOVRDEN_ipd : std_ulogic; + signal TXPIPPMEN_ipd : std_ulogic; + signal TXPIPPMOVRDEN_ipd : std_ulogic; + signal TXPIPPMPD_ipd : std_ulogic; + signal TXPIPPMSEL_ipd : std_ulogic; + signal TXPIPPMSTEPSIZE_ipd : std_logic_vector(4 downto 0); + signal TXPISOPD_ipd : std_ulogic; + signal TXPMARESET_ipd : std_ulogic; + signal TXPOLARITY_ipd : std_ulogic; + signal TXPOSTCURSORINV_ipd : std_ulogic; + signal TXPOSTCURSOR_ipd : std_logic_vector(4 downto 0); + signal TXPRBSFORCEERR_ipd : std_ulogic; + signal TXPRBSSEL_ipd : std_logic_vector(2 downto 0); + signal TXPRECURSORINV_ipd : std_ulogic; + signal TXPRECURSOR_ipd : std_logic_vector(4 downto 0); + signal TXQPIBIASEN_ipd : std_ulogic; + signal TXQPISTRONGPDOWN_ipd : std_ulogic; + signal TXQPIWEAKPUP_ipd : std_ulogic; + signal TXRATEMODE_ipd : std_ulogic; + signal TXRATE_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ_ipd : std_ulogic; + signal TXSWING_ipd : std_ulogic; + signal TXSYNCALLIN_ipd : std_ulogic; + signal TXSYNCIN_ipd : std_ulogic; + signal TXSYNCMODE_ipd : std_ulogic; + signal TXSYSCLKSEL_ipd : std_logic_vector(1 downto 0); + signal TXUSERRDY_ipd : std_ulogic; + signal TXUSRCLK2_ipd : std_ulogic; + signal TXUSRCLK_ipd : std_ulogic; + + signal CFGRESET_indelay : std_ulogic; + signal CLKRSVD0_indelay : std_ulogic; + signal CLKRSVD1_indelay : std_ulogic; + signal CPLLLOCKDETCLK_indelay : std_ulogic; + signal CPLLLOCKEN_indelay : std_ulogic; + signal CPLLPD_indelay : std_ulogic; + signal CPLLREFCLKSEL_indelay : std_logic_vector(2 downto 0); + signal CPLLRESET_indelay : std_ulogic; + signal DMONFIFORESET_indelay : std_ulogic; + signal DMONITORCLK_indelay : std_ulogic; + signal DRPADDR_indelay : std_logic_vector(8 downto 0); + signal DRPCLK_indelay : std_ulogic; + signal DRPDI_indelay : std_logic_vector(15 downto 0); + signal DRPEN_indelay : std_ulogic; + signal DRPWE_indelay : std_ulogic; + signal EYESCANMODE_indelay : std_ulogic; + signal EYESCANRESET_indelay : std_ulogic; + signal EYESCANTRIGGER_indelay : std_ulogic; + signal GTGREFCLK_indelay : std_ulogic; + signal GTHRXN_indelay : std_ulogic; + signal GTHRXP_indelay : std_ulogic; + signal GTNORTHREFCLK0_indelay : std_ulogic; + signal GTNORTHREFCLK1_indelay : std_ulogic; + signal GTREFCLK0_indelay : std_ulogic; + signal GTREFCLK1_indelay : std_ulogic; + signal GTRESETSEL_indelay : std_ulogic; + signal GTRSVD_indelay : std_logic_vector(15 downto 0); + signal GTRXRESET_indelay : std_ulogic; + signal GTSOUTHREFCLK0_indelay : std_ulogic; + signal GTSOUTHREFCLK1_indelay : std_ulogic; + signal GTTXRESET_indelay : std_ulogic; + signal LOOPBACK_indelay : std_logic_vector(2 downto 0); + signal PCSRSVDIN2_indelay : std_logic_vector(4 downto 0); + signal PCSRSVDIN_indelay : std_logic_vector(15 downto 0); + signal PMARSVDIN_indelay : std_logic_vector(4 downto 0); + signal QPLLCLK_indelay : std_ulogic; + signal QPLLREFCLK_indelay : std_ulogic; + signal RESETOVRD_indelay : std_ulogic; + signal RX8B10BEN_indelay : std_ulogic; + signal RXADAPTSELTEST_indelay : std_logic_vector(13 downto 0); + signal RXBUFRESET_indelay : std_ulogic; + signal RXCDRFREQRESET_indelay : std_ulogic; + signal RXCDRHOLD_indelay : std_ulogic; + signal RXCDROVRDEN_indelay : std_ulogic; + signal RXCDRRESETRSV_indelay : std_ulogic; + signal RXCDRRESET_indelay : std_ulogic; + signal RXCHBONDEN_indelay : std_ulogic; + signal RXCHBONDI_indelay : std_logic_vector(4 downto 0); + signal RXCHBONDLEVEL_indelay : std_logic_vector(2 downto 0); + signal RXCHBONDMASTER_indelay : std_ulogic; + signal RXCHBONDSLAVE_indelay : std_ulogic; + signal RXCOMMADETEN_indelay : std_ulogic; + signal RXDDIEN_indelay : std_ulogic; + signal RXDFEAGCHOLD_indelay : std_ulogic; + signal RXDFEAGCOVRDEN_indelay : std_ulogic; + signal RXDFEAGCTRL_indelay : std_logic_vector(4 downto 0); + signal RXDFECM1EN_indelay : std_ulogic; + signal RXDFELFHOLD_indelay : std_ulogic; + signal RXDFELFOVRDEN_indelay : std_ulogic; + signal RXDFELPMRESET_indelay : std_ulogic; + signal RXDFESLIDETAPADAPTEN_indelay : std_ulogic; + signal RXDFESLIDETAPHOLD_indelay : std_ulogic; + signal RXDFESLIDETAPID_indelay : std_logic_vector(5 downto 0); + signal RXDFESLIDETAPINITOVRDEN_indelay : std_ulogic; + signal RXDFESLIDETAPONLYADAPTEN_indelay : std_ulogic; + signal RXDFESLIDETAPOVRDEN_indelay : std_ulogic; + signal RXDFESLIDETAPSTROBE_indelay : std_ulogic; + signal RXDFESLIDETAP_indelay : std_logic_vector(4 downto 0); + signal RXDFETAP2HOLD_indelay : std_ulogic; + signal RXDFETAP2OVRDEN_indelay : std_ulogic; + signal RXDFETAP3HOLD_indelay : std_ulogic; + signal RXDFETAP3OVRDEN_indelay : std_ulogic; + signal RXDFETAP4HOLD_indelay : std_ulogic; + signal RXDFETAP4OVRDEN_indelay : std_ulogic; + signal RXDFETAP5HOLD_indelay : std_ulogic; + signal RXDFETAP5OVRDEN_indelay : std_ulogic; + signal RXDFETAP6HOLD_indelay : std_ulogic; + signal RXDFETAP6OVRDEN_indelay : std_ulogic; + signal RXDFETAP7HOLD_indelay : std_ulogic; + signal RXDFETAP7OVRDEN_indelay : std_ulogic; + signal RXDFEUTHOLD_indelay : std_ulogic; + signal RXDFEUTOVRDEN_indelay : std_ulogic; + signal RXDFEVPHOLD_indelay : std_ulogic; + signal RXDFEVPOVRDEN_indelay : std_ulogic; + signal RXDFEVSEN_indelay : std_ulogic; + signal RXDFEXYDEN_indelay : std_ulogic; + signal RXDLYBYPASS_indelay : std_ulogic; + signal RXDLYEN_indelay : std_ulogic; + signal RXDLYOVRDEN_indelay : std_ulogic; + signal RXDLYSRESET_indelay : std_ulogic; + signal RXELECIDLEMODE_indelay : std_logic_vector(1 downto 0); + signal RXGEARBOXSLIP_indelay : std_ulogic; + signal RXLPMEN_indelay : std_ulogic; + signal RXLPMHFHOLD_indelay : std_ulogic; + signal RXLPMHFOVRDEN_indelay : std_ulogic; + signal RXLPMLFHOLD_indelay : std_ulogic; + signal RXLPMLFKLOVRDEN_indelay : std_ulogic; + signal RXMCOMMAALIGNEN_indelay : std_ulogic; + signal RXMONITORSEL_indelay : std_logic_vector(1 downto 0); + signal RXOOBRESET_indelay : std_ulogic; + signal RXOSCALRESET_indelay : std_ulogic; + signal RXOSHOLD_indelay : std_ulogic; + signal RXOSINTCFG_indelay : std_logic_vector(3 downto 0); + signal RXOSINTEN_indelay : std_ulogic; + signal RXOSINTHOLD_indelay : std_ulogic; + signal RXOSINTID0_indelay : std_logic_vector(3 downto 0); + signal RXOSINTNTRLEN_indelay : std_ulogic; + signal RXOSINTOVRDEN_indelay : std_ulogic; + signal RXOSINTSTROBE_indelay : std_ulogic; + signal RXOSINTTESTOVRDEN_indelay : std_ulogic; + signal RXOSOVRDEN_indelay : std_ulogic; + signal RXOUTCLKSEL_indelay : std_logic_vector(2 downto 0); + signal RXPCOMMAALIGNEN_indelay : std_ulogic; + signal RXPCSRESET_indelay : std_ulogic; + signal RXPD_indelay : std_logic_vector(1 downto 0); + signal RXPHALIGNEN_indelay : std_ulogic; + signal RXPHALIGN_indelay : std_ulogic; + signal RXPHDLYPD_indelay : std_ulogic; + signal RXPHDLYRESET_indelay : std_ulogic; + signal RXPHOVRDEN_indelay : std_ulogic; + signal RXPMARESET_indelay : std_ulogic; + signal RXPOLARITY_indelay : std_ulogic; + signal RXPRBSCNTRESET_indelay : std_ulogic; + signal RXPRBSSEL_indelay : std_logic_vector(2 downto 0); + signal RXQPIEN_indelay : std_ulogic; + signal RXRATEMODE_indelay : std_ulogic; + signal RXRATE_indelay : std_logic_vector(2 downto 0); + signal RXSLIDE_indelay : std_ulogic; + signal RXSYNCALLIN_indelay : std_ulogic; + signal RXSYNCIN_indelay : std_ulogic; + signal RXSYNCMODE_indelay : std_ulogic; + signal RXSYSCLKSEL_indelay : std_logic_vector(1 downto 0); + signal RXUSERRDY_indelay : std_ulogic; + signal RXUSRCLK2_indelay : std_ulogic; + signal RXUSRCLK_indelay : std_ulogic; + signal SETERRSTATUS_indelay : std_ulogic; + signal SIGVALIDCLK_indelay : std_ulogic; + signal TSTIN_indelay : std_logic_vector(19 downto 0); + signal TX8B10BBYPASS_indelay : std_logic_vector(7 downto 0); + signal TX8B10BEN_indelay : std_ulogic; + signal TXBUFDIFFCTRL_indelay : std_logic_vector(2 downto 0); + signal TXCHARDISPMODE_indelay : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_indelay : std_logic_vector(7 downto 0); + signal TXCHARISK_indelay : std_logic_vector(7 downto 0); + signal TXCOMINIT_indelay : std_ulogic; + signal TXCOMSAS_indelay : std_ulogic; + signal TXCOMWAKE_indelay : std_ulogic; + signal TXDATA_indelay : std_logic_vector(63 downto 0); + signal TXDEEMPH_indelay : std_ulogic; + signal TXDETECTRX_indelay : std_ulogic; + signal TXDIFFCTRL_indelay : std_logic_vector(3 downto 0); + signal TXDIFFPD_indelay : std_ulogic; + signal TXDLYBYPASS_indelay : std_ulogic; + signal TXDLYEN_indelay : std_ulogic; + signal TXDLYHOLD_indelay : std_ulogic; + signal TXDLYOVRDEN_indelay : std_ulogic; + signal TXDLYSRESET_indelay : std_ulogic; + signal TXDLYUPDOWN_indelay : std_ulogic; + signal TXELECIDLE_indelay : std_ulogic; + signal TXHEADER_indelay : std_logic_vector(2 downto 0); + signal TXINHIBIT_indelay : std_ulogic; + signal TXMAINCURSOR_indelay : std_logic_vector(6 downto 0); + signal TXMARGIN_indelay : std_logic_vector(2 downto 0); + signal TXOUTCLKSEL_indelay : std_logic_vector(2 downto 0); + signal TXPCSRESET_indelay : std_ulogic; + signal TXPDELECIDLEMODE_indelay : std_ulogic; + signal TXPD_indelay : std_logic_vector(1 downto 0); + signal TXPHALIGNEN_indelay : std_ulogic; + signal TXPHALIGN_indelay : std_ulogic; + signal TXPHDLYPD_indelay : std_ulogic; + signal TXPHDLYRESET_indelay : std_ulogic; + signal TXPHDLYTSTCLK_indelay : std_ulogic; + signal TXPHINIT_indelay : std_ulogic; + signal TXPHOVRDEN_indelay : std_ulogic; + signal TXPIPPMEN_indelay : std_ulogic; + signal TXPIPPMOVRDEN_indelay : std_ulogic; + signal TXPIPPMPD_indelay : std_ulogic; + signal TXPIPPMSEL_indelay : std_ulogic; + signal TXPIPPMSTEPSIZE_indelay : std_logic_vector(4 downto 0); + signal TXPISOPD_indelay : std_ulogic; + signal TXPMARESET_indelay : std_ulogic; + signal TXPOLARITY_indelay : std_ulogic; + signal TXPOSTCURSORINV_indelay : std_ulogic; + signal TXPOSTCURSOR_indelay : std_logic_vector(4 downto 0); + signal TXPRBSFORCEERR_indelay : std_ulogic; + signal TXPRBSSEL_indelay : std_logic_vector(2 downto 0); + signal TXPRECURSORINV_indelay : std_ulogic; + signal TXPRECURSOR_indelay : std_logic_vector(4 downto 0); + signal TXQPIBIASEN_indelay : std_ulogic; + signal TXQPISTRONGPDOWN_indelay : std_ulogic; + signal TXQPIWEAKPUP_indelay : std_ulogic; + signal TXRATEMODE_indelay : std_ulogic; + signal TXRATE_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ_indelay : std_ulogic; + signal TXSWING_indelay : std_ulogic; + signal TXSYNCALLIN_indelay : std_ulogic; + signal TXSYNCIN_indelay : std_ulogic; + signal TXSYNCMODE_indelay : std_ulogic; + signal TXSYSCLKSEL_indelay : std_logic_vector(1 downto 0); + signal TXUSERRDY_indelay : std_ulogic; + signal TXUSRCLK2_indelay : std_ulogic; + signal TXUSRCLK_indelay : std_ulogic; + + begin + GTREFCLKMONITOR_out <= GTREFCLKMONITOR_outdelay after OUTCLK_DELAY; + RXOUTCLK_out <= RXOUTCLK_outdelay after OUTCLK_DELAY; + TXOUTCLK_out <= TXOUTCLK_outdelay after OUTCLK_DELAY; + + CPLLFBCLKLOST_out <= CPLLFBCLKLOST_outdelay after OUT_DELAY; + CPLLLOCK_out <= CPLLLOCK_outdelay after OUT_DELAY; + CPLLREFCLKLOST_out <= CPLLREFCLKLOST_outdelay after OUT_DELAY; + DMONITOROUT_out <= DMONITOROUT_outdelay after OUT_DELAY; + DRPDO_out <= DRPDO_outdelay after OUT_DELAY; + DRPRDY_out <= DRPRDY_outdelay after OUT_DELAY; + EYESCANDATAERROR_out <= EYESCANDATAERROR_outdelay after OUT_DELAY; + GTHTXN_out <= GTHTXN_outdelay after OUT_DELAY; + GTHTXP_out <= GTHTXP_outdelay after OUT_DELAY; + PCSRSVDOUT_out <= PCSRSVDOUT_outdelay after OUT_DELAY; + PHYSTATUS_out <= PHYSTATUS_outdelay after OUT_DELAY; + RSOSINTDONE_out <= RSOSINTDONE_outdelay after OUT_DELAY; + RXBUFSTATUS_out <= RXBUFSTATUS_outdelay after OUT_DELAY; + RXBYTEISALIGNED_out <= RXBYTEISALIGNED_outdelay after OUT_DELAY; + RXBYTEREALIGN_out <= RXBYTEREALIGN_outdelay after OUT_DELAY; + RXCDRLOCK_out <= RXCDRLOCK_outdelay after OUT_DELAY; + RXCHANBONDSEQ_out <= RXCHANBONDSEQ_outdelay after OUT_DELAY; + RXCHANISALIGNED_out <= RXCHANISALIGNED_outdelay after OUT_DELAY; + RXCHANREALIGN_out <= RXCHANREALIGN_outdelay after OUT_DELAY; + RXCHARISCOMMA_out <= RXCHARISCOMMA_outdelay after OUT_DELAY; + RXCHARISK_out <= RXCHARISK_outdelay after OUT_DELAY; + RXCHBONDO_out <= RXCHBONDO_outdelay after OUT_DELAY; + RXCLKCORCNT_out <= RXCLKCORCNT_outdelay after OUT_DELAY; + RXCOMINITDET_out <= RXCOMINITDET_outdelay after OUT_DELAY; + RXCOMMADET_out <= RXCOMMADET_outdelay after OUT_DELAY; + RXCOMSASDET_out <= RXCOMSASDET_outdelay after OUT_DELAY; + RXCOMWAKEDET_out <= RXCOMWAKEDET_outdelay after OUT_DELAY; + RXDATAVALID_out <= RXDATAVALID_outdelay after OUT_DELAY; + RXDATA_out <= RXDATA_outdelay after OUT_DELAY; + RXDFESLIDETAPSTARTED_out <= RXDFESLIDETAPSTARTED_outdelay after OUT_DELAY; + RXDFESLIDETAPSTROBEDONE_out <= RXDFESLIDETAPSTROBEDONE_outdelay after OUT_DELAY; + RXDFESLIDETAPSTROBESTARTED_out <= RXDFESLIDETAPSTROBESTARTED_outdelay after OUT_DELAY; + RXDFESTADAPTDONE_out <= RXDFESTADAPTDONE_outdelay after OUT_DELAY; + RXDISPERR_out <= RXDISPERR_outdelay after OUT_DELAY; + RXDLYSRESETDONE_out <= RXDLYSRESETDONE_outdelay after OUT_DELAY; + RXELECIDLE_out <= RXELECIDLE_outdelay after OUT_DELAY; + RXHEADERVALID_out <= RXHEADERVALID_outdelay after OUT_DELAY; + RXHEADER_out <= RXHEADER_outdelay after OUT_DELAY; + RXMONITOROUT_out <= RXMONITOROUT_outdelay after OUT_DELAY; + RXNOTINTABLE_out <= RXNOTINTABLE_outdelay after OUT_DELAY; + RXOSINTSTARTED_out <= RXOSINTSTARTED_outdelay after OUT_DELAY; + RXOSINTSTROBEDONE_out <= RXOSINTSTROBEDONE_outdelay after OUT_DELAY; + RXOSINTSTROBESTARTED_out <= RXOSINTSTROBESTARTED_outdelay after OUT_DELAY; + RXOUTCLKFABRIC_out <= RXOUTCLKFABRIC_outdelay after OUT_DELAY; + RXOUTCLKPCS_out <= RXOUTCLKPCS_outdelay after OUT_DELAY; + RXPHALIGNDONE_out <= RXPHALIGNDONE_outdelay after OUT_DELAY; + RXPHMONITOR_out <= RXPHMONITOR_outdelay after OUT_DELAY; + RXPHSLIPMONITOR_out <= RXPHSLIPMONITOR_outdelay after OUT_DELAY; + RXPMARESETDONE_out <= RXPMARESETDONE_outdelay after OUT_DELAY; + RXPRBSERR_out <= RXPRBSERR_outdelay after OUT_DELAY; + RXQPISENN_out <= RXQPISENN_outdelay after OUT_DELAY; + RXQPISENP_out <= RXQPISENP_outdelay after OUT_DELAY; + RXRATEDONE_out <= RXRATEDONE_outdelay after OUT_DELAY; + RXRESETDONE_out <= RXRESETDONE_outdelay after OUT_DELAY; + RXSTARTOFSEQ_out <= RXSTARTOFSEQ_outdelay after OUT_DELAY; + RXSTATUS_out <= RXSTATUS_outdelay after OUT_DELAY; + RXSYNCDONE_out <= RXSYNCDONE_outdelay after OUT_DELAY; + RXSYNCOUT_out <= RXSYNCOUT_outdelay after OUT_DELAY; + RXVALID_out <= RXVALID_outdelay after OUT_DELAY; + TXBUFSTATUS_out <= TXBUFSTATUS_outdelay after OUT_DELAY; + TXCOMFINISH_out <= TXCOMFINISH_outdelay after OUT_DELAY; + TXDLYSRESETDONE_out <= TXDLYSRESETDONE_outdelay after OUT_DELAY; + TXGEARBOXREADY_out <= TXGEARBOXREADY_outdelay after OUT_DELAY; + TXOUTCLKFABRIC_out <= TXOUTCLKFABRIC_outdelay after OUT_DELAY; + TXOUTCLKPCS_out <= TXOUTCLKPCS_outdelay after OUT_DELAY; + TXPHALIGNDONE_out <= TXPHALIGNDONE_outdelay after OUT_DELAY; + TXPHINITDONE_out <= TXPHINITDONE_outdelay after OUT_DELAY; + TXPMARESETDONE_out <= TXPMARESETDONE_outdelay after OUT_DELAY; + TXQPISENN_out <= TXQPISENN_outdelay after OUT_DELAY; + TXQPISENP_out <= TXQPISENP_outdelay after OUT_DELAY; + TXRATEDONE_out <= TXRATEDONE_outdelay after OUT_DELAY; + TXRESETDONE_out <= TXRESETDONE_outdelay after OUT_DELAY; + TXSYNCDONE_out <= TXSYNCDONE_outdelay after OUT_DELAY; + TXSYNCOUT_out <= TXSYNCOUT_outdelay after OUT_DELAY; + + CLKRSVD0_ipd <= CLKRSVD0; + CLKRSVD1_ipd <= CLKRSVD1; + CPLLLOCKDETCLK_ipd <= CPLLLOCKDETCLK; + DMONITORCLK_ipd <= DMONITORCLK; + DRPCLK_ipd <= DRPCLK; + GTGREFCLK_ipd <= GTGREFCLK; + GTNORTHREFCLK0_ipd <= GTNORTHREFCLK0; + GTNORTHREFCLK1_ipd <= GTNORTHREFCLK1; + GTREFCLK0_ipd <= GTREFCLK0; + GTREFCLK1_ipd <= GTREFCLK1; + GTSOUTHREFCLK0_ipd <= GTSOUTHREFCLK0; + GTSOUTHREFCLK1_ipd <= GTSOUTHREFCLK1; + QPLLCLK_ipd <= QPLLCLK; + RXUSRCLK2_ipd <= RXUSRCLK2; + RXUSRCLK_ipd <= RXUSRCLK; + SIGVALIDCLK_ipd <= SIGVALIDCLK; + TXPHDLYTSTCLK_ipd <= TXPHDLYTSTCLK; + TXUSRCLK2_ipd <= TXUSRCLK2; + TXUSRCLK_ipd <= TXUSRCLK; + + CFGRESET_ipd <= CFGRESET; + CPLLLOCKEN_ipd <= CPLLLOCKEN; + CPLLPD_ipd <= CPLLPD; + CPLLREFCLKSEL_ipd <= CPLLREFCLKSEL; + CPLLRESET_ipd <= CPLLRESET; + DMONFIFORESET_ipd <= DMONFIFORESET; + DRPADDR_ipd <= DRPADDR; + DRPDI_ipd <= DRPDI; + DRPEN_ipd <= DRPEN; + DRPWE_ipd <= DRPWE; + EYESCANMODE_ipd <= EYESCANMODE; + EYESCANRESET_ipd <= EYESCANRESET; + EYESCANTRIGGER_ipd <= EYESCANTRIGGER; + GTHRXN_ipd <= GTHRXN; + GTHRXP_ipd <= GTHRXP; + GTRESETSEL_ipd <= GTRESETSEL; + GTRSVD_ipd <= GTRSVD; + GTRXRESET_ipd <= GTRXRESET; + GTTXRESET_ipd <= GTTXRESET; + LOOPBACK_ipd <= LOOPBACK; + PCSRSVDIN2_ipd <= PCSRSVDIN2; + PCSRSVDIN_ipd <= PCSRSVDIN; + PMARSVDIN_ipd <= PMARSVDIN; + QPLLREFCLK_ipd <= QPLLREFCLK; + RESETOVRD_ipd <= RESETOVRD; + RX8B10BEN_ipd <= RX8B10BEN; + RXADAPTSELTEST_ipd <= RXADAPTSELTEST; + RXBUFRESET_ipd <= RXBUFRESET; + RXCDRFREQRESET_ipd <= RXCDRFREQRESET; + RXCDRHOLD_ipd <= RXCDRHOLD; + RXCDROVRDEN_ipd <= RXCDROVRDEN; + RXCDRRESETRSV_ipd <= RXCDRRESETRSV; + RXCDRRESET_ipd <= RXCDRRESET; + RXCHBONDEN_ipd <= RXCHBONDEN; + RXCHBONDI_ipd <= RXCHBONDI; + RXCHBONDLEVEL_ipd <= RXCHBONDLEVEL; + RXCHBONDMASTER_ipd <= RXCHBONDMASTER; + RXCHBONDSLAVE_ipd <= RXCHBONDSLAVE; + RXCOMMADETEN_ipd <= RXCOMMADETEN; + RXDDIEN_ipd <= RXDDIEN; + RXDFEAGCHOLD_ipd <= RXDFEAGCHOLD; + RXDFEAGCOVRDEN_ipd <= RXDFEAGCOVRDEN; + RXDFEAGCTRL_ipd <= RXDFEAGCTRL; + RXDFECM1EN_ipd <= RXDFECM1EN; + RXDFELFHOLD_ipd <= RXDFELFHOLD; + RXDFELFOVRDEN_ipd <= RXDFELFOVRDEN; + RXDFELPMRESET_ipd <= RXDFELPMRESET; + RXDFESLIDETAPADAPTEN_ipd <= RXDFESLIDETAPADAPTEN; + RXDFESLIDETAPHOLD_ipd <= RXDFESLIDETAPHOLD; + RXDFESLIDETAPID_ipd <= RXDFESLIDETAPID; + RXDFESLIDETAPINITOVRDEN_ipd <= RXDFESLIDETAPINITOVRDEN; + RXDFESLIDETAPONLYADAPTEN_ipd <= RXDFESLIDETAPONLYADAPTEN; + RXDFESLIDETAPOVRDEN_ipd <= RXDFESLIDETAPOVRDEN; + RXDFESLIDETAPSTROBE_ipd <= RXDFESLIDETAPSTROBE; + RXDFESLIDETAP_ipd <= RXDFESLIDETAP; + RXDFETAP2HOLD_ipd <= RXDFETAP2HOLD; + RXDFETAP2OVRDEN_ipd <= RXDFETAP2OVRDEN; + RXDFETAP3HOLD_ipd <= RXDFETAP3HOLD; + RXDFETAP3OVRDEN_ipd <= RXDFETAP3OVRDEN; + RXDFETAP4HOLD_ipd <= RXDFETAP4HOLD; + RXDFETAP4OVRDEN_ipd <= RXDFETAP4OVRDEN; + RXDFETAP5HOLD_ipd <= RXDFETAP5HOLD; + RXDFETAP5OVRDEN_ipd <= RXDFETAP5OVRDEN; + RXDFETAP6HOLD_ipd <= RXDFETAP6HOLD; + RXDFETAP6OVRDEN_ipd <= RXDFETAP6OVRDEN; + RXDFETAP7HOLD_ipd <= RXDFETAP7HOLD; + RXDFETAP7OVRDEN_ipd <= RXDFETAP7OVRDEN; + RXDFEUTHOLD_ipd <= RXDFEUTHOLD; + RXDFEUTOVRDEN_ipd <= RXDFEUTOVRDEN; + RXDFEVPHOLD_ipd <= RXDFEVPHOLD; + RXDFEVPOVRDEN_ipd <= RXDFEVPOVRDEN; + RXDFEVSEN_ipd <= RXDFEVSEN; + RXDFEXYDEN_ipd <= RXDFEXYDEN; + RXDLYBYPASS_ipd <= RXDLYBYPASS; + RXDLYEN_ipd <= RXDLYEN; + RXDLYOVRDEN_ipd <= RXDLYOVRDEN; + RXDLYSRESET_ipd <= RXDLYSRESET; + RXELECIDLEMODE_ipd <= RXELECIDLEMODE; + RXGEARBOXSLIP_ipd <= RXGEARBOXSLIP; + RXLPMEN_ipd <= RXLPMEN; + RXLPMHFHOLD_ipd <= RXLPMHFHOLD; + RXLPMHFOVRDEN_ipd <= RXLPMHFOVRDEN; + RXLPMLFHOLD_ipd <= RXLPMLFHOLD; + RXLPMLFKLOVRDEN_ipd <= RXLPMLFKLOVRDEN; + RXMCOMMAALIGNEN_ipd <= RXMCOMMAALIGNEN; + RXMONITORSEL_ipd <= RXMONITORSEL; + RXOOBRESET_ipd <= RXOOBRESET; + RXOSCALRESET_ipd <= RXOSCALRESET; + RXOSHOLD_ipd <= RXOSHOLD; + RXOSINTCFG_ipd <= RXOSINTCFG; + RXOSINTEN_ipd <= RXOSINTEN; + RXOSINTHOLD_ipd <= RXOSINTHOLD; + RXOSINTID0_ipd <= RXOSINTID0; + RXOSINTNTRLEN_ipd <= RXOSINTNTRLEN; + RXOSINTOVRDEN_ipd <= RXOSINTOVRDEN; + RXOSINTSTROBE_ipd <= RXOSINTSTROBE; + RXOSINTTESTOVRDEN_ipd <= RXOSINTTESTOVRDEN; + RXOSOVRDEN_ipd <= RXOSOVRDEN; + RXOUTCLKSEL_ipd <= RXOUTCLKSEL; + RXPCOMMAALIGNEN_ipd <= RXPCOMMAALIGNEN; + RXPCSRESET_ipd <= RXPCSRESET; + RXPD_ipd <= RXPD; + RXPHALIGNEN_ipd <= RXPHALIGNEN; + RXPHALIGN_ipd <= RXPHALIGN; + RXPHDLYPD_ipd <= RXPHDLYPD; + RXPHDLYRESET_ipd <= RXPHDLYRESET; + RXPHOVRDEN_ipd <= RXPHOVRDEN; + RXPMARESET_ipd <= RXPMARESET; + RXPOLARITY_ipd <= RXPOLARITY; + RXPRBSCNTRESET_ipd <= RXPRBSCNTRESET; + RXPRBSSEL_ipd <= RXPRBSSEL; + RXQPIEN_ipd <= RXQPIEN; + RXRATEMODE_ipd <= RXRATEMODE; + RXRATE_ipd <= RXRATE; + RXSLIDE_ipd <= RXSLIDE; + RXSYNCALLIN_ipd <= RXSYNCALLIN; + RXSYNCIN_ipd <= RXSYNCIN; + RXSYNCMODE_ipd <= RXSYNCMODE; + RXSYSCLKSEL_ipd <= RXSYSCLKSEL; + RXUSERRDY_ipd <= RXUSERRDY; + SETERRSTATUS_ipd <= SETERRSTATUS; + TSTIN_ipd <= TSTIN; + TX8B10BBYPASS_ipd <= TX8B10BBYPASS; + TX8B10BEN_ipd <= TX8B10BEN; + TXBUFDIFFCTRL_ipd <= TXBUFDIFFCTRL; + TXCHARDISPMODE_ipd <= TXCHARDISPMODE; + TXCHARDISPVAL_ipd <= TXCHARDISPVAL; + TXCHARISK_ipd <= TXCHARISK; + TXCOMINIT_ipd <= TXCOMINIT; + TXCOMSAS_ipd <= TXCOMSAS; + TXCOMWAKE_ipd <= TXCOMWAKE; + TXDATA_ipd <= TXDATA; + TXDEEMPH_ipd <= TXDEEMPH; + TXDETECTRX_ipd <= TXDETECTRX; + TXDIFFCTRL_ipd <= TXDIFFCTRL; + TXDIFFPD_ipd <= TXDIFFPD; + TXDLYBYPASS_ipd <= TXDLYBYPASS; + TXDLYEN_ipd <= TXDLYEN; + TXDLYHOLD_ipd <= TXDLYHOLD; + TXDLYOVRDEN_ipd <= TXDLYOVRDEN; + TXDLYSRESET_ipd <= TXDLYSRESET; + TXDLYUPDOWN_ipd <= TXDLYUPDOWN; + TXELECIDLE_ipd <= TXELECIDLE; + TXHEADER_ipd <= TXHEADER; + TXINHIBIT_ipd <= TXINHIBIT; + TXMAINCURSOR_ipd <= TXMAINCURSOR; + TXMARGIN_ipd <= TXMARGIN; + TXOUTCLKSEL_ipd <= TXOUTCLKSEL; + TXPCSRESET_ipd <= TXPCSRESET; + TXPDELECIDLEMODE_ipd <= TXPDELECIDLEMODE; + TXPD_ipd <= TXPD; + TXPHALIGNEN_ipd <= TXPHALIGNEN; + TXPHALIGN_ipd <= TXPHALIGN; + TXPHDLYPD_ipd <= TXPHDLYPD; + TXPHDLYRESET_ipd <= TXPHDLYRESET; + TXPHINIT_ipd <= TXPHINIT; + TXPHOVRDEN_ipd <= TXPHOVRDEN; + TXPIPPMEN_ipd <= TXPIPPMEN; + TXPIPPMOVRDEN_ipd <= TXPIPPMOVRDEN; + TXPIPPMPD_ipd <= TXPIPPMPD; + TXPIPPMSEL_ipd <= TXPIPPMSEL; + TXPIPPMSTEPSIZE_ipd <= TXPIPPMSTEPSIZE; + TXPISOPD_ipd <= TXPISOPD; + TXPMARESET_ipd <= TXPMARESET; + TXPOLARITY_ipd <= TXPOLARITY; + TXPOSTCURSORINV_ipd <= TXPOSTCURSORINV; + TXPOSTCURSOR_ipd <= TXPOSTCURSOR; + TXPRBSFORCEERR_ipd <= TXPRBSFORCEERR; + TXPRBSSEL_ipd <= TXPRBSSEL; + TXPRECURSORINV_ipd <= TXPRECURSORINV; + TXPRECURSOR_ipd <= TXPRECURSOR; + TXQPIBIASEN_ipd <= TXQPIBIASEN; + TXQPISTRONGPDOWN_ipd <= TXQPISTRONGPDOWN; + TXQPIWEAKPUP_ipd <= TXQPIWEAKPUP; + TXRATEMODE_ipd <= TXRATEMODE; + TXRATE_ipd <= TXRATE; + TXSEQUENCE_ipd <= TXSEQUENCE; + TXSTARTSEQ_ipd <= TXSTARTSEQ; + TXSWING_ipd <= TXSWING; + TXSYNCALLIN_ipd <= TXSYNCALLIN; + TXSYNCIN_ipd <= TXSYNCIN; + TXSYNCMODE_ipd <= TXSYNCMODE; + TXSYSCLKSEL_ipd <= TXSYSCLKSEL; + TXUSERRDY_ipd <= TXUSERRDY; + + CLKRSVD0_indelay <= CLKRSVD0_ipd xor IS_CLKRSVD0_INVERTED_BIN; + CLKRSVD1_indelay <= CLKRSVD1_ipd xor IS_CLKRSVD1_INVERTED_BIN; + CPLLLOCKDETCLK_indelay <= CPLLLOCKDETCLK_ipd xor IS_CPLLLOCKDETCLK_INVERTED_BIN; + DMONITORCLK_indelay <= DMONITORCLK_ipd xor IS_DMONITORCLK_INVERTED_BIN; + DRPCLK_indelay <= DRPCLK_ipd xor IS_DRPCLK_INVERTED_BIN; + GTGREFCLK_indelay <= GTGREFCLK_ipd xor IS_GTGREFCLK_INVERTED_BIN; + GTNORTHREFCLK0_indelay <= GTNORTHREFCLK0_ipd after INCLK_DELAY; + GTNORTHREFCLK1_indelay <= GTNORTHREFCLK1_ipd after INCLK_DELAY; + GTREFCLK0_indelay <= GTREFCLK0_ipd after INCLK_DELAY; + GTREFCLK1_indelay <= GTREFCLK1_ipd after INCLK_DELAY; + GTSOUTHREFCLK0_indelay <= GTSOUTHREFCLK0_ipd after INCLK_DELAY; + GTSOUTHREFCLK1_indelay <= GTSOUTHREFCLK1_ipd after INCLK_DELAY; + QPLLCLK_indelay <= QPLLCLK_ipd after INCLK_DELAY; + RXUSRCLK2_indelay <= RXUSRCLK2_ipd xor IS_RXUSRCLK2_INVERTED_BIN; + RXUSRCLK_indelay <= RXUSRCLK_ipd xor IS_RXUSRCLK_INVERTED_BIN; + SIGVALIDCLK_indelay <= SIGVALIDCLK_ipd xor IS_SIGVALIDCLK_INVERTED_BIN; + TXPHDLYTSTCLK_indelay <= TXPHDLYTSTCLK_ipd xor IS_TXPHDLYTSTCLK_INVERTED_BIN; + TXUSRCLK2_indelay <= TXUSRCLK2_ipd xor IS_TXUSRCLK2_INVERTED_BIN; + TXUSRCLK_indelay <= TXUSRCLK_ipd xor IS_TXUSRCLK2_INVERTED_BIN; + + CFGRESET_indelay <= CFGRESET_ipd after IN_DELAY; + CPLLLOCKEN_indelay <= CPLLLOCKEN_ipd after IN_DELAY; + CPLLPD_indelay <= CPLLPD_ipd after IN_DELAY; + CPLLREFCLKSEL_indelay <= CPLLREFCLKSEL_ipd after IN_DELAY; + CPLLRESET_indelay <= CPLLRESET_ipd after IN_DELAY; + DMONFIFORESET_indelay <= DMONFIFORESET_ipd after IN_DELAY; + DRPADDR_indelay <= DRPADDR_ipd after IN_DELAY; + DRPDI_indelay <= DRPDI_ipd after IN_DELAY; + DRPEN_indelay <= DRPEN_ipd after IN_DELAY; + DRPWE_indelay <= DRPWE_ipd after IN_DELAY; + EYESCANMODE_indelay <= EYESCANMODE_ipd after IN_DELAY; + EYESCANRESET_indelay <= EYESCANRESET_ipd after IN_DELAY; + EYESCANTRIGGER_indelay <= EYESCANTRIGGER_ipd after IN_DELAY; + GTHRXN_indelay <= GTHRXN_ipd after IN_DELAY; + GTHRXP_indelay <= GTHRXP_ipd after IN_DELAY; + GTRESETSEL_indelay <= GTRESETSEL_ipd after IN_DELAY; + GTRSVD_indelay <= GTRSVD_ipd after IN_DELAY; + GTRXRESET_indelay <= GTRXRESET_ipd after IN_DELAY; + GTTXRESET_indelay <= GTTXRESET_ipd after IN_DELAY; + LOOPBACK_indelay <= LOOPBACK_ipd after IN_DELAY; + PCSRSVDIN2_indelay <= PCSRSVDIN2_ipd after IN_DELAY; + PCSRSVDIN_indelay <= PCSRSVDIN_ipd after IN_DELAY; + PMARSVDIN_indelay <= PMARSVDIN_ipd after IN_DELAY; + QPLLREFCLK_indelay <= QPLLREFCLK_ipd after IN_DELAY; + RESETOVRD_indelay <= RESETOVRD_ipd after IN_DELAY; + RX8B10BEN_indelay <= RX8B10BEN_ipd after IN_DELAY; + RXADAPTSELTEST_indelay <= RXADAPTSELTEST_ipd after IN_DELAY; + RXBUFRESET_indelay <= RXBUFRESET_ipd after IN_DELAY; + RXCDRFREQRESET_indelay <= RXCDRFREQRESET_ipd after IN_DELAY; + RXCDRHOLD_indelay <= RXCDRHOLD_ipd after IN_DELAY; + RXCDROVRDEN_indelay <= RXCDROVRDEN_ipd after IN_DELAY; + RXCDRRESETRSV_indelay <= RXCDRRESETRSV_ipd after IN_DELAY; + RXCDRRESET_indelay <= RXCDRRESET_ipd after IN_DELAY; + RXCHBONDEN_indelay <= RXCHBONDEN_ipd after IN_DELAY; + RXCHBONDI_indelay <= RXCHBONDI_ipd after IN_DELAY; + RXCHBONDLEVEL_indelay <= RXCHBONDLEVEL_ipd after IN_DELAY; + RXCHBONDMASTER_indelay <= RXCHBONDMASTER_ipd after IN_DELAY; + RXCHBONDSLAVE_indelay <= RXCHBONDSLAVE_ipd after IN_DELAY; + RXCOMMADETEN_indelay <= RXCOMMADETEN_ipd after IN_DELAY; + RXDDIEN_indelay <= RXDDIEN_ipd after IN_DELAY; + RXDFEAGCHOLD_indelay <= RXDFEAGCHOLD_ipd after IN_DELAY; + RXDFEAGCOVRDEN_indelay <= RXDFEAGCOVRDEN_ipd after IN_DELAY; + RXDFEAGCTRL_indelay <= RXDFEAGCTRL_ipd after IN_DELAY; + RXDFECM1EN_indelay <= RXDFECM1EN_ipd after IN_DELAY; + RXDFELFHOLD_indelay <= RXDFELFHOLD_ipd after IN_DELAY; + RXDFELFOVRDEN_indelay <= RXDFELFOVRDEN_ipd after IN_DELAY; + RXDFELPMRESET_indelay <= RXDFELPMRESET_ipd after IN_DELAY; + RXDFESLIDETAPADAPTEN_indelay <= RXDFESLIDETAPADAPTEN_ipd after IN_DELAY; + RXDFESLIDETAPHOLD_indelay <= RXDFESLIDETAPHOLD_ipd after IN_DELAY; + RXDFESLIDETAPID_indelay <= RXDFESLIDETAPID_ipd after IN_DELAY; + RXDFESLIDETAPINITOVRDEN_indelay <= RXDFESLIDETAPINITOVRDEN_ipd after IN_DELAY; + RXDFESLIDETAPONLYADAPTEN_indelay <= RXDFESLIDETAPONLYADAPTEN_ipd after IN_DELAY; + RXDFESLIDETAPOVRDEN_indelay <= RXDFESLIDETAPOVRDEN_ipd after IN_DELAY; + RXDFESLIDETAPSTROBE_indelay <= RXDFESLIDETAPSTROBE_ipd after IN_DELAY; + RXDFESLIDETAP_indelay <= RXDFESLIDETAP_ipd after IN_DELAY; + RXDFETAP2HOLD_indelay <= RXDFETAP2HOLD_ipd after IN_DELAY; + RXDFETAP2OVRDEN_indelay <= RXDFETAP2OVRDEN_ipd after IN_DELAY; + RXDFETAP3HOLD_indelay <= RXDFETAP3HOLD_ipd after IN_DELAY; + RXDFETAP3OVRDEN_indelay <= RXDFETAP3OVRDEN_ipd after IN_DELAY; + RXDFETAP4HOLD_indelay <= RXDFETAP4HOLD_ipd after IN_DELAY; + RXDFETAP4OVRDEN_indelay <= RXDFETAP4OVRDEN_ipd after IN_DELAY; + RXDFETAP5HOLD_indelay <= RXDFETAP5HOLD_ipd after IN_DELAY; + RXDFETAP5OVRDEN_indelay <= RXDFETAP5OVRDEN_ipd after IN_DELAY; + RXDFETAP6HOLD_indelay <= RXDFETAP6HOLD_ipd after IN_DELAY; + RXDFETAP6OVRDEN_indelay <= RXDFETAP6OVRDEN_ipd after IN_DELAY; + RXDFETAP7HOLD_indelay <= RXDFETAP7HOLD_ipd after IN_DELAY; + RXDFETAP7OVRDEN_indelay <= RXDFETAP7OVRDEN_ipd after IN_DELAY; + RXDFEUTHOLD_indelay <= RXDFEUTHOLD_ipd after IN_DELAY; + RXDFEUTOVRDEN_indelay <= RXDFEUTOVRDEN_ipd after IN_DELAY; + RXDFEVPHOLD_indelay <= RXDFEVPHOLD_ipd after IN_DELAY; + RXDFEVPOVRDEN_indelay <= RXDFEVPOVRDEN_ipd after IN_DELAY; + RXDFEVSEN_indelay <= RXDFEVSEN_ipd after IN_DELAY; + RXDFEXYDEN_indelay <= RXDFEXYDEN_ipd after IN_DELAY; + RXDLYBYPASS_indelay <= RXDLYBYPASS_ipd after IN_DELAY; + RXDLYEN_indelay <= RXDLYEN_ipd after IN_DELAY; + RXDLYOVRDEN_indelay <= RXDLYOVRDEN_ipd after IN_DELAY; + RXDLYSRESET_indelay <= RXDLYSRESET_ipd after IN_DELAY; + RXELECIDLEMODE_indelay <= RXELECIDLEMODE_ipd after IN_DELAY; + RXGEARBOXSLIP_indelay <= RXGEARBOXSLIP_ipd after IN_DELAY; + RXLPMEN_indelay <= RXLPMEN_ipd after IN_DELAY; + RXLPMHFHOLD_indelay <= RXLPMHFHOLD_ipd after IN_DELAY; + RXLPMHFOVRDEN_indelay <= RXLPMHFOVRDEN_ipd after IN_DELAY; + RXLPMLFHOLD_indelay <= RXLPMLFHOLD_ipd after IN_DELAY; + RXLPMLFKLOVRDEN_indelay <= RXLPMLFKLOVRDEN_ipd after IN_DELAY; + RXMCOMMAALIGNEN_indelay <= RXMCOMMAALIGNEN_ipd after IN_DELAY; + RXMONITORSEL_indelay <= RXMONITORSEL_ipd after IN_DELAY; + RXOOBRESET_indelay <= RXOOBRESET_ipd after IN_DELAY; + RXOSCALRESET_indelay <= RXOSCALRESET_ipd after IN_DELAY; + RXOSHOLD_indelay <= RXOSHOLD_ipd after IN_DELAY; + RXOSINTCFG_indelay <= RXOSINTCFG_ipd after IN_DELAY; + RXOSINTEN_indelay <= RXOSINTEN_ipd after IN_DELAY; + RXOSINTHOLD_indelay <= RXOSINTHOLD_ipd after IN_DELAY; + RXOSINTID0_indelay <= RXOSINTID0_ipd after IN_DELAY; + RXOSINTNTRLEN_indelay <= RXOSINTNTRLEN_ipd after IN_DELAY; + RXOSINTOVRDEN_indelay <= RXOSINTOVRDEN_ipd after IN_DELAY; + RXOSINTSTROBE_indelay <= RXOSINTSTROBE_ipd after IN_DELAY; + RXOSINTTESTOVRDEN_indelay <= RXOSINTTESTOVRDEN_ipd after IN_DELAY; + RXOSOVRDEN_indelay <= RXOSOVRDEN_ipd after IN_DELAY; + RXOUTCLKSEL_indelay <= RXOUTCLKSEL_ipd after IN_DELAY; + RXPCOMMAALIGNEN_indelay <= RXPCOMMAALIGNEN_ipd after IN_DELAY; + RXPCSRESET_indelay <= RXPCSRESET_ipd after IN_DELAY; + RXPD_indelay <= RXPD_ipd after IN_DELAY; + RXPHALIGNEN_indelay <= RXPHALIGNEN_ipd after IN_DELAY; + RXPHALIGN_indelay <= RXPHALIGN_ipd after IN_DELAY; + RXPHDLYPD_indelay <= RXPHDLYPD_ipd after IN_DELAY; + RXPHDLYRESET_indelay <= RXPHDLYRESET_ipd after IN_DELAY; + RXPHOVRDEN_indelay <= RXPHOVRDEN_ipd after IN_DELAY; + RXPMARESET_indelay <= RXPMARESET_ipd after IN_DELAY; + RXPOLARITY_indelay <= RXPOLARITY_ipd after IN_DELAY; + RXPRBSCNTRESET_indelay <= RXPRBSCNTRESET_ipd after IN_DELAY; + RXPRBSSEL_indelay <= RXPRBSSEL_ipd after IN_DELAY; + RXQPIEN_indelay <= RXQPIEN_ipd after IN_DELAY; + RXRATEMODE_indelay <= RXRATEMODE_ipd after IN_DELAY; + RXRATE_indelay <= RXRATE_ipd after IN_DELAY; + RXSLIDE_indelay <= RXSLIDE_ipd after IN_DELAY; + RXSYNCALLIN_indelay <= RXSYNCALLIN_ipd after IN_DELAY; + RXSYNCIN_indelay <= RXSYNCIN_ipd after IN_DELAY; + RXSYNCMODE_indelay <= RXSYNCMODE_ipd after IN_DELAY; + RXSYSCLKSEL_indelay <= RXSYSCLKSEL_ipd after IN_DELAY; + RXUSERRDY_indelay <= RXUSERRDY_ipd after IN_DELAY; + SETERRSTATUS_indelay <= SETERRSTATUS_ipd after IN_DELAY; + TSTIN_indelay <= TSTIN_ipd after IN_DELAY; + TX8B10BBYPASS_indelay <= TX8B10BBYPASS_ipd after IN_DELAY; + TX8B10BEN_indelay <= TX8B10BEN_ipd after IN_DELAY; + TXBUFDIFFCTRL_indelay <= TXBUFDIFFCTRL_ipd after IN_DELAY; + TXCHARDISPMODE_indelay <= TXCHARDISPMODE_ipd after IN_DELAY; + TXCHARDISPVAL_indelay <= TXCHARDISPVAL_ipd after IN_DELAY; + TXCHARISK_indelay <= TXCHARISK_ipd after IN_DELAY; + TXCOMINIT_indelay <= TXCOMINIT_ipd after IN_DELAY; + TXCOMSAS_indelay <= TXCOMSAS_ipd after IN_DELAY; + TXCOMWAKE_indelay <= TXCOMWAKE_ipd after IN_DELAY; + TXDATA_indelay <= TXDATA_ipd after IN_DELAY; + TXDEEMPH_indelay <= TXDEEMPH_ipd after IN_DELAY; + TXDETECTRX_indelay <= TXDETECTRX_ipd after IN_DELAY; + TXDIFFCTRL_indelay <= TXDIFFCTRL_ipd after IN_DELAY; + TXDIFFPD_indelay <= TXDIFFPD_ipd after IN_DELAY; + TXDLYBYPASS_indelay <= TXDLYBYPASS_ipd after IN_DELAY; + TXDLYEN_indelay <= TXDLYEN_ipd after IN_DELAY; + TXDLYHOLD_indelay <= TXDLYHOLD_ipd after IN_DELAY; + TXDLYOVRDEN_indelay <= TXDLYOVRDEN_ipd after IN_DELAY; + TXDLYSRESET_indelay <= TXDLYSRESET_ipd after IN_DELAY; + TXDLYUPDOWN_indelay <= TXDLYUPDOWN_ipd after IN_DELAY; + TXELECIDLE_indelay <= TXELECIDLE_ipd after IN_DELAY; + TXHEADER_indelay <= TXHEADER_ipd after IN_DELAY; + TXINHIBIT_indelay <= TXINHIBIT_ipd after IN_DELAY; + TXMAINCURSOR_indelay <= TXMAINCURSOR_ipd after IN_DELAY; + TXMARGIN_indelay <= TXMARGIN_ipd after IN_DELAY; + TXOUTCLKSEL_indelay <= TXOUTCLKSEL_ipd after IN_DELAY; + TXPCSRESET_indelay <= TXPCSRESET_ipd after IN_DELAY; + TXPDELECIDLEMODE_indelay <= TXPDELECIDLEMODE_ipd after IN_DELAY; + TXPD_indelay <= TXPD_ipd after IN_DELAY; + TXPHALIGNEN_indelay <= TXPHALIGNEN_ipd after IN_DELAY; + TXPHALIGN_indelay <= TXPHALIGN_ipd after IN_DELAY; + TXPHDLYPD_indelay <= TXPHDLYPD_ipd after IN_DELAY; + TXPHDLYRESET_indelay <= TXPHDLYRESET_ipd after IN_DELAY; + TXPHINIT_indelay <= TXPHINIT_ipd after IN_DELAY; + TXPHOVRDEN_indelay <= TXPHOVRDEN_ipd after IN_DELAY; + TXPIPPMEN_indelay <= TXPIPPMEN_ipd after IN_DELAY; + TXPIPPMOVRDEN_indelay <= TXPIPPMOVRDEN_ipd after IN_DELAY; + TXPIPPMPD_indelay <= TXPIPPMPD_ipd after IN_DELAY; + TXPIPPMSEL_indelay <= TXPIPPMSEL_ipd after IN_DELAY; + TXPIPPMSTEPSIZE_indelay <= TXPIPPMSTEPSIZE_ipd after IN_DELAY; + TXPISOPD_indelay <= TXPISOPD_ipd after IN_DELAY; + TXPMARESET_indelay <= TXPMARESET_ipd after IN_DELAY; + TXPOLARITY_indelay <= TXPOLARITY_ipd after IN_DELAY; + TXPOSTCURSORINV_indelay <= TXPOSTCURSORINV_ipd after IN_DELAY; + TXPOSTCURSOR_indelay <= TXPOSTCURSOR_ipd after IN_DELAY; + TXPRBSFORCEERR_indelay <= TXPRBSFORCEERR_ipd after IN_DELAY; + TXPRBSSEL_indelay <= TXPRBSSEL_ipd after IN_DELAY; + TXPRECURSORINV_indelay <= TXPRECURSORINV_ipd after IN_DELAY; + TXPRECURSOR_indelay <= TXPRECURSOR_ipd after IN_DELAY; + TXQPIBIASEN_indelay <= TXQPIBIASEN_ipd after IN_DELAY; + TXQPISTRONGPDOWN_indelay <= TXQPISTRONGPDOWN_ipd after IN_DELAY; + TXQPIWEAKPUP_indelay <= TXQPIWEAKPUP_ipd after IN_DELAY; + TXRATEMODE_indelay <= TXRATEMODE_ipd after IN_DELAY; + TXRATE_indelay <= TXRATE_ipd after IN_DELAY; + TXSEQUENCE_indelay <= TXSEQUENCE_ipd after IN_DELAY; + TXSTARTSEQ_indelay <= TXSTARTSEQ_ipd after IN_DELAY; + TXSWING_indelay <= TXSWING_ipd after IN_DELAY; + TXSYNCALLIN_indelay <= TXSYNCALLIN_ipd after IN_DELAY; + TXSYNCIN_indelay <= TXSYNCIN_ipd after IN_DELAY; + TXSYNCMODE_indelay <= TXSYNCMODE_ipd after IN_DELAY; + TXSYSCLKSEL_indelay <= TXSYSCLKSEL_ipd after IN_DELAY; + TXUSERRDY_indelay <= TXUSERRDY_ipd after IN_DELAY; + + IS_CLKRSVD0_INVERTED_BIN <= TO_X01(IS_CLKRSVD0_INVERTED); + IS_CLKRSVD1_INVERTED_BIN <= TO_X01(IS_CLKRSVD1_INVERTED); + IS_CPLLLOCKDETCLK_INVERTED_BIN <= TO_X01(IS_CPLLLOCKDETCLK_INVERTED); + IS_DMONITORCLK_INVERTED_BIN <= TO_X01(IS_DMONITORCLK_INVERTED); + IS_DRPCLK_INVERTED_BIN <= TO_X01(IS_DRPCLK_INVERTED); + IS_GTGREFCLK_INVERTED_BIN <= TO_X01(IS_GTGREFCLK_INVERTED); + IS_RXUSRCLK2_INVERTED_BIN <= TO_X01(IS_RXUSRCLK2_INVERTED); + IS_RXUSRCLK_INVERTED_BIN <= TO_X01(IS_RXUSRCLK_INVERTED); + IS_SIGVALIDCLK_INVERTED_BIN <= TO_X01(IS_SIGVALIDCLK_INVERTED); + IS_TXPHDLYTSTCLK_INVERTED_BIN <= TO_X01(IS_TXPHDLYTSTCLK_INVERTED); + IS_TXUSRCLK2_INVERTED_BIN <= TO_X01(IS_TXUSRCLK2_INVERTED); + IS_TXUSRCLK_INVERTED_BIN <= TO_X01(IS_TXUSRCLK_INVERTED); + + + GTHE2_CHANNEL_INST : GTHE2_CHANNEL_FAST_WRAP + generic map ( + ACJTAG_DEBUG_MODE => ACJTAG_DEBUG_MODE_STRING, + ACJTAG_MODE => ACJTAG_MODE_STRING, + ACJTAG_RESET => ACJTAG_RESET_STRING, + ADAPT_CFG0 => ADAPT_CFG0_STRING, + ALIGN_COMMA_DOUBLE => ALIGN_COMMA_DOUBLE, + ALIGN_COMMA_ENABLE => ALIGN_COMMA_ENABLE_STRING, + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + ALIGN_MCOMMA_DET => ALIGN_MCOMMA_DET, + ALIGN_MCOMMA_VALUE => ALIGN_MCOMMA_VALUE_STRING, + ALIGN_PCOMMA_DET => ALIGN_PCOMMA_DET, + ALIGN_PCOMMA_VALUE => ALIGN_PCOMMA_VALUE_STRING, + A_RXOSCALRESET => A_RXOSCALRESET_STRING, + CBCC_DATA_SOURCE_SEL => CBCC_DATA_SOURCE_SEL, + CFOK_CFG => CFOK_CFG_STRING, + CFOK_CFG2 => CFOK_CFG2_STRING, + CFOK_CFG3 => CFOK_CFG3_STRING, + CHAN_BOND_KEEP_ALIGN => CHAN_BOND_KEEP_ALIGN, + CHAN_BOND_MAX_SKEW => CHAN_BOND_MAX_SKEW, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_STRING, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_STRING, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_STRING, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_STRING, + CHAN_BOND_SEQ_1_ENABLE => CHAN_BOND_SEQ_1_ENABLE_STRING, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_STRING, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_STRING, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_STRING, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_STRING, + CHAN_BOND_SEQ_2_ENABLE => CHAN_BOND_SEQ_2_ENABLE_STRING, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_PRECEDENCE => CLK_COR_PRECEDENCE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_STRING, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_STRING, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_STRING, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_STRING, + CLK_COR_SEQ_1_ENABLE => CLK_COR_SEQ_1_ENABLE_STRING, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_STRING, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_STRING, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_STRING, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_STRING, + CLK_COR_SEQ_2_ENABLE => CLK_COR_SEQ_2_ENABLE_STRING, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CPLL_CFG => CPLL_CFG_STRING, + CPLL_FBDIV => CPLL_FBDIV, + CPLL_FBDIV_45 => CPLL_FBDIV_45, + CPLL_INIT_CFG => CPLL_INIT_CFG_STRING, + CPLL_LOCK_CFG => CPLL_LOCK_CFG_STRING, + CPLL_REFCLK_DIV => CPLL_REFCLK_DIV, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + DMONITOR_CFG => DMONITOR_CFG_STRING, + ES_CLK_PHASE_SEL => ES_CLK_PHASE_SEL_STRING, + ES_CONTROL => ES_CONTROL_STRING, + ES_ERRDET_EN => ES_ERRDET_EN, + ES_EYE_SCAN_EN => ES_EYE_SCAN_EN, + ES_HORZ_OFFSET => ES_HORZ_OFFSET_STRING, + ES_PMA_CFG => ES_PMA_CFG_STRING, + ES_PRESCALE => ES_PRESCALE_STRING, + ES_QUALIFIER => ES_QUALIFIER_STRING, + ES_QUAL_MASK => ES_QUAL_MASK_STRING, + ES_SDATA_MASK => ES_SDATA_MASK_STRING, + ES_VERT_OFFSET => ES_VERT_OFFSET_STRING, + FTS_DESKEW_SEQ_ENABLE => FTS_DESKEW_SEQ_ENABLE_STRING, + FTS_LANE_DESKEW_CFG => FTS_LANE_DESKEW_CFG_STRING, + FTS_LANE_DESKEW_EN => FTS_LANE_DESKEW_EN, + GEARBOX_MODE => GEARBOX_MODE_STRING, + LOOPBACK_CFG => LOOPBACK_CFG_STRING, + OUTREFCLK_SEL_INV => OUTREFCLK_SEL_INV_STRING, + PCS_PCIE_EN => PCS_PCIE_EN, + PCS_RSVD_ATTR => PCS_RSVD_ATTR_STRING, + PD_TRANS_TIME_FROM_P2 => PD_TRANS_TIME_FROM_P2_STRING, + PD_TRANS_TIME_NONE_P2 => PD_TRANS_TIME_NONE_P2_STRING, + PD_TRANS_TIME_TO_P2 => PD_TRANS_TIME_TO_P2_STRING, + PMA_RSV => PMA_RSV_STRING, + PMA_RSV2 => PMA_RSV2_STRING, + PMA_RSV3 => PMA_RSV3_STRING, + PMA_RSV4 => PMA_RSV4_STRING, + PMA_RSV5 => PMA_RSV5_STRING, + RESET_POWERSAVE_DISABLE => RESET_POWERSAVE_DISABLE_STRING, + RXBUFRESET_TIME => RXBUFRESET_TIME_STRING, + RXBUF_ADDR_MODE => RXBUF_ADDR_MODE, + RXBUF_EIDLE_HI_CNT => RXBUF_EIDLE_HI_CNT_STRING, + RXBUF_EIDLE_LO_CNT => RXBUF_EIDLE_LO_CNT_STRING, + RXBUF_EN => RXBUF_EN, + RXBUF_RESET_ON_CB_CHANGE => RXBUF_RESET_ON_CB_CHANGE, + RXBUF_RESET_ON_COMMAALIGN => RXBUF_RESET_ON_COMMAALIGN, + RXBUF_RESET_ON_EIDLE => RXBUF_RESET_ON_EIDLE, + RXBUF_RESET_ON_RATE_CHANGE => RXBUF_RESET_ON_RATE_CHANGE, + RXBUF_THRESH_OVFLW => RXBUF_THRESH_OVFLW, + RXBUF_THRESH_OVRD => RXBUF_THRESH_OVRD, + RXBUF_THRESH_UNDFLW => RXBUF_THRESH_UNDFLW, + RXCDRFREQRESET_TIME => RXCDRFREQRESET_TIME_STRING, + RXCDRPHRESET_TIME => RXCDRPHRESET_TIME_STRING, + RXCDR_CFG => RXCDR_CFG_STRING, + RXCDR_FR_RESET_ON_EIDLE => RXCDR_FR_RESET_ON_EIDLE_STRING, + RXCDR_HOLD_DURING_EIDLE => RXCDR_HOLD_DURING_EIDLE_STRING, + RXCDR_LOCK_CFG => RXCDR_LOCK_CFG_STRING, + RXCDR_PH_RESET_ON_EIDLE => RXCDR_PH_RESET_ON_EIDLE_STRING, + RXDFELPMRESET_TIME => RXDFELPMRESET_TIME_STRING, + RXDLY_CFG => RXDLY_CFG_STRING, + RXDLY_LCFG => RXDLY_LCFG_STRING, + RXDLY_TAP_CFG => RXDLY_TAP_CFG_STRING, + RXGEARBOX_EN => RXGEARBOX_EN, + RXISCANRESET_TIME => RXISCANRESET_TIME_STRING, + RXLPM_HF_CFG => RXLPM_HF_CFG_STRING, + RXLPM_LF_CFG => RXLPM_LF_CFG_STRING, + RXOOB_CFG => RXOOB_CFG_STRING, + RXOOB_CLK_CFG => RXOOB_CLK_CFG, + RXOSCALRESET_TIME => RXOSCALRESET_TIME_STRING, + RXOSCALRESET_TIMEOUT => RXOSCALRESET_TIMEOUT_STRING, + RXOUT_DIV => RXOUT_DIV, + RXPCSRESET_TIME => RXPCSRESET_TIME_STRING, + RXPHDLY_CFG => RXPHDLY_CFG_STRING, + RXPH_CFG => RXPH_CFG_STRING, + RXPH_MONITOR_SEL => RXPH_MONITOR_SEL_STRING, + RXPI_CFG0 => RXPI_CFG0_STRING, + RXPI_CFG1 => RXPI_CFG1_STRING, + RXPI_CFG2 => RXPI_CFG2_STRING, + RXPI_CFG3 => RXPI_CFG3_STRING, + RXPI_CFG4 => RXPI_CFG4_STRING, + RXPI_CFG5 => RXPI_CFG5_STRING, + RXPI_CFG6 => RXPI_CFG6_STRING, + RXPMARESET_TIME => RXPMARESET_TIME_STRING, + RXPRBS_ERR_LOOPBACK => RXPRBS_ERR_LOOPBACK_STRING, + RXSLIDE_AUTO_WAIT => RXSLIDE_AUTO_WAIT, + RXSLIDE_MODE => RXSLIDE_MODE, + RXSYNC_MULTILANE => RXSYNC_MULTILANE_STRING, + RXSYNC_OVRD => RXSYNC_OVRD_STRING, + RXSYNC_SKIP_DA => RXSYNC_SKIP_DA_STRING, + RX_BIAS_CFG => RX_BIAS_CFG_STRING, + RX_BUFFER_CFG => RX_BUFFER_CFG_STRING, + RX_CLK25_DIV => RX_CLK25_DIV, + RX_CLKMUX_PD => RX_CLKMUX_PD_STRING, + RX_CM_SEL => RX_CM_SEL_STRING, + RX_CM_TRIM => RX_CM_TRIM_STRING, + RX_DATA_WIDTH => RX_DATA_WIDTH, + RX_DDI_SEL => RX_DDI_SEL_STRING, + RX_DEBUG_CFG => RX_DEBUG_CFG_STRING, + RX_DEFER_RESET_BUF_EN => RX_DEFER_RESET_BUF_EN, + RX_DFELPM_CFG0 => RX_DFELPM_CFG0_STRING, + RX_DFELPM_CFG1 => RX_DFELPM_CFG1_STRING, + RX_DFELPM_KLKH_AGC_STUP_EN => RX_DFELPM_KLKH_AGC_STUP_EN_STRING, + RX_DFE_AGC_CFG0 => RX_DFE_AGC_CFG0_STRING, + RX_DFE_AGC_CFG1 => RX_DFE_AGC_CFG1_STRING, + RX_DFE_AGC_CFG2 => RX_DFE_AGC_CFG2_STRING, + RX_DFE_AGC_OVRDEN => RX_DFE_AGC_OVRDEN_STRING, + RX_DFE_GAIN_CFG => RX_DFE_GAIN_CFG_STRING, + RX_DFE_H2_CFG => RX_DFE_H2_CFG_STRING, + RX_DFE_H3_CFG => RX_DFE_H3_CFG_STRING, + RX_DFE_H4_CFG => RX_DFE_H4_CFG_STRING, + RX_DFE_H5_CFG => RX_DFE_H5_CFG_STRING, + RX_DFE_H6_CFG => RX_DFE_H6_CFG_STRING, + RX_DFE_H7_CFG => RX_DFE_H7_CFG_STRING, + RX_DFE_KL_CFG => RX_DFE_KL_CFG_STRING, + RX_DFE_KL_LPM_KH_CFG0 => RX_DFE_KL_LPM_KH_CFG0_STRING, + RX_DFE_KL_LPM_KH_CFG1 => RX_DFE_KL_LPM_KH_CFG1_STRING, + RX_DFE_KL_LPM_KH_CFG2 => RX_DFE_KL_LPM_KH_CFG2_STRING, + RX_DFE_KL_LPM_KH_OVRDEN => RX_DFE_KL_LPM_KH_OVRDEN_STRING, + RX_DFE_KL_LPM_KL_CFG0 => RX_DFE_KL_LPM_KL_CFG0_STRING, + RX_DFE_KL_LPM_KL_CFG1 => RX_DFE_KL_LPM_KL_CFG1_STRING, + RX_DFE_KL_LPM_KL_CFG2 => RX_DFE_KL_LPM_KL_CFG2_STRING, + RX_DFE_KL_LPM_KL_OVRDEN => RX_DFE_KL_LPM_KL_OVRDEN_STRING, + RX_DFE_LPM_CFG => RX_DFE_LPM_CFG_STRING, + RX_DFE_LPM_HOLD_DURING_EIDLE => RX_DFE_LPM_HOLD_DURING_EIDLE_STRING, + RX_DFE_ST_CFG => RX_DFE_ST_CFG_STRING, + RX_DFE_UT_CFG => RX_DFE_UT_CFG_STRING, + RX_DFE_VP_CFG => RX_DFE_VP_CFG_STRING, + RX_DISPERR_SEQ_MATCH => RX_DISPERR_SEQ_MATCH, + RX_INT_DATAWIDTH => RX_INT_DATAWIDTH, + RX_OS_CFG => RX_OS_CFG_STRING, + RX_SIG_VALID_DLY => RX_SIG_VALID_DLY, + RX_XCLK_SEL => RX_XCLK_SEL, + SAS_MAX_COM => SAS_MAX_COM, + SAS_MIN_COM => SAS_MIN_COM, + SATA_BURST_SEQ_LEN => SATA_BURST_SEQ_LEN_STRING, + SATA_BURST_VAL => SATA_BURST_VAL_STRING, + SATA_CPLL_CFG => SATA_CPLL_CFG, + SATA_EIDLE_VAL => SATA_EIDLE_VAL_STRING, + SATA_MAX_BURST => SATA_MAX_BURST, + SATA_MAX_INIT => SATA_MAX_INIT, + SATA_MAX_WAKE => SATA_MAX_WAKE, + SATA_MIN_BURST => SATA_MIN_BURST, + SATA_MIN_INIT => SATA_MIN_INIT, + SATA_MIN_WAKE => SATA_MIN_WAKE, + SHOW_REALIGN_COMMA => SHOW_REALIGN_COMMA, + SIM_CPLLREFCLK_SEL => SIM_CPLLREFCLK_SEL_STRING, + SIM_RECEIVER_DETECT_PASS => SIM_RECEIVER_DETECT_PASS, + SIM_RESET_SPEEDUP => SIM_RESET_SPEEDUP, + SIM_TX_EIDLE_DRIVE_LEVEL => SIM_TX_EIDLE_DRIVE_LEVEL, + SIM_VERSION => SIM_VERSION, + TERM_RCAL_CFG => TERM_RCAL_CFG_STRING, + TERM_RCAL_OVRD => TERM_RCAL_OVRD_STRING, + TRANS_TIME_RATE => TRANS_TIME_RATE_STRING, + TST_RSV => TST_RSV_STRING, + TXBUF_EN => TXBUF_EN, + TXBUF_RESET_ON_RATE_CHANGE => TXBUF_RESET_ON_RATE_CHANGE, + TXDLY_CFG => TXDLY_CFG_STRING, + TXDLY_LCFG => TXDLY_LCFG_STRING, + TXDLY_TAP_CFG => TXDLY_TAP_CFG_STRING, + TXGEARBOX_EN => TXGEARBOX_EN, + TXOOB_CFG => TXOOB_CFG_STRING, + TXOUT_DIV => TXOUT_DIV, + TXPCSRESET_TIME => TXPCSRESET_TIME_STRING, + TXPHDLY_CFG => TXPHDLY_CFG_STRING, + TXPH_CFG => TXPH_CFG_STRING, + TXPH_MONITOR_SEL => TXPH_MONITOR_SEL_STRING, + TXPI_CFG0 => TXPI_CFG0_STRING, + TXPI_CFG1 => TXPI_CFG1_STRING, + TXPI_CFG2 => TXPI_CFG2_STRING, + TXPI_CFG3 => TXPI_CFG3_STRING, + TXPI_CFG4 => TXPI_CFG4_STRING, + TXPI_CFG5 => TXPI_CFG5_STRING, + TXPI_GREY_SEL => TXPI_GREY_SEL_STRING, + TXPI_INVSTROBE_SEL => TXPI_INVSTROBE_SEL_STRING, + TXPI_PPMCLK_SEL => TXPI_PPMCLK_SEL, + TXPI_PPM_CFG => TXPI_PPM_CFG_STRING, + TXPI_SYNFREQ_PPM => TXPI_SYNFREQ_PPM_STRING, + TXPMARESET_TIME => TXPMARESET_TIME_STRING, + TXSYNC_MULTILANE => TXSYNC_MULTILANE_STRING, + TXSYNC_OVRD => TXSYNC_OVRD_STRING, + TXSYNC_SKIP_DA => TXSYNC_SKIP_DA_STRING, + TX_CLK25_DIV => TX_CLK25_DIV, + TX_CLKMUX_PD => TX_CLKMUX_PD_STRING, + TX_DATA_WIDTH => TX_DATA_WIDTH, + TX_DEEMPH0 => TX_DEEMPH0_STRING, + TX_DEEMPH1 => TX_DEEMPH1_STRING, + TX_DRIVE_MODE => TX_DRIVE_MODE, + TX_EIDLE_ASSERT_DELAY => TX_EIDLE_ASSERT_DELAY_STRING, + TX_EIDLE_DEASSERT_DELAY => TX_EIDLE_DEASSERT_DELAY_STRING, + TX_INT_DATAWIDTH => TX_INT_DATAWIDTH, + TX_LOOPBACK_DRIVE_HIZ => TX_LOOPBACK_DRIVE_HIZ, + TX_MAINCURSOR_SEL => TX_MAINCURSOR_SEL_STRING, + TX_MARGIN_FULL_0 => TX_MARGIN_FULL_0_STRING, + TX_MARGIN_FULL_1 => TX_MARGIN_FULL_1_STRING, + TX_MARGIN_FULL_2 => TX_MARGIN_FULL_2_STRING, + TX_MARGIN_FULL_3 => TX_MARGIN_FULL_3_STRING, + TX_MARGIN_FULL_4 => TX_MARGIN_FULL_4_STRING, + TX_MARGIN_LOW_0 => TX_MARGIN_LOW_0_STRING, + TX_MARGIN_LOW_1 => TX_MARGIN_LOW_1_STRING, + TX_MARGIN_LOW_2 => TX_MARGIN_LOW_2_STRING, + TX_MARGIN_LOW_3 => TX_MARGIN_LOW_3_STRING, + TX_MARGIN_LOW_4 => TX_MARGIN_LOW_4_STRING, + TX_QPI_STATUS_EN => TX_QPI_STATUS_EN_STRING, + TX_RXDETECT_CFG => TX_RXDETECT_CFG_STRING, + TX_RXDETECT_PRECHARGE_TIME => TX_RXDETECT_PRECHARGE_TIME_STRING, + TX_RXDETECT_REF => TX_RXDETECT_REF_STRING, + TX_XCLK_SEL => TX_XCLK_SEL, + UCODEER_CLR => UCODEER_CLR_STRING, + USE_PCS_CLK_PHASE_SEL => USE_PCS_CLK_PHASE_SEL_STRING + ) + + port map ( + GSR => TO_X01(GSR), + CPLLFBCLKLOST => CPLLFBCLKLOST_outdelay, + CPLLLOCK => CPLLLOCK_outdelay, + CPLLREFCLKLOST => CPLLREFCLKLOST_outdelay, + DMONITOROUT => DMONITOROUT_outdelay, + DRPDO => DRPDO_outdelay, + DRPRDY => DRPRDY_outdelay, + EYESCANDATAERROR => EYESCANDATAERROR_outdelay, + GTHTXN => GTHTXN_outdelay, + GTHTXP => GTHTXP_outdelay, + GTREFCLKMONITOR => GTREFCLKMONITOR_outdelay, + PCSRSVDOUT => PCSRSVDOUT_outdelay, + PHYSTATUS => PHYSTATUS_outdelay, + RSOSINTDONE => RSOSINTDONE_outdelay, + RXBUFSTATUS => RXBUFSTATUS_outdelay, + RXBYTEISALIGNED => RXBYTEISALIGNED_outdelay, + RXBYTEREALIGN => RXBYTEREALIGN_outdelay, + RXCDRLOCK => RXCDRLOCK_outdelay, + RXCHANBONDSEQ => RXCHANBONDSEQ_outdelay, + RXCHANISALIGNED => RXCHANISALIGNED_outdelay, + RXCHANREALIGN => RXCHANREALIGN_outdelay, + RXCHARISCOMMA => RXCHARISCOMMA_outdelay, + RXCHARISK => RXCHARISK_outdelay, + RXCHBONDO => RXCHBONDO_outdelay, + RXCLKCORCNT => RXCLKCORCNT_outdelay, + RXCOMINITDET => RXCOMINITDET_outdelay, + RXCOMMADET => RXCOMMADET_outdelay, + RXCOMSASDET => RXCOMSASDET_outdelay, + RXCOMWAKEDET => RXCOMWAKEDET_outdelay, + RXDATA => RXDATA_outdelay, + RXDATAVALID => RXDATAVALID_outdelay, + RXDFESLIDETAPSTARTED => RXDFESLIDETAPSTARTED_outdelay, + RXDFESLIDETAPSTROBEDONE => RXDFESLIDETAPSTROBEDONE_outdelay, + RXDFESLIDETAPSTROBESTARTED => RXDFESLIDETAPSTROBESTARTED_outdelay, + RXDFESTADAPTDONE => RXDFESTADAPTDONE_outdelay, + RXDISPERR => RXDISPERR_outdelay, + RXDLYSRESETDONE => RXDLYSRESETDONE_outdelay, + RXELECIDLE => RXELECIDLE_outdelay, + RXHEADER => RXHEADER_outdelay, + RXHEADERVALID => RXHEADERVALID_outdelay, + RXMONITOROUT => RXMONITOROUT_outdelay, + RXNOTINTABLE => RXNOTINTABLE_outdelay, + RXOSINTSTARTED => RXOSINTSTARTED_outdelay, + RXOSINTSTROBEDONE => RXOSINTSTROBEDONE_outdelay, + RXOSINTSTROBESTARTED => RXOSINTSTROBESTARTED_outdelay, + RXOUTCLK => RXOUTCLK_outdelay, + RXOUTCLKFABRIC => RXOUTCLKFABRIC_outdelay, + RXOUTCLKPCS => RXOUTCLKPCS_outdelay, + RXPHALIGNDONE => RXPHALIGNDONE_outdelay, + RXPHMONITOR => RXPHMONITOR_outdelay, + RXPHSLIPMONITOR => RXPHSLIPMONITOR_outdelay, + RXPMARESETDONE => RXPMARESETDONE_outdelay, + RXPRBSERR => RXPRBSERR_outdelay, + RXQPISENN => RXQPISENN_outdelay, + RXQPISENP => RXQPISENP_outdelay, + RXRATEDONE => RXRATEDONE_outdelay, + RXRESETDONE => RXRESETDONE_outdelay, + RXSTARTOFSEQ => RXSTARTOFSEQ_outdelay, + RXSTATUS => RXSTATUS_outdelay, + RXSYNCDONE => RXSYNCDONE_outdelay, + RXSYNCOUT => RXSYNCOUT_outdelay, + RXVALID => RXVALID_outdelay, + TXBUFSTATUS => TXBUFSTATUS_outdelay, + TXCOMFINISH => TXCOMFINISH_outdelay, + TXDLYSRESETDONE => TXDLYSRESETDONE_outdelay, + TXGEARBOXREADY => TXGEARBOXREADY_outdelay, + TXOUTCLK => TXOUTCLK_outdelay, + TXOUTCLKFABRIC => TXOUTCLKFABRIC_outdelay, + TXOUTCLKPCS => TXOUTCLKPCS_outdelay, + TXPHALIGNDONE => TXPHALIGNDONE_outdelay, + TXPHINITDONE => TXPHINITDONE_outdelay, + TXPMARESETDONE => TXPMARESETDONE_outdelay, + TXQPISENN => TXQPISENN_outdelay, + TXQPISENP => TXQPISENP_outdelay, + TXRATEDONE => TXRATEDONE_outdelay, + TXRESETDONE => TXRESETDONE_outdelay, + TXSYNCDONE => TXSYNCDONE_outdelay, + TXSYNCOUT => TXSYNCOUT_outdelay, + CFGRESET => CFGRESET_indelay, + CLKRSVD0 => CLKRSVD0_indelay, + CLKRSVD1 => CLKRSVD1_indelay, + CPLLLOCKDETCLK => CPLLLOCKDETCLK_indelay, + CPLLLOCKEN => CPLLLOCKEN_indelay, + CPLLPD => CPLLPD_indelay, + CPLLREFCLKSEL => CPLLREFCLKSEL_indelay, + CPLLRESET => CPLLRESET_indelay, + DMONFIFORESET => DMONFIFORESET_indelay, + DMONITORCLK => DMONITORCLK_indelay, + DRPADDR => DRPADDR_indelay, + DRPCLK => DRPCLK_indelay, + DRPDI => DRPDI_indelay, + DRPEN => DRPEN_indelay, + DRPWE => DRPWE_indelay, + EYESCANMODE => EYESCANMODE_indelay, + EYESCANRESET => EYESCANRESET_indelay, + EYESCANTRIGGER => EYESCANTRIGGER_indelay, + GTGREFCLK => GTGREFCLK_indelay, + GTHRXN => GTHRXN_indelay, + GTHRXP => GTHRXP_indelay, + GTNORTHREFCLK0 => GTNORTHREFCLK0_indelay, + GTNORTHREFCLK1 => GTNORTHREFCLK1_indelay, + GTREFCLK0 => GTREFCLK0_indelay, + GTREFCLK1 => GTREFCLK1_indelay, + GTRESETSEL => GTRESETSEL_indelay, + GTRSVD => GTRSVD_indelay, + GTRXRESET => GTRXRESET_indelay, + GTSOUTHREFCLK0 => GTSOUTHREFCLK0_indelay, + GTSOUTHREFCLK1 => GTSOUTHREFCLK1_indelay, + GTTXRESET => GTTXRESET_indelay, + LOOPBACK => LOOPBACK_indelay, + PCSRSVDIN => PCSRSVDIN_indelay, + PCSRSVDIN2 => PCSRSVDIN2_indelay, + PMARSVDIN => PMARSVDIN_indelay, + QPLLCLK => QPLLCLK_indelay, + QPLLREFCLK => QPLLREFCLK_indelay, + RESETOVRD => RESETOVRD_indelay, + RX8B10BEN => RX8B10BEN_indelay, + RXADAPTSELTEST => RXADAPTSELTEST_indelay, + RXBUFRESET => RXBUFRESET_indelay, + RXCDRFREQRESET => RXCDRFREQRESET_indelay, + RXCDRHOLD => RXCDRHOLD_indelay, + RXCDROVRDEN => RXCDROVRDEN_indelay, + RXCDRRESET => RXCDRRESET_indelay, + RXCDRRESETRSV => RXCDRRESETRSV_indelay, + RXCHBONDEN => RXCHBONDEN_indelay, + RXCHBONDI => RXCHBONDI_indelay, + RXCHBONDLEVEL => RXCHBONDLEVEL_indelay, + RXCHBONDMASTER => RXCHBONDMASTER_indelay, + RXCHBONDSLAVE => RXCHBONDSLAVE_indelay, + RXCOMMADETEN => RXCOMMADETEN_indelay, + RXDDIEN => RXDDIEN_indelay, + RXDFEAGCHOLD => RXDFEAGCHOLD_indelay, + RXDFEAGCOVRDEN => RXDFEAGCOVRDEN_indelay, + RXDFEAGCTRL => RXDFEAGCTRL_indelay, + RXDFECM1EN => RXDFECM1EN_indelay, + RXDFELFHOLD => RXDFELFHOLD_indelay, + RXDFELFOVRDEN => RXDFELFOVRDEN_indelay, + RXDFELPMRESET => RXDFELPMRESET_indelay, + RXDFESLIDETAP => RXDFESLIDETAP_indelay, + RXDFESLIDETAPADAPTEN => RXDFESLIDETAPADAPTEN_indelay, + RXDFESLIDETAPHOLD => RXDFESLIDETAPHOLD_indelay, + RXDFESLIDETAPID => RXDFESLIDETAPID_indelay, + RXDFESLIDETAPINITOVRDEN => RXDFESLIDETAPINITOVRDEN_indelay, + RXDFESLIDETAPONLYADAPTEN => RXDFESLIDETAPONLYADAPTEN_indelay, + RXDFESLIDETAPOVRDEN => RXDFESLIDETAPOVRDEN_indelay, + RXDFESLIDETAPSTROBE => RXDFESLIDETAPSTROBE_indelay, + RXDFETAP2HOLD => RXDFETAP2HOLD_indelay, + RXDFETAP2OVRDEN => RXDFETAP2OVRDEN_indelay, + RXDFETAP3HOLD => RXDFETAP3HOLD_indelay, + RXDFETAP3OVRDEN => RXDFETAP3OVRDEN_indelay, + RXDFETAP4HOLD => RXDFETAP4HOLD_indelay, + RXDFETAP4OVRDEN => RXDFETAP4OVRDEN_indelay, + RXDFETAP5HOLD => RXDFETAP5HOLD_indelay, + RXDFETAP5OVRDEN => RXDFETAP5OVRDEN_indelay, + RXDFETAP6HOLD => RXDFETAP6HOLD_indelay, + RXDFETAP6OVRDEN => RXDFETAP6OVRDEN_indelay, + RXDFETAP7HOLD => RXDFETAP7HOLD_indelay, + RXDFETAP7OVRDEN => RXDFETAP7OVRDEN_indelay, + RXDFEUTHOLD => RXDFEUTHOLD_indelay, + RXDFEUTOVRDEN => RXDFEUTOVRDEN_indelay, + RXDFEVPHOLD => RXDFEVPHOLD_indelay, + RXDFEVPOVRDEN => RXDFEVPOVRDEN_indelay, + RXDFEVSEN => RXDFEVSEN_indelay, + RXDFEXYDEN => RXDFEXYDEN_indelay, + RXDLYBYPASS => RXDLYBYPASS_indelay, + RXDLYEN => RXDLYEN_indelay, + RXDLYOVRDEN => RXDLYOVRDEN_indelay, + RXDLYSRESET => RXDLYSRESET_indelay, + RXELECIDLEMODE => RXELECIDLEMODE_indelay, + RXGEARBOXSLIP => RXGEARBOXSLIP_indelay, + RXLPMEN => RXLPMEN_indelay, + RXLPMHFHOLD => RXLPMHFHOLD_indelay, + RXLPMHFOVRDEN => RXLPMHFOVRDEN_indelay, + RXLPMLFHOLD => RXLPMLFHOLD_indelay, + RXLPMLFKLOVRDEN => RXLPMLFKLOVRDEN_indelay, + RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_indelay, + RXMONITORSEL => RXMONITORSEL_indelay, + RXOOBRESET => RXOOBRESET_indelay, + RXOSCALRESET => RXOSCALRESET_indelay, + RXOSHOLD => RXOSHOLD_indelay, + RXOSINTCFG => RXOSINTCFG_indelay, + RXOSINTEN => RXOSINTEN_indelay, + RXOSINTHOLD => RXOSINTHOLD_indelay, + RXOSINTID0 => RXOSINTID0_indelay, + RXOSINTNTRLEN => RXOSINTNTRLEN_indelay, + RXOSINTOVRDEN => RXOSINTOVRDEN_indelay, + RXOSINTSTROBE => RXOSINTSTROBE_indelay, + RXOSINTTESTOVRDEN => RXOSINTTESTOVRDEN_indelay, + RXOSOVRDEN => RXOSOVRDEN_indelay, + RXOUTCLKSEL => RXOUTCLKSEL_indelay, + RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_indelay, + RXPCSRESET => RXPCSRESET_indelay, + RXPD => RXPD_indelay, + RXPHALIGN => RXPHALIGN_indelay, + RXPHALIGNEN => RXPHALIGNEN_indelay, + RXPHDLYPD => RXPHDLYPD_indelay, + RXPHDLYRESET => RXPHDLYRESET_indelay, + RXPHOVRDEN => RXPHOVRDEN_indelay, + RXPMARESET => RXPMARESET_indelay, + RXPOLARITY => RXPOLARITY_indelay, + RXPRBSCNTRESET => RXPRBSCNTRESET_indelay, + RXPRBSSEL => RXPRBSSEL_indelay, + RXQPIEN => RXQPIEN_indelay, + RXRATE => RXRATE_indelay, + RXRATEMODE => RXRATEMODE_indelay, + RXSLIDE => RXSLIDE_indelay, + RXSYNCALLIN => RXSYNCALLIN_indelay, + RXSYNCIN => RXSYNCIN_indelay, + RXSYNCMODE => RXSYNCMODE_indelay, + RXSYSCLKSEL => RXSYSCLKSEL_indelay, + RXUSERRDY => RXUSERRDY_indelay, + RXUSRCLK => RXUSRCLK_indelay, + RXUSRCLK2 => RXUSRCLK2_indelay, + SETERRSTATUS => SETERRSTATUS_indelay, + SIGVALIDCLK => SIGVALIDCLK_indelay, + TSTIN => TSTIN_indelay, + TX8B10BBYPASS => TX8B10BBYPASS_indelay, + TX8B10BEN => TX8B10BEN_indelay, + TXBUFDIFFCTRL => TXBUFDIFFCTRL_indelay, + TXCHARDISPMODE => TXCHARDISPMODE_indelay, + TXCHARDISPVAL => TXCHARDISPVAL_indelay, + TXCHARISK => TXCHARISK_indelay, + TXCOMINIT => TXCOMINIT_indelay, + TXCOMSAS => TXCOMSAS_indelay, + TXCOMWAKE => TXCOMWAKE_indelay, + TXDATA => TXDATA_indelay, + TXDEEMPH => TXDEEMPH_indelay, + TXDETECTRX => TXDETECTRX_indelay, + TXDIFFCTRL => TXDIFFCTRL_indelay, + TXDIFFPD => TXDIFFPD_indelay, + TXDLYBYPASS => TXDLYBYPASS_indelay, + TXDLYEN => TXDLYEN_indelay, + TXDLYHOLD => TXDLYHOLD_indelay, + TXDLYOVRDEN => TXDLYOVRDEN_indelay, + TXDLYSRESET => TXDLYSRESET_indelay, + TXDLYUPDOWN => TXDLYUPDOWN_indelay, + TXELECIDLE => TXELECIDLE_indelay, + TXHEADER => TXHEADER_indelay, + TXINHIBIT => TXINHIBIT_indelay, + TXMAINCURSOR => TXMAINCURSOR_indelay, + TXMARGIN => TXMARGIN_indelay, + TXOUTCLKSEL => TXOUTCLKSEL_indelay, + TXPCSRESET => TXPCSRESET_indelay, + TXPD => TXPD_indelay, + TXPDELECIDLEMODE => TXPDELECIDLEMODE_indelay, + TXPHALIGN => TXPHALIGN_indelay, + TXPHALIGNEN => TXPHALIGNEN_indelay, + TXPHDLYPD => TXPHDLYPD_indelay, + TXPHDLYRESET => TXPHDLYRESET_indelay, + TXPHDLYTSTCLK => TXPHDLYTSTCLK_indelay, + TXPHINIT => TXPHINIT_indelay, + TXPHOVRDEN => TXPHOVRDEN_indelay, + TXPIPPMEN => TXPIPPMEN_indelay, + TXPIPPMOVRDEN => TXPIPPMOVRDEN_indelay, + TXPIPPMPD => TXPIPPMPD_indelay, + TXPIPPMSEL => TXPIPPMSEL_indelay, + TXPIPPMSTEPSIZE => TXPIPPMSTEPSIZE_indelay, + TXPISOPD => TXPISOPD_indelay, + TXPMARESET => TXPMARESET_indelay, + TXPOLARITY => TXPOLARITY_indelay, + TXPOSTCURSOR => TXPOSTCURSOR_indelay, + TXPOSTCURSORINV => TXPOSTCURSORINV_indelay, + TXPRBSFORCEERR => TXPRBSFORCEERR_indelay, + TXPRBSSEL => TXPRBSSEL_indelay, + TXPRECURSOR => TXPRECURSOR_indelay, + TXPRECURSORINV => TXPRECURSORINV_indelay, + TXQPIBIASEN => TXQPIBIASEN_indelay, + TXQPISTRONGPDOWN => TXQPISTRONGPDOWN_indelay, + TXQPIWEAKPUP => TXQPIWEAKPUP_indelay, + TXRATE => TXRATE_indelay, + TXRATEMODE => TXRATEMODE_indelay, + TXSEQUENCE => TXSEQUENCE_indelay, + TXSTARTSEQ => TXSTARTSEQ_indelay, + TXSWING => TXSWING_indelay, + TXSYNCALLIN => TXSYNCALLIN_indelay, + TXSYNCIN => TXSYNCIN_indelay, + TXSYNCMODE => TXSYNCMODE_indelay, + TXSYSCLKSEL => TXSYSCLKSEL_indelay, + TXUSERRDY => TXUSERRDY_indelay, + TXUSRCLK => TXUSRCLK_indelay, + TXUSRCLK2 => TXUSRCLK2_indelay + ); + + + drp_monitor: process (DRPCLK_indelay) + + variable drpen_r1 : std_logic := '0'; + variable drpen_r2 : std_logic := '0'; + variable drpwe_r1 : std_logic := '0'; + variable drpwe_r2 : std_logic := '0'; + type statetype is (FSM_IDLE, FSM_WAIT); + variable sfsm : statetype := FSM_IDLE; + + begin -- process drp_monitor + + if (rising_edge(DRPCLK_indelay)) then + + -- pipeline the DRPEN and DRPWE + drpen_r2 := drpen_r1; + drpwe_r2 := drpwe_r1; + drpen_r1 := DRPEN_indelay; + drpwe_r1 := DRPWE_indelay; + + + -- Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 = '1') and (drpen_r2 = '1')) then + assert false + report "DRC Error : DRPEN is high for more than 1 DRPCLK." + severity failure; + end if; + + if ((drpwe_r1 = '1') and (drpwe_r2 = '1')) then + assert false + report "DRC Error : DRPWE is high for more than 1 DRPCLK." + severity failure; + end if; + + + -- After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case sfsm is + when FSM_IDLE => + if (DRPEN_indelay = '1') then + sfsm := FSM_WAIT; + end if; + + when FSM_WAIT => + + -- After the 1st DRPEN, 4 cases can happen + -- DRPEN DRPRDY NEXT STATE + -- 0 0 FSM_WAIT - wait for DRPRDY + -- 0 1 FSM_IDLE - normal operation + -- 1 0 FSM_WAIT - display error and wait for DRPRDY + -- 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.; + -- Add the check for another DPREN pulse + if(DRPEN_indelay = '1' and DRPRDY_out = '0') then + assert false + report "DRC Error : DRPEN is enabled before DRPRDY returns." + severity failure; + end if; + + -- Add the check for another DRPWE pulse + if ((DRPWE_indelay = '1') and (DRPEN_indelay = '0')) then + assert false + report "DRC Error : DRPWE is enabled before DRPRDY returns." + severity failure; + end if; + + if ((DRPRDY_out = '1') and (DRPEN_indelay = '0')) then + sfsm := FSM_IDLE; + end if; + + + if ((DRPRDY_out = '1') and (DRPEN_indelay = '1')) then + sfsm := FSM_WAIT; + end if; + + + when others => + assert false + report "DRC Error : Default state in DRP FSM." + severity failure; + + end case; + + end if; + + end process drp_monitor; + + + INIPROC : process + begin + -- case ALIGN_COMMA_DOUBLE is + if((ALIGN_COMMA_DOUBLE = "FALSE") or (ALIGN_COMMA_DOUBLE = "false")) then + ALIGN_COMMA_DOUBLE_BINARY <= '0'; + elsif((ALIGN_COMMA_DOUBLE = "TRUE") or (ALIGN_COMMA_DOUBLE= "true")) then + ALIGN_COMMA_DOUBLE_BINARY <= '1'; + else + assert FALSE report "Error : ALIGN_COMMA_DOUBLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case ALIGN_MCOMMA_DET is + if((ALIGN_MCOMMA_DET = "TRUE") or (ALIGN_MCOMMA_DET = "true")) then + ALIGN_MCOMMA_DET_BINARY <= '1'; + elsif((ALIGN_MCOMMA_DET = "FALSE") or (ALIGN_MCOMMA_DET= "false")) then + ALIGN_MCOMMA_DET_BINARY <= '0'; + else + assert FALSE report "Error : ALIGN_MCOMMA_DET = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case ALIGN_PCOMMA_DET is + if((ALIGN_PCOMMA_DET = "TRUE") or (ALIGN_PCOMMA_DET = "true")) then + ALIGN_PCOMMA_DET_BINARY <= '1'; + elsif((ALIGN_PCOMMA_DET = "FALSE") or (ALIGN_PCOMMA_DET= "false")) then + ALIGN_PCOMMA_DET_BINARY <= '0'; + else + assert FALSE report "Error : ALIGN_PCOMMA_DET = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CBCC_DATA_SOURCE_SEL is + if((CBCC_DATA_SOURCE_SEL = "DECODED") or (CBCC_DATA_SOURCE_SEL = "decoded")) then + CBCC_DATA_SOURCE_SEL_BINARY <= '1'; + elsif((CBCC_DATA_SOURCE_SEL = "ENCODED") or (CBCC_DATA_SOURCE_SEL= "encoded")) then + CBCC_DATA_SOURCE_SEL_BINARY <= '0'; + else + assert FALSE report "Error : CBCC_DATA_SOURCE_SEL = is not DECODED, ENCODED." severity error; + end if; + -- end case; + -- case CHAN_BOND_KEEP_ALIGN is + if((CHAN_BOND_KEEP_ALIGN = "FALSE") or (CHAN_BOND_KEEP_ALIGN = "false")) then + CHAN_BOND_KEEP_ALIGN_BINARY <= '0'; + elsif((CHAN_BOND_KEEP_ALIGN = "TRUE") or (CHAN_BOND_KEEP_ALIGN= "true")) then + CHAN_BOND_KEEP_ALIGN_BINARY <= '1'; + else + assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CHAN_BOND_SEQ_2_USE is + if((CHAN_BOND_SEQ_2_USE = "FALSE") or (CHAN_BOND_SEQ_2_USE = "false")) then + CHAN_BOND_SEQ_2_USE_BINARY <= '0'; + elsif((CHAN_BOND_SEQ_2_USE = "TRUE") or (CHAN_BOND_SEQ_2_USE= "true")) then + CHAN_BOND_SEQ_2_USE_BINARY <= '1'; + else + assert FALSE report "Error : CHAN_BOND_SEQ_2_USE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CLK_CORRECT_USE is + if((CLK_CORRECT_USE = "TRUE") or (CLK_CORRECT_USE = "true")) then + CLK_CORRECT_USE_BINARY <= '1'; + elsif((CLK_CORRECT_USE = "FALSE") or (CLK_CORRECT_USE= "false")) then + CLK_CORRECT_USE_BINARY <= '0'; + else + assert FALSE report "Error : CLK_CORRECT_USE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CLK_COR_KEEP_IDLE is + if((CLK_COR_KEEP_IDLE = "FALSE") or (CLK_COR_KEEP_IDLE = "false")) then + CLK_COR_KEEP_IDLE_BINARY <= '0'; + elsif((CLK_COR_KEEP_IDLE = "TRUE") or (CLK_COR_KEEP_IDLE= "true")) then + CLK_COR_KEEP_IDLE_BINARY <= '1'; + else + assert FALSE report "Error : CLK_COR_KEEP_IDLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CLK_COR_PRECEDENCE is + if((CLK_COR_PRECEDENCE = "TRUE") or (CLK_COR_PRECEDENCE = "true")) then + CLK_COR_PRECEDENCE_BINARY <= '1'; + elsif((CLK_COR_PRECEDENCE = "FALSE") or (CLK_COR_PRECEDENCE= "false")) then + CLK_COR_PRECEDENCE_BINARY <= '0'; + else + assert FALSE report "Error : CLK_COR_PRECEDENCE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CLK_COR_SEQ_2_USE is + if((CLK_COR_SEQ_2_USE = "FALSE") or (CLK_COR_SEQ_2_USE = "false")) then + CLK_COR_SEQ_2_USE_BINARY <= '0'; + elsif((CLK_COR_SEQ_2_USE = "TRUE") or (CLK_COR_SEQ_2_USE= "true")) then + CLK_COR_SEQ_2_USE_BINARY <= '1'; + else + assert FALSE report "Error : CLK_COR_SEQ_2_USE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case DEC_MCOMMA_DETECT is + if((DEC_MCOMMA_DETECT = "TRUE") or (DEC_MCOMMA_DETECT = "true")) then + DEC_MCOMMA_DETECT_BINARY <= '1'; + elsif((DEC_MCOMMA_DETECT = "FALSE") or (DEC_MCOMMA_DETECT= "false")) then + DEC_MCOMMA_DETECT_BINARY <= '0'; + else + assert FALSE report "Error : DEC_MCOMMA_DETECT = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case DEC_PCOMMA_DETECT is + if((DEC_PCOMMA_DETECT = "TRUE") or (DEC_PCOMMA_DETECT = "true")) then + DEC_PCOMMA_DETECT_BINARY <= '1'; + elsif((DEC_PCOMMA_DETECT = "FALSE") or (DEC_PCOMMA_DETECT= "false")) then + DEC_PCOMMA_DETECT_BINARY <= '0'; + else + assert FALSE report "Error : DEC_PCOMMA_DETECT = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case DEC_VALID_COMMA_ONLY is + if((DEC_VALID_COMMA_ONLY = "TRUE") or (DEC_VALID_COMMA_ONLY = "true")) then + DEC_VALID_COMMA_ONLY_BINARY <= '1'; + elsif((DEC_VALID_COMMA_ONLY = "FALSE") or (DEC_VALID_COMMA_ONLY= "false")) then + DEC_VALID_COMMA_ONLY_BINARY <= '0'; + else + assert FALSE report "Error : DEC_VALID_COMMA_ONLY = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case ES_ERRDET_EN is + if((ES_ERRDET_EN = "FALSE") or (ES_ERRDET_EN = "false")) then + ES_ERRDET_EN_BINARY <= '0'; + elsif((ES_ERRDET_EN = "TRUE") or (ES_ERRDET_EN= "true")) then + ES_ERRDET_EN_BINARY <= '1'; + else + assert FALSE report "Error : ES_ERRDET_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case ES_EYE_SCAN_EN is + if((ES_EYE_SCAN_EN = "FALSE") or (ES_EYE_SCAN_EN = "false")) then + ES_EYE_SCAN_EN_BINARY <= '0'; + elsif((ES_EYE_SCAN_EN = "TRUE") or (ES_EYE_SCAN_EN= "true")) then + ES_EYE_SCAN_EN_BINARY <= '1'; + else + assert FALSE report "Error : ES_EYE_SCAN_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case FTS_LANE_DESKEW_EN is + if((FTS_LANE_DESKEW_EN = "FALSE") or (FTS_LANE_DESKEW_EN = "false")) then + FTS_LANE_DESKEW_EN_BINARY <= '0'; + elsif((FTS_LANE_DESKEW_EN = "TRUE") or (FTS_LANE_DESKEW_EN= "true")) then + FTS_LANE_DESKEW_EN_BINARY <= '1'; + else + assert FALSE report "Error : FTS_LANE_DESKEW_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case PCS_PCIE_EN is + if((PCS_PCIE_EN = "FALSE") or (PCS_PCIE_EN = "false")) then + PCS_PCIE_EN_BINARY <= '0'; + elsif((PCS_PCIE_EN = "TRUE") or (PCS_PCIE_EN= "true")) then + PCS_PCIE_EN_BINARY <= '1'; + else + assert FALSE report "Error : PCS_PCIE_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_ADDR_MODE is + if((RXBUF_ADDR_MODE = "FULL") or (RXBUF_ADDR_MODE = "full")) then + RXBUF_ADDR_MODE_BINARY <= '0'; + elsif((RXBUF_ADDR_MODE = "FAST") or (RXBUF_ADDR_MODE= "fast")) then + RXBUF_ADDR_MODE_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_ADDR_MODE = is not FULL, FAST." severity error; + end if; + -- end case; + -- case RXBUF_EN is + if((RXBUF_EN = "TRUE") or (RXBUF_EN = "true")) then + RXBUF_EN_BINARY <= '1'; + elsif((RXBUF_EN = "FALSE") or (RXBUF_EN= "false")) then + RXBUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_CB_CHANGE is + if((RXBUF_RESET_ON_CB_CHANGE = "TRUE") or (RXBUF_RESET_ON_CB_CHANGE = "true")) then + RXBUF_RESET_ON_CB_CHANGE_BINARY <= '1'; + elsif((RXBUF_RESET_ON_CB_CHANGE = "FALSE") or (RXBUF_RESET_ON_CB_CHANGE= "false")) then + RXBUF_RESET_ON_CB_CHANGE_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_RESET_ON_CB_CHANGE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_COMMAALIGN is + if((RXBUF_RESET_ON_COMMAALIGN = "FALSE") or (RXBUF_RESET_ON_COMMAALIGN = "false")) then + RXBUF_RESET_ON_COMMAALIGN_BINARY <= '0'; + elsif((RXBUF_RESET_ON_COMMAALIGN = "TRUE") or (RXBUF_RESET_ON_COMMAALIGN= "true")) then + RXBUF_RESET_ON_COMMAALIGN_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_RESET_ON_COMMAALIGN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_EIDLE is + if((RXBUF_RESET_ON_EIDLE = "FALSE") or (RXBUF_RESET_ON_EIDLE = "false")) then + RXBUF_RESET_ON_EIDLE_BINARY <= '0'; + elsif((RXBUF_RESET_ON_EIDLE = "TRUE") or (RXBUF_RESET_ON_EIDLE= "true")) then + RXBUF_RESET_ON_EIDLE_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_RESET_ON_EIDLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_RATE_CHANGE is + if((RXBUF_RESET_ON_RATE_CHANGE = "TRUE") or (RXBUF_RESET_ON_RATE_CHANGE = "true")) then + RXBUF_RESET_ON_RATE_CHANGE_BINARY <= '1'; + elsif((RXBUF_RESET_ON_RATE_CHANGE = "FALSE") or (RXBUF_RESET_ON_RATE_CHANGE= "false")) then + RXBUF_RESET_ON_RATE_CHANGE_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_RESET_ON_RATE_CHANGE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_THRESH_OVRD is + if((RXBUF_THRESH_OVRD = "FALSE") or (RXBUF_THRESH_OVRD = "false")) then + RXBUF_THRESH_OVRD_BINARY <= '0'; + elsif((RXBUF_THRESH_OVRD = "TRUE") or (RXBUF_THRESH_OVRD= "true")) then + RXBUF_THRESH_OVRD_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_THRESH_OVRD = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXGEARBOX_EN is + if((RXGEARBOX_EN = "FALSE") or (RXGEARBOX_EN = "false")) then + RXGEARBOX_EN_BINARY <= '0'; + elsif((RXGEARBOX_EN = "TRUE") or (RXGEARBOX_EN= "true")) then + RXGEARBOX_EN_BINARY <= '1'; + else + assert FALSE report "Error : RXGEARBOX_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXOOB_CLK_CFG is + if((RXOOB_CLK_CFG = "PMA") or (RXOOB_CLK_CFG = "pma")) then + RXOOB_CLK_CFG_BINARY <= '0'; + elsif((RXOOB_CLK_CFG = "FABRIC") or (RXOOB_CLK_CFG= "fabric")) then + RXOOB_CLK_CFG_BINARY <= '1'; + else + assert FALSE report "Error : RXOOB_CLK_CFG = is not PMA, FABRIC." severity error; + end if; + -- end case; + -- case RXSLIDE_MODE is + if((RXSLIDE_MODE = "OFF") or (RXSLIDE_MODE = "off")) then + RXSLIDE_MODE_BINARY <= "00"; + elsif((RXSLIDE_MODE = "AUTO") or (RXSLIDE_MODE= "auto")) then + RXSLIDE_MODE_BINARY <= "01"; + elsif((RXSLIDE_MODE = "PCS") or (RXSLIDE_MODE= "pcs")) then + RXSLIDE_MODE_BINARY <= "10"; + elsif((RXSLIDE_MODE = "PMA") or (RXSLIDE_MODE= "pma")) then + RXSLIDE_MODE_BINARY <= "11"; + else + assert FALSE report "Error : RXSLIDE_MODE = is not OFF, AUTO, PCS, PMA." severity error; + end if; + -- end case; + -- case RX_DEFER_RESET_BUF_EN is + if((RX_DEFER_RESET_BUF_EN = "TRUE") or (RX_DEFER_RESET_BUF_EN = "true")) then + RX_DEFER_RESET_BUF_EN_BINARY <= '1'; + elsif((RX_DEFER_RESET_BUF_EN = "FALSE") or (RX_DEFER_RESET_BUF_EN= "false")) then + RX_DEFER_RESET_BUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : RX_DEFER_RESET_BUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RX_DISPERR_SEQ_MATCH is + if((RX_DISPERR_SEQ_MATCH = "TRUE") or (RX_DISPERR_SEQ_MATCH = "true")) then + RX_DISPERR_SEQ_MATCH_BINARY <= '1'; + elsif((RX_DISPERR_SEQ_MATCH = "FALSE") or (RX_DISPERR_SEQ_MATCH= "false")) then + RX_DISPERR_SEQ_MATCH_BINARY <= '0'; + else + assert FALSE report "Error : RX_DISPERR_SEQ_MATCH = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RX_XCLK_SEL is + if((RX_XCLK_SEL = "RXREC") or (RX_XCLK_SEL = "rxrec")) then + RX_XCLK_SEL_BINARY <= '0'; + elsif((RX_XCLK_SEL = "RXUSR") or (RX_XCLK_SEL= "rxusr")) then + RX_XCLK_SEL_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL = is not RXREC, RXUSR." severity error; + end if; + -- end case; + -- case SATA_CPLL_CFG is + if((SATA_CPLL_CFG = "VCO_3000MHZ") or (SATA_CPLL_CFG = "vco_3000mhz")) then + SATA_CPLL_CFG_BINARY <= "00"; + elsif((SATA_CPLL_CFG = "VCO_750MHZ") or (SATA_CPLL_CFG= "vco_750mhz")) then + SATA_CPLL_CFG_BINARY <= "10"; + elsif((SATA_CPLL_CFG = "VCO_1500MHZ") or (SATA_CPLL_CFG= "vco_1500mhz")) then + SATA_CPLL_CFG_BINARY <= "01"; + else + assert FALSE report "Error : SATA_CPLL_CFG = is not VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ." severity error; + end if; + -- end case; + -- case SHOW_REALIGN_COMMA is + if((SHOW_REALIGN_COMMA = "TRUE") or (SHOW_REALIGN_COMMA = "true")) then + SHOW_REALIGN_COMMA_BINARY <= '1'; + elsif((SHOW_REALIGN_COMMA = "FALSE") or (SHOW_REALIGN_COMMA= "false")) then + SHOW_REALIGN_COMMA_BINARY <= '0'; + else + assert FALSE report "Error : SHOW_REALIGN_COMMA = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case TXBUF_EN is + if((TXBUF_EN = "TRUE") or (TXBUF_EN = "true")) then + TXBUF_EN_BINARY <= '1'; + elsif((TXBUF_EN = "FALSE") or (TXBUF_EN= "false")) then + TXBUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : TXBUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case TXBUF_RESET_ON_RATE_CHANGE is + if((TXBUF_RESET_ON_RATE_CHANGE = "FALSE") or (TXBUF_RESET_ON_RATE_CHANGE = "false")) then + TXBUF_RESET_ON_RATE_CHANGE_BINARY <= '0'; + elsif((TXBUF_RESET_ON_RATE_CHANGE = "TRUE") or (TXBUF_RESET_ON_RATE_CHANGE= "true")) then + TXBUF_RESET_ON_RATE_CHANGE_BINARY <= '1'; + else + assert FALSE report "Error : TXBUF_RESET_ON_RATE_CHANGE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TXGEARBOX_EN is + if((TXGEARBOX_EN = "FALSE") or (TXGEARBOX_EN = "false")) then + TXGEARBOX_EN_BINARY <= '0'; + elsif((TXGEARBOX_EN = "TRUE") or (TXGEARBOX_EN= "true")) then + TXGEARBOX_EN_BINARY <= '1'; + else + assert FALSE report "Error : TXGEARBOX_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TXPI_PPMCLK_SEL is + if((TXPI_PPMCLK_SEL = "TXUSRCLK2") or (TXPI_PPMCLK_SEL = "txusrclk2")) then + TXPI_PPMCLK_SEL_BINARY <= '1'; + elsif((TXPI_PPMCLK_SEL = "TXUSRCLK") or (TXPI_PPMCLK_SEL= "txusrclk")) then + TXPI_PPMCLK_SEL_BINARY <= '0'; + else + assert FALSE report "Error : TXPI_PPMCLK_SEL = is not TXUSRCLK2, TXUSRCLK." severity error; + end if; + -- end case; + -- case TX_DRIVE_MODE is + if((TX_DRIVE_MODE = "DIRECT") or (TX_DRIVE_MODE = "direct")) then + TX_DRIVE_MODE_BINARY <= "00000"; + elsif((TX_DRIVE_MODE = "PIPE") or (TX_DRIVE_MODE= "pipe")) then + TX_DRIVE_MODE_BINARY <= "00001"; + elsif((TX_DRIVE_MODE = "PIPEGEN3") or (TX_DRIVE_MODE= "pipegen3")) then + TX_DRIVE_MODE_BINARY <= "00010"; + else + assert FALSE report "Error : TX_DRIVE_MODE = is not DIRECT, PIPE, PIPEGEN3." severity error; + end if; + -- end case; + -- case TX_LOOPBACK_DRIVE_HIZ is + if((TX_LOOPBACK_DRIVE_HIZ = "FALSE") or (TX_LOOPBACK_DRIVE_HIZ = "false")) then + TX_LOOPBACK_DRIVE_HIZ_BINARY <= '0'; + elsif((TX_LOOPBACK_DRIVE_HIZ = "TRUE") or (TX_LOOPBACK_DRIVE_HIZ= "true")) then + TX_LOOPBACK_DRIVE_HIZ_BINARY <= '1'; + else + assert FALSE report "Error : TX_LOOPBACK_DRIVE_HIZ = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TX_XCLK_SEL is + if((TX_XCLK_SEL = "TXUSR") or (TX_XCLK_SEL = "txusr")) then + TX_XCLK_SEL_BINARY <= '1'; + elsif((TX_XCLK_SEL = "TXOUT") or (TX_XCLK_SEL= "txout")) then + TX_XCLK_SEL_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL = is not TXUSR, TXOUT." severity error; + end if; + -- end case; + case CPLL_FBDIV_45 is + when 5 => CPLL_FBDIV_45_BINARY <= '1'; + when 4 => CPLL_FBDIV_45_BINARY <= '0'; + when others => assert FALSE report "Error : CPLL_FBDIV_45 is not in range 4 .. 5." severity error; + end case; + case RX_INT_DATAWIDTH is + when 0 => RX_INT_DATAWIDTH_BINARY <= '0'; + when 1 => RX_INT_DATAWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : RX_INT_DATAWIDTH is not in range 0 .. 1." severity error; + end case; + case TX_INT_DATAWIDTH is + when 0 => TX_INT_DATAWIDTH_BINARY <= '0'; + when 1 => TX_INT_DATAWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : TX_INT_DATAWIDTH is not in range 0 .. 1." severity error; + end case; + if ((ALIGN_COMMA_WORD >= 1) and (ALIGN_COMMA_WORD <= 4)) then + ALIGN_COMMA_WORD_BINARY <= CONV_STD_LOGIC_VECTOR(ALIGN_COMMA_WORD, 3); + else + assert FALSE report "Error : ALIGN_COMMA_WORD is not in range 1 .. 4." severity error; + end if; + if ((CHAN_BOND_MAX_SKEW >= 1) and (CHAN_BOND_MAX_SKEW <= 14)) then + CHAN_BOND_MAX_SKEW_BINARY <= CONV_STD_LOGIC_VECTOR(CHAN_BOND_MAX_SKEW, 4); + else + assert FALSE report "Error : CHAN_BOND_MAX_SKEW is not in range 1 .. 14." severity error; + end if; + if ((CHAN_BOND_SEQ_LEN >= 1) and (CHAN_BOND_SEQ_LEN <= 4)) then + CHAN_BOND_SEQ_LEN_BINARY <= CONV_STD_LOGIC_VECTOR(CHAN_BOND_SEQ_LEN, 2); + else + assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in range 1 .. 4." severity error; + end if; + if ((CLK_COR_MAX_LAT >= 3) and (CLK_COR_MAX_LAT <= 60)) then + CLK_COR_MAX_LAT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_MAX_LAT, 6); + else + assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 3 .. 60." severity error; + end if; + if ((CLK_COR_MIN_LAT >= 3) and (CLK_COR_MIN_LAT <= 60)) then + CLK_COR_MIN_LAT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_MIN_LAT, 6); + else + assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 3 .. 60." severity error; + end if; + if ((CLK_COR_REPEAT_WAIT >= 0) and (CLK_COR_REPEAT_WAIT <= 31)) then + CLK_COR_REPEAT_WAIT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_REPEAT_WAIT, 5); + else + assert FALSE report "Error : CLK_COR_REPEAT_WAIT is not in range 0 .. 31." severity error; + end if; + if ((CLK_COR_SEQ_LEN >= 1) and (CLK_COR_SEQ_LEN <= 4)) then + CLK_COR_SEQ_LEN_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_SEQ_LEN, 2); + else + assert FALSE report "Error : CLK_COR_SEQ_LEN is not in range 1 .. 4." severity error; + end if; + if ((CPLL_FBDIV >= 1) and (CPLL_FBDIV <= 20)) then + CPLL_FBDIV_BINARY <= CONV_STD_LOGIC_VECTOR(CPLL_FBDIV, 7); + else + assert FALSE report "Error : CPLL_FBDIV is not in range 1 .. 20." severity error; + end if; + if ((CPLL_REFCLK_DIV >= 1) and (CPLL_REFCLK_DIV <= 20)) then + CPLL_REFCLK_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(CPLL_REFCLK_DIV, 5); + else + assert FALSE report "Error : CPLL_REFCLK_DIV is not in range 1 .. 20." severity error; + end if; + if ((RXBUF_THRESH_OVFLW >= 0) and (RXBUF_THRESH_OVFLW <= 63)) then + RXBUF_THRESH_OVFLW_BINARY <= CONV_STD_LOGIC_VECTOR(RXBUF_THRESH_OVFLW, 6); + else + assert FALSE report "Error : RXBUF_THRESH_OVFLW is not in range 0 .. 63." severity error; + end if; + if ((RXBUF_THRESH_UNDFLW >= 0) and (RXBUF_THRESH_UNDFLW <= 63)) then + RXBUF_THRESH_UNDFLW_BINARY <= CONV_STD_LOGIC_VECTOR(RXBUF_THRESH_UNDFLW, 6); + else + assert FALSE report "Error : RXBUF_THRESH_UNDFLW is not in range 0 .. 63." severity error; + end if; + if ((RXOUT_DIV >= 1) and (RXOUT_DIV <= 16)) then + RXOUT_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(RXOUT_DIV, 3); + else + assert FALSE report "Error : RXOUT_DIV is not in range 1 .. 16." severity error; + end if; + if ((RXSLIDE_AUTO_WAIT >= 0) and (RXSLIDE_AUTO_WAIT <= 15)) then + RXSLIDE_AUTO_WAIT_BINARY <= CONV_STD_LOGIC_VECTOR(RXSLIDE_AUTO_WAIT, 4); + else + assert FALSE report "Error : RXSLIDE_AUTO_WAIT is not in range 0 .. 15." severity error; + end if; + if ((RX_CLK25_DIV >= 1) and (RX_CLK25_DIV <= 32)) then + RX_CLK25_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(RX_CLK25_DIV, 5); + else + assert FALSE report "Error : RX_CLK25_DIV is not in range 1 .. 32." severity error; + end if; + if ((RX_DATA_WIDTH >= 16) and (RX_DATA_WIDTH <= 80)) then + RX_DATA_WIDTH_BINARY <= CONV_STD_LOGIC_VECTOR(RX_DATA_WIDTH, 3); + else + assert FALSE report "Error : RX_DATA_WIDTH is not in range 16 .. 80." severity error; + end if; + if ((RX_SIG_VALID_DLY >= 1) and (RX_SIG_VALID_DLY <= 32)) then + RX_SIG_VALID_DLY_BINARY <= CONV_STD_LOGIC_VECTOR(RX_SIG_VALID_DLY, 5); + else + assert FALSE report "Error : RX_SIG_VALID_DLY is not in range 1 .. 32." severity error; + end if; + if ((SAS_MAX_COM >= 1) and (SAS_MAX_COM <= 127)) then + SAS_MAX_COM_BINARY <= CONV_STD_LOGIC_VECTOR(SAS_MAX_COM, 7); + else + assert FALSE report "Error : SAS_MAX_COM is not in range 1 .. 127." severity error; + end if; + if ((SAS_MIN_COM >= 1) and (SAS_MIN_COM <= 63)) then + SAS_MIN_COM_BINARY <= CONV_STD_LOGIC_VECTOR(SAS_MIN_COM, 6); + else + assert FALSE report "Error : SAS_MIN_COM is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_BURST >= 1) and (SATA_MAX_BURST <= 63)) then + SATA_MAX_BURST_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_BURST, 6); + else + assert FALSE report "Error : SATA_MAX_BURST is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_INIT >= 1) and (SATA_MAX_INIT <= 63)) then + SATA_MAX_INIT_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_INIT, 6); + else + assert FALSE report "Error : SATA_MAX_INIT is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_WAKE >= 1) and (SATA_MAX_WAKE <= 63)) then + SATA_MAX_WAKE_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_WAKE, 6); + else + assert FALSE report "Error : SATA_MAX_WAKE is not in range 1 .. 63." severity error; + end if; + if ((SATA_MIN_BURST >= 1) and (SATA_MIN_BURST <= 61)) then + SATA_MIN_BURST_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_BURST, 6); + else + assert FALSE report "Error : SATA_MIN_BURST is not in range 1 .. 61." severity error; + end if; + if ((SATA_MIN_INIT >= 1) and (SATA_MIN_INIT <= 63)) then + SATA_MIN_INIT_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_INIT, 6); + else + assert FALSE report "Error : SATA_MIN_INIT is not in range 1 .. 63." severity error; + end if; + if ((SATA_MIN_WAKE >= 1) and (SATA_MIN_WAKE <= 63)) then + SATA_MIN_WAKE_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_WAKE, 6); + else + assert FALSE report "Error : SATA_MIN_WAKE is not in range 1 .. 63." severity error; + end if; + if ((TXOUT_DIV >= 1) and (TXOUT_DIV <= 16)) then + TXOUT_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(TXOUT_DIV, 3); + else + assert FALSE report "Error : TXOUT_DIV is not in range 1 .. 16." severity error; + end if; + if ((TX_CLK25_DIV >= 1) and (TX_CLK25_DIV <= 32)) then + TX_CLK25_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(TX_CLK25_DIV, 5); + else + assert FALSE report "Error : TX_CLK25_DIV is not in range 1 .. 32." severity error; + end if; + if ((TX_DATA_WIDTH >= 16) and (TX_DATA_WIDTH <= 80)) then + TX_DATA_WIDTH_BINARY <= CONV_STD_LOGIC_VECTOR(TX_DATA_WIDTH, 3); + else + assert FALSE report "Error : TX_DATA_WIDTH is not in range 16 .. 80." severity error; + end if; + wait; + end process INIPROC; + CPLLFBCLKLOST <= CPLLFBCLKLOST_out; + CPLLLOCK <= CPLLLOCK_out; + CPLLREFCLKLOST <= CPLLREFCLKLOST_out; + DMONITOROUT <= DMONITOROUT_out; + DRPDO <= DRPDO_out; + DRPRDY <= DRPRDY_out; + EYESCANDATAERROR <= EYESCANDATAERROR_out; + GTHTXN <= GTHTXN_out; + GTHTXP <= GTHTXP_out; + GTREFCLKMONITOR <= GTREFCLKMONITOR_out; + PCSRSVDOUT <= PCSRSVDOUT_out; + PHYSTATUS <= PHYSTATUS_out; + RSOSINTDONE <= RSOSINTDONE_out; + RXBUFSTATUS <= RXBUFSTATUS_out; + RXBYTEISALIGNED <= RXBYTEISALIGNED_out; + RXBYTEREALIGN <= RXBYTEREALIGN_out; + RXCDRLOCK <= RXCDRLOCK_out; + RXCHANBONDSEQ <= RXCHANBONDSEQ_out; + RXCHANISALIGNED <= RXCHANISALIGNED_out; + RXCHANREALIGN <= RXCHANREALIGN_out; + RXCHARISCOMMA <= RXCHARISCOMMA_out; + RXCHARISK <= RXCHARISK_out; + RXCHBONDO <= RXCHBONDO_out; + RXCLKCORCNT <= RXCLKCORCNT_out; + RXCOMINITDET <= RXCOMINITDET_out; + RXCOMMADET <= RXCOMMADET_out; + RXCOMSASDET <= RXCOMSASDET_out; + RXCOMWAKEDET <= RXCOMWAKEDET_out; + RXDATA <= RXDATA_out; + RXDATAVALID <= RXDATAVALID_out; + RXDFESLIDETAPSTARTED <= RXDFESLIDETAPSTARTED_out; + RXDFESLIDETAPSTROBEDONE <= RXDFESLIDETAPSTROBEDONE_out; + RXDFESLIDETAPSTROBESTARTED <= RXDFESLIDETAPSTROBESTARTED_out; + RXDFESTADAPTDONE <= RXDFESTADAPTDONE_out; + RXDISPERR <= RXDISPERR_out; + RXDLYSRESETDONE <= RXDLYSRESETDONE_out; + RXELECIDLE <= RXELECIDLE_out; + RXHEADER <= RXHEADER_out; + RXHEADERVALID <= RXHEADERVALID_out; + RXMONITOROUT <= RXMONITOROUT_out; + RXNOTINTABLE <= RXNOTINTABLE_out; + RXOSINTSTARTED <= RXOSINTSTARTED_out; + RXOSINTSTROBEDONE <= RXOSINTSTROBEDONE_out; + RXOSINTSTROBESTARTED <= RXOSINTSTROBESTARTED_out; + RXOUTCLK <= RXOUTCLK_out; + RXOUTCLKFABRIC <= RXOUTCLKFABRIC_out; + RXOUTCLKPCS <= RXOUTCLKPCS_out; + RXPHALIGNDONE <= RXPHALIGNDONE_out; + RXPHMONITOR <= RXPHMONITOR_out; + RXPHSLIPMONITOR <= RXPHSLIPMONITOR_out; + RXPMARESETDONE <= RXPMARESETDONE_out; + RXPRBSERR <= RXPRBSERR_out; + RXQPISENN <= RXQPISENN_out; + RXQPISENP <= RXQPISENP_out; + RXRATEDONE <= RXRATEDONE_out; + RXRESETDONE <= RXRESETDONE_out; + RXSTARTOFSEQ <= RXSTARTOFSEQ_out; + RXSTATUS <= RXSTATUS_out; + RXSYNCDONE <= RXSYNCDONE_out; + RXSYNCOUT <= RXSYNCOUT_out; + RXVALID <= RXVALID_out; + TXBUFSTATUS <= TXBUFSTATUS_out; + TXCOMFINISH <= TXCOMFINISH_out; + TXDLYSRESETDONE <= TXDLYSRESETDONE_out; + TXGEARBOXREADY <= TXGEARBOXREADY_out; + TXOUTCLK <= TXOUTCLK_out; + TXOUTCLKFABRIC <= TXOUTCLKFABRIC_out; + TXOUTCLKPCS <= TXOUTCLKPCS_out; + TXPHALIGNDONE <= TXPHALIGNDONE_out; + TXPHINITDONE <= TXPHINITDONE_out; + TXPMARESETDONE <= TXPMARESETDONE_out; + TXQPISENN <= TXQPISENN_out; + TXQPISENP <= TXQPISENP_out; + TXRATEDONE <= TXRATEDONE_out; + TXRESETDONE <= TXRESETDONE_out; + TXSYNCDONE <= TXSYNCDONE_out; + TXSYNCOUT <= TXSYNCOUT_out; + end GTHE2_CHANNEL_FAST_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTXE2_CHANNEL.vhd b/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTXE2_CHANNEL.vhd new file mode 100644 index 0000000..b1b8077 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unifast/secureip/GTXE2_CHANNEL.vhd @@ -0,0 +1,3301 @@ +------------------------------------------------------- +-- Copyright (c) 2010 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Description : Xilinx Simulation Library Component +-- / / +-- /___/ /\ Filename : GTXE2_CHANNEL.vhd +-- \ \ / \ +-- \__ \/\__ \ +-- +-- Revision: 1.0 +-- 11/10/09 - CR - Initial version +-- 11/20/09 - CR - Attribute updates in YML +-- 04/27/10 - CR - YML update +-- 05/26/10 - CR561562 - SATA_CPLL_CFG attribute bug fixed +-- 06/17/10 - CR564909 - Complete VHDL support, YML & RTL updates +-- 08/05/10 - C569019 - gtxe2 yml and secureip update +-- 09/15/10 - CR575512 - gtxe2 yml and secureip update +-- 01/09/11 - CR582278,579504,588137, 591741 - GTXE2 YML/secureip update +-- 05/09/11 - CR608414- Attribute name YML update +-- 09/07/11 - CR624062 - YML update +-- 10/17/12 - 682802 - convert GSR H/L to 1/0 +-- 01/23/13 - Added DRP monitor (CR 695630). +-- 06/19/14 - PR785721 - IS_*INVERTED update from std_ulogic to bit +------------------------------------------------------- + +----- CELL GTXE2_CHANNEL ----- + +library IEEE; +use IEEE.STD_LOGIC_arith.all; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.vpkg.all; + +library secureip; +use secureip.all; + + entity GTXE2_CHANNEL is + generic ( + ALIGN_COMMA_DOUBLE : string := "FALSE"; + ALIGN_COMMA_ENABLE : bit_vector := "0001111111"; + ALIGN_COMMA_WORD : integer := 1; + ALIGN_MCOMMA_DET : string := "TRUE"; + ALIGN_MCOMMA_VALUE : bit_vector := "1010000011"; + ALIGN_PCOMMA_DET : string := "TRUE"; + ALIGN_PCOMMA_VALUE : bit_vector := "0101111100"; + CBCC_DATA_SOURCE_SEL : string := "DECODED"; + CHAN_BOND_KEEP_ALIGN : string := "FALSE"; + CHAN_BOND_MAX_SKEW : integer := 7; + CHAN_BOND_SEQ_1_1 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_2 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_ENABLE : bit_vector := "1111"; + CHAN_BOND_SEQ_2_1 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "0100000000"; + CHAN_BOND_SEQ_2_ENABLE : bit_vector := "1111"; + CHAN_BOND_SEQ_2_USE : string := "FALSE"; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : string := "TRUE"; + CLK_COR_KEEP_IDLE : string := "FALSE"; + CLK_COR_MAX_LAT : integer := 20; + CLK_COR_MIN_LAT : integer := 18; + CLK_COR_PRECEDENCE : string := "TRUE"; + CLK_COR_REPEAT_WAIT : integer := 0; + CLK_COR_SEQ_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE : bit_vector := "1111"; + CLK_COR_SEQ_2_1 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_2 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_3 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_4 : bit_vector := "0100000000"; + CLK_COR_SEQ_2_ENABLE : bit_vector := "1111"; + CLK_COR_SEQ_2_USE : string := "FALSE"; + CLK_COR_SEQ_LEN : integer := 1; + CPLL_CFG : bit_vector := X"B007D8"; + CPLL_FBDIV : integer := 4; + CPLL_FBDIV_45 : integer := 5; + CPLL_INIT_CFG : bit_vector := X"00001E"; + CPLL_LOCK_CFG : bit_vector := X"01E8"; + CPLL_REFCLK_DIV : integer := 1; + DEC_MCOMMA_DETECT : string := "TRUE"; + DEC_PCOMMA_DETECT : string := "TRUE"; + DEC_VALID_COMMA_ONLY : string := "TRUE"; + DMONITOR_CFG : bit_vector := X"000A00"; + ES_CONTROL : bit_vector := "000000"; + ES_ERRDET_EN : string := "FALSE"; + ES_EYE_SCAN_EN : string := "FALSE"; + ES_HORZ_OFFSET : bit_vector := X"000"; + ES_PMA_CFG : bit_vector := "0000000000"; + ES_PRESCALE : bit_vector := "00000"; + ES_QUALIFIER : bit_vector := X"00000000000000000000"; + ES_QUAL_MASK : bit_vector := X"00000000000000000000"; + ES_SDATA_MASK : bit_vector := X"00000000000000000000"; + ES_VERT_OFFSET : bit_vector := "000000000"; + FTS_DESKEW_SEQ_ENABLE : bit_vector := "1111"; + FTS_LANE_DESKEW_CFG : bit_vector := "1111"; + FTS_LANE_DESKEW_EN : string := "FALSE"; + GEARBOX_MODE : bit_vector := "000"; + IS_CPLLLOCKDETCLK_INVERTED : bit := '0'; + IS_DRPCLK_INVERTED : bit := '0'; + IS_GTGREFCLK_INVERTED : bit := '0'; + IS_RXUSRCLK2_INVERTED : bit := '0'; + IS_RXUSRCLK_INVERTED : bit := '0'; + IS_TXPHDLYTSTCLK_INVERTED : bit := '0'; + IS_TXUSRCLK2_INVERTED : bit := '0'; + IS_TXUSRCLK_INVERTED : bit := '0'; + OUTREFCLK_SEL_INV : bit_vector := "11"; + PCS_PCIE_EN : string := "FALSE"; + PCS_RSVD_ATTR : bit_vector := X"000000000000"; + PD_TRANS_TIME_FROM_P2 : bit_vector := X"03C"; + PD_TRANS_TIME_NONE_P2 : bit_vector := X"19"; + PD_TRANS_TIME_TO_P2 : bit_vector := X"64"; + PMA_RSV : bit_vector := X"00000000"; + PMA_RSV2 : bit_vector := X"2050"; + PMA_RSV3 : bit_vector := "00"; + PMA_RSV4 : bit_vector := X"00000000"; + RXBUFRESET_TIME : bit_vector := "00001"; + RXBUF_ADDR_MODE : string := "FULL"; + RXBUF_EIDLE_HI_CNT : bit_vector := "1000"; + RXBUF_EIDLE_LO_CNT : bit_vector := "0000"; + RXBUF_EN : string := "TRUE"; + RXBUF_RESET_ON_CB_CHANGE : string := "TRUE"; + RXBUF_RESET_ON_COMMAALIGN : string := "FALSE"; + RXBUF_RESET_ON_EIDLE : string := "FALSE"; + RXBUF_RESET_ON_RATE_CHANGE : string := "TRUE"; + RXBUF_THRESH_OVFLW : integer := 61; + RXBUF_THRESH_OVRD : string := "FALSE"; + RXBUF_THRESH_UNDFLW : integer := 4; + RXCDRFREQRESET_TIME : bit_vector := "00001"; + RXCDRPHRESET_TIME : bit_vector := "00001"; + RXCDR_CFG : bit_vector := X"0B000023FF20400020"; + RXCDR_FR_RESET_ON_EIDLE : bit := '0'; + RXCDR_HOLD_DURING_EIDLE : bit := '0'; + RXCDR_LOCK_CFG : bit_vector := "010101"; + RXCDR_PH_RESET_ON_EIDLE : bit := '0'; + RXDFELPMRESET_TIME : bit_vector := "0001111"; + RXDLY_CFG : bit_vector := X"001F"; + RXDLY_LCFG : bit_vector := X"030"; + RXDLY_TAP_CFG : bit_vector := X"0000"; + RXGEARBOX_EN : string := "FALSE"; + RXISCANRESET_TIME : bit_vector := "00001"; + RXLPM_HF_CFG : bit_vector := "00000011110000"; + RXLPM_LF_CFG : bit_vector := "00000011110000"; + RXOOB_CFG : bit_vector := "0000110"; + RXOUT_DIV : integer := 2; + RXPCSRESET_TIME : bit_vector := "00001"; + RXPHDLY_CFG : bit_vector := X"084020"; + RXPH_CFG : bit_vector := X"000000"; + RXPH_MONITOR_SEL : bit_vector := "00000"; + RXPMARESET_TIME : bit_vector := "00011"; + RXPRBS_ERR_LOOPBACK : bit := '0'; + RXSLIDE_AUTO_WAIT : integer := 7; + RXSLIDE_MODE : string := "OFF"; + RX_BIAS_CFG : bit_vector := "000000000000"; + RX_BUFFER_CFG : bit_vector := "000000"; + RX_CLK25_DIV : integer := 7; + RX_CLKMUX_PD : bit := '1'; + RX_CM_SEL : bit_vector := "11"; + RX_CM_TRIM : bit_vector := "100"; + RX_DATA_WIDTH : integer := 20; + RX_DDI_SEL : bit_vector := "000000"; + RX_DEBUG_CFG : bit_vector := "000000000000"; + RX_DEFER_RESET_BUF_EN : string := "TRUE"; + RX_DFE_GAIN_CFG : bit_vector := X"180E0F"; + RX_DFE_H2_CFG : bit_vector := "000111100000"; + RX_DFE_H3_CFG : bit_vector := "000111100000"; + RX_DFE_H4_CFG : bit_vector := "00011110000"; + RX_DFE_H5_CFG : bit_vector := "00011110000"; + RX_DFE_KL_CFG : bit_vector := "0001111110000"; + RX_DFE_KL_CFG2 : bit_vector := X"3008E56A"; + RX_DFE_LPM_CFG : bit_vector := X"0904"; + RX_DFE_LPM_HOLD_DURING_EIDLE : bit := '0'; + RX_DFE_UT_CFG : bit_vector := "00111111000000000"; + RX_DFE_VP_CFG : bit_vector := "00011111100000000"; + RX_DFE_XYD_CFG : bit_vector := "0000000010000"; + RX_DISPERR_SEQ_MATCH : string := "TRUE"; + RX_INT_DATAWIDTH : integer := 0; + RX_OS_CFG : bit_vector := "0001111110000"; + RX_SIG_VALID_DLY : integer := 10; + RX_XCLK_SEL : string := "RXREC"; + SAS_MAX_COM : integer := 64; + SAS_MIN_COM : integer := 36; + SATA_BURST_SEQ_LEN : bit_vector := "1111"; + SATA_BURST_VAL : bit_vector := "100"; + SATA_CPLL_CFG : string := "VCO_3000MHZ"; + SATA_EIDLE_VAL : bit_vector := "100"; + SATA_MAX_BURST : integer := 8; + SATA_MAX_INIT : integer := 21; + SATA_MAX_WAKE : integer := 7; + SATA_MIN_BURST : integer := 4; + SATA_MIN_INIT : integer := 12; + SATA_MIN_WAKE : integer := 4; + SHOW_REALIGN_COMMA : string := "TRUE"; + SIM_CPLLREFCLK_SEL : bit_vector := "001"; + SIM_RECEIVER_DETECT_PASS : string := "TRUE"; + SIM_RESET_SPEEDUP : string := "TRUE"; + SIM_TX_EIDLE_DRIVE_LEVEL : string := "X"; + SIM_VERSION : string := "4.0"; + TERM_RCAL_CFG : bit_vector := "10000"; + TERM_RCAL_OVRD : bit := '0'; + TRANS_TIME_RATE : bit_vector := X"0E"; + TST_RSV : bit_vector := X"00000000"; + TXBUF_EN : string := "TRUE"; + TXBUF_RESET_ON_RATE_CHANGE : string := "FALSE"; + TXDLY_CFG : bit_vector := X"001F"; + TXDLY_LCFG : bit_vector := X"030"; + TXDLY_TAP_CFG : bit_vector := X"0000"; + TXGEARBOX_EN : string := "FALSE"; + TXOUT_DIV : integer := 2; + TXPCSRESET_TIME : bit_vector := "00001"; + TXPHDLY_CFG : bit_vector := X"084020"; + TXPH_CFG : bit_vector := X"0780"; + TXPH_MONITOR_SEL : bit_vector := "00000"; + TXPMARESET_TIME : bit_vector := "00001"; + TX_CLK25_DIV : integer := 7; + TX_CLKMUX_PD : bit := '1'; + TX_DATA_WIDTH : integer := 20; + TX_DEEMPH0 : bit_vector := "00000"; + TX_DEEMPH1 : bit_vector := "00000"; + TX_DRIVE_MODE : string := "DIRECT"; + TX_EIDLE_ASSERT_DELAY : bit_vector := "110"; + TX_EIDLE_DEASSERT_DELAY : bit_vector := "100"; + TX_INT_DATAWIDTH : integer := 0; + TX_LOOPBACK_DRIVE_HIZ : string := "FALSE"; + TX_MAINCURSOR_SEL : bit := '0'; + TX_MARGIN_FULL_0 : bit_vector := "1001110"; + TX_MARGIN_FULL_1 : bit_vector := "1001001"; + TX_MARGIN_FULL_2 : bit_vector := "1000101"; + TX_MARGIN_FULL_3 : bit_vector := "1000010"; + TX_MARGIN_FULL_4 : bit_vector := "1000000"; + TX_MARGIN_LOW_0 : bit_vector := "1000110"; + TX_MARGIN_LOW_1 : bit_vector := "1000100"; + TX_MARGIN_LOW_2 : bit_vector := "1000010"; + TX_MARGIN_LOW_3 : bit_vector := "1000000"; + TX_MARGIN_LOW_4 : bit_vector := "1000000"; + TX_PREDRIVER_MODE : bit := '0'; + TX_QPI_STATUS_EN : bit := '0'; + TX_RXDETECT_CFG : bit_vector := X"1832"; + TX_RXDETECT_REF : bit_vector := "100"; + TX_XCLK_SEL : string := "TXUSR"; + UCODEER_CLR : bit := '0' + ); + + port ( + CPLLFBCLKLOST : out std_ulogic; + CPLLLOCK : out std_ulogic; + CPLLREFCLKLOST : out std_ulogic; + DMONITOROUT : out std_logic_vector(7 downto 0); + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_ulogic; + EYESCANDATAERROR : out std_ulogic; + GTREFCLKMONITOR : out std_ulogic; + GTXTXN : out std_ulogic; + GTXTXP : out std_ulogic; + PCSRSVDOUT : out std_logic_vector(15 downto 0); + PHYSTATUS : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED : out std_ulogic; + RXBYTEREALIGN : out std_ulogic; + RXCDRLOCK : out std_ulogic; + RXCHANBONDSEQ : out std_ulogic; + RXCHANISALIGNED : out std_ulogic; + RXCHANREALIGN : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCHBONDO : out std_logic_vector(4 downto 0); + RXCLKCORCNT : out std_logic_vector(1 downto 0); + RXCOMINITDET : out std_ulogic; + RXCOMMADET : out std_ulogic; + RXCOMSASDET : out std_ulogic; + RXCOMWAKEDET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDATAVALID : out std_ulogic; + RXDISPERR : out std_logic_vector(7 downto 0); + RXDLYSRESETDONE : out std_ulogic; + RXELECIDLE : out std_ulogic; + RXHEADER : out std_logic_vector(2 downto 0); + RXHEADERVALID : out std_ulogic; + RXMONITOROUT : out std_logic_vector(6 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXOUTCLK : out std_ulogic; + RXOUTCLKFABRIC : out std_ulogic; + RXOUTCLKPCS : out std_ulogic; + RXPHALIGNDONE : out std_ulogic; + RXPHMONITOR : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR : out std_logic_vector(4 downto 0); + RXPRBSERR : out std_ulogic; + RXQPISENN : out std_ulogic; + RXQPISENP : out std_ulogic; + RXRATEDONE : out std_ulogic; + RXRESETDONE : out std_ulogic; + RXSTARTOFSEQ : out std_ulogic; + RXSTATUS : out std_logic_vector(2 downto 0); + RXVALID : out std_ulogic; + TSTOUT : out std_logic_vector(9 downto 0); + TXBUFSTATUS : out std_logic_vector(1 downto 0); + TXCOMFINISH : out std_ulogic; + TXDLYSRESETDONE : out std_ulogic; + TXGEARBOXREADY : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXOUTCLKFABRIC : out std_ulogic; + TXOUTCLKPCS : out std_ulogic; + TXPHALIGNDONE : out std_ulogic; + TXPHINITDONE : out std_ulogic; + TXQPISENN : out std_ulogic; + TXQPISENP : out std_ulogic; + TXRATEDONE : out std_ulogic; + TXRESETDONE : out std_ulogic; + CFGRESET : in std_ulogic; + CLKRSVD : in std_logic_vector(3 downto 0); + CPLLLOCKDETCLK : in std_ulogic; + CPLLLOCKEN : in std_ulogic; + CPLLPD : in std_ulogic; + CPLLREFCLKSEL : in std_logic_vector(2 downto 0); + CPLLRESET : in std_ulogic; + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_ulogic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_ulogic; + DRPWE : in std_ulogic; + EYESCANMODE : in std_ulogic; + EYESCANRESET : in std_ulogic; + EYESCANTRIGGER : in std_ulogic; + GTGREFCLK : in std_ulogic; + GTNORTHREFCLK0 : in std_ulogic; + GTNORTHREFCLK1 : in std_ulogic; + GTREFCLK0 : in std_ulogic; + GTREFCLK1 : in std_ulogic; + GTRESETSEL : in std_ulogic; + GTRSVD : in std_logic_vector(15 downto 0); + GTRXRESET : in std_ulogic; + GTSOUTHREFCLK0 : in std_ulogic; + GTSOUTHREFCLK1 : in std_ulogic; + GTTXRESET : in std_ulogic; + GTXRXN : in std_ulogic; + GTXRXP : in std_ulogic; + LOOPBACK : in std_logic_vector(2 downto 0); + PCSRSVDIN : in std_logic_vector(15 downto 0); + PCSRSVDIN2 : in std_logic_vector(4 downto 0); + PMARSVDIN : in std_logic_vector(4 downto 0); + PMARSVDIN2 : in std_logic_vector(4 downto 0); + QPLLCLK : in std_ulogic; + QPLLREFCLK : in std_ulogic; + RESETOVRD : in std_ulogic; + RX8B10BEN : in std_ulogic; + RXBUFRESET : in std_ulogic; + RXCDRFREQRESET : in std_ulogic; + RXCDRHOLD : in std_ulogic; + RXCDROVRDEN : in std_ulogic; + RXCDRRESET : in std_ulogic; + RXCDRRESETRSV : in std_ulogic; + RXCHBONDEN : in std_ulogic; + RXCHBONDI : in std_logic_vector(4 downto 0); + RXCHBONDLEVEL : in std_logic_vector(2 downto 0); + RXCHBONDMASTER : in std_ulogic; + RXCHBONDSLAVE : in std_ulogic; + RXCOMMADETEN : in std_ulogic; + RXDDIEN : in std_ulogic; + RXDFEAGCHOLD : in std_ulogic; + RXDFEAGCOVRDEN : in std_ulogic; + RXDFECM1EN : in std_ulogic; + RXDFELFHOLD : in std_ulogic; + RXDFELFOVRDEN : in std_ulogic; + RXDFELPMRESET : in std_ulogic; + RXDFETAP2HOLD : in std_ulogic; + RXDFETAP2OVRDEN : in std_ulogic; + RXDFETAP3HOLD : in std_ulogic; + RXDFETAP3OVRDEN : in std_ulogic; + RXDFETAP4HOLD : in std_ulogic; + RXDFETAP4OVRDEN : in std_ulogic; + RXDFETAP5HOLD : in std_ulogic; + RXDFETAP5OVRDEN : in std_ulogic; + RXDFEUTHOLD : in std_ulogic; + RXDFEUTOVRDEN : in std_ulogic; + RXDFEVPHOLD : in std_ulogic; + RXDFEVPOVRDEN : in std_ulogic; + RXDFEVSEN : in std_ulogic; + RXDFEXYDEN : in std_ulogic; + RXDFEXYDHOLD : in std_ulogic; + RXDFEXYDOVRDEN : in std_ulogic; + RXDLYBYPASS : in std_ulogic; + RXDLYEN : in std_ulogic; + RXDLYOVRDEN : in std_ulogic; + RXDLYSRESET : in std_ulogic; + RXELECIDLEMODE : in std_logic_vector(1 downto 0); + RXGEARBOXSLIP : in std_ulogic; + RXLPMEN : in std_ulogic; + RXLPMHFHOLD : in std_ulogic; + RXLPMHFOVRDEN : in std_ulogic; + RXLPMLFHOLD : in std_ulogic; + RXLPMLFKLOVRDEN : in std_ulogic; + RXMCOMMAALIGNEN : in std_ulogic; + RXMONITORSEL : in std_logic_vector(1 downto 0); + RXOOBRESET : in std_ulogic; + RXOSHOLD : in std_ulogic; + RXOSOVRDEN : in std_ulogic; + RXOUTCLKSEL : in std_logic_vector(2 downto 0); + RXPCOMMAALIGNEN : in std_ulogic; + RXPCSRESET : in std_ulogic; + RXPD : in std_logic_vector(1 downto 0); + RXPHALIGN : in std_ulogic; + RXPHALIGNEN : in std_ulogic; + RXPHDLYPD : in std_ulogic; + RXPHDLYRESET : in std_ulogic; + RXPHOVRDEN : in std_ulogic; + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXPRBSCNTRESET : in std_ulogic; + RXPRBSSEL : in std_logic_vector(2 downto 0); + RXQPIEN : in std_ulogic; + RXRATE : in std_logic_vector(2 downto 0); + RXSLIDE : in std_ulogic; + RXSYSCLKSEL : in std_logic_vector(1 downto 0); + RXUSERRDY : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + SETERRSTATUS : in std_ulogic; + TSTIN : in std_logic_vector(19 downto 0); + TX8B10BBYPASS : in std_logic_vector(7 downto 0); + TX8B10BEN : in std_ulogic; + TXBUFDIFFCTRL : in std_logic_vector(2 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCOMINIT : in std_ulogic; + TXCOMSAS : in std_ulogic; + TXCOMWAKE : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDEEMPH : in std_ulogic; + TXDETECTRX : in std_ulogic; + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXDIFFPD : in std_ulogic; + TXDLYBYPASS : in std_ulogic; + TXDLYEN : in std_ulogic; + TXDLYHOLD : in std_ulogic; + TXDLYOVRDEN : in std_ulogic; + TXDLYSRESET : in std_ulogic; + TXDLYUPDOWN : in std_ulogic; + TXELECIDLE : in std_ulogic; + TXHEADER : in std_logic_vector(2 downto 0); + TXINHIBIT : in std_ulogic; + TXMAINCURSOR : in std_logic_vector(6 downto 0); + TXMARGIN : in std_logic_vector(2 downto 0); + TXOUTCLKSEL : in std_logic_vector(2 downto 0); + TXPCSRESET : in std_ulogic; + TXPD : in std_logic_vector(1 downto 0); + TXPDELECIDLEMODE : in std_ulogic; + TXPHALIGN : in std_ulogic; + TXPHALIGNEN : in std_ulogic; + TXPHDLYPD : in std_ulogic; + TXPHDLYRESET : in std_ulogic; + TXPHDLYTSTCLK : in std_ulogic; + TXPHINIT : in std_ulogic; + TXPHOVRDEN : in std_ulogic; + TXPISOPD : in std_ulogic; + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPOSTCURSORINV : in std_ulogic; + TXPRBSFORCEERR : in std_ulogic; + TXPRBSSEL : in std_logic_vector(2 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0); + TXPRECURSORINV : in std_ulogic; + TXQPIBIASEN : in std_ulogic; + TXQPISTRONGPDOWN : in std_ulogic; + TXQPIWEAKPUP : in std_ulogic; + TXRATE : in std_logic_vector(2 downto 0); + TXSEQUENCE : in std_logic_vector(6 downto 0); + TXSTARTSEQ : in std_ulogic; + TXSWING : in std_ulogic; + TXSYSCLKSEL : in std_logic_vector(1 downto 0); + TXUSERRDY : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); + end GTXE2_CHANNEL; + + architecture GTXE2_CHANNEL_FAST_V of GTXE2_CHANNEL is + component GTXE2_CHANNEL_FAST_WRAP + generic ( + ALIGN_COMMA_DOUBLE : string; + ALIGN_COMMA_ENABLE : string; + ALIGN_COMMA_WORD : integer; + ALIGN_MCOMMA_DET : string; + ALIGN_MCOMMA_VALUE : string; + ALIGN_PCOMMA_DET : string; + ALIGN_PCOMMA_VALUE : string; + CBCC_DATA_SOURCE_SEL : string; + CHAN_BOND_KEEP_ALIGN : string; + CHAN_BOND_MAX_SKEW : integer; + CHAN_BOND_SEQ_1_1 : string; + CHAN_BOND_SEQ_1_2 : string; + CHAN_BOND_SEQ_1_3 : string; + CHAN_BOND_SEQ_1_4 : string; + CHAN_BOND_SEQ_1_ENABLE : string; + CHAN_BOND_SEQ_2_1 : string; + CHAN_BOND_SEQ_2_2 : string; + CHAN_BOND_SEQ_2_3 : string; + CHAN_BOND_SEQ_2_4 : string; + CHAN_BOND_SEQ_2_ENABLE : string; + CHAN_BOND_SEQ_2_USE : string; + CHAN_BOND_SEQ_LEN : integer; + CLK_CORRECT_USE : string; + CLK_COR_KEEP_IDLE : string; + CLK_COR_MAX_LAT : integer; + CLK_COR_MIN_LAT : integer; + CLK_COR_PRECEDENCE : string; + CLK_COR_REPEAT_WAIT : integer; + CLK_COR_SEQ_1_1 : string; + CLK_COR_SEQ_1_2 : string; + CLK_COR_SEQ_1_3 : string; + CLK_COR_SEQ_1_4 : string; + CLK_COR_SEQ_1_ENABLE : string; + CLK_COR_SEQ_2_1 : string; + CLK_COR_SEQ_2_2 : string; + CLK_COR_SEQ_2_3 : string; + CLK_COR_SEQ_2_4 : string; + CLK_COR_SEQ_2_ENABLE : string; + CLK_COR_SEQ_2_USE : string; + CLK_COR_SEQ_LEN : integer; + CPLL_CFG : string; + CPLL_FBDIV : integer; + CPLL_FBDIV_45 : integer; + CPLL_INIT_CFG : string; + CPLL_LOCK_CFG : string; + CPLL_REFCLK_DIV : integer; + DEC_MCOMMA_DETECT : string; + DEC_PCOMMA_DETECT : string; + DEC_VALID_COMMA_ONLY : string; + DMONITOR_CFG : string; + ES_CONTROL : string; + ES_ERRDET_EN : string; + ES_EYE_SCAN_EN : string; + ES_HORZ_OFFSET : string; + ES_PMA_CFG : string; + ES_PRESCALE : string; + ES_QUALIFIER : string; + ES_QUAL_MASK : string; + ES_SDATA_MASK : string; + ES_VERT_OFFSET : string; + FTS_DESKEW_SEQ_ENABLE : string; + FTS_LANE_DESKEW_CFG : string; + FTS_LANE_DESKEW_EN : string; + GEARBOX_MODE : string; + OUTREFCLK_SEL_INV : string; + PCS_PCIE_EN : string; + PCS_RSVD_ATTR : string; + PD_TRANS_TIME_FROM_P2 : string; + PD_TRANS_TIME_NONE_P2 : string; + PD_TRANS_TIME_TO_P2 : string; + PMA_RSV : string; + PMA_RSV2 : string; + PMA_RSV3 : string; + PMA_RSV4 : string; + RXBUFRESET_TIME : string; + RXBUF_ADDR_MODE : string; + RXBUF_EIDLE_HI_CNT : string; + RXBUF_EIDLE_LO_CNT : string; + RXBUF_EN : string; + RXBUF_RESET_ON_CB_CHANGE : string; + RXBUF_RESET_ON_COMMAALIGN : string; + RXBUF_RESET_ON_EIDLE : string; + RXBUF_RESET_ON_RATE_CHANGE : string; + RXBUF_THRESH_OVFLW : integer; + RXBUF_THRESH_OVRD : string; + RXBUF_THRESH_UNDFLW : integer; + RXCDRFREQRESET_TIME : string; + RXCDRPHRESET_TIME : string; + RXCDR_CFG : string; + RXCDR_FR_RESET_ON_EIDLE : string; + RXCDR_HOLD_DURING_EIDLE : string; + RXCDR_LOCK_CFG : string; + RXCDR_PH_RESET_ON_EIDLE : string; + RXDFELPMRESET_TIME : string; + RXDLY_CFG : string; + RXDLY_LCFG : string; + RXDLY_TAP_CFG : string; + RXGEARBOX_EN : string; + RXISCANRESET_TIME : string; + RXLPM_HF_CFG : string; + RXLPM_LF_CFG : string; + RXOOB_CFG : string; + RXOUT_DIV : integer; + RXPCSRESET_TIME : string; + RXPHDLY_CFG : string; + RXPH_CFG : string; + RXPH_MONITOR_SEL : string; + RXPMARESET_TIME : string; + RXPRBS_ERR_LOOPBACK : string; + RXSLIDE_AUTO_WAIT : integer; + RXSLIDE_MODE : string; + RX_BIAS_CFG : string; + RX_BUFFER_CFG : string; + RX_CLK25_DIV : integer; + RX_CLKMUX_PD : string; + RX_CM_SEL : string; + RX_CM_TRIM : string; + RX_DATA_WIDTH : integer; + RX_DDI_SEL : string; + RX_DEBUG_CFG : string; + RX_DEFER_RESET_BUF_EN : string; + RX_DFE_GAIN_CFG : string; + RX_DFE_H2_CFG : string; + RX_DFE_H3_CFG : string; + RX_DFE_H4_CFG : string; + RX_DFE_H5_CFG : string; + RX_DFE_KL_CFG : string; + RX_DFE_KL_CFG2 : string; + RX_DFE_LPM_CFG : string; + RX_DFE_LPM_HOLD_DURING_EIDLE : string; + RX_DFE_UT_CFG : string; + RX_DFE_VP_CFG : string; + RX_DFE_XYD_CFG : string; + RX_DISPERR_SEQ_MATCH : string; + RX_INT_DATAWIDTH : integer; + RX_OS_CFG : string; + RX_SIG_VALID_DLY : integer; + RX_XCLK_SEL : string; + SAS_MAX_COM : integer; + SAS_MIN_COM : integer; + SATA_BURST_SEQ_LEN : string; + SATA_BURST_VAL : string; + SATA_CPLL_CFG : string; + SATA_EIDLE_VAL : string; + SATA_MAX_BURST : integer; + SATA_MAX_INIT : integer; + SATA_MAX_WAKE : integer; + SATA_MIN_BURST : integer; + SATA_MIN_INIT : integer; + SATA_MIN_WAKE : integer; + SHOW_REALIGN_COMMA : string; + SIM_CPLLREFCLK_SEL : string; + SIM_RECEIVER_DETECT_PASS : string; + SIM_RESET_SPEEDUP : string; + SIM_TX_EIDLE_DRIVE_LEVEL : string; + SIM_VERSION : string; + TERM_RCAL_CFG : string; + TERM_RCAL_OVRD : string; + TRANS_TIME_RATE : string; + TST_RSV : string; + TXBUF_EN : string; + TXBUF_RESET_ON_RATE_CHANGE : string; + TXDLY_CFG : string; + TXDLY_LCFG : string; + TXDLY_TAP_CFG : string; + TXGEARBOX_EN : string; + TXOUT_DIV : integer; + TXPCSRESET_TIME : string; + TXPHDLY_CFG : string; + TXPH_CFG : string; + TXPH_MONITOR_SEL : string; + TXPMARESET_TIME : string; + TX_CLK25_DIV : integer; + TX_CLKMUX_PD : string; + TX_DATA_WIDTH : integer; + TX_DEEMPH0 : string; + TX_DEEMPH1 : string; + TX_DRIVE_MODE : string; + TX_EIDLE_ASSERT_DELAY : string; + TX_EIDLE_DEASSERT_DELAY : string; + TX_INT_DATAWIDTH : integer; + TX_LOOPBACK_DRIVE_HIZ : string; + TX_MAINCURSOR_SEL : string; + TX_MARGIN_FULL_0 : string; + TX_MARGIN_FULL_1 : string; + TX_MARGIN_FULL_2 : string; + TX_MARGIN_FULL_3 : string; + TX_MARGIN_FULL_4 : string; + TX_MARGIN_LOW_0 : string; + TX_MARGIN_LOW_1 : string; + TX_MARGIN_LOW_2 : string; + TX_MARGIN_LOW_3 : string; + TX_MARGIN_LOW_4 : string; + TX_PREDRIVER_MODE : string; + TX_QPI_STATUS_EN : string; + TX_RXDETECT_CFG : string; + TX_RXDETECT_REF : string; + TX_XCLK_SEL : string; + UCODEER_CLR : string + ); + + port ( + CPLLFBCLKLOST : out std_ulogic; + CPLLLOCK : out std_ulogic; + CPLLREFCLKLOST : out std_ulogic; + DMONITOROUT : out std_logic_vector(7 downto 0); + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_ulogic; + EYESCANDATAERROR : out std_ulogic; + GTREFCLKMONITOR : out std_ulogic; + GTXTXN : out std_ulogic; + GTXTXP : out std_ulogic; + PCSRSVDOUT : out std_logic_vector(15 downto 0); + PHYSTATUS : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED : out std_ulogic; + RXBYTEREALIGN : out std_ulogic; + RXCDRLOCK : out std_ulogic; + RXCHANBONDSEQ : out std_ulogic; + RXCHANISALIGNED : out std_ulogic; + RXCHANREALIGN : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCHBONDO : out std_logic_vector(4 downto 0); + RXCLKCORCNT : out std_logic_vector(1 downto 0); + RXCOMINITDET : out std_ulogic; + RXCOMMADET : out std_ulogic; + RXCOMSASDET : out std_ulogic; + RXCOMWAKEDET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDATAVALID : out std_ulogic; + RXDISPERR : out std_logic_vector(7 downto 0); + RXDLYSRESETDONE : out std_ulogic; + RXELECIDLE : out std_ulogic; + RXHEADER : out std_logic_vector(2 downto 0); + RXHEADERVALID : out std_ulogic; + RXMONITOROUT : out std_logic_vector(6 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXOUTCLK : out std_ulogic; + RXOUTCLKFABRIC : out std_ulogic; + RXOUTCLKPCS : out std_ulogic; + RXPHALIGNDONE : out std_ulogic; + RXPHMONITOR : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR : out std_logic_vector(4 downto 0); + RXPRBSERR : out std_ulogic; + RXQPISENN : out std_ulogic; + RXQPISENP : out std_ulogic; + RXRATEDONE : out std_ulogic; + RXRESETDONE : out std_ulogic; + RXSTARTOFSEQ : out std_ulogic; + RXSTATUS : out std_logic_vector(2 downto 0); + RXVALID : out std_ulogic; + TSTOUT : out std_logic_vector(9 downto 0); + TXBUFSTATUS : out std_logic_vector(1 downto 0); + TXCOMFINISH : out std_ulogic; + TXDLYSRESETDONE : out std_ulogic; + TXGEARBOXREADY : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXOUTCLKFABRIC : out std_ulogic; + TXOUTCLKPCS : out std_ulogic; + TXPHALIGNDONE : out std_ulogic; + TXPHINITDONE : out std_ulogic; + TXQPISENN : out std_ulogic; + TXQPISENP : out std_ulogic; + TXRATEDONE : out std_ulogic; + TXRESETDONE : out std_ulogic; + + GSR : in std_ulogic; + CFGRESET : in std_ulogic; + CLKRSVD : in std_logic_vector(3 downto 0); + CPLLLOCKDETCLK : in std_ulogic; + CPLLLOCKEN : in std_ulogic; + CPLLPD : in std_ulogic; + CPLLREFCLKSEL : in std_logic_vector(2 downto 0); + CPLLRESET : in std_ulogic; + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_ulogic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_ulogic; + DRPWE : in std_ulogic; + EYESCANMODE : in std_ulogic; + EYESCANRESET : in std_ulogic; + EYESCANTRIGGER : in std_ulogic; + GTGREFCLK : in std_ulogic; + GTNORTHREFCLK0 : in std_ulogic; + GTNORTHREFCLK1 : in std_ulogic; + GTREFCLK0 : in std_ulogic; + GTREFCLK1 : in std_ulogic; + GTRESETSEL : in std_ulogic; + GTRSVD : in std_logic_vector(15 downto 0); + GTRXRESET : in std_ulogic; + GTSOUTHREFCLK0 : in std_ulogic; + GTSOUTHREFCLK1 : in std_ulogic; + GTTXRESET : in std_ulogic; + GTXRXN : in std_ulogic; + GTXRXP : in std_ulogic; + LOOPBACK : in std_logic_vector(2 downto 0); + PCSRSVDIN : in std_logic_vector(15 downto 0); + PCSRSVDIN2 : in std_logic_vector(4 downto 0); + PMARSVDIN : in std_logic_vector(4 downto 0); + PMARSVDIN2 : in std_logic_vector(4 downto 0); + QPLLCLK : in std_ulogic; + QPLLREFCLK : in std_ulogic; + RESETOVRD : in std_ulogic; + RX8B10BEN : in std_ulogic; + RXBUFRESET : in std_ulogic; + RXCDRFREQRESET : in std_ulogic; + RXCDRHOLD : in std_ulogic; + RXCDROVRDEN : in std_ulogic; + RXCDRRESET : in std_ulogic; + RXCDRRESETRSV : in std_ulogic; + RXCHBONDEN : in std_ulogic; + RXCHBONDI : in std_logic_vector(4 downto 0); + RXCHBONDLEVEL : in std_logic_vector(2 downto 0); + RXCHBONDMASTER : in std_ulogic; + RXCHBONDSLAVE : in std_ulogic; + RXCOMMADETEN : in std_ulogic; + RXDDIEN : in std_ulogic; + RXDFEAGCHOLD : in std_ulogic; + RXDFEAGCOVRDEN : in std_ulogic; + RXDFECM1EN : in std_ulogic; + RXDFELFHOLD : in std_ulogic; + RXDFELFOVRDEN : in std_ulogic; + RXDFELPMRESET : in std_ulogic; + RXDFETAP2HOLD : in std_ulogic; + RXDFETAP2OVRDEN : in std_ulogic; + RXDFETAP3HOLD : in std_ulogic; + RXDFETAP3OVRDEN : in std_ulogic; + RXDFETAP4HOLD : in std_ulogic; + RXDFETAP4OVRDEN : in std_ulogic; + RXDFETAP5HOLD : in std_ulogic; + RXDFETAP5OVRDEN : in std_ulogic; + RXDFEUTHOLD : in std_ulogic; + RXDFEUTOVRDEN : in std_ulogic; + RXDFEVPHOLD : in std_ulogic; + RXDFEVPOVRDEN : in std_ulogic; + RXDFEVSEN : in std_ulogic; + RXDFEXYDEN : in std_ulogic; + RXDFEXYDHOLD : in std_ulogic; + RXDFEXYDOVRDEN : in std_ulogic; + RXDLYBYPASS : in std_ulogic; + RXDLYEN : in std_ulogic; + RXDLYOVRDEN : in std_ulogic; + RXDLYSRESET : in std_ulogic; + RXELECIDLEMODE : in std_logic_vector(1 downto 0); + RXGEARBOXSLIP : in std_ulogic; + RXLPMEN : in std_ulogic; + RXLPMHFHOLD : in std_ulogic; + RXLPMHFOVRDEN : in std_ulogic; + RXLPMLFHOLD : in std_ulogic; + RXLPMLFKLOVRDEN : in std_ulogic; + RXMCOMMAALIGNEN : in std_ulogic; + RXMONITORSEL : in std_logic_vector(1 downto 0); + RXOOBRESET : in std_ulogic; + RXOSHOLD : in std_ulogic; + RXOSOVRDEN : in std_ulogic; + RXOUTCLKSEL : in std_logic_vector(2 downto 0); + RXPCOMMAALIGNEN : in std_ulogic; + RXPCSRESET : in std_ulogic; + RXPD : in std_logic_vector(1 downto 0); + RXPHALIGN : in std_ulogic; + RXPHALIGNEN : in std_ulogic; + RXPHDLYPD : in std_ulogic; + RXPHDLYRESET : in std_ulogic; + RXPHOVRDEN : in std_ulogic; + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXPRBSCNTRESET : in std_ulogic; + RXPRBSSEL : in std_logic_vector(2 downto 0); + RXQPIEN : in std_ulogic; + RXRATE : in std_logic_vector(2 downto 0); + RXSLIDE : in std_ulogic; + RXSYSCLKSEL : in std_logic_vector(1 downto 0); + RXUSERRDY : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + SETERRSTATUS : in std_ulogic; + TSTIN : in std_logic_vector(19 downto 0); + TX8B10BBYPASS : in std_logic_vector(7 downto 0); + TX8B10BEN : in std_ulogic; + TXBUFDIFFCTRL : in std_logic_vector(2 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCOMINIT : in std_ulogic; + TXCOMSAS : in std_ulogic; + TXCOMWAKE : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDEEMPH : in std_ulogic; + TXDETECTRX : in std_ulogic; + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXDIFFPD : in std_ulogic; + TXDLYBYPASS : in std_ulogic; + TXDLYEN : in std_ulogic; + TXDLYHOLD : in std_ulogic; + TXDLYOVRDEN : in std_ulogic; + TXDLYSRESET : in std_ulogic; + TXDLYUPDOWN : in std_ulogic; + TXELECIDLE : in std_ulogic; + TXHEADER : in std_logic_vector(2 downto 0); + TXINHIBIT : in std_ulogic; + TXMAINCURSOR : in std_logic_vector(6 downto 0); + TXMARGIN : in std_logic_vector(2 downto 0); + TXOUTCLKSEL : in std_logic_vector(2 downto 0); + TXPCSRESET : in std_ulogic; + TXPD : in std_logic_vector(1 downto 0); + TXPDELECIDLEMODE : in std_ulogic; + TXPHALIGN : in std_ulogic; + TXPHALIGNEN : in std_ulogic; + TXPHDLYPD : in std_ulogic; + TXPHDLYRESET : in std_ulogic; + TXPHDLYTSTCLK : in std_ulogic; + TXPHINIT : in std_ulogic; + TXPHOVRDEN : in std_ulogic; + TXPISOPD : in std_ulogic; + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPOSTCURSORINV : in std_ulogic; + TXPRBSFORCEERR : in std_ulogic; + TXPRBSSEL : in std_logic_vector(2 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0); + TXPRECURSORINV : in std_ulogic; + TXQPIBIASEN : in std_ulogic; + TXQPISTRONGPDOWN : in std_ulogic; + TXQPIWEAKPUP : in std_ulogic; + TXRATE : in std_logic_vector(2 downto 0); + TXSEQUENCE : in std_logic_vector(6 downto 0); + TXSTARTSEQ : in std_ulogic; + TXSWING : in std_ulogic; + TXSYSCLKSEL : in std_logic_vector(1 downto 0); + TXUSERRDY : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant INCLK_DELAY : time := 0 ps; + constant OUTCLK_DELAY : time := 0 ps; + + function SUL_TO_STR (sul : std_ulogic) + return string is + begin + if sul = '0' then + return "0"; + else + return "1"; + end if; + end SUL_TO_STR; + + function boolean_to_string(bool: boolean) + return string is + begin + if bool then + return "TRUE"; + else + return "FALSE"; + end if; + end boolean_to_string; + + function getstrlength(in_vec : std_logic_vector) + return integer is + variable string_length : integer; + begin + if ((in_vec'length mod 4) = 0) then + string_length := in_vec'length/4; + elsif ((in_vec'length mod 4) > 0) then + string_length := in_vec'length/4 + 1; + end if; + return string_length; + end getstrlength; + + -- Convert bit_vector to std_logic_vector + constant ALIGN_COMMA_ENABLE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_COMMA_ENABLE)(9 downto 0); + constant ALIGN_MCOMMA_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_MCOMMA_VALUE)(9 downto 0); + constant ALIGN_PCOMMA_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ALIGN_PCOMMA_VALUE)(9 downto 0); + constant CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1)(9 downto 0); + constant CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2)(9 downto 0); + constant CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3)(9 downto 0); + constant CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4)(9 downto 0); + constant CHAN_BOND_SEQ_1_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE)(3 downto 0); + constant CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1)(9 downto 0); + constant CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2)(9 downto 0); + constant CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3)(9 downto 0); + constant CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4)(9 downto 0); + constant CHAN_BOND_SEQ_2_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE)(3 downto 0); + constant CLK_COR_SEQ_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1)(9 downto 0); + constant CLK_COR_SEQ_1_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2)(9 downto 0); + constant CLK_COR_SEQ_1_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3)(9 downto 0); + constant CLK_COR_SEQ_1_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4)(9 downto 0); + constant CLK_COR_SEQ_1_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE)(3 downto 0); + constant CLK_COR_SEQ_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1)(9 downto 0); + constant CLK_COR_SEQ_2_2_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2)(9 downto 0); + constant CLK_COR_SEQ_2_3_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3)(9 downto 0); + constant CLK_COR_SEQ_2_4_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4)(9 downto 0); + constant CLK_COR_SEQ_2_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE)(3 downto 0); + constant CPLL_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CPLL_CFG)(23 downto 0); + constant CPLL_INIT_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CPLL_INIT_CFG)(23 downto 0); + constant CPLL_LOCK_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(CPLL_LOCK_CFG)(15 downto 0); + constant DMONITOR_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(DMONITOR_CFG)(23 downto 0); + constant ES_CONTROL_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(ES_CONTROL)(5 downto 0); + constant ES_HORZ_OFFSET_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(ES_HORZ_OFFSET)(11 downto 0); + constant ES_PMA_CFG_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(ES_PMA_CFG)(9 downto 0); + constant ES_PRESCALE_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(ES_PRESCALE)(4 downto 0); + constant ES_QUALIFIER_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_QUALIFIER)(79 downto 0); + constant ES_QUAL_MASK_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_QUAL_MASK)(79 downto 0); + constant ES_SDATA_MASK_BINARY : std_logic_vector(79 downto 0) := To_StdLogicVector(ES_SDATA_MASK)(79 downto 0); + constant ES_VERT_OFFSET_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(ES_VERT_OFFSET)(8 downto 0); + constant FTS_DESKEW_SEQ_ENABLE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(FTS_DESKEW_SEQ_ENABLE)(3 downto 0); + constant FTS_LANE_DESKEW_CFG_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(FTS_LANE_DESKEW_CFG)(3 downto 0); + constant GEARBOX_MODE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_MODE)(2 downto 0); + constant OUTREFCLK_SEL_INV_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(OUTREFCLK_SEL_INV)(1 downto 0); + constant PCS_RSVD_ATTR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(PCS_RSVD_ATTR)(47 downto 0); + constant PD_TRANS_TIME_FROM_P2_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PD_TRANS_TIME_FROM_P2)(11 downto 0); + constant PD_TRANS_TIME_NONE_P2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PD_TRANS_TIME_NONE_P2)(7 downto 0); + constant PD_TRANS_TIME_TO_P2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PD_TRANS_TIME_TO_P2)(7 downto 0); + constant PMA_RSV2_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(PMA_RSV2)(15 downto 0); + constant PMA_RSV3_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PMA_RSV3)(1 downto 0); + constant PMA_RSV4_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PMA_RSV4)(31 downto 0); + constant PMA_RSV_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PMA_RSV)(31 downto 0); + constant RXBUFRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXBUFRESET_TIME)(4 downto 0); + constant RXBUF_EIDLE_HI_CNT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXBUF_EIDLE_HI_CNT)(3 downto 0); + constant RXBUF_EIDLE_LO_CNT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXBUF_EIDLE_LO_CNT)(3 downto 0); + constant RXCDRFREQRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXCDRFREQRESET_TIME)(4 downto 0); + constant RXCDRPHRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXCDRPHRESET_TIME)(4 downto 0); + constant RXCDR_CFG_BINARY : std_logic_vector(71 downto 0) := To_StdLogicVector(RXCDR_CFG)(71 downto 0); + constant RXCDR_FR_RESET_ON_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_FR_RESET_ON_EIDLE); + constant RXCDR_HOLD_DURING_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_HOLD_DURING_EIDLE); + constant RXCDR_LOCK_CFG_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCDR_LOCK_CFG)(5 downto 0); + constant RXCDR_PH_RESET_ON_EIDLE_BINARY : std_ulogic := To_StduLogic(RXCDR_PH_RESET_ON_EIDLE); + constant RXDFELPMRESET_TIME_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(RXDFELPMRESET_TIME)(6 downto 0); + constant RXDLY_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RXDLY_CFG)(15 downto 0); + constant RXDLY_LCFG_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(RXDLY_LCFG)(8 downto 0); + constant RXDLY_TAP_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RXDLY_TAP_CFG)(15 downto 0); + constant RXISCANRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXISCANRESET_TIME)(4 downto 0); + constant RXLPM_HF_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(RXLPM_HF_CFG)(13 downto 0); + constant RXLPM_LF_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(RXLPM_LF_CFG)(13 downto 0); + constant RXOOB_CFG_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(RXOOB_CFG)(6 downto 0); + constant RXPCSRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPCSRESET_TIME)(4 downto 0); + constant RXPHDLY_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(RXPHDLY_CFG)(23 downto 0); + constant RXPH_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(RXPH_CFG)(23 downto 0); + constant RXPH_MONITOR_SEL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPH_MONITOR_SEL)(4 downto 0); + constant RXPMARESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXPMARESET_TIME)(4 downto 0); + constant RXPRBS_ERR_LOOPBACK_BINARY : std_ulogic := To_StduLogic(RXPRBS_ERR_LOOPBACK); + constant RX_BIAS_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_BIAS_CFG)(11 downto 0); + constant RX_BUFFER_CFG_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RX_BUFFER_CFG)(5 downto 0); + constant RX_CLKMUX_PD_BINARY : std_ulogic := To_StduLogic(RX_CLKMUX_PD); + constant RX_CM_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_CM_SEL)(1 downto 0); + constant RX_CM_TRIM_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RX_CM_TRIM)(2 downto 0); + constant RX_DDI_SEL_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RX_DDI_SEL)(5 downto 0); + constant RX_DEBUG_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_DEBUG_CFG)(11 downto 0); + constant RX_DFE_GAIN_CFG_BINARY : std_logic_vector(22 downto 0) := To_StdLogicVector(RX_DFE_GAIN_CFG)(22 downto 0); + constant RX_DFE_H2_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_DFE_H2_CFG)(11 downto 0); + constant RX_DFE_H3_CFG_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RX_DFE_H3_CFG)(11 downto 0); + constant RX_DFE_H4_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H4_CFG)(10 downto 0); + constant RX_DFE_H5_CFG_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(RX_DFE_H5_CFG)(10 downto 0); + constant RX_DFE_KL_CFG2_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(RX_DFE_KL_CFG2)(31 downto 0); + constant RX_DFE_KL_CFG_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RX_DFE_KL_CFG)(12 downto 0); + constant RX_DFE_LPM_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(RX_DFE_LPM_CFG)(15 downto 0); + constant RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY : std_ulogic := To_StduLogic(RX_DFE_LPM_HOLD_DURING_EIDLE); + constant RX_DFE_UT_CFG_BINARY : std_logic_vector(16 downto 0) := To_StdLogicVector(RX_DFE_UT_CFG)(16 downto 0); + constant RX_DFE_VP_CFG_BINARY : std_logic_vector(16 downto 0) := To_StdLogicVector(RX_DFE_VP_CFG)(16 downto 0); + constant RX_DFE_XYD_CFG_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RX_DFE_XYD_CFG)(12 downto 0); + constant RX_OS_CFG_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RX_OS_CFG)(12 downto 0); + constant SATA_BURST_SEQ_LEN_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(SATA_BURST_SEQ_LEN)(3 downto 0); + constant SATA_BURST_VAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL)(2 downto 0); + constant SATA_EIDLE_VAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_EIDLE_VAL)(2 downto 0); + constant SIM_CPLLREFCLK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SIM_CPLLREFCLK_SEL)(2 downto 0); + constant TERM_RCAL_CFG_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERM_RCAL_CFG)(4 downto 0); + constant TERM_RCAL_OVRD_BINARY : std_ulogic := To_StduLogic(TERM_RCAL_OVRD); + constant TRANS_TIME_RATE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_RATE)(7 downto 0); + constant TST_RSV_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(TST_RSV)(31 downto 0); + constant TXDLY_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXDLY_CFG)(15 downto 0); + constant TXDLY_LCFG_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(TXDLY_LCFG)(8 downto 0); + constant TXDLY_TAP_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXDLY_TAP_CFG)(15 downto 0); + constant TXPCSRESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPCSRESET_TIME)(4 downto 0); + constant TXPHDLY_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(TXPHDLY_CFG)(23 downto 0); + constant TXPH_CFG_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TXPH_CFG)(15 downto 0); + constant TXPH_MONITOR_SEL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPH_MONITOR_SEL)(4 downto 0); + constant TXPMARESET_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPMARESET_TIME)(4 downto 0); + constant TX_CLKMUX_PD_BINARY : std_ulogic := To_StduLogic(TX_CLKMUX_PD); + constant TX_DEEMPH0_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TX_DEEMPH0)(4 downto 0); + constant TX_DEEMPH1_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TX_DEEMPH1)(4 downto 0); + constant TX_EIDLE_ASSERT_DELAY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_EIDLE_ASSERT_DELAY)(2 downto 0); + constant TX_EIDLE_DEASSERT_DELAY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_EIDLE_DEASSERT_DELAY)(2 downto 0); + constant TX_MAINCURSOR_SEL_BINARY : std_ulogic := To_StduLogic(TX_MAINCURSOR_SEL); + constant TX_MARGIN_FULL_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_0)(6 downto 0); + constant TX_MARGIN_FULL_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_1)(6 downto 0); + constant TX_MARGIN_FULL_2_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_2)(6 downto 0); + constant TX_MARGIN_FULL_3_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_3)(6 downto 0); + constant TX_MARGIN_FULL_4_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_FULL_4)(6 downto 0); + constant TX_MARGIN_LOW_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_0)(6 downto 0); + constant TX_MARGIN_LOW_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_1)(6 downto 0); + constant TX_MARGIN_LOW_2_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_2)(6 downto 0); + constant TX_MARGIN_LOW_3_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_3)(6 downto 0); + constant TX_MARGIN_LOW_4_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(TX_MARGIN_LOW_4)(6 downto 0); + constant TX_PREDRIVER_MODE_BINARY : std_ulogic := To_StduLogic(TX_PREDRIVER_MODE); + constant TX_QPI_STATUS_EN_BINARY : std_ulogic := To_StduLogic(TX_QPI_STATUS_EN); + constant TX_RXDETECT_CFG_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_RXDETECT_CFG)(13 downto 0); + constant TX_RXDETECT_REF_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_RXDETECT_REF)(2 downto 0); + constant UCODEER_CLR_BINARY : std_ulogic := To_StduLogic(UCODEER_CLR); + + -- Get String Length + constant CPLL_CFG_STRLEN : integer := getstrlength(CPLL_CFG_BINARY); + constant CPLL_INIT_CFG_STRLEN : integer := getstrlength(CPLL_INIT_CFG_BINARY); + constant CPLL_LOCK_CFG_STRLEN : integer := getstrlength(CPLL_LOCK_CFG_BINARY); + constant DMONITOR_CFG_STRLEN : integer := getstrlength(DMONITOR_CFG_BINARY); + constant ES_HORZ_OFFSET_STRLEN : integer := getstrlength(ES_HORZ_OFFSET_BINARY); + constant ES_QUALIFIER_STRLEN : integer := getstrlength(ES_QUALIFIER_BINARY); + constant ES_QUAL_MASK_STRLEN : integer := getstrlength(ES_QUAL_MASK_BINARY); + constant ES_SDATA_MASK_STRLEN : integer := getstrlength(ES_SDATA_MASK_BINARY); + constant PCS_RSVD_ATTR_STRLEN : integer := getstrlength(PCS_RSVD_ATTR_BINARY); + constant PD_TRANS_TIME_FROM_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_FROM_P2_BINARY); + constant PD_TRANS_TIME_NONE_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_NONE_P2_BINARY); + constant PD_TRANS_TIME_TO_P2_STRLEN : integer := getstrlength(PD_TRANS_TIME_TO_P2_BINARY); + constant PMA_RSV2_STRLEN : integer := getstrlength(PMA_RSV2_BINARY); + constant PMA_RSV4_STRLEN : integer := getstrlength(PMA_RSV4_BINARY); + constant PMA_RSV_STRLEN : integer := getstrlength(PMA_RSV_BINARY); + constant RXCDR_CFG_STRLEN : integer := getstrlength(RXCDR_CFG_BINARY); + constant RXDLY_CFG_STRLEN : integer := getstrlength(RXDLY_CFG_BINARY); + constant RXDLY_LCFG_STRLEN : integer := getstrlength(RXDLY_LCFG_BINARY); + constant RXDLY_TAP_CFG_STRLEN : integer := getstrlength(RXDLY_TAP_CFG_BINARY); + constant RXPHDLY_CFG_STRLEN : integer := getstrlength(RXPHDLY_CFG_BINARY); + constant RXPH_CFG_STRLEN : integer := getstrlength(RXPH_CFG_BINARY); + constant RX_DFE_GAIN_CFG_STRLEN : integer := getstrlength(RX_DFE_GAIN_CFG_BINARY); + constant RX_DFE_KL_CFG2_STRLEN : integer := getstrlength(RX_DFE_KL_CFG2_BINARY); + constant RX_DFE_LPM_CFG_STRLEN : integer := getstrlength(RX_DFE_LPM_CFG_BINARY); + constant TRANS_TIME_RATE_STRLEN : integer := getstrlength(TRANS_TIME_RATE_BINARY); + constant TST_RSV_STRLEN : integer := getstrlength(TST_RSV_BINARY); + constant TXDLY_CFG_STRLEN : integer := getstrlength(TXDLY_CFG_BINARY); + constant TXDLY_LCFG_STRLEN : integer := getstrlength(TXDLY_LCFG_BINARY); + constant TXDLY_TAP_CFG_STRLEN : integer := getstrlength(TXDLY_TAP_CFG_BINARY); + constant TXPHDLY_CFG_STRLEN : integer := getstrlength(TXPHDLY_CFG_BINARY); + constant TXPH_CFG_STRLEN : integer := getstrlength(TXPH_CFG_BINARY); + constant TX_RXDETECT_CFG_STRLEN : integer := getstrlength(TX_RXDETECT_CFG_BINARY); + + -- Convert std_logic_vector to string + constant ALIGN_COMMA_ENABLE_STRING : string := SLV_TO_STR(ALIGN_COMMA_ENABLE_BINARY); + constant ALIGN_MCOMMA_VALUE_STRING : string := SLV_TO_STR(ALIGN_MCOMMA_VALUE_BINARY); + constant ALIGN_PCOMMA_VALUE_STRING : string := SLV_TO_STR(ALIGN_PCOMMA_VALUE_BINARY); + constant CHAN_BOND_SEQ_1_1_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_1_BINARY); + constant CHAN_BOND_SEQ_1_2_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_2_BINARY); + constant CHAN_BOND_SEQ_1_3_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_3_BINARY); + constant CHAN_BOND_SEQ_1_4_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_4_BINARY); + constant CHAN_BOND_SEQ_1_ENABLE_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_1_ENABLE_BINARY); + constant CHAN_BOND_SEQ_2_1_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_1_BINARY); + constant CHAN_BOND_SEQ_2_2_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_2_BINARY); + constant CHAN_BOND_SEQ_2_3_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_3_BINARY); + constant CHAN_BOND_SEQ_2_4_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_4_BINARY); + constant CHAN_BOND_SEQ_2_ENABLE_STRING : string := SLV_TO_STR(CHAN_BOND_SEQ_2_ENABLE_BINARY); + constant CLK_COR_SEQ_1_1_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_1_BINARY); + constant CLK_COR_SEQ_1_2_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_2_BINARY); + constant CLK_COR_SEQ_1_3_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_3_BINARY); + constant CLK_COR_SEQ_1_4_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_4_BINARY); + constant CLK_COR_SEQ_1_ENABLE_STRING : string := SLV_TO_STR(CLK_COR_SEQ_1_ENABLE_BINARY); + constant CLK_COR_SEQ_2_1_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_1_BINARY); + constant CLK_COR_SEQ_2_2_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_2_BINARY); + constant CLK_COR_SEQ_2_3_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_3_BINARY); + constant CLK_COR_SEQ_2_4_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_4_BINARY); + constant CLK_COR_SEQ_2_ENABLE_STRING : string := SLV_TO_STR(CLK_COR_SEQ_2_ENABLE_BINARY); + constant CPLL_CFG_STRING : string := SLV_TO_HEX(CPLL_CFG_BINARY, CPLL_CFG_STRLEN); + constant CPLL_INIT_CFG_STRING : string := SLV_TO_HEX(CPLL_INIT_CFG_BINARY, CPLL_INIT_CFG_STRLEN); + constant CPLL_LOCK_CFG_STRING : string := SLV_TO_HEX(CPLL_LOCK_CFG_BINARY, CPLL_LOCK_CFG_STRLEN); + constant DMONITOR_CFG_STRING : string := SLV_TO_HEX(DMONITOR_CFG_BINARY, DMONITOR_CFG_STRLEN); + constant ES_CONTROL_STRING : string := SLV_TO_STR(ES_CONTROL_BINARY); + constant ES_HORZ_OFFSET_STRING : string := SLV_TO_HEX(ES_HORZ_OFFSET_BINARY, ES_HORZ_OFFSET_STRLEN); + constant ES_PMA_CFG_STRING : string := SLV_TO_STR(ES_PMA_CFG_BINARY); + constant ES_PRESCALE_STRING : string := SLV_TO_STR(ES_PRESCALE_BINARY); + constant ES_QUALIFIER_STRING : string := SLV_TO_HEX(ES_QUALIFIER_BINARY, ES_QUALIFIER_STRLEN); + constant ES_QUAL_MASK_STRING : string := SLV_TO_HEX(ES_QUAL_MASK_BINARY, ES_QUAL_MASK_STRLEN); + constant ES_SDATA_MASK_STRING : string := SLV_TO_HEX(ES_SDATA_MASK_BINARY, ES_SDATA_MASK_STRLEN); + constant ES_VERT_OFFSET_STRING : string := SLV_TO_STR(ES_VERT_OFFSET_BINARY); + constant FTS_DESKEW_SEQ_ENABLE_STRING : string := SLV_TO_STR(FTS_DESKEW_SEQ_ENABLE_BINARY); + constant FTS_LANE_DESKEW_CFG_STRING : string := SLV_TO_STR(FTS_LANE_DESKEW_CFG_BINARY); + constant GEARBOX_MODE_STRING : string := SLV_TO_STR(GEARBOX_MODE_BINARY); + constant OUTREFCLK_SEL_INV_STRING : string := SLV_TO_STR(OUTREFCLK_SEL_INV_BINARY); + constant PCS_RSVD_ATTR_STRING : string := SLV_TO_HEX(PCS_RSVD_ATTR_BINARY, PCS_RSVD_ATTR_STRLEN); + constant PD_TRANS_TIME_FROM_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_FROM_P2_BINARY, PD_TRANS_TIME_FROM_P2_STRLEN); + constant PD_TRANS_TIME_NONE_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_NONE_P2_BINARY, PD_TRANS_TIME_NONE_P2_STRLEN); + constant PD_TRANS_TIME_TO_P2_STRING : string := SLV_TO_HEX(PD_TRANS_TIME_TO_P2_BINARY, PD_TRANS_TIME_TO_P2_STRLEN); + constant PMA_RSV2_STRING : string := SLV_TO_HEX(PMA_RSV2_BINARY, PMA_RSV2_STRLEN); + constant PMA_RSV3_STRING : string := SLV_TO_STR(PMA_RSV3_BINARY); + constant PMA_RSV4_STRING : string := SLV_TO_HEX(PMA_RSV4_BINARY, PMA_RSV4_STRLEN); + constant PMA_RSV_STRING : string := SLV_TO_HEX(PMA_RSV_BINARY, PMA_RSV_STRLEN); + constant RXBUFRESET_TIME_STRING : string := SLV_TO_STR(RXBUFRESET_TIME_BINARY); + constant RXBUF_EIDLE_HI_CNT_STRING : string := SLV_TO_STR(RXBUF_EIDLE_HI_CNT_BINARY); + constant RXBUF_EIDLE_LO_CNT_STRING : string := SLV_TO_STR(RXBUF_EIDLE_LO_CNT_BINARY); + constant RXCDRFREQRESET_TIME_STRING : string := SLV_TO_STR(RXCDRFREQRESET_TIME_BINARY); + constant RXCDRPHRESET_TIME_STRING : string := SLV_TO_STR(RXCDRPHRESET_TIME_BINARY); + constant RXCDR_CFG_STRING : string := SLV_TO_HEX(RXCDR_CFG_BINARY, RXCDR_CFG_STRLEN); + constant RXCDR_FR_RESET_ON_EIDLE_STRING : string := SUL_TO_STR(RXCDR_FR_RESET_ON_EIDLE_BINARY); + constant RXCDR_HOLD_DURING_EIDLE_STRING : string := SUL_TO_STR(RXCDR_HOLD_DURING_EIDLE_BINARY); + constant RXCDR_LOCK_CFG_STRING : string := SLV_TO_STR(RXCDR_LOCK_CFG_BINARY); + constant RXCDR_PH_RESET_ON_EIDLE_STRING : string := SUL_TO_STR(RXCDR_PH_RESET_ON_EIDLE_BINARY); + constant RXDFELPMRESET_TIME_STRING : string := SLV_TO_STR(RXDFELPMRESET_TIME_BINARY); + constant RXDLY_CFG_STRING : string := SLV_TO_HEX(RXDLY_CFG_BINARY, RXDLY_CFG_STRLEN); + constant RXDLY_LCFG_STRING : string := SLV_TO_HEX(RXDLY_LCFG_BINARY, RXDLY_LCFG_STRLEN); + constant RXDLY_TAP_CFG_STRING : string := SLV_TO_HEX(RXDLY_TAP_CFG_BINARY, RXDLY_TAP_CFG_STRLEN); + constant RXISCANRESET_TIME_STRING : string := SLV_TO_STR(RXISCANRESET_TIME_BINARY); + constant RXLPM_HF_CFG_STRING : string := SLV_TO_STR(RXLPM_HF_CFG_BINARY); + constant RXLPM_LF_CFG_STRING : string := SLV_TO_STR(RXLPM_LF_CFG_BINARY); + constant RXOOB_CFG_STRING : string := SLV_TO_STR(RXOOB_CFG_BINARY); + constant RXPCSRESET_TIME_STRING : string := SLV_TO_STR(RXPCSRESET_TIME_BINARY); + constant RXPHDLY_CFG_STRING : string := SLV_TO_HEX(RXPHDLY_CFG_BINARY, RXPHDLY_CFG_STRLEN); + constant RXPH_CFG_STRING : string := SLV_TO_HEX(RXPH_CFG_BINARY, RXPH_CFG_STRLEN); + constant RXPH_MONITOR_SEL_STRING : string := SLV_TO_STR(RXPH_MONITOR_SEL_BINARY); + constant RXPMARESET_TIME_STRING : string := SLV_TO_STR(RXPMARESET_TIME_BINARY); + constant RXPRBS_ERR_LOOPBACK_STRING : string := SUL_TO_STR(RXPRBS_ERR_LOOPBACK_BINARY); + constant RX_BIAS_CFG_STRING : string := SLV_TO_STR(RX_BIAS_CFG_BINARY); + constant RX_BUFFER_CFG_STRING : string := SLV_TO_STR(RX_BUFFER_CFG_BINARY); + constant RX_CLKMUX_PD_STRING : string := SUL_TO_STR(RX_CLKMUX_PD_BINARY); + constant RX_CM_SEL_STRING : string := SLV_TO_STR(RX_CM_SEL_BINARY); + constant RX_CM_TRIM_STRING : string := SLV_TO_STR(RX_CM_TRIM_BINARY); + constant RX_DDI_SEL_STRING : string := SLV_TO_STR(RX_DDI_SEL_BINARY); + constant RX_DEBUG_CFG_STRING : string := SLV_TO_STR(RX_DEBUG_CFG_BINARY); + constant RX_DFE_GAIN_CFG_STRING : string := SLV_TO_HEX(RX_DFE_GAIN_CFG_BINARY, RX_DFE_GAIN_CFG_STRLEN); + constant RX_DFE_H2_CFG_STRING : string := SLV_TO_STR(RX_DFE_H2_CFG_BINARY); + constant RX_DFE_H3_CFG_STRING : string := SLV_TO_STR(RX_DFE_H3_CFG_BINARY); + constant RX_DFE_H4_CFG_STRING : string := SLV_TO_STR(RX_DFE_H4_CFG_BINARY); + constant RX_DFE_H5_CFG_STRING : string := SLV_TO_STR(RX_DFE_H5_CFG_BINARY); + constant RX_DFE_KL_CFG2_STRING : string := SLV_TO_HEX(RX_DFE_KL_CFG2_BINARY, RX_DFE_KL_CFG2_STRLEN); + constant RX_DFE_KL_CFG_STRING : string := SLV_TO_STR(RX_DFE_KL_CFG_BINARY); + constant RX_DFE_LPM_CFG_STRING : string := SLV_TO_HEX(RX_DFE_LPM_CFG_BINARY, RX_DFE_LPM_CFG_STRLEN); + constant RX_DFE_LPM_HOLD_DURING_EIDLE_STRING : string := SUL_TO_STR(RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY); + constant RX_DFE_UT_CFG_STRING : string := SLV_TO_STR(RX_DFE_UT_CFG_BINARY); + constant RX_DFE_VP_CFG_STRING : string := SLV_TO_STR(RX_DFE_VP_CFG_BINARY); + constant RX_DFE_XYD_CFG_STRING : string := SLV_TO_STR(RX_DFE_XYD_CFG_BINARY); + constant RX_OS_CFG_STRING : string := SLV_TO_STR(RX_OS_CFG_BINARY); + constant SATA_BURST_SEQ_LEN_STRING : string := SLV_TO_STR(SATA_BURST_SEQ_LEN_BINARY); + constant SATA_BURST_VAL_STRING : string := SLV_TO_STR(SATA_BURST_VAL_BINARY); + constant SATA_EIDLE_VAL_STRING : string := SLV_TO_STR(SATA_EIDLE_VAL_BINARY); + constant SIM_CPLLREFCLK_SEL_STRING : string := SLV_TO_STR(SIM_CPLLREFCLK_SEL_BINARY); + constant TERM_RCAL_CFG_STRING : string := SLV_TO_STR(TERM_RCAL_CFG_BINARY); + constant TERM_RCAL_OVRD_STRING : string := SUL_TO_STR(TERM_RCAL_OVRD_BINARY); + constant TRANS_TIME_RATE_STRING : string := SLV_TO_HEX(TRANS_TIME_RATE_BINARY, TRANS_TIME_RATE_STRLEN); + constant TST_RSV_STRING : string := SLV_TO_HEX(TST_RSV_BINARY, TST_RSV_STRLEN); + constant TXDLY_CFG_STRING : string := SLV_TO_HEX(TXDLY_CFG_BINARY, TXDLY_CFG_STRLEN); + constant TXDLY_LCFG_STRING : string := SLV_TO_HEX(TXDLY_LCFG_BINARY, TXDLY_LCFG_STRLEN); + constant TXDLY_TAP_CFG_STRING : string := SLV_TO_HEX(TXDLY_TAP_CFG_BINARY, TXDLY_TAP_CFG_STRLEN); + constant TXPCSRESET_TIME_STRING : string := SLV_TO_STR(TXPCSRESET_TIME_BINARY); + constant TXPHDLY_CFG_STRING : string := SLV_TO_HEX(TXPHDLY_CFG_BINARY, TXPHDLY_CFG_STRLEN); + constant TXPH_CFG_STRING : string := SLV_TO_HEX(TXPH_CFG_BINARY, TXPH_CFG_STRLEN); + constant TXPH_MONITOR_SEL_STRING : string := SLV_TO_STR(TXPH_MONITOR_SEL_BINARY); + constant TXPMARESET_TIME_STRING : string := SLV_TO_STR(TXPMARESET_TIME_BINARY); + constant TX_CLKMUX_PD_STRING : string := SUL_TO_STR(TX_CLKMUX_PD_BINARY); + constant TX_DEEMPH0_STRING : string := SLV_TO_STR(TX_DEEMPH0_BINARY); + constant TX_DEEMPH1_STRING : string := SLV_TO_STR(TX_DEEMPH1_BINARY); + constant TX_EIDLE_ASSERT_DELAY_STRING : string := SLV_TO_STR(TX_EIDLE_ASSERT_DELAY_BINARY); + constant TX_EIDLE_DEASSERT_DELAY_STRING : string := SLV_TO_STR(TX_EIDLE_DEASSERT_DELAY_BINARY); + constant TX_MAINCURSOR_SEL_STRING : string := SUL_TO_STR(TX_MAINCURSOR_SEL_BINARY); + constant TX_MARGIN_FULL_0_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_0_BINARY); + constant TX_MARGIN_FULL_1_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_1_BINARY); + constant TX_MARGIN_FULL_2_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_2_BINARY); + constant TX_MARGIN_FULL_3_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_3_BINARY); + constant TX_MARGIN_FULL_4_STRING : string := SLV_TO_STR(TX_MARGIN_FULL_4_BINARY); + constant TX_MARGIN_LOW_0_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_0_BINARY); + constant TX_MARGIN_LOW_1_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_1_BINARY); + constant TX_MARGIN_LOW_2_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_2_BINARY); + constant TX_MARGIN_LOW_3_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_3_BINARY); + constant TX_MARGIN_LOW_4_STRING : string := SLV_TO_STR(TX_MARGIN_LOW_4_BINARY); + constant TX_PREDRIVER_MODE_STRING : string := SUL_TO_STR(TX_PREDRIVER_MODE_BINARY); + constant TX_QPI_STATUS_EN_STRING : string := SUL_TO_STR(TX_QPI_STATUS_EN_BINARY); + constant TX_RXDETECT_CFG_STRING : string := SLV_TO_HEX(TX_RXDETECT_CFG_BINARY, TX_RXDETECT_CFG_STRLEN); + constant TX_RXDETECT_REF_STRING : string := SLV_TO_STR(TX_RXDETECT_REF_BINARY); + constant UCODEER_CLR_STRING : string := SUL_TO_STR(UCODEER_CLR_BINARY); + + signal IS_CPLLLOCKDETCLK_INVERTED_BIN : std_ulogic; + signal IS_DRPCLK_INVERTED_BIN : std_ulogic; + signal IS_GTGREFCLK_INVERTED_BIN : std_ulogic; + signal IS_RXUSRCLK2_INVERTED_BIN : std_ulogic; + signal IS_RXUSRCLK_INVERTED_BIN : std_ulogic; + signal IS_TXPHDLYTSTCLK_INVERTED_BIN : std_ulogic; + signal IS_TXUSRCLK2_INVERTED_BIN : std_ulogic; + signal IS_TXUSRCLK_INVERTED_BIN : std_ulogic; + + signal ALIGN_COMMA_DOUBLE_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_BINARY : std_logic_vector(2 downto 0); + signal ALIGN_MCOMMA_DET_BINARY : std_ulogic; + signal ALIGN_PCOMMA_DET_BINARY : std_ulogic; + signal CBCC_DATA_SOURCE_SEL_BINARY : std_ulogic; + signal CHAN_BOND_KEEP_ALIGN_BINARY : std_ulogic; + signal CHAN_BOND_MAX_SKEW_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CLK_CORRECT_USE_BINARY : std_ulogic; + signal CLK_COR_KEEP_IDLE_BINARY : std_ulogic; + signal CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_PRECEDENCE_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; + signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CPLL_FBDIV_45_BINARY : std_ulogic; + signal CPLL_FBDIV_BINARY : std_logic_vector(6 downto 0); + signal CPLL_REFCLK_DIV_BINARY : std_logic_vector(4 downto 0); + signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; + signal ES_ERRDET_EN_BINARY : std_ulogic; + signal ES_EYE_SCAN_EN_BINARY : std_ulogic; + signal FTS_LANE_DESKEW_EN_BINARY : std_ulogic; + signal PCS_PCIE_EN_BINARY : std_ulogic; + signal RXBUF_ADDR_MODE_BINARY : std_ulogic; + signal RXBUF_EN_BINARY : std_ulogic; + signal RXBUF_RESET_ON_CB_CHANGE_BINARY : std_ulogic; + signal RXBUF_RESET_ON_COMMAALIGN_BINARY : std_ulogic; + signal RXBUF_RESET_ON_EIDLE_BINARY : std_ulogic; + signal RXBUF_RESET_ON_RATE_CHANGE_BINARY : std_ulogic; + signal RXBUF_THRESH_OVFLW_BINARY : std_logic_vector(5 downto 0); + signal RXBUF_THRESH_OVRD_BINARY : std_ulogic; + signal RXBUF_THRESH_UNDFLW_BINARY : std_logic_vector(5 downto 0); + signal RXGEARBOX_EN_BINARY : std_ulogic; + signal RXOUT_DIV_BINARY : std_logic_vector(2 downto 0); + signal RXSLIDE_AUTO_WAIT_BINARY : std_logic_vector(3 downto 0); + signal RXSLIDE_MODE_BINARY : std_logic_vector(1 downto 0); + signal RX_CLK25_DIV_BINARY : std_logic_vector(4 downto 0); + signal RX_DATA_WIDTH_BINARY : std_logic_vector(2 downto 0); + signal RX_DEFER_RESET_BUF_EN_BINARY : std_ulogic; + signal RX_DISPERR_SEQ_MATCH_BINARY : std_ulogic; + signal RX_INT_DATAWIDTH_BINARY : std_ulogic; + signal RX_SIG_VALID_DLY_BINARY : std_logic_vector(4 downto 0); + signal RX_XCLK_SEL_BINARY : std_ulogic; + signal SAS_MAX_COM_BINARY : std_logic_vector(6 downto 0); + signal SAS_MIN_COM_BINARY : std_logic_vector(5 downto 0); + signal SATA_CPLL_CFG_BINARY : std_logic_vector(1 downto 0); + signal SATA_MAX_BURST_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_BURST_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_BINARY : std_logic_vector(5 downto 0); + signal SHOW_REALIGN_COMMA_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS_BINARY : std_ulogic; + signal SIM_RESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_TX_EIDLE_DRIVE_LEVEL_BINARY : std_ulogic; + signal SIM_VERSION_BINARY : std_ulogic; + signal TXBUF_EN_BINARY : std_ulogic; + signal TXBUF_RESET_ON_RATE_CHANGE_BINARY : std_ulogic; + signal TXGEARBOX_EN_BINARY : std_ulogic; + signal TXOUT_DIV_BINARY : std_logic_vector(2 downto 0); + signal TX_CLK25_DIV_BINARY : std_logic_vector(4 downto 0); + signal TX_DATA_WIDTH_BINARY : std_logic_vector(2 downto 0); + signal TX_DRIVE_MODE_BINARY : std_logic_vector(4 downto 0); + signal TX_INT_DATAWIDTH_BINARY : std_ulogic; + signal TX_LOOPBACK_DRIVE_HIZ_BINARY : std_ulogic; + signal TX_XCLK_SEL_BINARY : std_ulogic; + + signal CPLLFBCLKLOST_out : std_ulogic; + signal CPLLLOCK_out : std_ulogic; + signal CPLLREFCLKLOST_out : std_ulogic; + signal DMONITOROUT_out : std_logic_vector(7 downto 0); + signal DRPDO_out : std_logic_vector(15 downto 0); + signal DRPRDY_out : std_ulogic; + signal EYESCANDATAERROR_out : std_ulogic; + signal GTREFCLKMONITOR_out : std_ulogic; + signal GTXTXN_out : std_ulogic; + signal GTXTXP_out : std_ulogic; + signal PCSRSVDOUT_out : std_logic_vector(15 downto 0); + signal PHYSTATUS_out : std_ulogic; + signal RXBUFSTATUS_out : std_logic_vector(2 downto 0); + signal RXBYTEISALIGNED_out : std_ulogic; + signal RXBYTEREALIGN_out : std_ulogic; + signal RXCDRLOCK_out : std_ulogic; + signal RXCHANBONDSEQ_out : std_ulogic; + signal RXCHANISALIGNED_out : std_ulogic; + signal RXCHANREALIGN_out : std_ulogic; + signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); + signal RXCHARISK_out : std_logic_vector(7 downto 0); + signal RXCHBONDO_out : std_logic_vector(4 downto 0); + signal RXCLKCORCNT_out : std_logic_vector(1 downto 0); + signal RXCOMINITDET_out : std_ulogic; + signal RXCOMMADET_out : std_ulogic; + signal RXCOMSASDET_out : std_ulogic; + signal RXCOMWAKEDET_out : std_ulogic; + signal RXDATAVALID_out : std_ulogic; + signal RXDATA_out : std_logic_vector(63 downto 0); + signal RXDISPERR_out : std_logic_vector(7 downto 0); + signal RXDLYSRESETDONE_out : std_ulogic; + signal RXELECIDLE_out : std_ulogic; + signal RXHEADERVALID_out : std_ulogic; + signal RXHEADER_out : std_logic_vector(2 downto 0); + signal RXMONITOROUT_out : std_logic_vector(6 downto 0); + signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); + signal RXOUTCLKFABRIC_out : std_ulogic; + signal RXOUTCLKPCS_out : std_ulogic; + signal RXOUTCLK_out : std_ulogic; + signal RXPHALIGNDONE_out : std_ulogic; + signal RXPHMONITOR_out : std_logic_vector(4 downto 0); + signal RXPHSLIPMONITOR_out : std_logic_vector(4 downto 0); + signal RXPRBSERR_out : std_ulogic; + signal RXQPISENN_out : std_ulogic; + signal RXQPISENP_out : std_ulogic; + signal RXRATEDONE_out : std_ulogic; + signal RXRESETDONE_out : std_ulogic; + signal RXSTARTOFSEQ_out : std_ulogic; + signal RXSTATUS_out : std_logic_vector(2 downto 0); + signal RXVALID_out : std_ulogic; + signal TSTOUT_out : std_logic_vector(9 downto 0); + signal TXBUFSTATUS_out : std_logic_vector(1 downto 0); + signal TXCOMFINISH_out : std_ulogic; + signal TXDLYSRESETDONE_out : std_ulogic; + signal TXGEARBOXREADY_out : std_ulogic; + signal TXOUTCLKFABRIC_out : std_ulogic; + signal TXOUTCLKPCS_out : std_ulogic; + signal TXOUTCLK_out : std_ulogic; + signal TXPHALIGNDONE_out : std_ulogic; + signal TXPHINITDONE_out : std_ulogic; + signal TXQPISENN_out : std_ulogic; + signal TXQPISENP_out : std_ulogic; + signal TXRATEDONE_out : std_ulogic; + signal TXRESETDONE_out : std_ulogic; + + signal CPLLFBCLKLOST_outdelay : std_ulogic; + signal CPLLLOCK_outdelay : std_ulogic; + signal CPLLREFCLKLOST_outdelay : std_ulogic; + signal DMONITOROUT_outdelay : std_logic_vector(7 downto 0); + signal DRPDO_outdelay : std_logic_vector(15 downto 0); + signal DRPRDY_outdelay : std_ulogic; + signal EYESCANDATAERROR_outdelay : std_ulogic; + signal GTREFCLKMONITOR_outdelay : std_ulogic; + signal GTXTXN_outdelay : std_ulogic; + signal GTXTXP_outdelay : std_ulogic; + signal PCSRSVDOUT_outdelay : std_logic_vector(15 downto 0); + signal PHYSTATUS_outdelay : std_ulogic; + signal RXBUFSTATUS_outdelay : std_logic_vector(2 downto 0); + signal RXBYTEISALIGNED_outdelay : std_ulogic; + signal RXBYTEREALIGN_outdelay : std_ulogic; + signal RXCDRLOCK_outdelay : std_ulogic; + signal RXCHANBONDSEQ_outdelay : std_ulogic; + signal RXCHANISALIGNED_outdelay : std_ulogic; + signal RXCHANREALIGN_outdelay : std_ulogic; + signal RXCHARISCOMMA_outdelay : std_logic_vector(7 downto 0); + signal RXCHARISK_outdelay : std_logic_vector(7 downto 0); + signal RXCHBONDO_outdelay : std_logic_vector(4 downto 0); + signal RXCLKCORCNT_outdelay : std_logic_vector(1 downto 0); + signal RXCOMINITDET_outdelay : std_ulogic; + signal RXCOMMADET_outdelay : std_ulogic; + signal RXCOMSASDET_outdelay : std_ulogic; + signal RXCOMWAKEDET_outdelay : std_ulogic; + signal RXDATAVALID_outdelay : std_ulogic; + signal RXDATA_outdelay : std_logic_vector(63 downto 0); + signal RXDISPERR_outdelay : std_logic_vector(7 downto 0); + signal RXDLYSRESETDONE_outdelay : std_ulogic; + signal RXELECIDLE_outdelay : std_ulogic; + signal RXHEADERVALID_outdelay : std_ulogic; + signal RXHEADER_outdelay : std_logic_vector(2 downto 0); + signal RXMONITOROUT_outdelay : std_logic_vector(6 downto 0); + signal RXNOTINTABLE_outdelay : std_logic_vector(7 downto 0); + signal RXOUTCLKFABRIC_outdelay : std_ulogic; + signal RXOUTCLKPCS_outdelay : std_ulogic; + signal RXOUTCLK_outdelay : std_ulogic; + signal RXPHALIGNDONE_outdelay : std_ulogic; + signal RXPHMONITOR_outdelay : std_logic_vector(4 downto 0); + signal RXPHSLIPMONITOR_outdelay : std_logic_vector(4 downto 0); + signal RXPRBSERR_outdelay : std_ulogic; + signal RXQPISENN_outdelay : std_ulogic; + signal RXQPISENP_outdelay : std_ulogic; + signal RXRATEDONE_outdelay : std_ulogic; + signal RXRESETDONE_outdelay : std_ulogic; + signal RXSTARTOFSEQ_outdelay : std_ulogic; + signal RXSTATUS_outdelay : std_logic_vector(2 downto 0); + signal RXVALID_outdelay : std_ulogic; + signal TSTOUT_outdelay : std_logic_vector(9 downto 0); + signal TXBUFSTATUS_outdelay : std_logic_vector(1 downto 0); + signal TXCOMFINISH_outdelay : std_ulogic; + signal TXDLYSRESETDONE_outdelay : std_ulogic; + signal TXGEARBOXREADY_outdelay : std_ulogic; + signal TXOUTCLKFABRIC_outdelay : std_ulogic; + signal TXOUTCLKPCS_outdelay : std_ulogic; + signal TXOUTCLK_outdelay : std_ulogic; + signal TXPHALIGNDONE_outdelay : std_ulogic; + signal TXPHINITDONE_outdelay : std_ulogic; + signal TXQPISENN_outdelay : std_ulogic; + signal TXQPISENP_outdelay : std_ulogic; + signal TXRATEDONE_outdelay : std_ulogic; + signal TXRESETDONE_outdelay : std_ulogic; + + signal CFGRESET_ipd : std_ulogic; + signal CLKRSVD_ipd : std_logic_vector(3 downto 0); + signal CPLLLOCKDETCLK_ipd : std_ulogic; + signal CPLLLOCKEN_ipd : std_ulogic; + signal CPLLPD_ipd : std_ulogic; + signal CPLLREFCLKSEL_ipd : std_logic_vector(2 downto 0); + signal CPLLRESET_ipd : std_ulogic; + signal DRPADDR_ipd : std_logic_vector(8 downto 0); + signal DRPCLK_ipd : std_ulogic; + signal DRPDI_ipd : std_logic_vector(15 downto 0); + signal DRPEN_ipd : std_ulogic; + signal DRPWE_ipd : std_ulogic; + signal EYESCANMODE_ipd : std_ulogic; + signal EYESCANRESET_ipd : std_ulogic; + signal EYESCANTRIGGER_ipd : std_ulogic; + signal GTGREFCLK_ipd : std_ulogic; + signal GTNORTHREFCLK0_ipd : std_ulogic; + signal GTNORTHREFCLK1_ipd : std_ulogic; + signal GTREFCLK0_ipd : std_ulogic; + signal GTREFCLK1_ipd : std_ulogic; + signal GTRESETSEL_ipd : std_ulogic; + signal GTRSVD_ipd : std_logic_vector(15 downto 0); + signal GTRXRESET_ipd : std_ulogic; + signal GTSOUTHREFCLK0_ipd : std_ulogic; + signal GTSOUTHREFCLK1_ipd : std_ulogic; + signal GTTXRESET_ipd : std_ulogic; + signal GTXRXN_ipd : std_ulogic; + signal GTXRXP_ipd : std_ulogic; + signal LOOPBACK_ipd : std_logic_vector(2 downto 0); + signal PCSRSVDIN2_ipd : std_logic_vector(4 downto 0); + signal PCSRSVDIN_ipd : std_logic_vector(15 downto 0); + signal PMARSVDIN2_ipd : std_logic_vector(4 downto 0); + signal PMARSVDIN_ipd : std_logic_vector(4 downto 0); + signal QPLLCLK_ipd : std_ulogic; + signal QPLLREFCLK_ipd : std_ulogic; + signal RESETOVRD_ipd : std_ulogic; + signal RX8B10BEN_ipd : std_ulogic; + signal RXBUFRESET_ipd : std_ulogic; + signal RXCDRFREQRESET_ipd : std_ulogic; + signal RXCDRHOLD_ipd : std_ulogic; + signal RXCDROVRDEN_ipd : std_ulogic; + signal RXCDRRESETRSV_ipd : std_ulogic; + signal RXCDRRESET_ipd : std_ulogic; + signal RXCHBONDEN_ipd : std_ulogic; + signal RXCHBONDI_ipd : std_logic_vector(4 downto 0); + signal RXCHBONDLEVEL_ipd : std_logic_vector(2 downto 0); + signal RXCHBONDMASTER_ipd : std_ulogic; + signal RXCHBONDSLAVE_ipd : std_ulogic; + signal RXCOMMADETEN_ipd : std_ulogic; + signal RXDDIEN_ipd : std_ulogic; + signal RXDFEAGCHOLD_ipd : std_ulogic; + signal RXDFEAGCOVRDEN_ipd : std_ulogic; + signal RXDFECM1EN_ipd : std_ulogic; + signal RXDFELFHOLD_ipd : std_ulogic; + signal RXDFELFOVRDEN_ipd : std_ulogic; + signal RXDFELPMRESET_ipd : std_ulogic; + signal RXDFETAP2HOLD_ipd : std_ulogic; + signal RXDFETAP2OVRDEN_ipd : std_ulogic; + signal RXDFETAP3HOLD_ipd : std_ulogic; + signal RXDFETAP3OVRDEN_ipd : std_ulogic; + signal RXDFETAP4HOLD_ipd : std_ulogic; + signal RXDFETAP4OVRDEN_ipd : std_ulogic; + signal RXDFETAP5HOLD_ipd : std_ulogic; + signal RXDFETAP5OVRDEN_ipd : std_ulogic; + signal RXDFEUTHOLD_ipd : std_ulogic; + signal RXDFEUTOVRDEN_ipd : std_ulogic; + signal RXDFEVPHOLD_ipd : std_ulogic; + signal RXDFEVPOVRDEN_ipd : std_ulogic; + signal RXDFEVSEN_ipd : std_ulogic; + signal RXDFEXYDEN_ipd : std_ulogic; + signal RXDFEXYDHOLD_ipd : std_ulogic; + signal RXDFEXYDOVRDEN_ipd : std_ulogic; + signal RXDLYBYPASS_ipd : std_ulogic; + signal RXDLYEN_ipd : std_ulogic; + signal RXDLYOVRDEN_ipd : std_ulogic; + signal RXDLYSRESET_ipd : std_ulogic; + signal RXELECIDLEMODE_ipd : std_logic_vector(1 downto 0); + signal RXGEARBOXSLIP_ipd : std_ulogic; + signal RXLPMEN_ipd : std_ulogic; + signal RXLPMHFHOLD_ipd : std_ulogic; + signal RXLPMHFOVRDEN_ipd : std_ulogic; + signal RXLPMLFHOLD_ipd : std_ulogic; + signal RXLPMLFKLOVRDEN_ipd : std_ulogic; + signal RXMCOMMAALIGNEN_ipd : std_ulogic; + signal RXMONITORSEL_ipd : std_logic_vector(1 downto 0); + signal RXOOBRESET_ipd : std_ulogic; + signal RXOSHOLD_ipd : std_ulogic; + signal RXOSOVRDEN_ipd : std_ulogic; + signal RXOUTCLKSEL_ipd : std_logic_vector(2 downto 0); + signal RXPCOMMAALIGNEN_ipd : std_ulogic; + signal RXPCSRESET_ipd : std_ulogic; + signal RXPD_ipd : std_logic_vector(1 downto 0); + signal RXPHALIGNEN_ipd : std_ulogic; + signal RXPHALIGN_ipd : std_ulogic; + signal RXPHDLYPD_ipd : std_ulogic; + signal RXPHDLYRESET_ipd : std_ulogic; + signal RXPHOVRDEN_ipd : std_ulogic; + signal RXPMARESET_ipd : std_ulogic; + signal RXPOLARITY_ipd : std_ulogic; + signal RXPRBSCNTRESET_ipd : std_ulogic; + signal RXPRBSSEL_ipd : std_logic_vector(2 downto 0); + signal RXQPIEN_ipd : std_ulogic; + signal RXRATE_ipd : std_logic_vector(2 downto 0); + signal RXSLIDE_ipd : std_ulogic; + signal RXSYSCLKSEL_ipd : std_logic_vector(1 downto 0); + signal RXUSERRDY_ipd : std_ulogic; + signal RXUSRCLK2_ipd : std_ulogic; + signal RXUSRCLK_ipd : std_ulogic; + signal SETERRSTATUS_ipd : std_ulogic; + signal TSTIN_ipd : std_logic_vector(19 downto 0); + signal TX8B10BBYPASS_ipd : std_logic_vector(7 downto 0); + signal TX8B10BEN_ipd : std_ulogic; + signal TXBUFDIFFCTRL_ipd : std_logic_vector(2 downto 0); + signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); + signal TXCHARISK_ipd : std_logic_vector(7 downto 0); + signal TXCOMINIT_ipd : std_ulogic; + signal TXCOMSAS_ipd : std_ulogic; + signal TXCOMWAKE_ipd : std_ulogic; + signal TXDATA_ipd : std_logic_vector(63 downto 0); + signal TXDEEMPH_ipd : std_ulogic; + signal TXDETECTRX_ipd : std_ulogic; + signal TXDIFFCTRL_ipd : std_logic_vector(3 downto 0); + signal TXDIFFPD_ipd : std_ulogic; + signal TXDLYBYPASS_ipd : std_ulogic; + signal TXDLYEN_ipd : std_ulogic; + signal TXDLYHOLD_ipd : std_ulogic; + signal TXDLYOVRDEN_ipd : std_ulogic; + signal TXDLYSRESET_ipd : std_ulogic; + signal TXDLYUPDOWN_ipd : std_ulogic; + signal TXELECIDLE_ipd : std_ulogic; + signal TXHEADER_ipd : std_logic_vector(2 downto 0); + signal TXINHIBIT_ipd : std_ulogic; + signal TXMAINCURSOR_ipd : std_logic_vector(6 downto 0); + signal TXMARGIN_ipd : std_logic_vector(2 downto 0); + signal TXOUTCLKSEL_ipd : std_logic_vector(2 downto 0); + signal TXPCSRESET_ipd : std_ulogic; + signal TXPDELECIDLEMODE_ipd : std_ulogic; + signal TXPD_ipd : std_logic_vector(1 downto 0); + signal TXPHALIGNEN_ipd : std_ulogic; + signal TXPHALIGN_ipd : std_ulogic; + signal TXPHDLYPD_ipd : std_ulogic; + signal TXPHDLYRESET_ipd : std_ulogic; + signal TXPHDLYTSTCLK_ipd : std_ulogic; + signal TXPHINIT_ipd : std_ulogic; + signal TXPHOVRDEN_ipd : std_ulogic; + signal TXPISOPD_ipd : std_ulogic; + signal TXPMARESET_ipd : std_ulogic; + signal TXPOLARITY_ipd : std_ulogic; + signal TXPOSTCURSORINV_ipd : std_ulogic; + signal TXPOSTCURSOR_ipd : std_logic_vector(4 downto 0); + signal TXPRBSFORCEERR_ipd : std_ulogic; + signal TXPRBSSEL_ipd : std_logic_vector(2 downto 0); + signal TXPRECURSORINV_ipd : std_ulogic; + signal TXPRECURSOR_ipd : std_logic_vector(4 downto 0); + signal TXQPIBIASEN_ipd : std_ulogic; + signal TXQPISTRONGPDOWN_ipd : std_ulogic; + signal TXQPIWEAKPUP_ipd : std_ulogic; + signal TXRATE_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ_ipd : std_ulogic; + signal TXSWING_ipd : std_ulogic; + signal TXSYSCLKSEL_ipd : std_logic_vector(1 downto 0); + signal TXUSERRDY_ipd : std_ulogic; + signal TXUSRCLK2_ipd : std_ulogic; + signal TXUSRCLK_ipd : std_ulogic; + + signal CFGRESET_indelay : std_ulogic; + signal CLKRSVD_indelay : std_logic_vector(3 downto 0); + signal CPLLLOCKDETCLK_indelay : std_ulogic; + signal CPLLLOCKEN_indelay : std_ulogic; + signal CPLLPD_indelay : std_ulogic; + signal CPLLREFCLKSEL_indelay : std_logic_vector(2 downto 0); + signal CPLLRESET_indelay : std_ulogic; + signal DRPADDR_indelay : std_logic_vector(8 downto 0); + signal DRPCLK_indelay : std_ulogic; + signal DRPDI_indelay : std_logic_vector(15 downto 0); + signal DRPEN_indelay : std_ulogic; + signal DRPWE_indelay : std_ulogic; + signal EYESCANMODE_indelay : std_ulogic; + signal EYESCANRESET_indelay : std_ulogic; + signal EYESCANTRIGGER_indelay : std_ulogic; + signal GTGREFCLK_indelay : std_ulogic; + signal GTNORTHREFCLK0_indelay : std_ulogic; + signal GTNORTHREFCLK1_indelay : std_ulogic; + signal GTREFCLK0_indelay : std_ulogic; + signal GTREFCLK1_indelay : std_ulogic; + signal GTRESETSEL_indelay : std_ulogic; + signal GTRSVD_indelay : std_logic_vector(15 downto 0); + signal GTRXRESET_indelay : std_ulogic; + signal GTSOUTHREFCLK0_indelay : std_ulogic; + signal GTSOUTHREFCLK1_indelay : std_ulogic; + signal GTTXRESET_indelay : std_ulogic; + signal GTXRXN_indelay : std_ulogic; + signal GTXRXP_indelay : std_ulogic; + signal LOOPBACK_indelay : std_logic_vector(2 downto 0); + signal PCSRSVDIN2_indelay : std_logic_vector(4 downto 0); + signal PCSRSVDIN_indelay : std_logic_vector(15 downto 0); + signal PMARSVDIN2_indelay : std_logic_vector(4 downto 0); + signal PMARSVDIN_indelay : std_logic_vector(4 downto 0); + signal QPLLCLK_indelay : std_ulogic; + signal QPLLREFCLK_indelay : std_ulogic; + signal RESETOVRD_indelay : std_ulogic; + signal RX8B10BEN_indelay : std_ulogic; + signal RXBUFRESET_indelay : std_ulogic; + signal RXCDRFREQRESET_indelay : std_ulogic; + signal RXCDRHOLD_indelay : std_ulogic; + signal RXCDROVRDEN_indelay : std_ulogic; + signal RXCDRRESETRSV_indelay : std_ulogic; + signal RXCDRRESET_indelay : std_ulogic; + signal RXCHBONDEN_indelay : std_ulogic; + signal RXCHBONDI_indelay : std_logic_vector(4 downto 0); + signal RXCHBONDLEVEL_indelay : std_logic_vector(2 downto 0); + signal RXCHBONDMASTER_indelay : std_ulogic; + signal RXCHBONDSLAVE_indelay : std_ulogic; + signal RXCOMMADETEN_indelay : std_ulogic; + signal RXDDIEN_indelay : std_ulogic; + signal RXDFEAGCHOLD_indelay : std_ulogic; + signal RXDFEAGCOVRDEN_indelay : std_ulogic; + signal RXDFECM1EN_indelay : std_ulogic; + signal RXDFELFHOLD_indelay : std_ulogic; + signal RXDFELFOVRDEN_indelay : std_ulogic; + signal RXDFELPMRESET_indelay : std_ulogic; + signal RXDFETAP2HOLD_indelay : std_ulogic; + signal RXDFETAP2OVRDEN_indelay : std_ulogic; + signal RXDFETAP3HOLD_indelay : std_ulogic; + signal RXDFETAP3OVRDEN_indelay : std_ulogic; + signal RXDFETAP4HOLD_indelay : std_ulogic; + signal RXDFETAP4OVRDEN_indelay : std_ulogic; + signal RXDFETAP5HOLD_indelay : std_ulogic; + signal RXDFETAP5OVRDEN_indelay : std_ulogic; + signal RXDFEUTHOLD_indelay : std_ulogic; + signal RXDFEUTOVRDEN_indelay : std_ulogic; + signal RXDFEVPHOLD_indelay : std_ulogic; + signal RXDFEVPOVRDEN_indelay : std_ulogic; + signal RXDFEVSEN_indelay : std_ulogic; + signal RXDFEXYDEN_indelay : std_ulogic; + signal RXDFEXYDHOLD_indelay : std_ulogic; + signal RXDFEXYDOVRDEN_indelay : std_ulogic; + signal RXDLYBYPASS_indelay : std_ulogic; + signal RXDLYEN_indelay : std_ulogic; + signal RXDLYOVRDEN_indelay : std_ulogic; + signal RXDLYSRESET_indelay : std_ulogic; + signal RXELECIDLEMODE_indelay : std_logic_vector(1 downto 0); + signal RXGEARBOXSLIP_indelay : std_ulogic; + signal RXLPMEN_indelay : std_ulogic; + signal RXLPMHFHOLD_indelay : std_ulogic; + signal RXLPMHFOVRDEN_indelay : std_ulogic; + signal RXLPMLFHOLD_indelay : std_ulogic; + signal RXLPMLFKLOVRDEN_indelay : std_ulogic; + signal RXMCOMMAALIGNEN_indelay : std_ulogic; + signal RXMONITORSEL_indelay : std_logic_vector(1 downto 0); + signal RXOOBRESET_indelay : std_ulogic; + signal RXOSHOLD_indelay : std_ulogic; + signal RXOSOVRDEN_indelay : std_ulogic; + signal RXOUTCLKSEL_indelay : std_logic_vector(2 downto 0); + signal RXPCOMMAALIGNEN_indelay : std_ulogic; + signal RXPCSRESET_indelay : std_ulogic; + signal RXPD_indelay : std_logic_vector(1 downto 0); + signal RXPHALIGNEN_indelay : std_ulogic; + signal RXPHALIGN_indelay : std_ulogic; + signal RXPHDLYPD_indelay : std_ulogic; + signal RXPHDLYRESET_indelay : std_ulogic; + signal RXPHOVRDEN_indelay : std_ulogic; + signal RXPMARESET_indelay : std_ulogic; + signal RXPOLARITY_indelay : std_ulogic; + signal RXPRBSCNTRESET_indelay : std_ulogic; + signal RXPRBSSEL_indelay : std_logic_vector(2 downto 0); + signal RXQPIEN_indelay : std_ulogic; + signal RXRATE_indelay : std_logic_vector(2 downto 0); + signal RXSLIDE_indelay : std_ulogic; + signal RXSYSCLKSEL_indelay : std_logic_vector(1 downto 0); + signal RXUSERRDY_indelay : std_ulogic; + signal RXUSRCLK2_indelay : std_ulogic; + signal RXUSRCLK_indelay : std_ulogic; + signal SETERRSTATUS_indelay : std_ulogic; + signal TSTIN_indelay : std_logic_vector(19 downto 0); + signal TX8B10BBYPASS_indelay : std_logic_vector(7 downto 0); + signal TX8B10BEN_indelay : std_ulogic; + signal TXBUFDIFFCTRL_indelay : std_logic_vector(2 downto 0); + signal TXCHARDISPMODE_indelay : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_indelay : std_logic_vector(7 downto 0); + signal TXCHARISK_indelay : std_logic_vector(7 downto 0); + signal TXCOMINIT_indelay : std_ulogic; + signal TXCOMSAS_indelay : std_ulogic; + signal TXCOMWAKE_indelay : std_ulogic; + signal TXDATA_indelay : std_logic_vector(63 downto 0); + signal TXDEEMPH_indelay : std_ulogic; + signal TXDETECTRX_indelay : std_ulogic; + signal TXDIFFCTRL_indelay : std_logic_vector(3 downto 0); + signal TXDIFFPD_indelay : std_ulogic; + signal TXDLYBYPASS_indelay : std_ulogic; + signal TXDLYEN_indelay : std_ulogic; + signal TXDLYHOLD_indelay : std_ulogic; + signal TXDLYOVRDEN_indelay : std_ulogic; + signal TXDLYSRESET_indelay : std_ulogic; + signal TXDLYUPDOWN_indelay : std_ulogic; + signal TXELECIDLE_indelay : std_ulogic; + signal TXHEADER_indelay : std_logic_vector(2 downto 0); + signal TXINHIBIT_indelay : std_ulogic; + signal TXMAINCURSOR_indelay : std_logic_vector(6 downto 0); + signal TXMARGIN_indelay : std_logic_vector(2 downto 0); + signal TXOUTCLKSEL_indelay : std_logic_vector(2 downto 0); + signal TXPCSRESET_indelay : std_ulogic; + signal TXPDELECIDLEMODE_indelay : std_ulogic; + signal TXPD_indelay : std_logic_vector(1 downto 0); + signal TXPHALIGNEN_indelay : std_ulogic; + signal TXPHALIGN_indelay : std_ulogic; + signal TXPHDLYPD_indelay : std_ulogic; + signal TXPHDLYRESET_indelay : std_ulogic; + signal TXPHDLYTSTCLK_indelay : std_ulogic; + signal TXPHINIT_indelay : std_ulogic; + signal TXPHOVRDEN_indelay : std_ulogic; + signal TXPISOPD_indelay : std_ulogic; + signal TXPMARESET_indelay : std_ulogic; + signal TXPOLARITY_indelay : std_ulogic; + signal TXPOSTCURSORINV_indelay : std_ulogic; + signal TXPOSTCURSOR_indelay : std_logic_vector(4 downto 0); + signal TXPRBSFORCEERR_indelay : std_ulogic; + signal TXPRBSSEL_indelay : std_logic_vector(2 downto 0); + signal TXPRECURSORINV_indelay : std_ulogic; + signal TXPRECURSOR_indelay : std_logic_vector(4 downto 0); + signal TXQPIBIASEN_indelay : std_ulogic; + signal TXQPISTRONGPDOWN_indelay : std_ulogic; + signal TXQPIWEAKPUP_indelay : std_ulogic; + signal TXRATE_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ_indelay : std_ulogic; + signal TXSWING_indelay : std_ulogic; + signal TXSYSCLKSEL_indelay : std_logic_vector(1 downto 0); + signal TXUSERRDY_indelay : std_ulogic; + signal TXUSRCLK2_indelay : std_ulogic; + signal TXUSRCLK_indelay : std_ulogic; + + begin + GTREFCLKMONITOR_out <= GTREFCLKMONITOR_outdelay after OUTCLK_DELAY; + RXOUTCLK_out <= RXOUTCLK_outdelay after OUTCLK_DELAY; + TXOUTCLK_out <= TXOUTCLK_outdelay after OUTCLK_DELAY; + + CPLLFBCLKLOST_out <= CPLLFBCLKLOST_outdelay after OUT_DELAY; + CPLLLOCK_out <= CPLLLOCK_outdelay after OUT_DELAY; + CPLLREFCLKLOST_out <= CPLLREFCLKLOST_outdelay after OUT_DELAY; + DMONITOROUT_out <= DMONITOROUT_outdelay after OUT_DELAY; + DRPDO_out <= DRPDO_outdelay after OUT_DELAY; + DRPRDY_out <= DRPRDY_outdelay after OUT_DELAY; + EYESCANDATAERROR_out <= EYESCANDATAERROR_outdelay after OUT_DELAY; + GTXTXN_out <= GTXTXN_outdelay after OUT_DELAY; + GTXTXP_out <= GTXTXP_outdelay after OUT_DELAY; + PCSRSVDOUT_out <= PCSRSVDOUT_outdelay after OUT_DELAY; + PHYSTATUS_out <= PHYSTATUS_outdelay after OUT_DELAY; + RXBUFSTATUS_out <= RXBUFSTATUS_outdelay after OUT_DELAY; + RXBYTEISALIGNED_out <= RXBYTEISALIGNED_outdelay after OUT_DELAY; + RXBYTEREALIGN_out <= RXBYTEREALIGN_outdelay after OUT_DELAY; + RXCDRLOCK_out <= RXCDRLOCK_outdelay after OUT_DELAY; + RXCHANBONDSEQ_out <= RXCHANBONDSEQ_outdelay after OUT_DELAY; + RXCHANISALIGNED_out <= RXCHANISALIGNED_outdelay after OUT_DELAY; + RXCHANREALIGN_out <= RXCHANREALIGN_outdelay after OUT_DELAY; + RXCHARISCOMMA_out <= RXCHARISCOMMA_outdelay after OUT_DELAY; + RXCHARISK_out <= RXCHARISK_outdelay after OUT_DELAY; + RXCHBONDO_out <= RXCHBONDO_outdelay after OUT_DELAY; + RXCLKCORCNT_out <= RXCLKCORCNT_outdelay after OUT_DELAY; + RXCOMINITDET_out <= RXCOMINITDET_outdelay after OUT_DELAY; + RXCOMMADET_out <= RXCOMMADET_outdelay after OUT_DELAY; + RXCOMSASDET_out <= RXCOMSASDET_outdelay after OUT_DELAY; + RXCOMWAKEDET_out <= RXCOMWAKEDET_outdelay after OUT_DELAY; + RXDATAVALID_out <= RXDATAVALID_outdelay after OUT_DELAY; + RXDATA_out <= RXDATA_outdelay after OUT_DELAY; + RXDISPERR_out <= RXDISPERR_outdelay after OUT_DELAY; + RXDLYSRESETDONE_out <= RXDLYSRESETDONE_outdelay after OUT_DELAY; + RXELECIDLE_out <= RXELECIDLE_outdelay after OUT_DELAY; + RXHEADERVALID_out <= RXHEADERVALID_outdelay after OUT_DELAY; + RXHEADER_out <= RXHEADER_outdelay after OUT_DELAY; + RXMONITOROUT_out <= RXMONITOROUT_outdelay after OUT_DELAY; + RXNOTINTABLE_out <= RXNOTINTABLE_outdelay after OUT_DELAY; + RXOUTCLKFABRIC_out <= RXOUTCLKFABRIC_outdelay after OUT_DELAY; + RXOUTCLKPCS_out <= RXOUTCLKPCS_outdelay after OUT_DELAY; + RXPHALIGNDONE_out <= RXPHALIGNDONE_outdelay after OUT_DELAY; + RXPHMONITOR_out <= RXPHMONITOR_outdelay after OUT_DELAY; + RXPHSLIPMONITOR_out <= RXPHSLIPMONITOR_outdelay after OUT_DELAY; + RXPRBSERR_out <= RXPRBSERR_outdelay after OUT_DELAY; + RXQPISENN_out <= RXQPISENN_outdelay after OUT_DELAY; + RXQPISENP_out <= RXQPISENP_outdelay after OUT_DELAY; + RXRATEDONE_out <= RXRATEDONE_outdelay after OUT_DELAY; + RXRESETDONE_out <= RXRESETDONE_outdelay after OUT_DELAY; + RXSTARTOFSEQ_out <= RXSTARTOFSEQ_outdelay after OUT_DELAY; + RXSTATUS_out <= RXSTATUS_outdelay after OUT_DELAY; + RXVALID_out <= RXVALID_outdelay after OUT_DELAY; + TSTOUT_out <= TSTOUT_outdelay after OUT_DELAY; + TXBUFSTATUS_out <= TXBUFSTATUS_outdelay after OUT_DELAY; + TXCOMFINISH_out <= TXCOMFINISH_outdelay after OUT_DELAY; + TXDLYSRESETDONE_out <= TXDLYSRESETDONE_outdelay after OUT_DELAY; + TXGEARBOXREADY_out <= TXGEARBOXREADY_outdelay after OUT_DELAY; + TXOUTCLKFABRIC_out <= TXOUTCLKFABRIC_outdelay after OUT_DELAY; + TXOUTCLKPCS_out <= TXOUTCLKPCS_outdelay after OUT_DELAY; + TXPHALIGNDONE_out <= TXPHALIGNDONE_outdelay after OUT_DELAY; + TXPHINITDONE_out <= TXPHINITDONE_outdelay after OUT_DELAY; + TXQPISENN_out <= TXQPISENN_outdelay after OUT_DELAY; + TXQPISENP_out <= TXQPISENP_outdelay after OUT_DELAY; + TXRATEDONE_out <= TXRATEDONE_outdelay after OUT_DELAY; + TXRESETDONE_out <= TXRESETDONE_outdelay after OUT_DELAY; + + CPLLLOCKDETCLK_ipd <= CPLLLOCKDETCLK; + DRPCLK_ipd <= DRPCLK; + GTGREFCLK_ipd <= GTGREFCLK; + GTNORTHREFCLK0_ipd <= GTNORTHREFCLK0; + GTNORTHREFCLK1_ipd <= GTNORTHREFCLK1; + GTREFCLK0_ipd <= GTREFCLK0; + GTREFCLK1_ipd <= GTREFCLK1; + GTSOUTHREFCLK0_ipd <= GTSOUTHREFCLK0; + GTSOUTHREFCLK1_ipd <= GTSOUTHREFCLK1; + QPLLCLK_ipd <= QPLLCLK; + RXUSRCLK2_ipd <= RXUSRCLK2; + RXUSRCLK_ipd <= RXUSRCLK; + TXPHDLYTSTCLK_ipd <= TXPHDLYTSTCLK; + TXUSRCLK2_ipd <= TXUSRCLK2; + TXUSRCLK_ipd <= TXUSRCLK; + + CFGRESET_ipd <= CFGRESET; + CLKRSVD_ipd <= CLKRSVD; + CPLLLOCKEN_ipd <= CPLLLOCKEN; + CPLLPD_ipd <= CPLLPD; + CPLLREFCLKSEL_ipd <= CPLLREFCLKSEL; + CPLLRESET_ipd <= CPLLRESET; + DRPADDR_ipd <= DRPADDR; + DRPDI_ipd <= DRPDI; + DRPEN_ipd <= DRPEN; + DRPWE_ipd <= DRPWE; + EYESCANMODE_ipd <= EYESCANMODE; + EYESCANRESET_ipd <= EYESCANRESET; + EYESCANTRIGGER_ipd <= EYESCANTRIGGER; + GTRESETSEL_ipd <= GTRESETSEL; + GTRSVD_ipd <= GTRSVD; + GTRXRESET_ipd <= GTRXRESET; + GTTXRESET_ipd <= GTTXRESET; + GTXRXN_ipd <= GTXRXN; + GTXRXP_ipd <= GTXRXP; + LOOPBACK_ipd <= LOOPBACK; + PCSRSVDIN2_ipd <= PCSRSVDIN2; + PCSRSVDIN_ipd <= PCSRSVDIN; + PMARSVDIN2_ipd <= PMARSVDIN2; + PMARSVDIN_ipd <= PMARSVDIN; + QPLLREFCLK_ipd <= QPLLREFCLK; + RESETOVRD_ipd <= RESETOVRD; + RX8B10BEN_ipd <= RX8B10BEN; + RXBUFRESET_ipd <= RXBUFRESET; + RXCDRFREQRESET_ipd <= RXCDRFREQRESET; + RXCDRHOLD_ipd <= RXCDRHOLD; + RXCDROVRDEN_ipd <= RXCDROVRDEN; + RXCDRRESETRSV_ipd <= RXCDRRESETRSV; + RXCDRRESET_ipd <= RXCDRRESET; + RXCHBONDEN_ipd <= RXCHBONDEN; + RXCHBONDI_ipd <= RXCHBONDI; + RXCHBONDLEVEL_ipd <= RXCHBONDLEVEL; + RXCHBONDMASTER_ipd <= RXCHBONDMASTER; + RXCHBONDSLAVE_ipd <= RXCHBONDSLAVE; + RXCOMMADETEN_ipd <= RXCOMMADETEN; + RXDDIEN_ipd <= RXDDIEN; + RXDFEAGCHOLD_ipd <= RXDFEAGCHOLD; + RXDFEAGCOVRDEN_ipd <= RXDFEAGCOVRDEN; + RXDFECM1EN_ipd <= RXDFECM1EN; + RXDFELFHOLD_ipd <= RXDFELFHOLD; + RXDFELFOVRDEN_ipd <= RXDFELFOVRDEN; + RXDFELPMRESET_ipd <= RXDFELPMRESET; + RXDFETAP2HOLD_ipd <= RXDFETAP2HOLD; + RXDFETAP2OVRDEN_ipd <= RXDFETAP2OVRDEN; + RXDFETAP3HOLD_ipd <= RXDFETAP3HOLD; + RXDFETAP3OVRDEN_ipd <= RXDFETAP3OVRDEN; + RXDFETAP4HOLD_ipd <= RXDFETAP4HOLD; + RXDFETAP4OVRDEN_ipd <= RXDFETAP4OVRDEN; + RXDFETAP5HOLD_ipd <= RXDFETAP5HOLD; + RXDFETAP5OVRDEN_ipd <= RXDFETAP5OVRDEN; + RXDFEUTHOLD_ipd <= RXDFEUTHOLD; + RXDFEUTOVRDEN_ipd <= RXDFEUTOVRDEN; + RXDFEVPHOLD_ipd <= RXDFEVPHOLD; + RXDFEVPOVRDEN_ipd <= RXDFEVPOVRDEN; + RXDFEVSEN_ipd <= RXDFEVSEN; + RXDFEXYDEN_ipd <= RXDFEXYDEN; + RXDFEXYDHOLD_ipd <= RXDFEXYDHOLD; + RXDFEXYDOVRDEN_ipd <= RXDFEXYDOVRDEN; + RXDLYBYPASS_ipd <= RXDLYBYPASS; + RXDLYEN_ipd <= RXDLYEN; + RXDLYOVRDEN_ipd <= RXDLYOVRDEN; + RXDLYSRESET_ipd <= RXDLYSRESET; + RXELECIDLEMODE_ipd <= RXELECIDLEMODE; + RXGEARBOXSLIP_ipd <= RXGEARBOXSLIP; + RXLPMEN_ipd <= RXLPMEN; + RXLPMHFHOLD_ipd <= RXLPMHFHOLD; + RXLPMHFOVRDEN_ipd <= RXLPMHFOVRDEN; + RXLPMLFHOLD_ipd <= RXLPMLFHOLD; + RXLPMLFKLOVRDEN_ipd <= RXLPMLFKLOVRDEN; + RXMCOMMAALIGNEN_ipd <= RXMCOMMAALIGNEN; + RXMONITORSEL_ipd <= RXMONITORSEL; + RXOOBRESET_ipd <= RXOOBRESET; + RXOSHOLD_ipd <= RXOSHOLD; + RXOSOVRDEN_ipd <= RXOSOVRDEN; + RXOUTCLKSEL_ipd <= RXOUTCLKSEL; + RXPCOMMAALIGNEN_ipd <= RXPCOMMAALIGNEN; + RXPCSRESET_ipd <= RXPCSRESET; + RXPD_ipd <= RXPD; + RXPHALIGNEN_ipd <= RXPHALIGNEN; + RXPHALIGN_ipd <= RXPHALIGN; + RXPHDLYPD_ipd <= RXPHDLYPD; + RXPHDLYRESET_ipd <= RXPHDLYRESET; + RXPHOVRDEN_ipd <= RXPHOVRDEN; + RXPMARESET_ipd <= RXPMARESET; + RXPOLARITY_ipd <= RXPOLARITY; + RXPRBSCNTRESET_ipd <= RXPRBSCNTRESET; + RXPRBSSEL_ipd <= RXPRBSSEL; + RXQPIEN_ipd <= RXQPIEN; + RXRATE_ipd <= RXRATE; + RXSLIDE_ipd <= RXSLIDE; + RXSYSCLKSEL_ipd <= RXSYSCLKSEL; + RXUSERRDY_ipd <= RXUSERRDY; + SETERRSTATUS_ipd <= SETERRSTATUS; + TSTIN_ipd <= TSTIN; + TX8B10BBYPASS_ipd <= TX8B10BBYPASS; + TX8B10BEN_ipd <= TX8B10BEN; + TXBUFDIFFCTRL_ipd <= TXBUFDIFFCTRL; + TXCHARDISPMODE_ipd <= TXCHARDISPMODE; + TXCHARDISPVAL_ipd <= TXCHARDISPVAL; + TXCHARISK_ipd <= TXCHARISK; + TXCOMINIT_ipd <= TXCOMINIT; + TXCOMSAS_ipd <= TXCOMSAS; + TXCOMWAKE_ipd <= TXCOMWAKE; + TXDATA_ipd <= TXDATA; + TXDEEMPH_ipd <= TXDEEMPH; + TXDETECTRX_ipd <= TXDETECTRX; + TXDIFFCTRL_ipd <= TXDIFFCTRL; + TXDIFFPD_ipd <= TXDIFFPD; + TXDLYBYPASS_ipd <= TXDLYBYPASS; + TXDLYEN_ipd <= TXDLYEN; + TXDLYHOLD_ipd <= TXDLYHOLD; + TXDLYOVRDEN_ipd <= TXDLYOVRDEN; + TXDLYSRESET_ipd <= TXDLYSRESET; + TXDLYUPDOWN_ipd <= TXDLYUPDOWN; + TXELECIDLE_ipd <= TXELECIDLE; + TXHEADER_ipd <= TXHEADER; + TXINHIBIT_ipd <= TXINHIBIT; + TXMAINCURSOR_ipd <= TXMAINCURSOR; + TXMARGIN_ipd <= TXMARGIN; + TXOUTCLKSEL_ipd <= TXOUTCLKSEL; + TXPCSRESET_ipd <= TXPCSRESET; + TXPDELECIDLEMODE_ipd <= TXPDELECIDLEMODE; + TXPD_ipd <= TXPD; + TXPHALIGNEN_ipd <= TXPHALIGNEN; + TXPHALIGN_ipd <= TXPHALIGN; + TXPHDLYPD_ipd <= TXPHDLYPD; + TXPHDLYRESET_ipd <= TXPHDLYRESET; + TXPHINIT_ipd <= TXPHINIT; + TXPHOVRDEN_ipd <= TXPHOVRDEN; + TXPISOPD_ipd <= TXPISOPD; + TXPMARESET_ipd <= TXPMARESET; + TXPOLARITY_ipd <= TXPOLARITY; + TXPOSTCURSORINV_ipd <= TXPOSTCURSORINV; + TXPOSTCURSOR_ipd <= TXPOSTCURSOR; + TXPRBSFORCEERR_ipd <= TXPRBSFORCEERR; + TXPRBSSEL_ipd <= TXPRBSSEL; + TXPRECURSORINV_ipd <= TXPRECURSORINV; + TXPRECURSOR_ipd <= TXPRECURSOR; + TXQPIBIASEN_ipd <= TXQPIBIASEN; + TXQPISTRONGPDOWN_ipd <= TXQPISTRONGPDOWN; + TXQPIWEAKPUP_ipd <= TXQPIWEAKPUP; + TXRATE_ipd <= TXRATE; + TXSEQUENCE_ipd <= TXSEQUENCE; + TXSTARTSEQ_ipd <= TXSTARTSEQ; + TXSWING_ipd <= TXSWING; + TXSYSCLKSEL_ipd <= TXSYSCLKSEL; + TXUSERRDY_ipd <= TXUSERRDY; + + CPLLLOCKDETCLK_indelay <= CPLLLOCKDETCLK_ipd xor IS_CPLLLOCKDETCLK_INVERTED_BIN; + DRPCLK_indelay <= DRPCLK_ipd xor IS_DRPCLK_INVERTED_BIN; + GTGREFCLK_indelay <= GTGREFCLK_ipd xor IS_GTGREFCLK_INVERTED_BIN; + GTNORTHREFCLK0_indelay <= GTNORTHREFCLK0_ipd after INCLK_DELAY; + GTNORTHREFCLK1_indelay <= GTNORTHREFCLK1_ipd after INCLK_DELAY; + GTREFCLK0_indelay <= GTREFCLK0_ipd after INCLK_DELAY; + GTREFCLK1_indelay <= GTREFCLK1_ipd after INCLK_DELAY; + GTSOUTHREFCLK0_indelay <= GTSOUTHREFCLK0_ipd after INCLK_DELAY; + GTSOUTHREFCLK1_indelay <= GTSOUTHREFCLK1_ipd after INCLK_DELAY; + QPLLCLK_indelay <= QPLLCLK_ipd after INCLK_DELAY; + RXUSRCLK2_indelay <= RXUSRCLK2_ipd xor IS_RXUSRCLK2_INVERTED_BIN; + RXUSRCLK_indelay <= RXUSRCLK_ipd xor IS_RXUSRCLK_INVERTED_BIN; + TXPHDLYTSTCLK_indelay <= TXPHDLYTSTCLK_ipd xor IS_TXPHDLYTSTCLK_INVERTED_BIN; + TXUSRCLK2_indelay <= TXUSRCLK2_ipd xor IS_TXUSRCLK2_INVERTED_BIN; + TXUSRCLK_indelay <= TXUSRCLK_ipd xor IS_TXUSRCLK2_INVERTED_BIN; + + CFGRESET_indelay <= CFGRESET_ipd after IN_DELAY; + CLKRSVD_indelay <= CLKRSVD_ipd after IN_DELAY; + CPLLLOCKEN_indelay <= CPLLLOCKEN_ipd after IN_DELAY; + CPLLPD_indelay <= CPLLPD_ipd after IN_DELAY; + CPLLREFCLKSEL_indelay <= CPLLREFCLKSEL_ipd after IN_DELAY; + CPLLRESET_indelay <= CPLLRESET_ipd after IN_DELAY; + DRPADDR_indelay <= DRPADDR_ipd after IN_DELAY; + DRPDI_indelay <= DRPDI_ipd after IN_DELAY; + DRPEN_indelay <= DRPEN_ipd after IN_DELAY; + DRPWE_indelay <= DRPWE_ipd after IN_DELAY; + EYESCANMODE_indelay <= EYESCANMODE_ipd after IN_DELAY; + EYESCANRESET_indelay <= EYESCANRESET_ipd after IN_DELAY; + EYESCANTRIGGER_indelay <= EYESCANTRIGGER_ipd after IN_DELAY; + GTRESETSEL_indelay <= GTRESETSEL_ipd after IN_DELAY; + GTRSVD_indelay <= GTRSVD_ipd after IN_DELAY; + GTRXRESET_indelay <= GTRXRESET_ipd after IN_DELAY; + GTTXRESET_indelay <= GTTXRESET_ipd after IN_DELAY; + GTXRXN_indelay <= GTXRXN_ipd after IN_DELAY; + GTXRXP_indelay <= GTXRXP_ipd after IN_DELAY; + LOOPBACK_indelay <= LOOPBACK_ipd after IN_DELAY; + PCSRSVDIN2_indelay <= PCSRSVDIN2_ipd after IN_DELAY; + PCSRSVDIN_indelay <= PCSRSVDIN_ipd after IN_DELAY; + PMARSVDIN2_indelay <= PMARSVDIN2_ipd after IN_DELAY; + PMARSVDIN_indelay <= PMARSVDIN_ipd after IN_DELAY; + QPLLREFCLK_indelay <= QPLLREFCLK_ipd after IN_DELAY; + RESETOVRD_indelay <= RESETOVRD_ipd after IN_DELAY; + RX8B10BEN_indelay <= RX8B10BEN_ipd after IN_DELAY; + RXBUFRESET_indelay <= RXBUFRESET_ipd after IN_DELAY; + RXCDRFREQRESET_indelay <= RXCDRFREQRESET_ipd after IN_DELAY; + RXCDRHOLD_indelay <= RXCDRHOLD_ipd after IN_DELAY; + RXCDROVRDEN_indelay <= RXCDROVRDEN_ipd after IN_DELAY; + RXCDRRESETRSV_indelay <= RXCDRRESETRSV_ipd after IN_DELAY; + RXCDRRESET_indelay <= RXCDRRESET_ipd after IN_DELAY; + RXCHBONDEN_indelay <= RXCHBONDEN_ipd after IN_DELAY; + RXCHBONDI_indelay <= RXCHBONDI_ipd after IN_DELAY; + RXCHBONDLEVEL_indelay <= RXCHBONDLEVEL_ipd after IN_DELAY; + RXCHBONDMASTER_indelay <= RXCHBONDMASTER_ipd after IN_DELAY; + RXCHBONDSLAVE_indelay <= RXCHBONDSLAVE_ipd after IN_DELAY; + RXCOMMADETEN_indelay <= RXCOMMADETEN_ipd after IN_DELAY; + RXDDIEN_indelay <= RXDDIEN_ipd after IN_DELAY; + RXDFEAGCHOLD_indelay <= RXDFEAGCHOLD_ipd after IN_DELAY; + RXDFEAGCOVRDEN_indelay <= RXDFEAGCOVRDEN_ipd after IN_DELAY; + RXDFECM1EN_indelay <= RXDFECM1EN_ipd after IN_DELAY; + RXDFELFHOLD_indelay <= RXDFELFHOLD_ipd after IN_DELAY; + RXDFELFOVRDEN_indelay <= RXDFELFOVRDEN_ipd after IN_DELAY; + RXDFELPMRESET_indelay <= RXDFELPMRESET_ipd after IN_DELAY; + RXDFETAP2HOLD_indelay <= RXDFETAP2HOLD_ipd after IN_DELAY; + RXDFETAP2OVRDEN_indelay <= RXDFETAP2OVRDEN_ipd after IN_DELAY; + RXDFETAP3HOLD_indelay <= RXDFETAP3HOLD_ipd after IN_DELAY; + RXDFETAP3OVRDEN_indelay <= RXDFETAP3OVRDEN_ipd after IN_DELAY; + RXDFETAP4HOLD_indelay <= RXDFETAP4HOLD_ipd after IN_DELAY; + RXDFETAP4OVRDEN_indelay <= RXDFETAP4OVRDEN_ipd after IN_DELAY; + RXDFETAP5HOLD_indelay <= RXDFETAP5HOLD_ipd after IN_DELAY; + RXDFETAP5OVRDEN_indelay <= RXDFETAP5OVRDEN_ipd after IN_DELAY; + RXDFEUTHOLD_indelay <= RXDFEUTHOLD_ipd after IN_DELAY; + RXDFEUTOVRDEN_indelay <= RXDFEUTOVRDEN_ipd after IN_DELAY; + RXDFEVPHOLD_indelay <= RXDFEVPHOLD_ipd after IN_DELAY; + RXDFEVPOVRDEN_indelay <= RXDFEVPOVRDEN_ipd after IN_DELAY; + RXDFEVSEN_indelay <= RXDFEVSEN_ipd after IN_DELAY; + RXDFEXYDEN_indelay <= RXDFEXYDEN_ipd after IN_DELAY; + RXDFEXYDHOLD_indelay <= RXDFEXYDHOLD_ipd after IN_DELAY; + RXDFEXYDOVRDEN_indelay <= RXDFEXYDOVRDEN_ipd after IN_DELAY; + RXDLYBYPASS_indelay <= RXDLYBYPASS_ipd after IN_DELAY; + RXDLYEN_indelay <= RXDLYEN_ipd after IN_DELAY; + RXDLYOVRDEN_indelay <= RXDLYOVRDEN_ipd after IN_DELAY; + RXDLYSRESET_indelay <= RXDLYSRESET_ipd after IN_DELAY; + RXELECIDLEMODE_indelay <= RXELECIDLEMODE_ipd after IN_DELAY; + RXGEARBOXSLIP_indelay <= RXGEARBOXSLIP_ipd after IN_DELAY; + RXLPMEN_indelay <= RXLPMEN_ipd after IN_DELAY; + RXLPMHFHOLD_indelay <= RXLPMHFHOLD_ipd after IN_DELAY; + RXLPMHFOVRDEN_indelay <= RXLPMHFOVRDEN_ipd after IN_DELAY; + RXLPMLFHOLD_indelay <= RXLPMLFHOLD_ipd after IN_DELAY; + RXLPMLFKLOVRDEN_indelay <= RXLPMLFKLOVRDEN_ipd after IN_DELAY; + RXMCOMMAALIGNEN_indelay <= RXMCOMMAALIGNEN_ipd after IN_DELAY; + RXMONITORSEL_indelay <= RXMONITORSEL_ipd after IN_DELAY; + RXOOBRESET_indelay <= RXOOBRESET_ipd after IN_DELAY; + RXOSHOLD_indelay <= RXOSHOLD_ipd after IN_DELAY; + RXOSOVRDEN_indelay <= RXOSOVRDEN_ipd after IN_DELAY; + RXOUTCLKSEL_indelay <= RXOUTCLKSEL_ipd after IN_DELAY; + RXPCOMMAALIGNEN_indelay <= RXPCOMMAALIGNEN_ipd after IN_DELAY; + RXPCSRESET_indelay <= RXPCSRESET_ipd after IN_DELAY; + RXPD_indelay <= RXPD_ipd after IN_DELAY; + RXPHALIGNEN_indelay <= RXPHALIGNEN_ipd after IN_DELAY; + RXPHALIGN_indelay <= RXPHALIGN_ipd after IN_DELAY; + RXPHDLYPD_indelay <= RXPHDLYPD_ipd after IN_DELAY; + RXPHDLYRESET_indelay <= RXPHDLYRESET_ipd after IN_DELAY; + RXPHOVRDEN_indelay <= RXPHOVRDEN_ipd after IN_DELAY; + RXPMARESET_indelay <= RXPMARESET_ipd after IN_DELAY; + RXPOLARITY_indelay <= RXPOLARITY_ipd after IN_DELAY; + RXPRBSCNTRESET_indelay <= RXPRBSCNTRESET_ipd after IN_DELAY; + RXPRBSSEL_indelay <= RXPRBSSEL_ipd after IN_DELAY; + RXQPIEN_indelay <= RXQPIEN_ipd after IN_DELAY; + RXRATE_indelay <= RXRATE_ipd after IN_DELAY; + RXSLIDE_indelay <= RXSLIDE_ipd after IN_DELAY; + RXSYSCLKSEL_indelay <= RXSYSCLKSEL_ipd after IN_DELAY; + RXUSERRDY_indelay <= RXUSERRDY_ipd after IN_DELAY; + SETERRSTATUS_indelay <= SETERRSTATUS_ipd after IN_DELAY; + TSTIN_indelay <= TSTIN_ipd after IN_DELAY; + TX8B10BBYPASS_indelay <= TX8B10BBYPASS_ipd after IN_DELAY; + TX8B10BEN_indelay <= TX8B10BEN_ipd after IN_DELAY; + TXBUFDIFFCTRL_indelay <= TXBUFDIFFCTRL_ipd after IN_DELAY; + TXCHARDISPMODE_indelay <= TXCHARDISPMODE_ipd after IN_DELAY; + TXCHARDISPVAL_indelay <= TXCHARDISPVAL_ipd after IN_DELAY; + TXCHARISK_indelay <= TXCHARISK_ipd after IN_DELAY; + TXCOMINIT_indelay <= TXCOMINIT_ipd after IN_DELAY; + TXCOMSAS_indelay <= TXCOMSAS_ipd after IN_DELAY; + TXCOMWAKE_indelay <= TXCOMWAKE_ipd after IN_DELAY; + TXDATA_indelay <= TXDATA_ipd after IN_DELAY; + TXDEEMPH_indelay <= TXDEEMPH_ipd after IN_DELAY; + TXDETECTRX_indelay <= TXDETECTRX_ipd after IN_DELAY; + TXDIFFCTRL_indelay <= TXDIFFCTRL_ipd after IN_DELAY; + TXDIFFPD_indelay <= TXDIFFPD_ipd after IN_DELAY; + TXDLYBYPASS_indelay <= TXDLYBYPASS_ipd after IN_DELAY; + TXDLYEN_indelay <= TXDLYEN_ipd after IN_DELAY; + TXDLYHOLD_indelay <= TXDLYHOLD_ipd after IN_DELAY; + TXDLYOVRDEN_indelay <= TXDLYOVRDEN_ipd after IN_DELAY; + TXDLYSRESET_indelay <= TXDLYSRESET_ipd after IN_DELAY; + TXDLYUPDOWN_indelay <= TXDLYUPDOWN_ipd after IN_DELAY; + TXELECIDLE_indelay <= TXELECIDLE_ipd after IN_DELAY; + TXHEADER_indelay <= TXHEADER_ipd after IN_DELAY; + TXINHIBIT_indelay <= TXINHIBIT_ipd after IN_DELAY; + TXMAINCURSOR_indelay <= TXMAINCURSOR_ipd after IN_DELAY; + TXMARGIN_indelay <= TXMARGIN_ipd after IN_DELAY; + TXOUTCLKSEL_indelay <= TXOUTCLKSEL_ipd after IN_DELAY; + TXPCSRESET_indelay <= TXPCSRESET_ipd after IN_DELAY; + TXPDELECIDLEMODE_indelay <= TXPDELECIDLEMODE_ipd after IN_DELAY; + TXPD_indelay <= TXPD_ipd after IN_DELAY; + TXPHALIGNEN_indelay <= TXPHALIGNEN_ipd after IN_DELAY; + TXPHALIGN_indelay <= TXPHALIGN_ipd after IN_DELAY; + TXPHDLYPD_indelay <= TXPHDLYPD_ipd after IN_DELAY; + TXPHDLYRESET_indelay <= TXPHDLYRESET_ipd after IN_DELAY; + TXPHINIT_indelay <= TXPHINIT_ipd after IN_DELAY; + TXPHOVRDEN_indelay <= TXPHOVRDEN_ipd after IN_DELAY; + TXPISOPD_indelay <= TXPISOPD_ipd after IN_DELAY; + TXPMARESET_indelay <= TXPMARESET_ipd after IN_DELAY; + TXPOLARITY_indelay <= TXPOLARITY_ipd after IN_DELAY; + TXPOSTCURSORINV_indelay <= TXPOSTCURSORINV_ipd after IN_DELAY; + TXPOSTCURSOR_indelay <= TXPOSTCURSOR_ipd after IN_DELAY; + TXPRBSFORCEERR_indelay <= TXPRBSFORCEERR_ipd after IN_DELAY; + TXPRBSSEL_indelay <= TXPRBSSEL_ipd after IN_DELAY; + TXPRECURSORINV_indelay <= TXPRECURSORINV_ipd after IN_DELAY; + TXPRECURSOR_indelay <= TXPRECURSOR_ipd after IN_DELAY; + TXQPIBIASEN_indelay <= TXQPIBIASEN_ipd after IN_DELAY; + TXQPISTRONGPDOWN_indelay <= TXQPISTRONGPDOWN_ipd after IN_DELAY; + TXQPIWEAKPUP_indelay <= TXQPIWEAKPUP_ipd after IN_DELAY; + TXRATE_indelay <= TXRATE_ipd after IN_DELAY; + TXSEQUENCE_indelay <= TXSEQUENCE_ipd after IN_DELAY; + TXSTARTSEQ_indelay <= TXSTARTSEQ_ipd after IN_DELAY; + TXSWING_indelay <= TXSWING_ipd after IN_DELAY; + TXSYSCLKSEL_indelay <= TXSYSCLKSEL_ipd after IN_DELAY; + TXUSERRDY_indelay <= TXUSERRDY_ipd after IN_DELAY; + + + IS_CPLLLOCKDETCLK_INVERTED_BIN <= TO_X01(IS_CPLLLOCKDETCLK_INVERTED); + IS_DRPCLK_INVERTED_BIN <= TO_X01(IS_DRPCLK_INVERTED); + IS_GTGREFCLK_INVERTED_BIN <= TO_X01(IS_GTGREFCLK_INVERTED); + IS_RXUSRCLK2_INVERTED_BIN <= TO_X01(IS_RXUSRCLK2_INVERTED); + IS_RXUSRCLK_INVERTED_BIN <= TO_X01(IS_RXUSRCLK_INVERTED); + IS_TXPHDLYTSTCLK_INVERTED_BIN <= TO_X01(IS_TXPHDLYTSTCLK_INVERTED); + IS_TXUSRCLK2_INVERTED_BIN <= TO_X01(IS_TXUSRCLK2_INVERTED); + IS_TXUSRCLK_INVERTED_BIN <= TO_X01(IS_TXUSRCLK_INVERTED); + + GTXE2_CHANNEL_INST : GTXE2_CHANNEL_FAST_WRAP + generic map ( + ALIGN_COMMA_DOUBLE => ALIGN_COMMA_DOUBLE, + ALIGN_COMMA_ENABLE => ALIGN_COMMA_ENABLE_STRING, + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + ALIGN_MCOMMA_DET => ALIGN_MCOMMA_DET, + ALIGN_MCOMMA_VALUE => ALIGN_MCOMMA_VALUE_STRING, + ALIGN_PCOMMA_DET => ALIGN_PCOMMA_DET, + ALIGN_PCOMMA_VALUE => ALIGN_PCOMMA_VALUE_STRING, + CBCC_DATA_SOURCE_SEL => CBCC_DATA_SOURCE_SEL, + CHAN_BOND_KEEP_ALIGN => CHAN_BOND_KEEP_ALIGN, + CHAN_BOND_MAX_SKEW => CHAN_BOND_MAX_SKEW, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_STRING, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_STRING, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_STRING, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_STRING, + CHAN_BOND_SEQ_1_ENABLE => CHAN_BOND_SEQ_1_ENABLE_STRING, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_STRING, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_STRING, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_STRING, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_STRING, + CHAN_BOND_SEQ_2_ENABLE => CHAN_BOND_SEQ_2_ENABLE_STRING, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_PRECEDENCE => CLK_COR_PRECEDENCE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_STRING, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_STRING, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_STRING, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_STRING, + CLK_COR_SEQ_1_ENABLE => CLK_COR_SEQ_1_ENABLE_STRING, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_STRING, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_STRING, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_STRING, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_STRING, + CLK_COR_SEQ_2_ENABLE => CLK_COR_SEQ_2_ENABLE_STRING, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CPLL_CFG => CPLL_CFG_STRING, + CPLL_FBDIV => CPLL_FBDIV, + CPLL_FBDIV_45 => CPLL_FBDIV_45, + CPLL_INIT_CFG => CPLL_INIT_CFG_STRING, + CPLL_LOCK_CFG => CPLL_LOCK_CFG_STRING, + CPLL_REFCLK_DIV => CPLL_REFCLK_DIV, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + DMONITOR_CFG => DMONITOR_CFG_STRING, + ES_CONTROL => ES_CONTROL_STRING, + ES_ERRDET_EN => ES_ERRDET_EN, + ES_EYE_SCAN_EN => ES_EYE_SCAN_EN, + ES_HORZ_OFFSET => ES_HORZ_OFFSET_STRING, + ES_PMA_CFG => ES_PMA_CFG_STRING, + ES_PRESCALE => ES_PRESCALE_STRING, + ES_QUALIFIER => ES_QUALIFIER_STRING, + ES_QUAL_MASK => ES_QUAL_MASK_STRING, + ES_SDATA_MASK => ES_SDATA_MASK_STRING, + ES_VERT_OFFSET => ES_VERT_OFFSET_STRING, + FTS_DESKEW_SEQ_ENABLE => FTS_DESKEW_SEQ_ENABLE_STRING, + FTS_LANE_DESKEW_CFG => FTS_LANE_DESKEW_CFG_STRING, + FTS_LANE_DESKEW_EN => FTS_LANE_DESKEW_EN, + GEARBOX_MODE => GEARBOX_MODE_STRING, + OUTREFCLK_SEL_INV => OUTREFCLK_SEL_INV_STRING, + PCS_PCIE_EN => PCS_PCIE_EN, + PCS_RSVD_ATTR => PCS_RSVD_ATTR_STRING, + PD_TRANS_TIME_FROM_P2 => PD_TRANS_TIME_FROM_P2_STRING, + PD_TRANS_TIME_NONE_P2 => PD_TRANS_TIME_NONE_P2_STRING, + PD_TRANS_TIME_TO_P2 => PD_TRANS_TIME_TO_P2_STRING, + PMA_RSV => PMA_RSV_STRING, + PMA_RSV2 => PMA_RSV2_STRING, + PMA_RSV3 => PMA_RSV3_STRING, + PMA_RSV4 => PMA_RSV4_STRING, + RXBUFRESET_TIME => RXBUFRESET_TIME_STRING, + RXBUF_ADDR_MODE => RXBUF_ADDR_MODE, + RXBUF_EIDLE_HI_CNT => RXBUF_EIDLE_HI_CNT_STRING, + RXBUF_EIDLE_LO_CNT => RXBUF_EIDLE_LO_CNT_STRING, + RXBUF_EN => RXBUF_EN, + RXBUF_RESET_ON_CB_CHANGE => RXBUF_RESET_ON_CB_CHANGE, + RXBUF_RESET_ON_COMMAALIGN => RXBUF_RESET_ON_COMMAALIGN, + RXBUF_RESET_ON_EIDLE => RXBUF_RESET_ON_EIDLE, + RXBUF_RESET_ON_RATE_CHANGE => RXBUF_RESET_ON_RATE_CHANGE, + RXBUF_THRESH_OVFLW => RXBUF_THRESH_OVFLW, + RXBUF_THRESH_OVRD => RXBUF_THRESH_OVRD, + RXBUF_THRESH_UNDFLW => RXBUF_THRESH_UNDFLW, + RXCDRFREQRESET_TIME => RXCDRFREQRESET_TIME_STRING, + RXCDRPHRESET_TIME => RXCDRPHRESET_TIME_STRING, + RXCDR_CFG => RXCDR_CFG_STRING, + RXCDR_FR_RESET_ON_EIDLE => RXCDR_FR_RESET_ON_EIDLE_STRING, + RXCDR_HOLD_DURING_EIDLE => RXCDR_HOLD_DURING_EIDLE_STRING, + RXCDR_LOCK_CFG => RXCDR_LOCK_CFG_STRING, + RXCDR_PH_RESET_ON_EIDLE => RXCDR_PH_RESET_ON_EIDLE_STRING, + RXDFELPMRESET_TIME => RXDFELPMRESET_TIME_STRING, + RXDLY_CFG => RXDLY_CFG_STRING, + RXDLY_LCFG => RXDLY_LCFG_STRING, + RXDLY_TAP_CFG => RXDLY_TAP_CFG_STRING, + RXGEARBOX_EN => RXGEARBOX_EN, + RXISCANRESET_TIME => RXISCANRESET_TIME_STRING, + RXLPM_HF_CFG => RXLPM_HF_CFG_STRING, + RXLPM_LF_CFG => RXLPM_LF_CFG_STRING, + RXOOB_CFG => RXOOB_CFG_STRING, + RXOUT_DIV => RXOUT_DIV, + RXPCSRESET_TIME => RXPCSRESET_TIME_STRING, + RXPHDLY_CFG => RXPHDLY_CFG_STRING, + RXPH_CFG => RXPH_CFG_STRING, + RXPH_MONITOR_SEL => RXPH_MONITOR_SEL_STRING, + RXPMARESET_TIME => RXPMARESET_TIME_STRING, + RXPRBS_ERR_LOOPBACK => RXPRBS_ERR_LOOPBACK_STRING, + RXSLIDE_AUTO_WAIT => RXSLIDE_AUTO_WAIT, + RXSLIDE_MODE => RXSLIDE_MODE, + RX_BIAS_CFG => RX_BIAS_CFG_STRING, + RX_BUFFER_CFG => RX_BUFFER_CFG_STRING, + RX_CLK25_DIV => RX_CLK25_DIV, + RX_CLKMUX_PD => RX_CLKMUX_PD_STRING, + RX_CM_SEL => RX_CM_SEL_STRING, + RX_CM_TRIM => RX_CM_TRIM_STRING, + RX_DATA_WIDTH => RX_DATA_WIDTH, + RX_DDI_SEL => RX_DDI_SEL_STRING, + RX_DEBUG_CFG => RX_DEBUG_CFG_STRING, + RX_DEFER_RESET_BUF_EN => RX_DEFER_RESET_BUF_EN, + RX_DFE_GAIN_CFG => RX_DFE_GAIN_CFG_STRING, + RX_DFE_H2_CFG => RX_DFE_H2_CFG_STRING, + RX_DFE_H3_CFG => RX_DFE_H3_CFG_STRING, + RX_DFE_H4_CFG => RX_DFE_H4_CFG_STRING, + RX_DFE_H5_CFG => RX_DFE_H5_CFG_STRING, + RX_DFE_KL_CFG => RX_DFE_KL_CFG_STRING, + RX_DFE_KL_CFG2 => RX_DFE_KL_CFG2_STRING, + RX_DFE_LPM_CFG => RX_DFE_LPM_CFG_STRING, + RX_DFE_LPM_HOLD_DURING_EIDLE => RX_DFE_LPM_HOLD_DURING_EIDLE_STRING, + RX_DFE_UT_CFG => RX_DFE_UT_CFG_STRING, + RX_DFE_VP_CFG => RX_DFE_VP_CFG_STRING, + RX_DFE_XYD_CFG => RX_DFE_XYD_CFG_STRING, + RX_DISPERR_SEQ_MATCH => RX_DISPERR_SEQ_MATCH, + RX_INT_DATAWIDTH => RX_INT_DATAWIDTH, + RX_OS_CFG => RX_OS_CFG_STRING, + RX_SIG_VALID_DLY => RX_SIG_VALID_DLY, + RX_XCLK_SEL => RX_XCLK_SEL, + SAS_MAX_COM => SAS_MAX_COM, + SAS_MIN_COM => SAS_MIN_COM, + SATA_BURST_SEQ_LEN => SATA_BURST_SEQ_LEN_STRING, + SATA_BURST_VAL => SATA_BURST_VAL_STRING, + SATA_CPLL_CFG => SATA_CPLL_CFG, + SATA_EIDLE_VAL => SATA_EIDLE_VAL_STRING, + SATA_MAX_BURST => SATA_MAX_BURST, + SATA_MAX_INIT => SATA_MAX_INIT, + SATA_MAX_WAKE => SATA_MAX_WAKE, + SATA_MIN_BURST => SATA_MIN_BURST, + SATA_MIN_INIT => SATA_MIN_INIT, + SATA_MIN_WAKE => SATA_MIN_WAKE, + SHOW_REALIGN_COMMA => SHOW_REALIGN_COMMA, + SIM_CPLLREFCLK_SEL => SIM_CPLLREFCLK_SEL_STRING, + SIM_RECEIVER_DETECT_PASS => SIM_RECEIVER_DETECT_PASS, + SIM_RESET_SPEEDUP => SIM_RESET_SPEEDUP, + SIM_TX_EIDLE_DRIVE_LEVEL => SIM_TX_EIDLE_DRIVE_LEVEL, + SIM_VERSION => SIM_VERSION, + TERM_RCAL_CFG => TERM_RCAL_CFG_STRING, + TERM_RCAL_OVRD => TERM_RCAL_OVRD_STRING, + TRANS_TIME_RATE => TRANS_TIME_RATE_STRING, + TST_RSV => TST_RSV_STRING, + TXBUF_EN => TXBUF_EN, + TXBUF_RESET_ON_RATE_CHANGE => TXBUF_RESET_ON_RATE_CHANGE, + TXDLY_CFG => TXDLY_CFG_STRING, + TXDLY_LCFG => TXDLY_LCFG_STRING, + TXDLY_TAP_CFG => TXDLY_TAP_CFG_STRING, + TXGEARBOX_EN => TXGEARBOX_EN, + TXOUT_DIV => TXOUT_DIV, + TXPCSRESET_TIME => TXPCSRESET_TIME_STRING, + TXPHDLY_CFG => TXPHDLY_CFG_STRING, + TXPH_CFG => TXPH_CFG_STRING, + TXPH_MONITOR_SEL => TXPH_MONITOR_SEL_STRING, + TXPMARESET_TIME => TXPMARESET_TIME_STRING, + TX_CLK25_DIV => TX_CLK25_DIV, + TX_CLKMUX_PD => TX_CLKMUX_PD_STRING, + TX_DATA_WIDTH => TX_DATA_WIDTH, + TX_DEEMPH0 => TX_DEEMPH0_STRING, + TX_DEEMPH1 => TX_DEEMPH1_STRING, + TX_DRIVE_MODE => TX_DRIVE_MODE, + TX_EIDLE_ASSERT_DELAY => TX_EIDLE_ASSERT_DELAY_STRING, + TX_EIDLE_DEASSERT_DELAY => TX_EIDLE_DEASSERT_DELAY_STRING, + TX_INT_DATAWIDTH => TX_INT_DATAWIDTH, + TX_LOOPBACK_DRIVE_HIZ => TX_LOOPBACK_DRIVE_HIZ, + TX_MAINCURSOR_SEL => TX_MAINCURSOR_SEL_STRING, + TX_MARGIN_FULL_0 => TX_MARGIN_FULL_0_STRING, + TX_MARGIN_FULL_1 => TX_MARGIN_FULL_1_STRING, + TX_MARGIN_FULL_2 => TX_MARGIN_FULL_2_STRING, + TX_MARGIN_FULL_3 => TX_MARGIN_FULL_3_STRING, + TX_MARGIN_FULL_4 => TX_MARGIN_FULL_4_STRING, + TX_MARGIN_LOW_0 => TX_MARGIN_LOW_0_STRING, + TX_MARGIN_LOW_1 => TX_MARGIN_LOW_1_STRING, + TX_MARGIN_LOW_2 => TX_MARGIN_LOW_2_STRING, + TX_MARGIN_LOW_3 => TX_MARGIN_LOW_3_STRING, + TX_MARGIN_LOW_4 => TX_MARGIN_LOW_4_STRING, + TX_PREDRIVER_MODE => TX_PREDRIVER_MODE_STRING, + TX_QPI_STATUS_EN => TX_QPI_STATUS_EN_STRING, + TX_RXDETECT_CFG => TX_RXDETECT_CFG_STRING, + TX_RXDETECT_REF => TX_RXDETECT_REF_STRING, + TX_XCLK_SEL => TX_XCLK_SEL, + UCODEER_CLR => UCODEER_CLR_STRING + ) + + port map ( + GSR => TO_X01(GSR), + CPLLFBCLKLOST => CPLLFBCLKLOST_outdelay, + CPLLLOCK => CPLLLOCK_outdelay, + CPLLREFCLKLOST => CPLLREFCLKLOST_outdelay, + DMONITOROUT => DMONITOROUT_outdelay, + DRPDO => DRPDO_outdelay, + DRPRDY => DRPRDY_outdelay, + EYESCANDATAERROR => EYESCANDATAERROR_outdelay, + GTREFCLKMONITOR => GTREFCLKMONITOR_outdelay, + GTXTXN => GTXTXN_outdelay, + GTXTXP => GTXTXP_outdelay, + PCSRSVDOUT => PCSRSVDOUT_outdelay, + PHYSTATUS => PHYSTATUS_outdelay, + RXBUFSTATUS => RXBUFSTATUS_outdelay, + RXBYTEISALIGNED => RXBYTEISALIGNED_outdelay, + RXBYTEREALIGN => RXBYTEREALIGN_outdelay, + RXCDRLOCK => RXCDRLOCK_outdelay, + RXCHANBONDSEQ => RXCHANBONDSEQ_outdelay, + RXCHANISALIGNED => RXCHANISALIGNED_outdelay, + RXCHANREALIGN => RXCHANREALIGN_outdelay, + RXCHARISCOMMA => RXCHARISCOMMA_outdelay, + RXCHARISK => RXCHARISK_outdelay, + RXCHBONDO => RXCHBONDO_outdelay, + RXCLKCORCNT => RXCLKCORCNT_outdelay, + RXCOMINITDET => RXCOMINITDET_outdelay, + RXCOMMADET => RXCOMMADET_outdelay, + RXCOMSASDET => RXCOMSASDET_outdelay, + RXCOMWAKEDET => RXCOMWAKEDET_outdelay, + RXDATA => RXDATA_outdelay, + RXDATAVALID => RXDATAVALID_outdelay, + RXDISPERR => RXDISPERR_outdelay, + RXDLYSRESETDONE => RXDLYSRESETDONE_outdelay, + RXELECIDLE => RXELECIDLE_outdelay, + RXHEADER => RXHEADER_outdelay, + RXHEADERVALID => RXHEADERVALID_outdelay, + RXMONITOROUT => RXMONITOROUT_outdelay, + RXNOTINTABLE => RXNOTINTABLE_outdelay, + RXOUTCLK => RXOUTCLK_outdelay, + RXOUTCLKFABRIC => RXOUTCLKFABRIC_outdelay, + RXOUTCLKPCS => RXOUTCLKPCS_outdelay, + RXPHALIGNDONE => RXPHALIGNDONE_outdelay, + RXPHMONITOR => RXPHMONITOR_outdelay, + RXPHSLIPMONITOR => RXPHSLIPMONITOR_outdelay, + RXPRBSERR => RXPRBSERR_outdelay, + RXQPISENN => RXQPISENN_outdelay, + RXQPISENP => RXQPISENP_outdelay, + RXRATEDONE => RXRATEDONE_outdelay, + RXRESETDONE => RXRESETDONE_outdelay, + RXSTARTOFSEQ => RXSTARTOFSEQ_outdelay, + RXSTATUS => RXSTATUS_outdelay, + RXVALID => RXVALID_outdelay, + TSTOUT => TSTOUT_outdelay, + TXBUFSTATUS => TXBUFSTATUS_outdelay, + TXCOMFINISH => TXCOMFINISH_outdelay, + TXDLYSRESETDONE => TXDLYSRESETDONE_outdelay, + TXGEARBOXREADY => TXGEARBOXREADY_outdelay, + TXOUTCLK => TXOUTCLK_outdelay, + TXOUTCLKFABRIC => TXOUTCLKFABRIC_outdelay, + TXOUTCLKPCS => TXOUTCLKPCS_outdelay, + TXPHALIGNDONE => TXPHALIGNDONE_outdelay, + TXPHINITDONE => TXPHINITDONE_outdelay, + TXQPISENN => TXQPISENN_outdelay, + TXQPISENP => TXQPISENP_outdelay, + TXRATEDONE => TXRATEDONE_outdelay, + TXRESETDONE => TXRESETDONE_outdelay, + CFGRESET => CFGRESET_indelay, + CLKRSVD => CLKRSVD_indelay, + CPLLLOCKDETCLK => CPLLLOCKDETCLK_indelay, + CPLLLOCKEN => CPLLLOCKEN_indelay, + CPLLPD => CPLLPD_indelay, + CPLLREFCLKSEL => CPLLREFCLKSEL_indelay, + CPLLRESET => CPLLRESET_indelay, + DRPADDR => DRPADDR_indelay, + DRPCLK => DRPCLK_indelay, + DRPDI => DRPDI_indelay, + DRPEN => DRPEN_indelay, + DRPWE => DRPWE_indelay, + EYESCANMODE => EYESCANMODE_indelay, + EYESCANRESET => EYESCANRESET_indelay, + EYESCANTRIGGER => EYESCANTRIGGER_indelay, + GTGREFCLK => GTGREFCLK_indelay, + GTNORTHREFCLK0 => GTNORTHREFCLK0_indelay, + GTNORTHREFCLK1 => GTNORTHREFCLK1_indelay, + GTREFCLK0 => GTREFCLK0_indelay, + GTREFCLK1 => GTREFCLK1_indelay, + GTRESETSEL => GTRESETSEL_indelay, + GTRSVD => GTRSVD_indelay, + GTRXRESET => GTRXRESET_indelay, + GTSOUTHREFCLK0 => GTSOUTHREFCLK0_indelay, + GTSOUTHREFCLK1 => GTSOUTHREFCLK1_indelay, + GTTXRESET => GTTXRESET_indelay, + GTXRXN => GTXRXN_indelay, + GTXRXP => GTXRXP_indelay, + LOOPBACK => LOOPBACK_indelay, + PCSRSVDIN => PCSRSVDIN_indelay, + PCSRSVDIN2 => PCSRSVDIN2_indelay, + PMARSVDIN => PMARSVDIN_indelay, + PMARSVDIN2 => PMARSVDIN2_indelay, + QPLLCLK => QPLLCLK_indelay, + QPLLREFCLK => QPLLREFCLK_indelay, + RESETOVRD => RESETOVRD_indelay, + RX8B10BEN => RX8B10BEN_indelay, + RXBUFRESET => RXBUFRESET_indelay, + RXCDRFREQRESET => RXCDRFREQRESET_indelay, + RXCDRHOLD => RXCDRHOLD_indelay, + RXCDROVRDEN => RXCDROVRDEN_indelay, + RXCDRRESET => RXCDRRESET_indelay, + RXCDRRESETRSV => RXCDRRESETRSV_indelay, + RXCHBONDEN => RXCHBONDEN_indelay, + RXCHBONDI => RXCHBONDI_indelay, + RXCHBONDLEVEL => RXCHBONDLEVEL_indelay, + RXCHBONDMASTER => RXCHBONDMASTER_indelay, + RXCHBONDSLAVE => RXCHBONDSLAVE_indelay, + RXCOMMADETEN => RXCOMMADETEN_indelay, + RXDDIEN => RXDDIEN_indelay, + RXDFEAGCHOLD => RXDFEAGCHOLD_indelay, + RXDFEAGCOVRDEN => RXDFEAGCOVRDEN_indelay, + RXDFECM1EN => RXDFECM1EN_indelay, + RXDFELFHOLD => RXDFELFHOLD_indelay, + RXDFELFOVRDEN => RXDFELFOVRDEN_indelay, + RXDFELPMRESET => RXDFELPMRESET_indelay, + RXDFETAP2HOLD => RXDFETAP2HOLD_indelay, + RXDFETAP2OVRDEN => RXDFETAP2OVRDEN_indelay, + RXDFETAP3HOLD => RXDFETAP3HOLD_indelay, + RXDFETAP3OVRDEN => RXDFETAP3OVRDEN_indelay, + RXDFETAP4HOLD => RXDFETAP4HOLD_indelay, + RXDFETAP4OVRDEN => RXDFETAP4OVRDEN_indelay, + RXDFETAP5HOLD => RXDFETAP5HOLD_indelay, + RXDFETAP5OVRDEN => RXDFETAP5OVRDEN_indelay, + RXDFEUTHOLD => RXDFEUTHOLD_indelay, + RXDFEUTOVRDEN => RXDFEUTOVRDEN_indelay, + RXDFEVPHOLD => RXDFEVPHOLD_indelay, + RXDFEVPOVRDEN => RXDFEVPOVRDEN_indelay, + RXDFEVSEN => RXDFEVSEN_indelay, + RXDFEXYDEN => RXDFEXYDEN_indelay, + RXDFEXYDHOLD => RXDFEXYDHOLD_indelay, + RXDFEXYDOVRDEN => RXDFEXYDOVRDEN_indelay, + RXDLYBYPASS => RXDLYBYPASS_indelay, + RXDLYEN => RXDLYEN_indelay, + RXDLYOVRDEN => RXDLYOVRDEN_indelay, + RXDLYSRESET => RXDLYSRESET_indelay, + RXELECIDLEMODE => RXELECIDLEMODE_indelay, + RXGEARBOXSLIP => RXGEARBOXSLIP_indelay, + RXLPMEN => RXLPMEN_indelay, + RXLPMHFHOLD => RXLPMHFHOLD_indelay, + RXLPMHFOVRDEN => RXLPMHFOVRDEN_indelay, + RXLPMLFHOLD => RXLPMLFHOLD_indelay, + RXLPMLFKLOVRDEN => RXLPMLFKLOVRDEN_indelay, + RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_indelay, + RXMONITORSEL => RXMONITORSEL_indelay, + RXOOBRESET => RXOOBRESET_indelay, + RXOSHOLD => RXOSHOLD_indelay, + RXOSOVRDEN => RXOSOVRDEN_indelay, + RXOUTCLKSEL => RXOUTCLKSEL_indelay, + RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_indelay, + RXPCSRESET => RXPCSRESET_indelay, + RXPD => RXPD_indelay, + RXPHALIGN => RXPHALIGN_indelay, + RXPHALIGNEN => RXPHALIGNEN_indelay, + RXPHDLYPD => RXPHDLYPD_indelay, + RXPHDLYRESET => RXPHDLYRESET_indelay, + RXPHOVRDEN => RXPHOVRDEN_indelay, + RXPMARESET => RXPMARESET_indelay, + RXPOLARITY => RXPOLARITY_indelay, + RXPRBSCNTRESET => RXPRBSCNTRESET_indelay, + RXPRBSSEL => RXPRBSSEL_indelay, + RXQPIEN => RXQPIEN_indelay, + RXRATE => RXRATE_indelay, + RXSLIDE => RXSLIDE_indelay, + RXSYSCLKSEL => RXSYSCLKSEL_indelay, + RXUSERRDY => RXUSERRDY_indelay, + RXUSRCLK => RXUSRCLK_indelay, + RXUSRCLK2 => RXUSRCLK2_indelay, + SETERRSTATUS => SETERRSTATUS_indelay, + TSTIN => TSTIN_indelay, + TX8B10BBYPASS => TX8B10BBYPASS_indelay, + TX8B10BEN => TX8B10BEN_indelay, + TXBUFDIFFCTRL => TXBUFDIFFCTRL_indelay, + TXCHARDISPMODE => TXCHARDISPMODE_indelay, + TXCHARDISPVAL => TXCHARDISPVAL_indelay, + TXCHARISK => TXCHARISK_indelay, + TXCOMINIT => TXCOMINIT_indelay, + TXCOMSAS => TXCOMSAS_indelay, + TXCOMWAKE => TXCOMWAKE_indelay, + TXDATA => TXDATA_indelay, + TXDEEMPH => TXDEEMPH_indelay, + TXDETECTRX => TXDETECTRX_indelay, + TXDIFFCTRL => TXDIFFCTRL_indelay, + TXDIFFPD => TXDIFFPD_indelay, + TXDLYBYPASS => TXDLYBYPASS_indelay, + TXDLYEN => TXDLYEN_indelay, + TXDLYHOLD => TXDLYHOLD_indelay, + TXDLYOVRDEN => TXDLYOVRDEN_indelay, + TXDLYSRESET => TXDLYSRESET_indelay, + TXDLYUPDOWN => TXDLYUPDOWN_indelay, + TXELECIDLE => TXELECIDLE_indelay, + TXHEADER => TXHEADER_indelay, + TXINHIBIT => TXINHIBIT_indelay, + TXMAINCURSOR => TXMAINCURSOR_indelay, + TXMARGIN => TXMARGIN_indelay, + TXOUTCLKSEL => TXOUTCLKSEL_indelay, + TXPCSRESET => TXPCSRESET_indelay, + TXPD => TXPD_indelay, + TXPDELECIDLEMODE => TXPDELECIDLEMODE_indelay, + TXPHALIGN => TXPHALIGN_indelay, + TXPHALIGNEN => TXPHALIGNEN_indelay, + TXPHDLYPD => TXPHDLYPD_indelay, + TXPHDLYRESET => TXPHDLYRESET_indelay, + TXPHDLYTSTCLK => TXPHDLYTSTCLK_indelay, + TXPHINIT => TXPHINIT_indelay, + TXPHOVRDEN => TXPHOVRDEN_indelay, + TXPISOPD => TXPISOPD_indelay, + TXPMARESET => TXPMARESET_indelay, + TXPOLARITY => TXPOLARITY_indelay, + TXPOSTCURSOR => TXPOSTCURSOR_indelay, + TXPOSTCURSORINV => TXPOSTCURSORINV_indelay, + TXPRBSFORCEERR => TXPRBSFORCEERR_indelay, + TXPRBSSEL => TXPRBSSEL_indelay, + TXPRECURSOR => TXPRECURSOR_indelay, + TXPRECURSORINV => TXPRECURSORINV_indelay, + TXQPIBIASEN => TXQPIBIASEN_indelay, + TXQPISTRONGPDOWN => TXQPISTRONGPDOWN_indelay, + TXQPIWEAKPUP => TXQPIWEAKPUP_indelay, + TXRATE => TXRATE_indelay, + TXSEQUENCE => TXSEQUENCE_indelay, + TXSTARTSEQ => TXSTARTSEQ_indelay, + TXSWING => TXSWING_indelay, + TXSYSCLKSEL => TXSYSCLKSEL_indelay, + TXUSERRDY => TXUSERRDY_indelay, + TXUSRCLK => TXUSRCLK_indelay, + TXUSRCLK2 => TXUSRCLK2_indelay + ); + + + drp_monitor: process (DRPCLK_indelay) + + variable drpen_r1 : std_logic := '0'; + variable drpen_r2 : std_logic := '0'; + variable drpwe_r1 : std_logic := '0'; + variable drpwe_r2 : std_logic := '0'; + type statetype is (FSM_IDLE, FSM_WAIT); + variable sfsm : statetype := FSM_IDLE; + + begin -- process drp_monitor + + if (rising_edge(DRPCLK_indelay)) then + + -- pipeline the DRPEN and DRPWE + drpen_r2 := drpen_r1; + drpwe_r2 := drpwe_r1; + drpen_r1 := DRPEN_indelay; + drpwe_r1 := DRPWE_indelay; + + + -- Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 = '1') and (drpen_r2 = '1')) then + assert false + report "DRC Error : DRPEN is high for more than 1 DRPCLK." + severity failure; + end if; + + if ((drpwe_r1 = '1') and (drpwe_r2 = '1')) then + assert false + report "DRC Error : DRPWE is high for more than 1 DRPCLK." + severity failure; + end if; + + + -- After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case sfsm is + when FSM_IDLE => + if (DRPEN_indelay = '1') then + sfsm := FSM_WAIT; + end if; + + when FSM_WAIT => + + -- After the 1st DRPEN, 4 cases can happen + -- DRPEN DRPRDY NEXT STATE + -- 0 0 FSM_WAIT - wait for DRPRDY + -- 0 1 FSM_IDLE - normal operation + -- 1 0 FSM_WAIT - display error and wait for DRPRDY + -- 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.; + -- Add the check for another DPREN pulse + if(DRPEN_indelay = '1' and DRPRDY_out = '0') then + assert false + report "DRC Error : DRPEN is enabled before DRPRDY returns." + severity failure; + end if; + + -- Add the check for another DRPWE pulse + if ((DRPWE_indelay = '1') and (DRPEN_indelay = '0')) then + assert false + report "DRC Error : DRPWE is enabled before DRPRDY returns." + severity failure; + end if; + + if ((DRPRDY_out = '1') and (DRPEN_indelay = '0')) then + sfsm := FSM_IDLE; + end if; + + + if ((DRPRDY_out = '1') and (DRPEN_indelay = '1')) then + sfsm := FSM_WAIT; + end if; + + + when others => + assert false + report "DRC Error : Default state in DRP FSM." + severity failure; + + end case; + + end if; + + end process drp_monitor; + + + INIPROC : process + begin + -- case ALIGN_COMMA_DOUBLE is + if((ALIGN_COMMA_DOUBLE = "FALSE") or (ALIGN_COMMA_DOUBLE = "false")) then + ALIGN_COMMA_DOUBLE_BINARY <= '0'; + elsif((ALIGN_COMMA_DOUBLE = "TRUE") or (ALIGN_COMMA_DOUBLE= "true")) then + ALIGN_COMMA_DOUBLE_BINARY <= '1'; + else + assert FALSE report "Error : ALIGN_COMMA_DOUBLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case ALIGN_MCOMMA_DET is + if((ALIGN_MCOMMA_DET = "TRUE") or (ALIGN_MCOMMA_DET = "true")) then + ALIGN_MCOMMA_DET_BINARY <= '1'; + elsif((ALIGN_MCOMMA_DET = "FALSE") or (ALIGN_MCOMMA_DET= "false")) then + ALIGN_MCOMMA_DET_BINARY <= '0'; + else + assert FALSE report "Error : ALIGN_MCOMMA_DET = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case ALIGN_PCOMMA_DET is + if((ALIGN_PCOMMA_DET = "TRUE") or (ALIGN_PCOMMA_DET = "true")) then + ALIGN_PCOMMA_DET_BINARY <= '1'; + elsif((ALIGN_PCOMMA_DET = "FALSE") or (ALIGN_PCOMMA_DET= "false")) then + ALIGN_PCOMMA_DET_BINARY <= '0'; + else + assert FALSE report "Error : ALIGN_PCOMMA_DET = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CBCC_DATA_SOURCE_SEL is + if((CBCC_DATA_SOURCE_SEL = "DECODED") or (CBCC_DATA_SOURCE_SEL = "decoded")) then + CBCC_DATA_SOURCE_SEL_BINARY <= '1'; + elsif((CBCC_DATA_SOURCE_SEL = "ENCODED") or (CBCC_DATA_SOURCE_SEL= "encoded")) then + CBCC_DATA_SOURCE_SEL_BINARY <= '0'; + else + assert FALSE report "Error : CBCC_DATA_SOURCE_SEL = is not DECODED, ENCODED." severity error; + end if; + -- end case; + -- case CHAN_BOND_KEEP_ALIGN is + if((CHAN_BOND_KEEP_ALIGN = "FALSE") or (CHAN_BOND_KEEP_ALIGN = "false")) then + CHAN_BOND_KEEP_ALIGN_BINARY <= '0'; + elsif((CHAN_BOND_KEEP_ALIGN = "TRUE") or (CHAN_BOND_KEEP_ALIGN= "true")) then + CHAN_BOND_KEEP_ALIGN_BINARY <= '1'; + else + assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CHAN_BOND_SEQ_2_USE is + if((CHAN_BOND_SEQ_2_USE = "FALSE") or (CHAN_BOND_SEQ_2_USE = "false")) then + CHAN_BOND_SEQ_2_USE_BINARY <= '0'; + elsif((CHAN_BOND_SEQ_2_USE = "TRUE") or (CHAN_BOND_SEQ_2_USE= "true")) then + CHAN_BOND_SEQ_2_USE_BINARY <= '1'; + else + assert FALSE report "Error : CHAN_BOND_SEQ_2_USE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CLK_CORRECT_USE is + if((CLK_CORRECT_USE = "TRUE") or (CLK_CORRECT_USE = "true")) then + CLK_CORRECT_USE_BINARY <= '1'; + elsif((CLK_CORRECT_USE = "FALSE") or (CLK_CORRECT_USE= "false")) then + CLK_CORRECT_USE_BINARY <= '0'; + else + assert FALSE report "Error : CLK_CORRECT_USE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CLK_COR_KEEP_IDLE is + if((CLK_COR_KEEP_IDLE = "FALSE") or (CLK_COR_KEEP_IDLE = "false")) then + CLK_COR_KEEP_IDLE_BINARY <= '0'; + elsif((CLK_COR_KEEP_IDLE = "TRUE") or (CLK_COR_KEEP_IDLE= "true")) then + CLK_COR_KEEP_IDLE_BINARY <= '1'; + else + assert FALSE report "Error : CLK_COR_KEEP_IDLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case CLK_COR_PRECEDENCE is + if((CLK_COR_PRECEDENCE = "TRUE") or (CLK_COR_PRECEDENCE = "true")) then + CLK_COR_PRECEDENCE_BINARY <= '1'; + elsif((CLK_COR_PRECEDENCE = "FALSE") or (CLK_COR_PRECEDENCE= "false")) then + CLK_COR_PRECEDENCE_BINARY <= '0'; + else + assert FALSE report "Error : CLK_COR_PRECEDENCE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case CLK_COR_SEQ_2_USE is + if((CLK_COR_SEQ_2_USE = "FALSE") or (CLK_COR_SEQ_2_USE = "false")) then + CLK_COR_SEQ_2_USE_BINARY <= '0'; + elsif((CLK_COR_SEQ_2_USE = "TRUE") or (CLK_COR_SEQ_2_USE= "true")) then + CLK_COR_SEQ_2_USE_BINARY <= '1'; + else + assert FALSE report "Error : CLK_COR_SEQ_2_USE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case DEC_MCOMMA_DETECT is + if((DEC_MCOMMA_DETECT = "TRUE") or (DEC_MCOMMA_DETECT = "true")) then + DEC_MCOMMA_DETECT_BINARY <= '1'; + elsif((DEC_MCOMMA_DETECT = "FALSE") or (DEC_MCOMMA_DETECT= "false")) then + DEC_MCOMMA_DETECT_BINARY <= '0'; + else + assert FALSE report "Error : DEC_MCOMMA_DETECT = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case DEC_PCOMMA_DETECT is + if((DEC_PCOMMA_DETECT = "TRUE") or (DEC_PCOMMA_DETECT = "true")) then + DEC_PCOMMA_DETECT_BINARY <= '1'; + elsif((DEC_PCOMMA_DETECT = "FALSE") or (DEC_PCOMMA_DETECT= "false")) then + DEC_PCOMMA_DETECT_BINARY <= '0'; + else + assert FALSE report "Error : DEC_PCOMMA_DETECT = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case DEC_VALID_COMMA_ONLY is + if((DEC_VALID_COMMA_ONLY = "TRUE") or (DEC_VALID_COMMA_ONLY = "true")) then + DEC_VALID_COMMA_ONLY_BINARY <= '1'; + elsif((DEC_VALID_COMMA_ONLY = "FALSE") or (DEC_VALID_COMMA_ONLY= "false")) then + DEC_VALID_COMMA_ONLY_BINARY <= '0'; + else + assert FALSE report "Error : DEC_VALID_COMMA_ONLY = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case ES_ERRDET_EN is + if((ES_ERRDET_EN = "FALSE") or (ES_ERRDET_EN = "false")) then + ES_ERRDET_EN_BINARY <= '0'; + elsif((ES_ERRDET_EN = "TRUE") or (ES_ERRDET_EN= "true")) then + ES_ERRDET_EN_BINARY <= '1'; + else + assert FALSE report "Error : ES_ERRDET_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case ES_EYE_SCAN_EN is + if((ES_EYE_SCAN_EN = "FALSE") or (ES_EYE_SCAN_EN = "false")) then + ES_EYE_SCAN_EN_BINARY <= '0'; + elsif((ES_EYE_SCAN_EN = "TRUE") or (ES_EYE_SCAN_EN= "true")) then + ES_EYE_SCAN_EN_BINARY <= '1'; + else + assert FALSE report "Error : ES_EYE_SCAN_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case FTS_LANE_DESKEW_EN is + if((FTS_LANE_DESKEW_EN = "FALSE") or (FTS_LANE_DESKEW_EN = "false")) then + FTS_LANE_DESKEW_EN_BINARY <= '0'; + elsif((FTS_LANE_DESKEW_EN = "TRUE") or (FTS_LANE_DESKEW_EN= "true")) then + FTS_LANE_DESKEW_EN_BINARY <= '1'; + else + assert FALSE report "Error : FTS_LANE_DESKEW_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case PCS_PCIE_EN is + if((PCS_PCIE_EN = "FALSE") or (PCS_PCIE_EN = "false")) then + PCS_PCIE_EN_BINARY <= '0'; + elsif((PCS_PCIE_EN = "TRUE") or (PCS_PCIE_EN= "true")) then + PCS_PCIE_EN_BINARY <= '1'; + else + assert FALSE report "Error : PCS_PCIE_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_ADDR_MODE is + if((RXBUF_ADDR_MODE = "FULL") or (RXBUF_ADDR_MODE = "full")) then + RXBUF_ADDR_MODE_BINARY <= '0'; + elsif((RXBUF_ADDR_MODE = "FAST") or (RXBUF_ADDR_MODE= "fast")) then + RXBUF_ADDR_MODE_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_ADDR_MODE = is not FULL, FAST." severity error; + end if; + -- end case; + -- case RXBUF_EN is + if((RXBUF_EN = "TRUE") or (RXBUF_EN = "true")) then + RXBUF_EN_BINARY <= '1'; + elsif((RXBUF_EN = "FALSE") or (RXBUF_EN= "false")) then + RXBUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_CB_CHANGE is + if((RXBUF_RESET_ON_CB_CHANGE = "TRUE") or (RXBUF_RESET_ON_CB_CHANGE = "true")) then + RXBUF_RESET_ON_CB_CHANGE_BINARY <= '1'; + elsif((RXBUF_RESET_ON_CB_CHANGE = "FALSE") or (RXBUF_RESET_ON_CB_CHANGE= "false")) then + RXBUF_RESET_ON_CB_CHANGE_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_RESET_ON_CB_CHANGE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_COMMAALIGN is + if((RXBUF_RESET_ON_COMMAALIGN = "FALSE") or (RXBUF_RESET_ON_COMMAALIGN = "false")) then + RXBUF_RESET_ON_COMMAALIGN_BINARY <= '0'; + elsif((RXBUF_RESET_ON_COMMAALIGN = "TRUE") or (RXBUF_RESET_ON_COMMAALIGN= "true")) then + RXBUF_RESET_ON_COMMAALIGN_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_RESET_ON_COMMAALIGN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_EIDLE is + if((RXBUF_RESET_ON_EIDLE = "FALSE") or (RXBUF_RESET_ON_EIDLE = "false")) then + RXBUF_RESET_ON_EIDLE_BINARY <= '0'; + elsif((RXBUF_RESET_ON_EIDLE = "TRUE") or (RXBUF_RESET_ON_EIDLE= "true")) then + RXBUF_RESET_ON_EIDLE_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_RESET_ON_EIDLE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXBUF_RESET_ON_RATE_CHANGE is + if((RXBUF_RESET_ON_RATE_CHANGE = "TRUE") or (RXBUF_RESET_ON_RATE_CHANGE = "true")) then + RXBUF_RESET_ON_RATE_CHANGE_BINARY <= '1'; + elsif((RXBUF_RESET_ON_RATE_CHANGE = "FALSE") or (RXBUF_RESET_ON_RATE_CHANGE= "false")) then + RXBUF_RESET_ON_RATE_CHANGE_BINARY <= '0'; + else + assert FALSE report "Error : RXBUF_RESET_ON_RATE_CHANGE = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RXBUF_THRESH_OVRD is + if((RXBUF_THRESH_OVRD = "FALSE") or (RXBUF_THRESH_OVRD = "false")) then + RXBUF_THRESH_OVRD_BINARY <= '0'; + elsif((RXBUF_THRESH_OVRD = "TRUE") or (RXBUF_THRESH_OVRD= "true")) then + RXBUF_THRESH_OVRD_BINARY <= '1'; + else + assert FALSE report "Error : RXBUF_THRESH_OVRD = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXGEARBOX_EN is + if((RXGEARBOX_EN = "FALSE") or (RXGEARBOX_EN = "false")) then + RXGEARBOX_EN_BINARY <= '0'; + elsif((RXGEARBOX_EN = "TRUE") or (RXGEARBOX_EN= "true")) then + RXGEARBOX_EN_BINARY <= '1'; + else + assert FALSE report "Error : RXGEARBOX_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case RXSLIDE_MODE is + if((RXSLIDE_MODE = "OFF") or (RXSLIDE_MODE = "off")) then + RXSLIDE_MODE_BINARY <= "00"; + elsif((RXSLIDE_MODE = "AUTO") or (RXSLIDE_MODE= "auto")) then + RXSLIDE_MODE_BINARY <= "01"; + elsif((RXSLIDE_MODE = "PCS") or (RXSLIDE_MODE= "pcs")) then + RXSLIDE_MODE_BINARY <= "10"; + elsif((RXSLIDE_MODE = "PMA") or (RXSLIDE_MODE= "pma")) then + RXSLIDE_MODE_BINARY <= "11"; + else + assert FALSE report "Error : RXSLIDE_MODE = is not OFF, AUTO, PCS, PMA." severity error; + end if; + -- end case; + -- case RX_DEFER_RESET_BUF_EN is + if((RX_DEFER_RESET_BUF_EN = "TRUE") or (RX_DEFER_RESET_BUF_EN = "true")) then + RX_DEFER_RESET_BUF_EN_BINARY <= '1'; + elsif((RX_DEFER_RESET_BUF_EN = "FALSE") or (RX_DEFER_RESET_BUF_EN= "false")) then + RX_DEFER_RESET_BUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : RX_DEFER_RESET_BUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RX_DISPERR_SEQ_MATCH is + if((RX_DISPERR_SEQ_MATCH = "TRUE") or (RX_DISPERR_SEQ_MATCH = "true")) then + RX_DISPERR_SEQ_MATCH_BINARY <= '1'; + elsif((RX_DISPERR_SEQ_MATCH = "FALSE") or (RX_DISPERR_SEQ_MATCH= "false")) then + RX_DISPERR_SEQ_MATCH_BINARY <= '0'; + else + assert FALSE report "Error : RX_DISPERR_SEQ_MATCH = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case RX_XCLK_SEL is + if((RX_XCLK_SEL = "RXREC") or (RX_XCLK_SEL = "rxrec")) then + RX_XCLK_SEL_BINARY <= '0'; + elsif((RX_XCLK_SEL = "RXUSR") or (RX_XCLK_SEL= "rxusr")) then + RX_XCLK_SEL_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL = is not RXREC, RXUSR." severity error; + end if; + -- end case; + -- case SATA_CPLL_CFG is + if((SATA_CPLL_CFG = "VCO_3000MHZ") or (SATA_CPLL_CFG = "vco_3000mhz")) then + SATA_CPLL_CFG_BINARY <= "00"; + elsif((SATA_CPLL_CFG = "VCO_750MHZ") or (SATA_CPLL_CFG= "vco_750mhz")) then + SATA_CPLL_CFG_BINARY <= "10"; + elsif((SATA_CPLL_CFG = "VCO_1500MHZ") or (SATA_CPLL_CFG= "vco_1500mhz")) then + SATA_CPLL_CFG_BINARY <= "01"; + else + assert FALSE report "Error : SATA_CPLL_CFG = is not VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ." severity error; + end if; + -- end case; + -- case SHOW_REALIGN_COMMA is + if((SHOW_REALIGN_COMMA = "TRUE") or (SHOW_REALIGN_COMMA = "true")) then + SHOW_REALIGN_COMMA_BINARY <= '1'; + elsif((SHOW_REALIGN_COMMA = "FALSE") or (SHOW_REALIGN_COMMA= "false")) then + SHOW_REALIGN_COMMA_BINARY <= '0'; + else + assert FALSE report "Error : SHOW_REALIGN_COMMA = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case TXBUF_EN is + if((TXBUF_EN = "TRUE") or (TXBUF_EN = "true")) then + TXBUF_EN_BINARY <= '1'; + elsif((TXBUF_EN = "FALSE") or (TXBUF_EN= "false")) then + TXBUF_EN_BINARY <= '0'; + else + assert FALSE report "Error : TXBUF_EN = is not TRUE, FALSE." severity error; + end if; + -- end case; + -- case TXBUF_RESET_ON_RATE_CHANGE is + if((TXBUF_RESET_ON_RATE_CHANGE = "FALSE") or (TXBUF_RESET_ON_RATE_CHANGE = "false")) then + TXBUF_RESET_ON_RATE_CHANGE_BINARY <= '0'; + elsif((TXBUF_RESET_ON_RATE_CHANGE = "TRUE") or (TXBUF_RESET_ON_RATE_CHANGE= "true")) then + TXBUF_RESET_ON_RATE_CHANGE_BINARY <= '1'; + else + assert FALSE report "Error : TXBUF_RESET_ON_RATE_CHANGE = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TXGEARBOX_EN is + if((TXGEARBOX_EN = "FALSE") or (TXGEARBOX_EN = "false")) then + TXGEARBOX_EN_BINARY <= '0'; + elsif((TXGEARBOX_EN = "TRUE") or (TXGEARBOX_EN= "true")) then + TXGEARBOX_EN_BINARY <= '1'; + else + assert FALSE report "Error : TXGEARBOX_EN = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TX_DRIVE_MODE is + if((TX_DRIVE_MODE = "DIRECT") or (TX_DRIVE_MODE = "direct")) then + TX_DRIVE_MODE_BINARY <= "00000"; + elsif((TX_DRIVE_MODE = "PIPE") or (TX_DRIVE_MODE= "pipe")) then + TX_DRIVE_MODE_BINARY <= "00001"; + elsif((TX_DRIVE_MODE = "PIPEGEN3") or (TX_DRIVE_MODE= "pipegen3")) then + TX_DRIVE_MODE_BINARY <= "00010"; + else + assert FALSE report "Error : TX_DRIVE_MODE = is not DIRECT, PIPE, PIPEGEN3." severity error; + end if; + -- end case; + -- case TX_LOOPBACK_DRIVE_HIZ is + if((TX_LOOPBACK_DRIVE_HIZ = "FALSE") or (TX_LOOPBACK_DRIVE_HIZ = "false")) then + TX_LOOPBACK_DRIVE_HIZ_BINARY <= '0'; + elsif((TX_LOOPBACK_DRIVE_HIZ = "TRUE") or (TX_LOOPBACK_DRIVE_HIZ= "true")) then + TX_LOOPBACK_DRIVE_HIZ_BINARY <= '1'; + else + assert FALSE report "Error : TX_LOOPBACK_DRIVE_HIZ = is not FALSE, TRUE." severity error; + end if; + -- end case; + -- case TX_XCLK_SEL is + if((TX_XCLK_SEL = "TXUSR") or (TX_XCLK_SEL = "txusr")) then + TX_XCLK_SEL_BINARY <= '1'; + elsif((TX_XCLK_SEL = "TXOUT") or (TX_XCLK_SEL= "txout")) then + TX_XCLK_SEL_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL = is not TXUSR, TXOUT." severity error; + end if; + -- end case; + case CPLL_FBDIV_45 is + when 5 => CPLL_FBDIV_45_BINARY <= '1'; + when 4 => CPLL_FBDIV_45_BINARY <= '0'; + when others => assert FALSE report "Error : CPLL_FBDIV_45 is not in range 4 .. 5." severity error; + end case; + case RX_INT_DATAWIDTH is + when 0 => RX_INT_DATAWIDTH_BINARY <= '0'; + when 1 => RX_INT_DATAWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : RX_INT_DATAWIDTH is not in range 0 .. 1." severity error; + end case; + case TX_INT_DATAWIDTH is + when 0 => TX_INT_DATAWIDTH_BINARY <= '0'; + when 1 => TX_INT_DATAWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : TX_INT_DATAWIDTH is not in range 0 .. 1." severity error; + end case; + if ((ALIGN_COMMA_WORD >= 1) and (ALIGN_COMMA_WORD <= 4)) then + ALIGN_COMMA_WORD_BINARY <= CONV_STD_LOGIC_VECTOR(ALIGN_COMMA_WORD, 3); + else + assert FALSE report "Error : ALIGN_COMMA_WORD is not in range 1 .. 4." severity error; + end if; + if ((CHAN_BOND_MAX_SKEW >= 1) and (CHAN_BOND_MAX_SKEW <= 14)) then + CHAN_BOND_MAX_SKEW_BINARY <= CONV_STD_LOGIC_VECTOR(CHAN_BOND_MAX_SKEW, 4); + else + assert FALSE report "Error : CHAN_BOND_MAX_SKEW is not in range 1 .. 14." severity error; + end if; + if ((CHAN_BOND_SEQ_LEN >= 1) and (CHAN_BOND_SEQ_LEN <= 4)) then + CHAN_BOND_SEQ_LEN_BINARY <= CONV_STD_LOGIC_VECTOR(CHAN_BOND_SEQ_LEN, 2); + else + assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in range 1 .. 4." severity error; + end if; + if ((CLK_COR_MAX_LAT >= 3) and (CLK_COR_MAX_LAT <= 60)) then + CLK_COR_MAX_LAT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_MAX_LAT, 6); + else + assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 3 .. 60." severity error; + end if; + if ((CLK_COR_MIN_LAT >= 3) and (CLK_COR_MIN_LAT <= 60)) then + CLK_COR_MIN_LAT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_MIN_LAT, 6); + else + assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 3 .. 60." severity error; + end if; + if ((CLK_COR_REPEAT_WAIT >= 0) and (CLK_COR_REPEAT_WAIT <= 31)) then + CLK_COR_REPEAT_WAIT_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_REPEAT_WAIT, 5); + else + assert FALSE report "Error : CLK_COR_REPEAT_WAIT is not in range 0 .. 31." severity error; + end if; + if ((CLK_COR_SEQ_LEN >= 1) and (CLK_COR_SEQ_LEN <= 4)) then + CLK_COR_SEQ_LEN_BINARY <= CONV_STD_LOGIC_VECTOR(CLK_COR_SEQ_LEN, 2); + else + assert FALSE report "Error : CLK_COR_SEQ_LEN is not in range 1 .. 4." severity error; + end if; + if ((CPLL_FBDIV >= 1) and (CPLL_FBDIV <= 20)) then + CPLL_FBDIV_BINARY <= CONV_STD_LOGIC_VECTOR(CPLL_FBDIV, 7); + else + assert FALSE report "Error : CPLL_FBDIV is not in range 1 .. 20." severity error; + end if; + if ((CPLL_REFCLK_DIV >= 1) and (CPLL_REFCLK_DIV <= 20)) then + CPLL_REFCLK_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(CPLL_REFCLK_DIV, 5); + else + assert FALSE report "Error : CPLL_REFCLK_DIV is not in range 1 .. 20." severity error; + end if; + if ((RXBUF_THRESH_OVFLW >= 0) and (RXBUF_THRESH_OVFLW <= 63)) then + RXBUF_THRESH_OVFLW_BINARY <= CONV_STD_LOGIC_VECTOR(RXBUF_THRESH_OVFLW, 6); + else + assert FALSE report "Error : RXBUF_THRESH_OVFLW is not in range 0 .. 63." severity error; + end if; + if ((RXBUF_THRESH_UNDFLW >= 0) and (RXBUF_THRESH_UNDFLW <= 63)) then + RXBUF_THRESH_UNDFLW_BINARY <= CONV_STD_LOGIC_VECTOR(RXBUF_THRESH_UNDFLW, 6); + else + assert FALSE report "Error : RXBUF_THRESH_UNDFLW is not in range 0 .. 63." severity error; + end if; + if ((RXOUT_DIV >= 1) and (RXOUT_DIV <= 16)) then + RXOUT_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(RXOUT_DIV, 3); + else + assert FALSE report "Error : RXOUT_DIV is not in range 1 .. 16." severity error; + end if; + if ((RXSLIDE_AUTO_WAIT >= 0) and (RXSLIDE_AUTO_WAIT <= 15)) then + RXSLIDE_AUTO_WAIT_BINARY <= CONV_STD_LOGIC_VECTOR(RXSLIDE_AUTO_WAIT, 4); + else + assert FALSE report "Error : RXSLIDE_AUTO_WAIT is not in range 0 .. 15." severity error; + end if; + if ((RX_CLK25_DIV >= 1) and (RX_CLK25_DIV <= 32)) then + RX_CLK25_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(RX_CLK25_DIV, 5); + else + assert FALSE report "Error : RX_CLK25_DIV is not in range 1 .. 32." severity error; + end if; + if ((RX_DATA_WIDTH >= 16) and (RX_DATA_WIDTH <= 80)) then + RX_DATA_WIDTH_BINARY <= CONV_STD_LOGIC_VECTOR(RX_DATA_WIDTH, 3); + else + assert FALSE report "Error : RX_DATA_WIDTH is not in range 16 .. 80." severity error; + end if; + if ((RX_SIG_VALID_DLY >= 1) and (RX_SIG_VALID_DLY <= 32)) then + RX_SIG_VALID_DLY_BINARY <= CONV_STD_LOGIC_VECTOR(RX_SIG_VALID_DLY, 5); + else + assert FALSE report "Error : RX_SIG_VALID_DLY is not in range 1 .. 32." severity error; + end if; + if ((SAS_MAX_COM >= 1) and (SAS_MAX_COM <= 127)) then + SAS_MAX_COM_BINARY <= CONV_STD_LOGIC_VECTOR(SAS_MAX_COM, 7); + else + assert FALSE report "Error : SAS_MAX_COM is not in range 1 .. 127." severity error; + end if; + if ((SAS_MIN_COM >= 1) and (SAS_MIN_COM <= 63)) then + SAS_MIN_COM_BINARY <= CONV_STD_LOGIC_VECTOR(SAS_MIN_COM, 6); + else + assert FALSE report "Error : SAS_MIN_COM is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_BURST >= 1) and (SATA_MAX_BURST <= 63)) then + SATA_MAX_BURST_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_BURST, 6); + else + assert FALSE report "Error : SATA_MAX_BURST is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_INIT >= 1) and (SATA_MAX_INIT <= 63)) then + SATA_MAX_INIT_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_INIT, 6); + else + assert FALSE report "Error : SATA_MAX_INIT is not in range 1 .. 63." severity error; + end if; + if ((SATA_MAX_WAKE >= 1) and (SATA_MAX_WAKE <= 63)) then + SATA_MAX_WAKE_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MAX_WAKE, 6); + else + assert FALSE report "Error : SATA_MAX_WAKE is not in range 1 .. 63." severity error; + end if; + if ((SATA_MIN_BURST >= 1) and (SATA_MIN_BURST <= 61)) then + SATA_MIN_BURST_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_BURST, 6); + else + assert FALSE report "Error : SATA_MIN_BURST is not in range 1 .. 61." severity error; + end if; + if ((SATA_MIN_INIT >= 1) and (SATA_MIN_INIT <= 63)) then + SATA_MIN_INIT_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_INIT, 6); + else + assert FALSE report "Error : SATA_MIN_INIT is not in range 1 .. 63." severity error; + end if; + if ((SATA_MIN_WAKE >= 1) and (SATA_MIN_WAKE <= 63)) then + SATA_MIN_WAKE_BINARY <= CONV_STD_LOGIC_VECTOR(SATA_MIN_WAKE, 6); + else + assert FALSE report "Error : SATA_MIN_WAKE is not in range 1 .. 63." severity error; + end if; + if ((TXOUT_DIV >= 1) and (TXOUT_DIV <= 16)) then + TXOUT_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(TXOUT_DIV, 3); + else + assert FALSE report "Error : TXOUT_DIV is not in range 1 .. 16." severity error; + end if; + if ((TX_CLK25_DIV >= 1) and (TX_CLK25_DIV <= 32)) then + TX_CLK25_DIV_BINARY <= CONV_STD_LOGIC_VECTOR(TX_CLK25_DIV, 5); + else + assert FALSE report "Error : TX_CLK25_DIV is not in range 1 .. 32." severity error; + end if; + if ((TX_DATA_WIDTH >= 16) and (TX_DATA_WIDTH <= 80)) then + TX_DATA_WIDTH_BINARY <= CONV_STD_LOGIC_VECTOR(TX_DATA_WIDTH, 3); + else + assert FALSE report "Error : TX_DATA_WIDTH is not in range 16 .. 80." severity error; + end if; + wait; + end process INIPROC; + CPLLFBCLKLOST <= CPLLFBCLKLOST_out; + CPLLLOCK <= CPLLLOCK_out; + CPLLREFCLKLOST <= CPLLREFCLKLOST_out; + DMONITOROUT <= DMONITOROUT_out; + DRPDO <= DRPDO_out; + DRPRDY <= DRPRDY_out; + EYESCANDATAERROR <= EYESCANDATAERROR_out; + GTREFCLKMONITOR <= GTREFCLKMONITOR_out; + GTXTXN <= GTXTXN_out; + GTXTXP <= GTXTXP_out; + PCSRSVDOUT <= PCSRSVDOUT_out; + PHYSTATUS <= PHYSTATUS_out; + RXBUFSTATUS <= RXBUFSTATUS_out; + RXBYTEISALIGNED <= RXBYTEISALIGNED_out; + RXBYTEREALIGN <= RXBYTEREALIGN_out; + RXCDRLOCK <= RXCDRLOCK_out; + RXCHANBONDSEQ <= RXCHANBONDSEQ_out; + RXCHANISALIGNED <= RXCHANISALIGNED_out; + RXCHANREALIGN <= RXCHANREALIGN_out; + RXCHARISCOMMA <= RXCHARISCOMMA_out; + RXCHARISK <= RXCHARISK_out; + RXCHBONDO <= RXCHBONDO_out; + RXCLKCORCNT <= RXCLKCORCNT_out; + RXCOMINITDET <= RXCOMINITDET_out; + RXCOMMADET <= RXCOMMADET_out; + RXCOMSASDET <= RXCOMSASDET_out; + RXCOMWAKEDET <= RXCOMWAKEDET_out; + RXDATA <= RXDATA_out; + RXDATAVALID <= RXDATAVALID_out; + RXDISPERR <= RXDISPERR_out; + RXDLYSRESETDONE <= RXDLYSRESETDONE_out; + RXELECIDLE <= RXELECIDLE_out; + RXHEADER <= RXHEADER_out; + RXHEADERVALID <= RXHEADERVALID_out; + RXMONITOROUT <= RXMONITOROUT_out; + RXNOTINTABLE <= RXNOTINTABLE_out; + RXOUTCLK <= RXOUTCLK_out; + RXOUTCLKFABRIC <= RXOUTCLKFABRIC_out; + RXOUTCLKPCS <= RXOUTCLKPCS_out; + RXPHALIGNDONE <= RXPHALIGNDONE_out; + RXPHMONITOR <= RXPHMONITOR_out; + RXPHSLIPMONITOR <= RXPHSLIPMONITOR_out; + RXPRBSERR <= RXPRBSERR_out; + RXQPISENN <= RXQPISENN_out; + RXQPISENP <= RXQPISENP_out; + RXRATEDONE <= RXRATEDONE_out; + RXRESETDONE <= RXRESETDONE_out; + RXSTARTOFSEQ <= RXSTARTOFSEQ_out; + RXSTATUS <= RXSTATUS_out; + RXVALID <= RXVALID_out; + TSTOUT <= TSTOUT_out; + TXBUFSTATUS <= TXBUFSTATUS_out; + TXCOMFINISH <= TXCOMFINISH_out; + TXDLYSRESETDONE <= TXDLYSRESETDONE_out; + TXGEARBOXREADY <= TXGEARBOXREADY_out; + TXOUTCLK <= TXOUTCLK_out; + TXOUTCLKFABRIC <= TXOUTCLKFABRIC_out; + TXOUTCLKPCS <= TXOUTCLKPCS_out; + TXPHALIGNDONE <= TXPHALIGNDONE_out; + TXPHINITDONE <= TXPHINITDONE_out; + TXQPISENN <= TXQPISENN_out; + TXQPISENP <= TXQPISENP_out; + TXRATEDONE <= TXRATEDONE_out; + TXRESETDONE <= TXRESETDONE_out; + end GTXE2_CHANNEL_FAST_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDMACC_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDMACC_MACRO.vhd new file mode 100644 index 0000000..50583ea --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDMACC_MACRO.vhd @@ -0,0 +1,453 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2015 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 2015.3 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : ADDMACC_MACRO.vhd +-- \ \ / \ +-- \___\/\___\ +-- +-- Revision: +-- 04/18/08 - Initial version. +-- 04/09/15 - 852167 - align with verilog +-- End Revision + +----- CELL ADDMACC_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + + +entity ADDMACC_MACRO is + generic ( + DEVICE : string := "VIRTEX6"; + LATENCY : integer := 4; + WIDTH_PREADD : integer := 25; + WIDTH_MULTIPLIER : integer := 18; + WIDTH_PRODUCT : integer := 48 + ); + + port ( + PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0); + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0); + PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0); + PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0); + RST : in std_logic + ); +end entity ADDMACC_MACRO; + +architecture addmacc of ADDMACC_MACRO is + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidthPreadd ( + width : in integer; + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (width > 0 and width <= 25) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") ); + write ( Message, WIDTH_PREADD); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 25 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- begin s1 + else + if (DEVICE = "SPARTAN6" and width > 0 and width <= 18) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") ); + write ( Message, WIDTH_PREADD); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- end s1 + end if; + return func_val; + end; + function GetWidthPreadd ( + device : in string + ) return integer is + variable func_val : integer; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_val := 25; + else + func_val := 18; + DEALLOCATE (Message); + end if; + return func_val; + end; + + function CheckWidthMult ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 18 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_MULTPLIER : ") ); + write ( Message, WIDTH_MULTIPLIER); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidthProd ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 48 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_PRODUCT : ") ); + write ( Message, WIDTH_PRODUCT); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 48 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetABREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3) then + func_width := 1; + elsif (LATENCY = 4 ) then + func_width := 2; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG1_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG0_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetMREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetPREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + else + func_width := 0; + write( Message, STRING'("Illegal value of Attribute LATENCY : ") ); + write ( Message, LATENCY); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 4 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_width; + end; + + function GetOPMODE_IN ( + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_width := 7; + elsif (DEVICE = "SPARTAN6") then + func_width := 8; + else + func_width := 8; + end if; + return func_width; + end; + +--Signal Declarations: + + constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE); + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkWidthPreAdd : boolean := CheckWidthPreAdd(WIDTH_PREADD, DEVICE); + constant MaxWidthPreAdd : integer := GetWidthPreAdd(DEVICE); + constant ChkWidthMult : boolean := CheckWidthMult(WIDTH_MULTIPLIER); + constant ChkWidthProd : boolean := CheckWidthProd(WIDTH_PRODUCT); + constant AREG_IN : integer := GetABREG_IN(LATENCY); + constant BREG_IN : integer := GetABREG_IN(LATENCY); + constant A0REG_IN : integer := GetABREG0_IN(LATENCY); + constant B0REG_IN : integer := GetABREG0_IN(LATENCY); + constant A1REG_IN : integer := GetABREG1_IN(LATENCY); + constant B1REG_IN : integer := GetABREG1_IN(LATENCY); + constant MREG_IN : integer := GetMREG_IN(LATENCY); + constant PREG_IN : integer := GetPREG_IN(LATENCY); + + signal OPMODE_IN : std_logic_vector((OPMODE_WIDTH-1) downto 0); + signal PREADD1_IN : std_logic_vector(29 downto 0) := "000000000000000000000000000000"; + signal PREADD2_IN : std_logic_vector(24 downto 0) := "0000000000000000000000000"; + signal MULTIPLIER_IN : std_logic_vector(17 downto 0) := "000000000000000000"; + signal LOAD_DATA_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal CEA1_IN : std_logic; + signal CEA2_IN : std_logic; + signal CEB1_IN : std_logic; + signal CEB2_IN : std_logic; + +-- Architecture Section: instantiation +begin + + CEA1_IN <= CE when (AREG_IN = 2) else '0'; + CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0'; + CEB1_IN <= CE when (BREG_IN = 2) else '0'; + CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0'; + + v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + OPMODE_IN <= "01" & LOAD & "0101"; + end generate v; + + s : if (DEVICE = "SPARTAN6") generate + OPMODE_IN <= "00011" & LOAD & "01"; + end generate s; + + load1 : if (WIDTH_PRODUCT = 48) generate + begin + LOAD_DATA_IN <= LOAD_DATA; + end generate load1; + load2 : if (WIDTH_PRODUCT < 48) generate + begin + l1: for i in 47 downto WIDTH_PRODUCT generate + LOAD_DATA_IN(i) <= '0'; + end generate; + LOAD_DATA_IN(WIDTH_PRODUCT-1 downto 0) <= LOAD_DATA; + end generate load2; + + pa1 : if (WIDTH_PREADD = MaxWidthPreAdd) generate + begin + PREADD1_IN(MaxWidthPreAdd-1 downto 0) <= PREADD1; + PREADD2_IN(MaxWidthPreAdd-1 downto 0) <= PREADD2; + end generate pa1; + mult1 : if (WIDTH_MULTIPLIER = 18) generate + begin + MULTIPLIER_IN <= MULTIPLIER; + end generate mult1; + pa2 : if (WIDTH_PREADD < MaxWidthPreAdd) generate + begin + pa: for i in MaxWidthPreAdd-1 downto WIDTH_PREADD generate + PREADD1_IN(i) <= PREADD1((WIDTH_PREADD-1)); + PREADD2_IN(i) <= PREADD2((WIDTH_PREADD-1)); + end generate; + PREADD1_IN(WIDTH_PREADD-1 downto 0) <= PREADD1; + PREADD2_IN(WIDTH_PREADD-1 downto 0) <= PREADD2; + end generate pa2; + mult2 : if (WIDTH_MULTIPLIER < 18) generate + begin + m1: for i in 17 downto WIDTH_MULTIPLIER generate + MULTIPLIER_IN(i) <= MULTIPLIER((WIDTH_MULTIPLIER-1)); + end generate; + MULTIPLIER_IN(WIDTH_MULTIPLIER-1 downto 0) <= MULTIPLIER; + end generate mult2; + + PRODUCT <= RESULT_OUT(WIDTH_PRODUCT-1 downto 0); + + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_1: DSP48E1 + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN, + USE_DPORT => TRUE) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => PREADD1_IN, + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => MULTIPLIER_IN, + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN, + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEAD => CE, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => CE, + CEINMODE => CE, + CEM => CE, + CEP => CE, + CLK => CLK, + D => PREADD2_IN, + INMODE => "00100", + MULTSIGNIN => '0', + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); +end generate bl; +-- end generate virtex6 +-- begin generate spartan6 +st : if DEVICE = "SPARTAN6" generate + begin + DSP48E_2: DSP48A1 + generic map ( + A0REG => A0REG_IN, + A1REG => A1REG_IN, + B0REG => B0REG_IN, + B1REG => B1REG_IN, + MREG => MREG_IN, + PREG => PREG_IN ) + port map ( + BCOUT => open, + CARRYOUT => open, + CARRYOUTF => open, + M => open, + P => RESULT_OUT, + PCOUT => open, + A => MULTIPLIER_IN, + B => PREADD1_IN(17 downto 0), + C => LOAD_DATA_IN, + CARRYIN => CARRYIN, + CEA => CE, + CEB => CE, + CEC => CE, + CECARRYIN => '0', + CED => CE, + CEM => CE, + CEOPMODE => CE, + CEP => CE, + CLK => CLK, + D => PREADD2_IN(17 downto 0), + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTB => RST, + RSTC => RST, + RSTCARRYIN => RST, + RSTD => RST, + RSTM => RST, + RSTOPMODE => RST, + RSTP => RST + ); + end generate st; +-- end generate spartan6 + + +end addmacc; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDSUB_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDSUB_MACRO.vhd new file mode 100644 index 0000000..063b371 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDSUB_MACRO.vhd @@ -0,0 +1,404 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2015 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 2015.3 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : ADDSUB_MACRO.vhd +-- \ \ / \ +-- \___\/\___\ +-- +-- Revision: +-- 06/06/08 - Initial version. +-- 04/18/11 - 652098 - Fix for latency 0 +-- 10/27/14 - Added missing ALUMODEREG (CR 827820). +-- 04/09/15 - 852167 - align with verilog +-- End Revision + +----- CELL ADDSUB_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + + +entity ADDSUB_MACRO is + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 2; + STYLE : string := "DSP"; + WIDTH : integer := 48; + WIDTH_B : integer := 48; + WIDTH_RESULT : integer := 48; + MODEL_TYPE : integer := 0; + VERBOSITY : integer := 0 + ); + + port ( + CARRYOUT : out std_logic; + RESULT : out std_logic_vector(WIDTH-1 downto 0); + A : in std_logic_vector(WIDTH-1 downto 0); + ADD_SUB : in std_logic; + B : in std_logic_vector(WIDTH-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end entity ADDSUB_MACRO; + +architecture addsub of ADDSUB_MACRO is + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckStyle ( + style : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (style = "AUTO" or style = "DSP" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute STYLE : ") ); + write ( Message, STYLE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" AUTO, DSP ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckLatency ( + lat : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (LATENCY = 0 or LATENCY = 1 or LATENCY = 2) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute LATENCY : ") ); + write ( Message, LATENCY); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 0, 1, 2. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidth ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 48 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH : ") ); + write ( Message, WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 48 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + + function GetABREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetPREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 1 or LATENCY = 2 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + + +--Signal Declarations: + + signal ALUMODE_IN : std_logic_vector(3 downto 0); + signal OPMODEST_IN : std_logic_vector(7 downto 0); + signal A_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal B_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal A_INST : std_logic_vector(17 downto 0) := "000000000000000000"; + signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal CARRYOUT_OUT : std_logic_vector(3 downto 0); + signal CARRYOUTST : std_logic; + signal CARRYIN_IN : std_logic; + + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkStyle : boolean := CheckStyle(STYLE); + constant ChkWidth : boolean := CheckWidth(WIDTH); + constant ChkLatency : boolean := CheckLatency(LATENCY); + constant AREG_IN : integer := GetABREG_IN(LATENCY); + constant ALUMODEREG_IN : integer := GetABREG_IN(LATENCY); + constant BREG_IN : integer := GetABREG_IN(LATENCY); + constant CREG_IN : integer := GetABREG_IN(LATENCY); + constant PREG_IN : integer := GetPREG_IN(LATENCY); + +-- Architecture Section: instantiation +begin + + ALUMODE_IN <= "00" & (not ADD_SUB) & (not ADD_SUB); + CARRYIN_IN <= CARRYIN when (WIDTH = 48) else '0'; + + OPMODEST_IN <= (not ADD_SUB) & (not ADD_SUB) & "001111"; + + add48 : if (WIDTH = 48) generate + begin + A_IN <= A; + B_IN <= B; + end generate add48; + add : if (WIDTH < 48) generate + begin + A_IN(47 downto (47-(WIDTH-1))) <= A; + A_IN((47-WIDTH)) <= ADD_SUB; + sa: for i in (47-(WIDTH+1)) downto 0 generate + A_IN(i) <= '0'; + end generate; + B_IN(47 downto (47-(WIDTH-1))) <= B; + B_IN((47-WIDTH)) <= CARRYIN; + sb: for i in (47-(WIDTH+1)) downto 0 generate + B_IN(i) <= '0'; + end generate; + end generate add; + + A_INST <= "000000" & A_IN(47 downto 36); + RESULT <= RESULT_OUT(47 downto (47-(WIDTH-1))); + + c1: if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + CARRYOUT <= CARRYOUT_OUT(3); + end generate c1; + -- begin s1 + c2: if (DEVICE = "SPARTAN6") generate + CARRYOUT <= CARRYOUTST; + end generate c2; + -- end s1 + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + begin + DSP48_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + ALUMODEREG => ALUMODEREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + CREG => CREG_IN, + PREG => PREG_IN, + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => CARRYOUT_OUT(3 downto 0), + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => B_IN(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => B_IN(17 downto 0), + BCIN => "000000000000000000", + C => A_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN_IN, + CARRYINSEL => "000", + CEA1 => CE, + CEA2 => CE, + CEALUMODE => CE, + CEB1 => CE, + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => '0', + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => "0110011", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); + end generate v5; + -- end generate virtex5 + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48_2: DSP48E1 + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + ADREG => 0, + ALUMODEREG => ALUMODEREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + CREG => CREG_IN, + DREG => 0, + MREG => 0, + PREG => PREG_IN, + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => CARRYOUT_OUT, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => B_IN(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => B_IN(17 downto 0), + BCIN => "000000000000000000", + C => A_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN_IN, + CARRYINSEL => "000", + CEA1 => CE, + CEA2 => CE, + CEAD => '0', + CEALUMODE => CE, + CEB1 => CE, + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => '0', + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => "0110011", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); + end generate bl; + -- end generate virtex6 + -- begin generate spartan6 + st : if DEVICE = "SPARTAN6" generate + begin + DSP48_3: DSP48A1 + generic map ( + A1REG => AREG_IN, + B1REG => BREG_IN, + CREG => CREG_IN, + PREG => PREG_IN ) + port map ( + BCOUT => open, + CARRYOUT => CARRYOUTST, + CARRYOUTF => open, + M => open, + P => RESULT_OUT, + PCOUT => open, + A => A_IN(35 downto 18), + B => A_IN(17 downto 0), + C => B_IN, + CARRYIN => CARRYIN_IN, + CEA => CE, + CEB => CE, + CEC => CE, + CECARRYIN => CE, + CED => CE, + CEM => '0', + CEOPMODE => CE, + CEP => CE, + CLK => CLK, + D => A_INST, + OPMODE => OPMODEST_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTB => RST, + RSTC => RST, + RSTCARRYIN => RST, + RSTD => RST, + RSTM => RST, + RSTOPMODE => RST, + RSTP => RST + ); + end generate st; + -- end generate spartan6 +end addsub; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SDP_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SDP_MACRO.vhd new file mode 100644 index 0000000..a5e9da3 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SDP_MACRO.vhd @@ -0,0 +1,3923 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 14.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for Simple Dual Port Block RAM +-- /___/ /\ Filename : BRAM_SDP_MACRO.vhd +-- \ \ / \ Timestamp : Wed April 18 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 04/11/06 - Initial version. +-- 04/28/10 - 605949 - Corrected V6 SDP mode +-- 05/04/11 - 609013 - Corrected DIP for width 72. +-- 05/25/11 - 607722 - Reset output latch for DO_REG=1 +-- 10/26/11 - 624543 - Fix DO for assymetric widths, drc to check for read,write widths equal or ratio of 2. +-- 11/30/11 - 636062 - Fix drc and do +-- 01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking. +-- 04/24/12 - 657517 - fix for write_width = 2* read_width +-- 11/01/12 - 679413 - pass INIT_FILE to Spartan6 BRAM +-- 09/29/14 - Update DI and DO for parity intersperse every byte (CR 773917). +-- End Revision + +----- CELL BRAM_SDP_MACRO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library unisim; +use unisim.VCOMPONENTS.all; +library STD; +use STD.TEXTIO.ALL; + + +entity BRAM_SDP_MACRO is +generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT : bit_vector := X"000000000000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH : integer := 0; + WRITE_MODE : string := "WRITE_FIRST"; + WRITE_WIDTH : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; -- This parameter is valid only for Virtex5 + SRVAL : bit_vector := X"000000000000000000" + + + ); +-- ports are unconstrained arrays +port ( + + DO : out std_logic_vector(READ_WIDTH-1 downto 0); + + DI : in std_logic_vector(WRITE_WIDTH-1 downto 0); + RDADDR : in std_logic_vector; + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + RST : in std_ulogic; + WE : in std_logic_vector; + WRADDR : in std_logic_vector; + WRCLK : in std_ulogic; + WREN : in std_ulogic + + ); +end BRAM_SDP_MACRO; + +architecture bram_V of BRAM_SDP_MACRO is + + function GetWEWidth ( + bram_size : in string; + device : in string; + wr_width : in integer + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size= "18Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + end if; + elsif bram_size = "36Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + elsif wr_width > 36 and wr_width <= 72 then + func_width := 8; + end if; + else + func_width := 8; + end if; + -- begin s1 + elsif(DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; + elsif bram_size = "18Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; + end if; -- end s1 + else + func_width := 8; + end if; + return func_width; + end; + + function GetDataWidth ( + rd_width : in integer; + wr_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5") then + if rd_width = wr_width then + func_width := rd_width; + else + write( Message, STRING'("Illegal values of Attributes READ_WIDTH, WRITE_WIDTH : ") ); + write ( Message, READ_WIDTH); + write ( Message, STRING'(" and ")); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". To use BRAM_SDP_MACRO, READ_WIDTH and WRITE_WIDTH must be equal ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + if (DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if rd_width = wr_width then + func_width := rd_width; + elsif ((rd_width /= wr_width) and (rd_width/wr_width /=2) and (wr_width/rd_width /=2) and ((rd_width /= 1 and rd_width /= 2 and rd_width /= 4 and rd_width /= 8 and rd_width /= 9 and rd_width /= 16 and rd_width /= 18 and rd_width /= 32 and rd_width /= 36 and rd_width /= 64 and rd_width /= 72) or (wr_width /= 1 and wr_width /= 2 and wr_width /= 4 and wr_width /= 8 and wr_width /= 9 and wr_width /= 16 and wr_width /= 18 and wr_width /= 32 and wr_width /= 36 and wr_width /= 64 and wr_width /= 72)) ) then + write( Message, STRING'("Illegal values of Attributes READ_WIDTH, WRITE_WIDTH : ") ); + write ( Message, READ_WIDTH); + write ( Message, STRING'(" and ")); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(" To use BRAM_SDP_MACRO. One of the following conditions must be true- 1. READ_WIDTH must be equal to WRITE_WIDTH 2. If assymetric, READ_WIDTH and WRITE_WIDTH must have a ratio of 2. 3. If assymetric, READ_WIDTH and WRITE_WIDTH should have values 1, 2, 4, 8, 9, 16, 18, 32, 36, 64, 72.") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if rd_width = 0 then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s2 + elsif (DEVICE = "SPARTAN6" and bram_size = "9Kb" and rd_width > 36 and DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s2 + elsif bram_size = "18Kb" and rd_width > 36 then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + elsif bram_size = "36Kb" and rd_width > 72 then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 9Kb, 18Kb and ") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + if wr_width = 0 then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s3 + elsif (DEVICE = "SPARTAN6" and bram_size = "9Kb" and wr_width > 36) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s3 + elsif bram_size = "18Kb" and wr_width > 36 then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + elsif bram_size = "36Kb" and wr_width > 72 then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 9Kb, 18Kb and") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + if (DEVICE = "SPARTAN6" and bram_size = "9Kb" and (wr_width > 18 or rd_width > 18) and ( write_width /= read_width) ) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(" . Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". For BRAM_SIZE 9Kb and read or write widths greater than 18 ") ); + write( Message, STRING'(" same port width must be used for read and write.") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end sx + end if; + + end if; + return func_width; + end; + + function GetWriteBusSize ( + w_width : in integer; + dip_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case w_width is + when 0 => func_width := 1; + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if(bram_size = "36Kb") then + func_width := 32; + else + func_width := w_width - dip_width; + end if; + when 37 to 72 => func_width := w_width - dip_width; + when others => func_width := 64; + end case; + else + func_width := 64; + end if; + return func_width; + end; + + function GetReadBusSize ( + r_width : in integer; + dop_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case r_width is + when 0 => func_width := 1; + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if(bram_size = "36Kb") then + func_width := 32; + else + func_width := r_width - dop_width; + end if; + when 37 to 72 => func_width := r_width - dop_width; + when others => func_width := 64; + end case; + else + func_width := 64; + end if; + return func_width; + end; + + function GetDataPSize ( + d_width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case d_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 0; + end case; + else + func_width := 0; + end if; + return func_width; + end; + + function GetMaxADDRSize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 14; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 9; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 16; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 9; + else + func_width := 16; + end if; + -- begin b1 + elsif ( DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" then + func_width := 14; + elsif bram_size = "36Kb" then + func_width := 16; + else + func_width := 16; + end if; -- end b1 + -- begin s4 + elsif ( DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + func_width := 13; + elsif bram_size = "18Kb" then + func_width := 14; + else + func_width := 14; + end if; -- end s4 + else + func_width := 16; + end if; + return func_width; + end; + + function GetMaxDataSize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 16; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 32; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 32; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 64; + else + func_width := 64; + end if; + -- begin s5 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 16; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 32; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 32; + else + func_width := 32; + end if; -- end s5 + else + func_width := 64; + end if; + return func_width; + end; + + function GetMaxDataPSize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 8; + else + func_width := 8; + end if; + -- begin s6 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; -- end s6 + else + func_width := 8; + end if; + return func_width; + end; + function GetMaxWESize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 8; + else + func_width := 8; + end if; + -- begin b4 + elsif (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width <= 72 then + func_width := 8; + else + func_width := 4; + end if; -- end b4 + -- begin s7 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; -- end s7 + else + func_width := 8; + end if; + return func_width; + end; + function GetADDRWidth ( + d_width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case d_width is + when 1 => if (func_bram_size = "9Kb") then + func_width := 13; + elsif (func_bram_size = "18Kb") then + func_width := 14; + else + func_width := 15; + end if; + when 2 => if (func_bram_size = "9Kb") then + func_width := 12; + elsif (func_bram_size = "18Kb") then + func_width := 13; + else + func_width := 14; + end if; + when 3|4 => if (func_bram_size = "9Kb") then + func_width := 11; + elsif (func_bram_size = "18Kb") then + func_width := 12; + else + func_width := 13; + end if; + when 5|6|7|8|9 => if (func_bram_size = "9Kb") then + func_width := 10; + elsif (func_bram_size = "18Kb") then + func_width := 11; + else + func_width := 12; + end if; + when 10 to 18 => if (func_bram_size = "9Kb") then + func_width := 9; + elsif (func_bram_size = "18Kb") then + func_width := 10; + else + func_width := 11; + end if; + when 19 to 36 => if (func_bram_size = "9Kb") then + func_width := 8; + elsif (func_bram_size = "18Kb") then + func_width := 9; + elsif (func_bram_size = "36Kb") then + func_width := 10; + else + func_width := 14; + end if; + when 37 to 72 => if (func_bram_size = "36Kb") then + func_width := 9; + end if; + when others => func_width := 15; + end case; + else + func_width := 15; + end if; + return func_width; + end; + + function GetWidthDP ( + d_width : in integer; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case d_width is + when 0 => func_width := 0; + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 9; + when 10 to 18 => func_width := 18; + when 19 to 36 => func_width := 36; + when 37 to 72 => func_width := 72; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetFinalWidth ( + d_width : in integer + ) return integer is + variable func_least_width : integer; + begin + if (d_width = 0) then + func_least_width := 1; + else + func_least_width := d_width; + end if; + return func_least_width; + end; + + function GetBRAMSize ( + bram_size : in string; + device : in string + ) return boolean is + variable bram_val : boolean; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "36Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 18Kb, 36Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + -- begin s8 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" or bram_size = "18Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 9Kb, 18Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; -- end s8 + + return bram_val; + end; + function GetD_P ( + dw : in integer; + device : in string + ) return boolean is + variable wp : boolean; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then + wp := TRUE; + else + wp := FALSE; + end if; + else + wp := FALSE; + end if; + return wp; + end; + function CheckParity ( + wp, rp : in boolean; + device : in string + ) return boolean is + variable Message : LINE; + variable check : boolean; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if ( (wp = FALSE and rp = FALSE ) or (wp = TRUE and rp = TRUE) ) then + check := FALSE; + elsif(wp = TRUE and rp = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("WRITE_WIDTH on BRAM_SDP_MACRO is set to ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp = FALSE and rp = TRUE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("READ_WIDTH on BRAM_SDP_MACRO is set to ") ); + write( Message, READ_WIDTH); + write( Message, STRING'(". The parity bit(s) have not been written and hence cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + end if; + end if; + return check; + end; + function GetINITSRVALWidth ( + bram_size : in string; + device : in string + ) return integer is + variable init_srval : integer; + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(bram_size = "18Kb") then + init_srval := 20; + elsif (bram_size = "36Kb") then + init_srval := 36; + end if; + end if; + -- begin s12 + if ( DEVICE = "SPARTAN6") then + if(bram_size = "9Kb") then + init_srval := 20; + elsif(bram_size = "18Kb") then + init_srval := 20; + end if; + end if; -- end s12 + return init_srval; + end; + function init_b_size ( + inputvec : in bit_vector; + init_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable init_b_resize : bit_vector(0 to (init_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((bram_size = "18Kb") and ((rd_width > 18) and (wr_width > 18))) then + init_b_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif ((bram_size = "36Kb") and ((rd_width > 36) and (wr_width > 36))) then + init_b_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; + -- begin s13 + if ( DEVICE = "SPARTAN6") then + if((bram_size = "9Kb") and ((rd_width > 18) and (wr_width > 18))) then + init_b_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + end if; + end if; -- end s13 + return init_b_resize; + end; + function init_a_size ( + inputvec : in bit_vector; + init_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable init_a_resize : bit_vector(0 to (init_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((bram_size = "18Kb") and ((rd_width > 18) and (wr_width > 18))) then + init_a_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif ((bram_size = "36Kb") and ((rd_width > 36) and (wr_width > 36))) then + init_a_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; + -- begin s14 + if ( DEVICE = "SPARTAN6") then + if((bram_size = "9Kb") and ((rd_width > 18) and (wr_width > 18))) then + init_a_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + end if; + end if; -- end s14 + return init_a_resize; + end; + function srval_b_size ( + inputvec : in bit_vector; + srval_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable srval_b_resize : bit_vector(0 to (srval_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((bram_size = "18Kb") and ((rd_width > 18) and (wr_width > 18))) then + srval_b_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif ((bram_size = "36Kb") and ((rd_width > 36) and (wr_width > 36))) then + srval_b_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; + -- begin s15 + if ( DEVICE = "SPARTAN6") then + if((bram_size = "9Kb") and ((rd_width > 18) and (wr_width > 18))) then + srval_b_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + end if; + end if; -- end s15 + return srval_b_resize; + end; + function srval_a_size ( + inputvec : in bit_vector; + srval_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable srval_a_resize : bit_vector(0 to (srval_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((bram_size = "18Kb") and ((rd_width > 18) and (wr_width > 18))) then + srval_a_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif ((bram_size = "36Kb") and ((rd_width > 36) and (wr_width > 36))) then + srval_a_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; + -- begin s16 + if ( DEVICE = "SPARTAN6") then + if((bram_size = "9Kb") and ((rd_width > 18) and (wr_width > 18))) then + srval_a_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + end if; + end if; -- end s16 + return srval_a_resize; + end; + + function GetSIMDev ( + device : in string + ) return string is + begin + if(DEVICE = "VIRTEX6") then + return "VIRTEX6"; + else + return "7SERIES"; + end if; + end; + + function GetValWidth ( + rd_width : in integer; + wr_width : in integer + ) return boolean is + begin + if ((rd_width = 1 or rd_width = 2 or rd_width = 4 or rd_width = 8 or rd_width = 9 or rd_width = 16 or rd_width = 18 or rd_width = 32 or rd_width = 36 or rd_width = 64 or rd_width = 72) and (wr_width = 1 or wr_width = 2 or wr_width = 4 or wr_width = 8 or wr_width = 9 or wr_width = 16 or wr_width = 18 or wr_width = 32 or wr_width = 36 or wr_width = 64 or wr_width = 72)) then + return TRUE; + else + return FALSE; + end if; + end; + + function CheckWEWidth ( + wr_width : in integer; + we_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if ( wr_width <= 9 and we_vec /= 1) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 1 (0 downto 0) . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 9 and wr_width <= 18) and we_vec /= 2) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 2 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 18 and wr_width <= 36) and we_vec /= 4) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 4 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 36 and wr_width <= 72) and we_vec /= 8) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 8 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + end; + + function CheckRDADDRWidth ( + rd_width : in integer; + func_bram_size : in string; + device : in string; + rdaddr_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if (func_bram_size = "9Kb") then + if (rd_width = 1 and rdaddr_vec /= 13) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (rd_width = 2 and rdaddr_vec /= 12) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 2 and rd_width <= 4) and rdaddr_vec /= 11) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 4 and rd_width <= 9) and rdaddr_vec /= 10) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 9 and rd_width <= 18) and rdaddr_vec /= 9) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 18 and rd_width <= 36) and rdaddr_vec /= 8) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 8 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "18Kb") then + if (rd_width = 1 and rdaddr_vec /= 14) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (rd_width = 2 and rdaddr_vec /= 13) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 2 and rd_width <= 4) and rdaddr_vec /= 12) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 4 and rd_width <= 9) and rdaddr_vec /= 11) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 9 and rd_width <= 18) and rdaddr_vec /= 10) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 18 and rd_width <= 36) and rdaddr_vec /= 9) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "36Kb") then + if (rd_width = 1 and rdaddr_vec /= 15) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 15 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (rd_width = 2 and rdaddr_vec /= 14) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 2 and rd_width <= 4) and rdaddr_vec /= 13) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 4 and rd_width <= 9) and rdaddr_vec /= 12) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 9 and rd_width <= 18) and rdaddr_vec /= 11) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 18 and rd_width <= 36) and rdaddr_vec /= 10) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((rd_width > 36 and rd_width <= 72) and rdaddr_vec /= 9) then + write( Message, STRING'("RDADDR port width incorrectly set. ") ); + write( Message, STRING'(". RDADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + else + return TRUE; + end if; + end; + + function CheckWRADDRWidth ( + wr_width : in integer; + func_bram_size : in string; + device : in string; + wraddr_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if (func_bram_size = "9Kb") then + if (wr_width = 1 and wraddr_vec /= 13) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (wr_width = 2 and wraddr_vec /= 12) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 2 and wr_width <= 4) and wraddr_vec /= 11) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 4 and wr_width <= 9) and wraddr_vec /= 10) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 9 and wr_width <= 18) and wraddr_vec /= 9) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 18 and wr_width <= 36) and wraddr_vec /= 8) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 8 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "18Kb") then + if (wr_width = 1 and wraddr_vec /= 14) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (wr_width = 2 and wraddr_vec /= 13) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 2 and wr_width <= 4) and wraddr_vec /= 12) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 4 and wr_width <= 9) and wraddr_vec /= 11) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 9 and wr_width <= 18) and wraddr_vec /= 10) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 18 and wr_width <= 36) and wraddr_vec /= 9) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "36Kb") then + if (wr_width = 1 and wraddr_vec /= 15) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 15 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (wr_width = 2 and wraddr_vec /= 14) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 2 and wr_width <= 4) and wraddr_vec /= 13) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 4 and wr_width <= 9) and wraddr_vec /= 12) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 9 and wr_width <= 18) and wraddr_vec /= 11) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 18 and wr_width <= 36) and wraddr_vec /= 10) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((wr_width > 36 and wr_width <= 72) and wraddr_vec /= 9) then + write( Message, STRING'("WRADDR port width incorrectly set. ") ); + write( Message, STRING'(". WRADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + else + return TRUE; + end if; + end; + + + function Get_Parity_Width ( + wd : in integer + ) return integer is + variable wp : integer; + begin + if (wd = 9 or wd = 17 or wd = 33 or wd = 65) then + wp := 1; + elsif (wd = 18 or wd = 34 or wd = 66) then + wp := 2; + elsif (wd = 35 or wd = 67) then + wp := 3; + elsif (wd = 36 or wd = 68) then + wp := 4; + elsif (wd = 69) then + wp := 5; + elsif (wd = 70) then + wp := 6; + elsif (wd = 71) then + wp := 7; + elsif (wd = 72) then + wp := 8; + else + wp := 8; + end if; + return wp; + end; + + function Pad_INIT_SRVAL ( + func_in_init_srval : in bit_vector; + func_init_srval_width_size : in integer) + return bit_vector is variable func_paded_init_srval : bit_vector(0 to func_init_srval_width_size-1) := (others=>'0'); + variable func_padded_width : integer; + begin + + if (func_in_init_srval'length > func_init_srval_width_size) then + func_padded_width := func_init_srval_width_size; + else + func_padded_width := func_in_init_srval'length; + end if; + + for i in 0 to func_padded_width-1 loop + func_paded_init_srval(((func_init_srval_width_size-1) - (func_padded_width-1)) + i) := func_in_init_srval(i); + end loop; + + return func_paded_init_srval; + end; + + + function Get_INIT_SRVAL_Width ( + func_bram_size : in string; + func_device : in string) + return integer is variable init_srval_width : integer; + begin + if(bram_size = "36Kb") then + if (READ_WIDTH > 36 or WRITE_WIDTH > 36) then + init_srval_width := 72; + else + init_srval_width := 36; + end if; + + elsif(bram_size = "18Kb") then + if (func_device = "SPARTAN6" or (READ_WIDTH > 18 or WRITE_WIDTH > 18)) then + init_srval_width := 36; + else + init_srval_width := 20; + end if; + elsif (bram_size = "9Kb") then + if (WRITE_WIDTH > 18) then + init_srval_width := 36; + else + init_srval_width := 20; + end if; + else + init_srval_width := 36; + end if; + + return init_srval_width; + end; + + + function INIT_SRVAL_parity_byte ( + in_init_srval : in bit_vector; + readp : in boolean; + writep : in boolean; + read_widthp : in integer; + init_srval_width : in integer) + return bit_vector is variable out_init_srval : bit_vector(0 to in_init_srval'length-1); + begin + + if (readp = TRUE and writep = TRUE) then + + if (read_widthp = 9) then + if (init_srval_width = 20) then + out_init_srval := "00000000000" & in_init_srval(11) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "000000000000000000000000000" & in_init_srval(27) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"000000000000000" & in_init_srval(63) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 17) then + if (init_srval_width = 20) then + out_init_srval := "000" & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "0000000000000000000" & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"0000000000000" & in_init_srval(63) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 18) then + if (init_srval_width = 20) then + out_init_srval := "00" & in_init_srval(2) & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "000000000000000000" & in_init_srval(18) & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "00" & X"0000000000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 33) then + if (init_srval_width = 36) then + out_init_srval := "000" & in_init_srval(27) & in_init_srval(3 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"000000000" & in_init_srval(63) & in_init_srval(39 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 34) then + if (init_srval_width = 36) then + out_init_srval := "00" & in_init_srval(18) & in_init_srval(27) & in_init_srval(2 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "00" & X"000000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(38 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 35) then + if (init_srval_width = 36) then + out_init_srval := '0' & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := '0' & X"000000000" & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 36) then + if (init_srval_width = 36) then + out_init_srval := in_init_srval(0) & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := X"000000000" & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 65) then + out_init_srval := "0000000" & in_init_srval(63) & in_init_srval(7 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 66) then + out_init_srval := "000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(6 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 67) then + out_init_srval := "00000" & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(5 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 68) then + out_init_srval := "0000" & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(4 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 69) then + out_init_srval := "000" & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(3 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 70) then + out_init_srval := "00" & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(2 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 71) then + out_init_srval := '0' & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 72) then + out_init_srval := in_init_srval(0) & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + else + out_init_srval := in_init_srval; + end if; + + else + out_init_srval := in_init_srval; + end if; + + return out_init_srval; + + end; + + constant data_width : integer := GetDataWidth(READ_WIDTH, WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant wrwidth : integer := GetWidthDP(WRITE_WIDTH, DEVICE); + constant rdwidth : integer := GetWidthDP(READ_WIDTH, DEVICE); + constant bram_size_val : boolean := GetBRAMSize(BRAM_SIZE, DEVICE); + constant write_p : boolean := GetD_P(WRITE_WIDTH, DEVICE); + constant read_p : boolean := GetD_P(READ_WIDTH, DEVICE); + constant check_p : boolean := CheckParity(write_p, read_p, DEVICE); + constant dip_width : integer := GetDataPSize(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant dop_width : integer := GetDataPSize(READ_WIDTH, BRAM_SIZE, DEVICE); + constant wraddr_width : integer := GetADDRWidth(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant rdaddr_width : integer := GetADDRWidth(READ_WIDTH, BRAM_SIZE, DEVICE); + constant write_size : integer := GetWriteBusSize(WRITE_WIDTH, dip_width, BRAM_SIZE, DEVICE); + constant read_size : integer := GetReadBusSize(READ_WIDTH, dop_width, BRAM_SIZE, DEVICE); + constant we_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, WRITE_WIDTH); + constant rd_byte_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, READ_WIDTH); + constant fin_wr_width : integer := GetFinalWidth(WRITE_WIDTH); + constant fin_rd_width : integer := GetFinalWidth(READ_WIDTH); + constant max_rdaddr_width : integer := GetMaxADDRSize(READ_WIDTH, BRAM_SIZE, DEVICE); + constant max_wraddr_width : integer := GetMaxADDRSize(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant max_write_width : integer := GetMaxDataSize(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant max_read_width : integer := GetMaxDataSize(READ_WIDTH, BRAM_SIZE, DEVICE); + constant max_writep_width : integer := GetMaxDataPSize(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant max_readp_width : integer := GetMaxDataPSize(READ_WIDTH, BRAM_SIZE, DEVICE); + constant max_we_width : integer := GetMaxWESize(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant sim_device_dp : string := GetSIMDev(DEVICE); + constant valid_width : boolean := GetValWidth(READ_WIDTH,WRITE_WIDTH); + constant weleng : integer := WE'length; + constant rdaddrleng : integer := RDADDR'length; + constant wraddrleng : integer := WRADDR'length; + constant checkwe : boolean := CheckWEWidth(WRITE_WIDTH, weleng); + constant checkrdaddr : boolean := CheckRDADDRWidth(READ_WIDTH, BRAM_SIZE, DEVICE, rdaddrleng); + constant checkwraddr : boolean := CheckWRADDRWidth(WRITE_WIDTH, BRAM_SIZE, DEVICE, wraddrleng); + + signal rdaddr_pattern : std_logic_vector(max_rdaddr_width-1 downto 0) := (others=>'0'); + signal wraddr_pattern : std_logic_vector(max_wraddr_width-1 downto 0) := (others=>'0'); + signal di_pattern : std_logic_vector(max_write_width-1 downto 0) := (others=>'0'); + signal dip_pattern : std_logic_vector(max_writep_width-1 downto 0) := (others=>'0'); + signal do_pattern : std_logic_vector(max_read_width-1 downto 0); + signal dop_pattern : std_logic_vector(max_readp_width-1 downto 0) := (others=>'0'); + signal we_pattern : std_logic_vector(max_we_width-1 downto 0) := (others=>'0'); + + signal rstram_pattern : std_logic := '0'; + signal rstreg_pattern : std_logic := '0'; + constant init_srval_width : integer := GetINITSRVALWidth(BRAM_SIZE, DEVICE); + + constant init_srval_width_size : integer := Get_INIT_SRVAL_Width(BRAM_SIZE, DEVICE); + constant padded_init : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(INIT, init_srval_width_size); + constant padded_srval : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(SRVAL, init_srval_width_size); + constant wr_widthp : integer := Get_Parity_Width(WRITE_WIDTH); + constant rd_widthp : integer := Get_Parity_Width(READ_WIDTH); + + + signal INIT_byte_tmp : bit_vector(0 to INIT'length -1) := (others => '0'); + + constant init_a_pattern : bit_vector := init_a_size(INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant init_b_pattern : bit_vector := init_b_size(INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant srval_a_pattern : bit_vector := srval_a_size(INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant srval_b_pattern : bit_vector := srval_b_size(INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + + constant read_double :integer:= READ_WIDTH * 2; + +begin + + a1 : rdaddr_pattern <= + -- begin s9 + RDADDR when (BRAM_SIZE = "9Kb" and rdaddr_width = 13 ) else + (RDADDR & '1') when (BRAM_SIZE = "9Kb" and rdaddr_width = 12 ) else + (RDADDR & "11") when (BRAM_SIZE = "9Kb" and rdaddr_width = 11 ) else + (RDADDR & "111") when (BRAM_SIZE = "9Kb" and rdaddr_width = 10) else + (RDADDR & "1111") when (BRAM_SIZE = "9Kb" and rdaddr_width = 9 ) else + (RDADDR & "11111") when (BRAM_SIZE = "9Kb" and rdaddr_width = 8 ) else -- end s9 + RDADDR when (BRAM_SIZE = "18Kb" and rdaddr_width = 14 ) else + (RDADDR & '1') when (BRAM_SIZE = "18Kb" and rdaddr_width = 13 ) else + (RDADDR & "11") when (BRAM_SIZE = "18Kb" and rdaddr_width = 12) else + (RDADDR & "111") when (BRAM_SIZE = "18Kb" and rdaddr_width = 11 ) else + (RDADDR & "1111") when (BRAM_SIZE = "18Kb" and rdaddr_width = 10) else + RDADDR when (DEVICE = "VIRTEX5" and BRAM_SIZE = "18Kb" and rdaddr_width = 9) else + (RDADDR & "11111") when ( BRAM_SIZE = "18Kb" and rdaddr_width = 9) else + RDADDR when (BRAM_SIZE = "36Kb" and rdaddr_width = 16 ) else + ('1' & RDADDR) when (BRAM_SIZE = "36Kb" and rdaddr_width = 15 ) else + ('1' & RDADDR & '1') when (BRAM_SIZE = "36Kb" and rdaddr_width = 14 ) else + ('1' & RDADDR & "11") when (BRAM_SIZE = "36Kb" and rdaddr_width = 13 ) else + ('1' & RDADDR & "111") when (BRAM_SIZE = "36Kb" and rdaddr_width = 12 ) else + ('1' & RDADDR & "1111") when (BRAM_SIZE = "36Kb" and rdaddr_width = 11 ) else + ('1' & RDADDR & "11111") when (BRAM_SIZE = "36Kb" and rdaddr_width = 10) else + RDADDR when (DEVICE = "VIRTEX5" and BRAM_SIZE = "36Kb" and rdaddr_width = 9) else + ('1' & RDADDR & "111111") when (BRAM_SIZE = "36Kb" and rdaddr_width = 9) else + (others => '1') ; + a2 : wraddr_pattern <= + -- begin s10 + WRADDR when (BRAM_SIZE = "9Kb" and wraddr_width = 13 ) else + (WRADDR & '1') when (BRAM_SIZE = "9Kb" and wraddr_width = 12 ) else + (WRADDR & "11") when (BRAM_SIZE = "9Kb" and wraddr_width = 11) else + (WRADDR & "111") when (BRAM_SIZE = "9Kb" and wraddr_width = 10) else + (WRADDR & "1111") when (BRAM_SIZE = "9Kb" and wraddr_width = 9) else + (WRADDR & "11111") when (BRAM_SIZE = "9Kb" and wraddr_width = 8) else -- end s10 + WRADDR when (BRAM_SIZE = "18Kb" and wraddr_width = 14 ) else + (WRADDR & '1') when (BRAM_SIZE = "18Kb" and wraddr_width = 13 ) else + (WRADDR & "11") when (BRAM_SIZE = "18Kb" and wraddr_width = 12 ) else + (WRADDR & "111") when (BRAM_SIZE = "18Kb" and wraddr_width = 11 ) else + (WRADDR & "1111") when (BRAM_SIZE = "18Kb" and wraddr_width = 10) else + (WRADDR) when (DEVICE = "VIRTEX5" and BRAM_SIZE = "18Kb" and wraddr_width = 9) else + (WRADDR & "11111") when ( BRAM_SIZE = "18Kb" and wraddr_width = 9) else + WRADDR when (BRAM_SIZE = "36Kb" and wraddr_width = 16 ) else + ('1' & WRADDR) when (BRAM_SIZE = "36Kb" and wraddr_width = 15) else + ('1' & WRADDR & '1') when (BRAM_SIZE = "36Kb" and wraddr_width = 14) else + ('1' & WRADDR & "11") when (BRAM_SIZE = "36Kb" and wraddr_width = 13) else + ('1' & WRADDR & "111") when (BRAM_SIZE = "36Kb" and wraddr_width = 12) else + ('1' & WRADDR & "1111") when (BRAM_SIZE = "36Kb" and wraddr_width = 11 ) else + ('1' & WRADDR & "11111") when (BRAM_SIZE = "36Kb" and wraddr_width = 10) else + WRADDR when (DEVICE = "VIRTEX5" and BRAM_SIZE = "36Kb" and wraddr_width = 9) else + ('1' & WRADDR & "111111") when (BRAM_SIZE = "36Kb" and wraddr_width = 9) else + (others => '1') ; + + digen : if ( (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES" or DEVICE = "SPARTAN6") and ((BRAM_SIZE = "9Kb" and WRITE_WIDTH <= 36) or (BRAM_SIZE = "18Kb" and WRITE_WIDTH <= 36) or (BRAM_SIZE = "36Kb" and WRITE_WIDTH <= 72)) ) generate + di1 : if (read_p = TRUE and write_p = TRUE) generate + + di11 : if (WRITE_WIDTH >= 71 or WRITE_WIDTH = 35 or WRITE_WIDTH = 36 or WRITE_WIDTH <= 32) generate + i1 : for i in 0 to we_width-1 generate + di_pattern((i*8)+7 downto (i*8)) <= DI(((i*8)+i)+7 downto ((i*8)+i)); + end generate i1; + end generate di11; + + di12 : if (WRITE_WIDTH = 33) generate + di_pattern <= DI(32 downto 9) & DI(7 downto 0); + end generate di12; + + di13 : if (WRITE_WIDTH = 34) generate + di_pattern <= DI(33 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di13; + + di14 : if (WRITE_WIDTH = 65) generate + di_pattern <= DI(64 downto 9) & DI(7 downto 0); + end generate di14; + + di15 : if (WRITE_WIDTH = 66) generate + di_pattern <= DI(65 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di15; + + di16 : if (WRITE_WIDTH = 67) generate + di_pattern <= DI(66 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di16; + + di17 : if (WRITE_WIDTH = 68) generate + di_pattern <= DI(67 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di17; + + di18 : if (WRITE_WIDTH = 69) generate + di_pattern <= DI(68 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di18; + + di19 : if (WRITE_WIDTH = 70) generate + di_pattern <= DI(69 downto 54) & DI(52 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di19; + + + i1p : for j in 1 to wr_widthp generate + dip_pattern(j-1) <= DI((j*8)+j-1); + end generate i1p; + + end generate di1; + di2 : if ( (read_p = FALSE and write_p = FALSE) and ((READ_WIDTH = WRITE_WIDTH) or (READ_WIDTH/WRITE_WIDTH = 2) or (valid_width = TRUE)) ) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di2; + di3 : if ((READ_WIDTH = 1 and WRITE_WIDTH = 2) or (READ_WIDTH = 2 and WRITE_WIDTH = 4) or (READ_WIDTH = 4 and WRITE_WIDTH = 8) or (READ_WIDTH = 8 and WRITE_WIDTH = 16) or (READ_WIDTH = 16 and WRITE_WIDTH = 32) or (READ_WIDTH = 32 and WRITE_WIDTH = 64 )) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di3; + di4 : if ( (read_p = FALSE and write_p = FALSE) and (WRITE_WIDTH/READ_WIDTH = 2)) generate + di_pattern(READ_WIDTH-1 downto 0) <= DI(READ_WIDTH-1 downto 0); + di_pattern (read_double-1 downto READ_WIDTH) <= DI(read_double-1 downto READ_WIDTH); + end generate di4; + end generate digen; + + dogen : if ( (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES" or DEVICE = "SPARTAN6") and ((BRAM_SIZE = "9Kb" and READ_WIDTH <= 36) or (BRAM_SIZE = "18Kb" and READ_WIDTH <= 36) or (BRAM_SIZE = "36Kb" and READ_WIDTH <= 72)) ) generate + do11 : if (read_p = TRUE and write_p = TRUE) generate + + do110 : if (READ_WIDTH >= 71 or READ_WIDTH = 35 or READ_WIDTH = 36 or READ_WIDTH <= 32) generate + o1 : for i1 in 0 to rd_byte_width-1 generate + DO(((i1*8)+i1)+7 downto ((i1*8)+i1)) <= do_pattern((i1*8)+7 downto (i1*8)); + end generate o1; + end generate do110; + + do111 : if (READ_WIDTH = 33) generate + DO(32 downto 9) <= do_pattern(31 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do111; + + do112 : if (READ_WIDTH = 34) generate + DO(33 downto 18) <= do_pattern(31 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do112; + + do113 : if (READ_WIDTH = 65) generate + DO(64 downto 9) <= do_pattern(63 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do113; + + do114 : if (READ_WIDTH = 66) generate + DO(65 downto 18) <= do_pattern(63 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do114; + + do115 : if (READ_WIDTH = 67) generate + DO(66 downto 27) <= do_pattern(63 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do115; + + do116 : if (READ_WIDTH = 68) generate + DO(67 downto 36) <= do_pattern(63 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do116; + + do117 : if (READ_WIDTH = 69) generate + DO(68 downto 45) <= do_pattern(63 downto 40); + DO(43 downto 36) <= do_pattern(39 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do117; + + do118 : if (READ_WIDTH = 70) generate + DO(69 downto 54) <= do_pattern(63 downto 48); + DO(52 downto 45) <= do_pattern(47 downto 40); + DO(43 downto 36) <= do_pattern(39 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do118; + + do119 : if (READ_WIDTH >= 71) generate + DO(70 downto 63) <= do_pattern(63 downto 56); + DO(61 downto 54) <= do_pattern(55 downto 48); + DO(52 downto 45) <= do_pattern(47 downto 40); + DO(43 downto 36) <= do_pattern(39 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do119; + + o1p : for j1 in 1 to rd_widthp generate + DO((j1*8)+j1-1) <= dop_pattern(j1-1); + end generate o1p; + + end generate do11; + do121 : if ( (read_p = FALSE and write_p = FALSE) and ( (READ_WIDTH = WRITE_WIDTH) or (WRITE_WIDTH/READ_WIDTH =2) or (valid_width = TRUE) )) generate + DO <= ( do_pattern(fin_rd_width-1 downto 0) ); + end generate do121; + do12 : if ((READ_WIDTH = 2 and WRITE_WIDTH = 1) or (READ_WIDTH = 4 and WRITE_WIDTH = 2) or (READ_WIDTH = 8 and WRITE_WIDTH = 4) or (READ_WIDTH = 16 and WRITE_WIDTH = 8) or (READ_WIDTH = 32 and WRITE_WIDTH = 16) or (READ_WIDTH = 64 and WRITE_WIDTH = 32 )) generate + DO <= ( do_pattern(fin_rd_width-1 downto 0) ); + end generate do12; + do3 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH = 3)) generate + -- write width 3 + DO <= ( do_pattern((4+(WRITE_WIDTH-1)) downto 4) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do3; + + do47 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH > 4 and WRITE_WIDTH < 8)) generate + -- write width between 4 and 7 + DO <= ( do_pattern((8+(WRITE_WIDTH-1)) downto 8) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do47; + + do815 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH > 8 and WRITE_WIDTH < 16)) generate + -- write width between 8 and 15 + DO <= ( do_pattern((16+(WRITE_WIDTH-1)) downto 16) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do815; + do1831 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH > 16 and WRITE_WIDTH < 32)) generate + DO <= ( do_pattern((32+(WRITE_WIDTH-1)) downto 32) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do1831; + + end generate dogen; + + we1 : if (DEVICE = "VIRTEX5") generate + w1 : we_pattern <= + (WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 1 ) else + WE when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + (WE & WE & WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 1 ) else + (WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 2 ) else + WE when (BRAM_SIZE = "36Kb" and we_width = 4 ) else + WE; + end generate we1; + web_bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + w1 : we_pattern <= + (WE & WE & WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 1 ) else + (WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + WE when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + (WE & WE & WE & WE & WE & WE & WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 1 ) else + (WE & WE & WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 2 ) else + (WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 4 ) else + WE when (BRAM_SIZE = "36Kb" and we_width = 8 ) else + WE; + end generate web_bl; + -- begin s11 + we2 : if (DEVICE = "SPARTAN6") generate + w2 : we_pattern <= + (WE & WE) when (BRAM_SIZE = "9Kb" and we_width = 1 ) else + WE when (BRAM_SIZE = "9Kb" and we_width = 2 ) else + (WE & WE & WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 1 ) else + (WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + WE when (BRAM_SIZE = "18Kb" and we_width = 4 ) else + WE; + end generate we2; + -- end s11 + + rstram_pattern <= RST ; + rstreg_pattern <= RST when (DO_REG = 1) else '0'; + + -- begin generate virtex5 + sdp_v5 : if DEVICE = "VIRTEX5" generate + + ramb18_dp : if (BRAM_SIZE = "18Kb" and DATA_WIDTH <= 18) generate + begin + ram18 : RAMB18 + generic map( + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_B => "READ_FIRST", + WRITE_WIDTH_B => wrwidth + ) + port map ( + ADDRA => rdaddr_pattern, + ADDRB => wraddr_pattern, + CLKA => RDCLK, + CLKB => WRCLK, + DIA => X"0000", + DIB => di_pattern, + DIPA => "00", + DIPB => dip_pattern, + ENA => RDEN, + ENB => WREN, + SSRA => RST, + SSRB => '0', + WEA => "00", + WEB => we_pattern, + DOA => do_pattern, + DOB => OPEN, + DOPA => dop_pattern, + DOPB => OPEN, + REGCEA => REGCE, + REGCEB => '0' + ); + + end generate ramb18_dp; + + ramb18_sdp : if (BRAM_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36) generate + begin + ram18sd : RAMB18SDP + generic map ( + + DO_REG => DO_REG, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size) + ) + + port map ( + DI => di_pattern, + DIP => dip_pattern, + RDADDR => RDADDR, + RDCLK => RDCLK, + RDEN => RDEN, + SSR => RST, + WRADDR => WRADDR, + WRCLK => WRCLK, + WREN => WREN, + WE => we_pattern, + DO => do_pattern, + DOP => dop_pattern, + REGCE => REGCE + ); + + end generate ramb18_sdp; + ramb36_dp : if (BRAM_SIZE = "36Kb" and DATA_WIDTH <= 36) generate + begin + ram36 : RAMB36 + generic map ( + + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + READ_WIDTH_A => rdwidth, + WRITE_MODE_B => "READ_FIRST", + WRITE_WIDTH_B => wrwidth + + ) + port map ( + ADDRA => rdaddr_pattern, + ADDRB => wraddr_pattern, + CLKA => RDCLK, + CLKB => WRCLK, + DIA => X"00000000", + DIB => di_pattern, + DIPA => "0000", + DIPB => dip_pattern, + ENA => RDEN, + ENB => WREN, + SSRA => RST, + SSRB => '0', + WEA => "0000", + WEB => we_pattern, + DOA => do_pattern, + DOB => OPEN, + DOPA => dop_pattern, + DOPB => OPEN, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => '0', + CASCADEINLATB => '0', + CASCADEINREGA => '0', + CASCADEINREGB => '0', + REGCEA => REGCE, + REGCEB => '0' + ); + end generate ramb36_dp; + + ramb36_sdp : if (BRAM_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72) generate + begin + ram36sd : RAMB36SDP + generic map ( + + DO_REG => DO_REG, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + INIT => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size) + ) + + port map ( + DI => di_pattern, + DIP => dip_pattern, + RDADDR => RDADDR, + RDCLK => RDCLK, + RDEN => RDEN, + SSR => RST, + WRADDR => WRADDR, + WRCLK => WRCLK, + WREN => WREN, + WE => we_pattern, + DO => do_pattern, + DOP => dop_pattern, + DBITERR => OPEN, + ECCPARITY => OPEN, + REGCE => REGCE, + SBITERR => OPEN + ); + + end generate ramb36_sdp; + end generate sdp_v5; + -- end generate virtex5 + -- begin generate virtex6 + sdp_bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + + ramb18_dp_bl : if (BRAM_SIZE = "18Kb" and READ_WIDTH <= 18 and WRITE_WIDTH <= 18) generate + begin + ram18_bl : RAMB18E1 + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + RAM_MODE => "TDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => X"0000", + DIBDI => di_pattern, + DIPADIP => "00", + DIPBDIP => dip_pattern, + ENARDEN => RDEN, + ENBWREN => WREN, + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "00", + WEBWE => we_pattern, + DOADO => do_pattern, + DOBDO => OPEN, + DOPADOP => dop_pattern, + DOPBDOP => OPEN + ); + + end generate ramb18_dp_bl; + + ramb18_sdp_bl1 : if (BRAM_SIZE = "18Kb" and ( (READ_WIDTH > 18 and READ_WIDTH <= 36) and (WRITE_WIDTH <= 18) )) generate + begin + ram18sd_bl1 : RAMB18E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => "0000000000000000", + DIBDI => di_pattern(15 downto 0), + DIPADIP => "00", + DIPBDIP => dip_pattern(1 downto 0), + ENARDEN => RDEN, + ENBWREN => WREN, + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "00", + WEBWE => we_pattern, + DOADO => do_pattern(15 downto 0), + DOBDO => do_pattern(31 downto 16), + DOPADOP => dop_pattern(1 downto 0), + DOPBDOP => dop_pattern(3 downto 2) + ); + + end generate ramb18_sdp_bl1; + ramb18_sdp_bl2 : if (BRAM_SIZE = "18Kb" and ( READ_WIDTH <= 18 and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36))) generate + begin + ram18sd_bl2 : RAMB18E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => di_pattern(15 downto 0), + DIBDI => di_pattern(31 downto 16), + DIPADIP => dip_pattern(1 downto 0), + DIPBDIP => dip_pattern(3 downto 2), + ENARDEN => RDEN, + ENBWREN => WREN, + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "00", + WEBWE => we_pattern, + DOADO => do_pattern(15 downto 0), + DOBDO => OPEN, + DOPADOP => dop_pattern(1 downto 0), + DOPBDOP => OPEN + ); + + end generate ramb18_sdp_bl2; + ramb18_sdp_bl3 : if (BRAM_SIZE = "18Kb" and ( (READ_WIDTH > 18 and READ_WIDTH <= 36) and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36))) generate + begin + ram18sd_bl3 : RAMB18E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => di_pattern(15 downto 0), + DIBDI => di_pattern(31 downto 16), + DIPADIP => dip_pattern(1 downto 0), + DIPBDIP => dip_pattern(3 downto 2), + ENARDEN => RDEN, + ENBWREN => WREN, + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "00", + WEBWE => we_pattern, + DOADO => do_pattern(15 downto 0), + DOBDO => do_pattern(31 downto 16), + DOPADOP => dop_pattern(1 downto 0), + DOPBDOP => dop_pattern(3 downto 2) + ); + + end generate ramb18_sdp_bl3; + ramb36_dp_bl : if (BRAM_SIZE = "36Kb" and READ_WIDTH <= 36 and WRITE_WIDTH <= 36) generate + begin + ram36_bl : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + READ_WIDTH_A => rdwidth, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + + ) + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CASCADEINA => '0', + CASCADEINB => '0', + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => X"00000000", + DIBDI => di_pattern, + DIPADIP => "0000", + DIPBDIP => dip_pattern, + ENARDEN => RDEN, + ENBWREN => WREN, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "0000", + WEBWE => we_pattern, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + DOADO => do_pattern, + DOBDO => OPEN, + DOPADOP => dop_pattern, + DOPBDOP => OPEN, + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN + ); + + end generate ramb36_dp_bl; + ramb36_sdp_bl : if (BRAM_SIZE = "36Kb" and ( (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72) and READ_WIDTH <= 36 )) generate + begin + ram36sd_bl : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CASCADEINA => '0', + CASCADEINB => '0', + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => di_pattern(31 downto 0), + DIBDI => di_pattern(63 downto 32), + DIPADIP => dip_pattern(3 downto 0), + DIPBDIP => dip_pattern(7 downto 4), + ENARDEN => RDEN, + ENBWREN => WREN, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "0000", + WEBWE => we_pattern, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + DOADO=> do_pattern(31 downto 0), + DOBDO=> OPEN, + DOPADOP => dop_pattern(3 downto 0), + DOPBDOP => OPEN, + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN + ); + + end generate ramb36_sdp_bl; + ramb36_sdp_bl_1 : if (BRAM_SIZE = "36Kb" and ( (WRITE_WIDTH <= 36) and (READ_WIDTH > 36 and READ_WIDTH <= 72) )) generate + begin + ram36sd_bl_1 : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CASCADEINA => '0', + CASCADEINB => '0', + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => "00000000000000000000000000000000", + DIBDI => di_pattern(31 downto 0), + DIPADIP => "0000", + DIPBDIP => dip_pattern(3 downto 0), + ENARDEN => RDEN, + ENBWREN => WREN, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "0000", + WEBWE => we_pattern, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + DOADO => do_pattern(31 downto 0), + DOBDO => do_pattern(63 downto 32), + DOPADOP => dop_pattern(3 downto 0), + DOPBDOP => dop_pattern(7 downto 4), + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN + ); + + end generate ramb36_sdp_bl_1; + ramb36_sdp_bl_2 : if (BRAM_SIZE = "36Kb" and ( (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72) and (READ_WIDTH > 36 and READ_WIDTH <= 72) )) generate + begin + ram36sd_bl_2 : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + RAM_MODE => "SDP", + READ_WIDTH_A => rdwidth, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_B => wrwidth + ) + + port map ( + ADDRARDADDR => rdaddr_pattern, + ADDRBWRADDR => wraddr_pattern, + CASCADEINA => '0', + CASCADEINB => '0', + CLKARDCLK => RDCLK, + CLKBWRCLK => WRCLK, + DIADI => di_pattern(31 downto 0), + DIBDI => di_pattern(63 downto 32), + DIPADIP => dip_pattern(3 downto 0), + DIPBDIP => dip_pattern(7 downto 4), + ENARDEN => RDEN, + ENBWREN => WREN, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + REGCEAREGCE => REGCE, + REGCEB => '0', + RSTREGARSTREG => rstreg_pattern, + RSTREGB => rstreg_pattern, + RSTRAMARSTRAM => rstram_pattern, + RSTRAMB => rstram_pattern, + WEA => "0000", + WEBWE => we_pattern, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + DOADO => do_pattern(31 downto 0), + DOBDO => do_pattern(63 downto 32), + DOPADOP => dop_pattern(3 downto 0), + DOPBDOP => dop_pattern(7 downto 4), + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN + ); + + end generate ramb36_sdp_bl_2; + end generate sdp_bl; + -- end generate virtex6 + -- begin generate spartan6 + ramb_st : if DEVICE = "SPARTAN6" generate + ramb9_dp_st : if (BRAM_SIZE = "9Kb" and WRITE_WIDTH <= 18) generate + begin + ram9_st : RAMB8BWER + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INIT_FILE => INIT_FILE, + DATA_WIDTH_A => rdwidth, + DATA_WIDTH_B => wrwidth, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE + ) + port map ( + ADDRAWRADDR => wraddr_pattern, + ADDRBRDADDR => rdaddr_pattern, + CLKAWRCLK => WRCLK, + CLKBRDCLK => RDCLK, + DIADI => di_pattern, + DIBDI => X"0000", + DIPADIP => dip_pattern, + DIPBDIP => "00", + ENAWREN => WREN, + ENBRDEN => RDEN, + REGCEA => '0', + REGCEBREGCE => REGCE, + RSTA => '0', + RSTBRST => RST, + WEAWEL => we_pattern, + WEBWEU => "00", + DOADO => OPEN, + DOBDO => do_pattern, + DOPADOP => OPEN, + DOPBDOP => dop_pattern + ); + + end generate ramb9_dp_st; + ramb9_sdp_st : if (BRAM_SIZE = "9Kb" and WRITE_WIDTH > 18 and WRITE_WIDTH <= 36) generate + begin + ram9_st : RAMB8BWER + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INIT_FILE => INIT_FILE, + DATA_WIDTH_A => rdwidth, + DATA_WIDTH_B => wrwidth, + RAM_MODE => "SDP", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE + ) + port map ( + ADDRAWRADDR => wraddr_pattern, + ADDRBRDADDR => rdaddr_pattern, + CLKAWRCLK => WRCLK, + CLKBRDCLK => RDCLK, + DIADI => di_pattern(15 downto 0), + DIBDI => di_pattern(31 downto 16), + DIPADIP => dip_pattern(1 downto 0), + DIPBDIP => dip_pattern(3 downto 2), + ENAWREN => WREN, + ENBRDEN => RDEN, + REGCEA => REGCE, + REGCEBREGCE => REGCE, + RSTA => '0', + RSTBRST => RST, + WEAWEL => we_pattern(1 downto 0), + WEBWEU => we_pattern(3 downto 2), + DOADO => do_pattern(15 downto 0), + DOBDO => do_pattern(31 downto 16), + DOPADOP => dop_pattern(1 downto 0), + DOPBDOP => dop_pattern(3 downto 2) + ); + + end generate ramb9_sdp_st; + ramb18_sdp_st : if BRAM_SIZE = "18Kb" generate + begin + ram18_st : RAMB16BWER + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + SIM_DEVICE => "SPARTAN6", + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + DATA_WIDTH_A => rdwidth, + DATA_WIDTH_B => wrwidth, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE + + ) + port map ( + ADDRA => wraddr_pattern, + ADDRB => rdaddr_pattern, + CLKA => WRCLK, + CLKB => RDCLK, + DIA => di_pattern, + DIB => X"00000000", + DIPA => dip_pattern, + DIPB => "0000", + ENA => WREN, + ENB => RDEN, + REGCEA => '0', + REGCEB => REGCE, + RSTA => '0', + RSTB => RST, + WEA => we_pattern, + WEB => "0000", + DOA => OPEN, + DOB => do_pattern, + DOPA => OPEN, + DOPB => dop_pattern + ); + end generate ramb18_sdp_st; + + end generate ramb_st; + -- end generate spartan6 + + end bram_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SINGLE_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SINGLE_MACRO.vhd new file mode 100644 index 0000000..fc39109 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_SINGLE_MACRO.vhd @@ -0,0 +1,3313 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 14.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for Single Port Block RAM +-- /___/ /\ Filename : BRAM_SINGLE_MACRO.vhd +-- \ \ / \ Timestamp : Wed April 11 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 04/11/08 - Initial version. +-- 05/25/11 - 607722 - Reset output latch for DO_REG=1 +-- 10/26/11 - 624543 - Fix DO for assymetric widths, drc to check for read,write widths equal or ratio of 2. +-- 11/30/11 - 636062 - Fix drc and do +-- 01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking. +-- 04/24/12 - 657517 - fix for write_width = 2* read_width +-- 11/01/12 - 679413 - pass INIT_FILE to Spartan6 BRAM +-- 09/29/14 - Update DI and DO for parity intersperse every byte (CR 773917). +-- End Revision + +----- CELL BRAM_SINGLE_MACRO ----- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; +library STD; +use STD.TEXTIO.ALL; + + +entity BRAM_SINGLE_MACRO is +generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT : bit_vector := X"000000000000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH : integer := 1; + SIM_MODE : string := "SAFE"; -- This parameter is valid only for Virtex5 + SRVAL : bit_vector := X"000000000000000000"; + WRITE_MODE : string := "WRITE_FIRST"; + WRITE_WIDTH : integer := 1 + ); +-- ports are unconstrained arrays +port ( + + DO : out std_logic_vector(READ_WIDTH-1 downto 0); + + ADDR : in std_logic_vector; + CLK : in std_ulogic; + DI : in std_logic_vector(WRITE_WIDTH-1 downto 0); + EN : in std_ulogic; + REGCE : in std_ulogic; + RST : in std_ulogic; + WE : in std_logic_vector + + ); +end BRAM_SINGLE_MACRO; + +architecture bram_V of BRAM_SINGLE_MACRO is + + function GetDIWidth ( + wr_width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case wr_width is + when 0 => func_width := 1; + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => func_width := 32; + when 37 to 72 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s1 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s1 + else + func_width := 64; + end if; + when others => if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s2 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH : ") ); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s2 + end if; + end case; + else + func_width := 1; + end if; + return func_width; + end; + function GetDOWidth ( + rd_width : in integer; + func_bram_size : in string; + device : in string; + wr_width : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + -- begin s15 + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if(DEVICE = "SPARTAN6") then + if(rd_width /= wr_width) then + write( Message, STRING'("WRITE_WIDTH and READ_WIDTH must be equal. ") ); + write ( Message, WRITE_WIDTH); + write ( Message, READ_WIDTH); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((rd_width /= wr_width) and (rd_width/wr_width /=2) and (wr_width/rd_width /=2) and (wr_width/rd_width /=2) and ((rd_width /= 1 and rd_width /= 2 and rd_width /= 4 and rd_width /= 8 and rd_width /= 9 and rd_width /= 16 and rd_width /= 18 and rd_width /= 32 and rd_width /= 36 and rd_width /= 64 and rd_width /= 72) or (wr_width /= 1 and wr_width /= 2 and wr_width /= 4 and wr_width /= 8 and wr_width /= 9 and wr_width /= 16 and wr_width /= 18 and wr_width /= 32 and wr_width /= 36 and wr_width /= 64 and wr_width /= 72)) ) then + write( Message, STRING'("Illegal values of Attributes READ_WIDTH, WRITE_WIDTH : ") ); + write ( Message, READ_WIDTH); + write ( Message, STRING'(" and ")); + write ( Message, WRITE_WIDTH); + write( Message, STRING'(" To use BRAM_SINGLE_MACRO. One of the following conditions must be true- 1. READ_WIDTH must be equal to WRITE_WIDTH 2. If assymetric, READ_WIDTH and WRITE_WIDTH must have a ratio of 2. 3. If assymetric, READ_WIDTH and WRITE_WIDTH should have values 1, 2, 4, 8, 9, 16, 18, 32, 36, 64, 72.") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + case rd_width is + when 0 => func_width := 1; + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => func_width := 32; + when 37 to 72 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") ) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s3 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 36 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s3 + else + func_width := 64; + end if; + when others => if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s4 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH : ") ); + write ( Message, READ_WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 72 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s4 + end if; + func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + function GetD_Width ( + d_width : in integer; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case d_width is + when 0 => func_width := 0; + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 9; + when 10 to 18 => func_width := 18; + when 19 to 36 => func_width := 36; + when 37 to 72 => func_width := 72; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + function GetDPWidth ( + wr_width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case wr_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 0; + end case; + else + func_width := 0; + end if; + return func_width; + end; + function GetLeastWidth ( + wr_width_a : in integer; + rd_width_a : in integer + ) return integer is + variable func_least_width : integer; + begin + if (wr_width_a <= rd_width_a) then + func_least_width := wr_width_a; + else + func_least_width := rd_width_a; + end if; + return func_least_width; + end; + function GetADDRWidth ( + least_widthA : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case least_widthA is + when 1 => if (func_bram_size = "9Kb") then + func_width := 13; + elsif (func_bram_size = "18Kb") then + func_width := 14; + else + func_width := 15; + end if; + when 2 => if (func_bram_size = "9Kb") then + func_width := 12; + elsif (func_bram_size = "18Kb") then + func_width := 13; + else + func_width := 14; + end if; + when 3|4 => if (func_bram_size = "9Kb") then + func_width := 11; + elsif (func_bram_size = "18Kb") then + func_width := 12; + else + func_width := 13; + end if; + when 5|6|7|8|9 => if (func_bram_size = "9Kb") then + func_width := 10; + elsif (func_bram_size = "18Kb") then + func_width := 11; + else + func_width := 12; + end if; + when 10 to 18 => if (func_bram_size = "9Kb") then + func_width := 9; + elsif (func_bram_size = "18Kb") then + func_width := 10; + else + func_width := 11; + end if; + when 19 to 36 => if (func_bram_size = "9Kb") then + func_width := 8; + elsif (func_bram_size = "18Kb") then + func_width := 9; + else + func_width := 10; + end if; + when 37 to 72 => if (func_bram_size = "36Kb") then + func_width := 9; + else + func_width := 14; + end if; + when others => func_width := 15; + end case; + else + func_width := 15; + end if; + return func_width; + end; + function GetWEWidth ( + bram_size : in string; + device : in string; + wr_width : in integer + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size= "18Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + end if; + elsif bram_size = "36Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + elsif wr_width > 36 and wr_width <= 72 then + func_width := 8; + end if; + else + func_width := 8; + end if; + -- begin s1 + elsif(DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; + elsif bram_size = "18Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + elsif wr_width > 36 and wr_width <= 72 then + func_width := 8; + else + func_width := 4; + end if; + end if; -- end s1 + else + func_width := 8; + end if; + return func_width; + end; + function GetMaxADDRSize ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if bram_size = "9Kb" then + func_width := 13; + elsif bram_size = "18Kb" then + func_width := 14; + elsif bram_size = "36Kb" then + func_width := 16; + else + func_width := 16; + end if; + else + func_width := 16; + end if; + return func_width; + end; + function GetMaxDataSize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 16; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 32; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 32; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 64; + else + func_width := 64; + end if; + -- begin s5 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 16; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 32; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 32; + elsif bram_size = "18Kb" and d_width <= 72 then + func_width := 64; + else + func_width := 32; + end if; -- end s5 + else + func_width := 64; + end if; + return func_width; + end; + + function GetMaxDataPSize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 8; + else + func_width := 8; + end if; + -- begin s6 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width <= 72 then + func_width := 8; + else + func_width := 4; + end if; -- end s6 + else + func_width := 8; + end if; + return func_width; + end; + function GetMaxWESize ( + d_width : in integer; + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size = "18Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "18Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "36Kb" and d_width > 36 and d_width <= 72 then + func_width := 8; + else + func_width := 8; + end if; + -- begin s7 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" and d_width <= 18 then + func_width := 2; + elsif bram_size = "9Kb" and d_width > 18 and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width <= 36 then + func_width := 4; + elsif bram_size = "18Kb" and d_width > 36 and d_width <= 72 then + func_width := 8; + else + func_width := 4; + end if; -- end s7 + else + func_width := 8; + end if; + return func_width; + end; + function GetFinalWidthRD ( + rd_width_a : in integer + ) return integer is + variable func_least_width : integer; + begin + if (rd_width_a = 0) then + func_least_width := 1; + else + func_least_width := rd_width_a; + end if; + return func_least_width; + end; + function GetFinalWidthWRA ( + wr_width_a : in integer + ) return integer is + variable func_least_width : integer; + begin + if (wr_width_a = 0) then + func_least_width := 1; + else + func_least_width := wr_width_a; + end if; + return func_least_width; + end; + + function GetBRAMSize ( + bram_size : in string; + device : in string + ) return boolean is + variable bram_val : boolean; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "36Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 18Kb, 36Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + -- begin s9 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" or bram_size = "18Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 9Kb, 18Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; -- end s9 + return bram_val; + end; + function GetD_P ( + dw : in integer; + device : in string + ) return boolean is + variable wp : boolean; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then + wp := TRUE; + else + wp := FALSE; + end if; + else + wp := FALSE; + end if; + return wp; + end; + function CheckParity ( + wp_a, rp_a : in boolean; + device : in string + ) return boolean is + variable Message : LINE; + variable check : boolean; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if ( (wp_a = FALSE and rp_a = FALSE ) or (wp_a = TRUE and rp_a = TRUE) ) then + check := FALSE; + elsif(wp_a = TRUE and rp_a = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("WRITE_WIDTH on BRAM_SINGLE_MACRO is set to ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = FALSE and rp_a = TRUE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("READ_WIDTH on BRAM_SINGLE_MACRO is set to ") ); + write( Message, READ_WIDTH); + write( Message, STRING'(". The parity bit(s) have not been written and hence cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + end if; + end if; + return check; + end; + + function GetINITSRVALWidth ( + bram_size : in string; + device : in string + ) return integer is + variable init_srval : integer; + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(bram_size = "18Kb") then + init_srval := 20; + elsif (bram_size = "36Kb") then + init_srval := 36; + end if; + end if; + -- begin s20 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb") then + init_srval := 20; + elsif (bram_size = "18Kb") then + init_srval := 36; + end if; + end if; -- end s20 + return init_srval; + end; + function init_a_size ( + inputvec : in bit_vector; + init_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable init_a_resize : bit_vector(0 to (init_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(bram_size = "18Kb" and ((rd_width > 18) and (wr_width > 18))) then + init_a_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif (bram_size = "36Kb" and ((rd_width > 36) and (wr_width > 36))) then + init_a_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; + -- begin s16 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" and ((rd_width > 18) and (wr_width > 18))) then + init_a_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif(bram_size = "18Kb" and ((rd_width > 36) and (wr_width > 36))) then + init_a_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; -- end s16 + return init_a_resize; + end; + + function init_b_size ( + inputvec : in bit_vector; + init_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable init_b_resize : bit_vector(0 to (init_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(BRAM_SIZE = "18Kb" and ((rd_width > 18) and (wr_width > 18))) then + init_b_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif (bram_size = "36Kb" and ((rd_width > 36) and (wr_width > 36))) then + init_b_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; + -- begin s17 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" and ((rd_width > 18) and (wr_width > 18))) then + init_b_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif(bram_size = "18Kb" and ((rd_width > 36) and (wr_width > 36))) then + init_b_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; -- end s17 + return init_b_resize; + end; + function srval_a_size ( + inputvec : in bit_vector; + srval_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable srval_a_resize : bit_vector(0 to (srval_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(bram_size = "18Kb" and ((rd_width > 18) and (wr_width > 18))) then + srval_a_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif (bram_size = "36Kb" and ((rd_width > 36) and (wr_width > 36))) then + srval_a_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; + -- begin s18 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" and ((rd_width > 18) and (wr_width > 18))) then + srval_a_resize := "00" & inputvec(0 to 1) & inputvec(4 to 19); + elsif(bram_size = "18Kb" and ((rd_width > 36) and (wr_width > 36))) then + srval_a_resize := inputvec(0 to 3) & inputvec(8 to 39); + end if; + end if; -- end s18 + return srval_a_resize; + end; + function srval_b_size ( + inputvec : in bit_vector; + srval_width : in integer; + rd_width : in integer; + wr_width : in integer; + device : in string + ) return bit_vector is + variable srval_b_resize : bit_vector(0 to (srval_width-1)); + begin + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(bram_size = "18Kb" and ((rd_width > 18) and (wr_width > 18))) then + srval_b_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif (BRAM_SIZE = "36Kb" and ((rd_width > 36) and (wr_width > 36))) then + srval_b_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; + -- begin s19 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" and ((rd_width > 18) and (wr_width > 18))) then + srval_b_resize := "00" & inputvec(2 to 3) & inputvec(20 to 35); + elsif(bram_size = "18Kb" and ((rd_width > 36) and (wr_width > 36))) then + srval_b_resize := inputvec(4 to 7) & inputvec(40 to 71); + end if; + end if; -- end s19 + return srval_b_resize; + end; + + function GetSIMDev ( + device : in string + ) return string is + begin + if(DEVICE = "VIRTEX6") then + return "VIRTEX6"; + else + return "7SERIES"; + end if; + end; + + function GetValWidth ( + rd_width : in integer; + wr_width : in integer + ) return boolean is + begin + if ((rd_width = 1 or rd_width = 2 or rd_width = 4 or rd_width = 8 or rd_width = 9 or rd_width = 16 or rd_width = 18 or rd_width = 32 or rd_width = 36 or rd_width = 64 or rd_width = 72) and (wr_width = 1 or wr_width = 2 or wr_width = 4 or wr_width = 8 or wr_width = 9 or wr_width = 16 or wr_width = 18 or wr_width = 32 or wr_width = 36 or wr_width = 64 or wr_width = 72)) then + return TRUE; + else + return FALSE; + end if; + end; + + function CheckWEWidth ( + wr_width : in integer; + we_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if ( wr_width <= 9 and we_vec /= 1) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 1 (0 downto 0) . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 9 and wr_width <= 18) and we_vec /= 2) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 2 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 18 and wr_width <= 36) and we_vec /= 4) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 4 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 36 and wr_width <= 72) and we_vec /= 8) then + write( Message, STRING'("WE port width incorrectly set for WRITE_WIDTH : ") ); + write( Message, WRITE_WIDTH); + write( Message, STRING'(". WE port width must be of width 8 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + end; + + function CheckADDRWidth ( + least_widthA : in integer; + func_bram_size : in string; + device : in string; + addr_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if (func_bram_size = "9Kb") then + if (least_widthA = 1 and addr_vec /= 13) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_widthA = 2 and addr_vec /= 12) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 2 and least_widthA <= 4) and addr_vec /= 11) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 4 and least_widthA <= 9) and addr_vec /= 10) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 9 and least_widthA <= 18) and addr_vec /= 9) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 18 and least_widthA <= 36) and addr_vec /= 8) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 8 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "18Kb") then + if (least_widthA = 1 and addr_vec /= 14) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_widthA = 2 and addr_vec /= 13) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 2 and least_widthA <= 4) and addr_vec /= 12) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 4 and least_widthA <= 9) and addr_vec /= 11) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 9 and least_widthA <= 18) and addr_vec /= 10) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 18 and least_widthA <= 36) and addr_vec /= 9) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "36Kb") then + if (least_widthA = 1 and addr_vec /= 15) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 15 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_widthA = 2 and addr_vec /= 14) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 2 and least_widthA <= 4) and addr_vec /= 13) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 4 and least_widthA <= 9) and addr_vec /= 12) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 9 and least_widthA <= 18) and addr_vec /= 11) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 18 and least_widthA <= 36) and addr_vec /= 10) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_widthA > 36 and least_widthA <= 72) and addr_vec /= 9) then + write( Message, STRING'("ADDR port width incorrectly set. ") ); + write( Message, STRING'(". ADDR port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + else + return TRUE; + end if; + end; + + + function Get_Parity_Width ( + wd : in integer + ) return integer is + variable wp : integer; + begin + if (wd = 9 or wd = 17 or wd = 33 or wd = 65) then + wp := 1; + elsif (wd = 18 or wd = 34 or wd = 66) then + wp := 2; + elsif (wd = 35 or wd = 67) then + wp := 3; + elsif (wd = 36 or wd = 68) then + wp := 4; + elsif (wd = 69) then + wp := 5; + elsif (wd = 70) then + wp := 6; + elsif (wd = 71) then + wp := 7; + elsif (wd = 72) then + wp := 8; + else + wp := 8; + end if; + return wp; + end; + + function Pad_INIT_SRVAL ( + func_in_init_srval : in bit_vector; + func_init_srval_width_size : in integer) + return bit_vector is variable func_paded_init_srval : bit_vector(0 to func_init_srval_width_size-1) := (others=>'0'); + variable func_padded_width : integer; + + begin + + if (func_in_init_srval'length > func_init_srval_width_size) then + func_padded_width := func_init_srval_width_size; + else + func_padded_width := func_in_init_srval'length; + end if; + + for i in 0 to func_padded_width-1 loop + func_paded_init_srval(((func_init_srval_width_size-1) - (func_padded_width-1)) + i) := func_in_init_srval(i); + end loop; + + return func_paded_init_srval; + end; + + + function Get_INIT_SRVAL_Width ( + func_bram_size : in string; + func_device : in string) + return integer is variable init_srval_width : integer; + begin + if(bram_size = "36Kb") then + if (READ_WIDTH > 36 or WRITE_WIDTH > 36) then + init_srval_width := 72; + else + init_srval_width := 36; + end if; + + elsif(bram_size = "18Kb") then + if (func_device = "SPARTAN6" or (READ_WIDTH > 18 or WRITE_WIDTH > 18)) then + init_srval_width := 36; + else + init_srval_width := 20; + end if; + elsif (bram_size = "9Kb") then + if (WRITE_WIDTH > 18) then + init_srval_width := 36; + else + init_srval_width := 20; + end if; + else + init_srval_width := 36; + end if; + + return init_srval_width; + end; + + + function INIT_SRVAL_parity_byte ( + in_init_srval : in bit_vector; + readp : in boolean; + writep : in boolean; + read_widthp : in integer; + init_srval_width : in integer) + return bit_vector is variable out_init_srval : bit_vector(0 to in_init_srval'length-1); + begin + + if (readp = TRUE and writep = TRUE) then + + if (read_widthp = 9) then + if (init_srval_width = 20) then + out_init_srval := "00000000000" & in_init_srval(11) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "000000000000000000000000000" & in_init_srval(27) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"000000000000000" & in_init_srval(63) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 17) then + if (init_srval_width = 20) then + out_init_srval := "000" & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "0000000000000000000" & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"0000000000000" & in_init_srval(63) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 18) then + if (init_srval_width = 20) then + out_init_srval := "00" & in_init_srval(2) & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + elsif (init_srval_width = 36) then + out_init_srval := "000000000000000000" & in_init_srval(18) & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "00" & X"0000000000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 33) then + if (init_srval_width = 36) then + out_init_srval := "000" & in_init_srval(27) & in_init_srval(3 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "000" & X"000000000" & in_init_srval(63) & in_init_srval(39 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 34) then + if (init_srval_width = 36) then + out_init_srval := "00" & in_init_srval(18) & in_init_srval(27) & in_init_srval(2 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := "00" & X"000000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(38 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 35) then + if (init_srval_width = 36) then + out_init_srval := '0' & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := '0' & X"000000000" & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 36) then + if (init_srval_width = 36) then + out_init_srval := in_init_srval(0) & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := X"000000000" & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + end if; + elsif (read_widthp = 65) then + out_init_srval := "0000000" & in_init_srval(63) & in_init_srval(7 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 66) then + out_init_srval := "000000" & in_init_srval(54) & in_init_srval(63) & in_init_srval(6 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 67) then + out_init_srval := "00000" & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(5 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 68) then + out_init_srval := "0000" & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(4 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 69) then + out_init_srval := "000" & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(3 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 70) then + out_init_srval := "00" & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(2 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 71) then + out_init_srval := '0' & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + elsif (read_widthp = 72) then + out_init_srval := in_init_srval(0) & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(36) & in_init_srval(45) & in_init_srval(54) & in_init_srval(63) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35) & in_init_srval(37 to 44) & in_init_srval(46 to 53) & in_init_srval(55 to 62) & in_init_srval(64 to 71); + else + out_init_srval := in_init_srval; + end if; + + else + out_init_srval := in_init_srval; + end if; + + return out_init_srval; + + end; + + + constant bram_size_val : boolean := GetBRAMSize(BRAM_SIZE, DEVICE); + constant write_p : boolean := GetD_P(WRITE_WIDTH, DEVICE); + constant read_p : boolean := GetD_P(READ_WIDTH, DEVICE); + constant di_width : integer := GetDIWidth(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant dip_width : integer := GetDPWidth(WRITE_WIDTH, BRAM_SIZE, DEVICE); + constant do_width : integer := GetDOWidth(READ_WIDTH, BRAM_SIZE, DEVICE, WRITE_WIDTH); + constant dop_width : integer := GetDPWidth(READ_WIDTH, BRAM_SIZE, DEVICE); + constant wr_width : integer := GetD_Width (WRITE_WIDTH, DEVICE); + constant rd_width : integer := GetD_Width (READ_WIDTH, DEVICE); + constant check_p : boolean := CheckParity(write_p, read_p, DEVICE); + constant least_width : integer := GetLeastWidth(di_width, do_width); + constant addr_width : integer := GetADDRWidth(least_width, BRAM_SIZE, DEVICE); + constant we_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, WRITE_WIDTH); + constant rd_byte_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, READ_WIDTH); + constant fin_rd_width : integer := GetFinalWidthRD(READ_WIDTH); + constant fin_wr_width : integer := GetFinalWidthWRA(WRITE_WIDTH); + constant sim_device_dp : string := GetSIMDev(DEVICE); + constant valid_width : boolean := GetValWidth(READ_WIDTH,WRITE_WIDTH); + constant weleng : integer := WE'length; + constant addrleng : integer := ADDR'length; + constant checkwe : boolean := CheckWEWidth(WRITE_WIDTH, weleng); + constant checkaddr : boolean := CheckADDRWidth(least_width, BRAM_SIZE, DEVICE, addrleng); + + constant max_addr_width : integer := GetMaxADDRSize(BRAM_SIZE, DEVICE); + constant max_read_width : integer := GetMaxDataSize(READ_WIDTH,BRAM_SIZE, DEVICE); + constant max_write_width : integer := GetMaxDataSize(WRITE_WIDTH,BRAM_SIZE, DEVICE); + constant max_readp_width : integer := GetMaxDataPSize(READ_WIDTH,BRAM_SIZE, DEVICE); + constant max_writep_width : integer := GetMaxDataPSize(WRITE_WIDTH,BRAM_SIZE, DEVICE); + constant max_we_width : integer := GetMaxWESize(WRITE_WIDTH,BRAM_SIZE, DEVICE); + + signal addr_pattern : std_logic_vector(max_addr_width-1 downto 0) := (others=> '0'); + signal addra_pattern : std_logic_vector(max_addr_width-1 downto 0) := (others=> '0'); + signal addrb_pattern : std_logic_vector(max_addr_width-1 downto 0) := (others=> '0'); + +-- signal di_pattern : std_logic_vector(max_read_width-1 downto 0) := (others=>'0'); + signal di_pattern : std_logic_vector(max_write_width-1 downto 0) := (others=>'0'); + signal dip_pattern : std_logic_vector(max_writep_width-1 downto 0) := (others=>'0'); +-- signal do_pattern : std_logic_vector(max_write_width-1 downto 0); + signal do_pattern : std_logic_vector(max_read_width-1 downto 0); + signal dop_pattern : std_logic_vector(max_readp_width-1 downto 0) := (others=>'0'); + signal we_pattern : std_logic_vector(max_we_width-1 downto 0) := (others=>'0'); + signal rstram_pattern : std_logic := '0'; + signal rstreg_pattern : std_logic := '0'; + + constant init_srval_width_size : integer := Get_INIT_SRVAL_Width(BRAM_SIZE, DEVICE); + constant padded_init : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(INIT, init_srval_width_size); + constant padded_srval : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(SRVAL, init_srval_width_size); + constant wr_widthp : integer := Get_Parity_Width(WRITE_WIDTH); + constant rd_widthp : integer := Get_Parity_Width(READ_WIDTH); + + constant init_srval_width : integer := GetINITSRVALWidth(BRAM_SIZE, DEVICE); + constant init_a_pattern : bit_vector := init_a_size(INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant init_b_pattern : bit_vector := init_b_size(INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant srval_a_pattern : bit_vector := srval_a_size(INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + constant srval_b_pattern : bit_vector := srval_b_size(INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), init_srval_width, READ_WIDTH, WRITE_WIDTH, DEVICE); + + constant read_double :integer:= READ_WIDTH * 2; + +begin + + +adr_vir : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + adgen1 : if ( (BRAM_SIZE = "18Kb" and READ_WIDTH <= 18 and WRITE_WIDTH <= 18) or (BRAM_SIZE = "36Kb" and READ_WIDTH <= 36 and WRITE_WIDTH <= 36) ) generate + begin + a1 : addr_pattern <= + ADDR when (BRAM_SIZE = "18Kb" and addr_width = 14 ) else + (ADDR & '1') when (BRAM_SIZE = "18Kb" and addr_width = 13 ) else + (ADDR & "11") when (BRAM_SIZE = "18Kb" and addr_width = 12) else + (ADDR & "111") when (BRAM_SIZE = "18Kb" and addr_width = 11 ) else + (ADDR & "1111") when (BRAM_SIZE = "18Kb" and addr_width = 10 ) else + ADDR when (BRAM_SIZE = "36Kb" and addr_width = 16 ) else + ('1' & ADDR) when (BRAM_SIZE = "36Kb" and addr_width = 15 ) else + ('1' & ADDR & '1') when (BRAM_SIZE = "36Kb" and addr_width = 14 ) else + ('1' & ADDR & "11") when (BRAM_SIZE = "36Kb" and addr_width = 13 ) else + ('1' & ADDR & "111") when (BRAM_SIZE = "36Kb" and addr_width = 12 ) else + ('1' & ADDR & "1111") when (BRAM_SIZE = "36Kb" and addr_width = 11 ) else + ('1' & ADDR & "11111") when (BRAM_SIZE = "36Kb" and addr_width = 10 ) else + (others => '1'); + end generate adgen1; + adgen2 : if ( (BRAM_SIZE = "18Kb" and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36) and (READ_WIDTH > 18 and READ_WIDTH <= 36)) or + (BRAM_SIZE = "36Kb" and (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72) and (READ_WIDTH > 36 and READ_WIDTH <= 72)) ) generate + aa : addra_pattern <= (ADDR & '0' & "1111") when (BRAM_SIZE = "18Kb") else + ('1' & ADDR & '0' & "11111") when (BRAM_SIZE = "36Kb") else + (others => '1'); + + ab : addrb_pattern <= (ADDR & '1' & "1111") when (BRAM_SIZE = "18Kb") else + ('1' & ADDR & '1' & "11111") when (BRAM_SIZE = "36Kb") else + (others => '1'); + end generate adgen2; + end generate adr_vir; + -- begin s14 + adr_st : if (DEVICE = "SPARTAN6") generate + adgen3 : if ( (BRAM_SIZE = "9Kb" and READ_WIDTH <= 18 and WRITE_WIDTH <= 18) or (BRAM_SIZE = "18Kb" and READ_WIDTH <= 36 and WRITE_WIDTH <= 36) ) generate + begin + a1 : addr_pattern <= + ADDR when (BRAM_SIZE = "9Kb" and addr_width = 13) else + (ADDR & '1') when (BRAM_SIZE = "9Kb" and addr_width = 12 ) else + (ADDR & "11") when (BRAM_SIZE = "9Kb" and addr_width = 11) else + (ADDR & "111") when (BRAM_SIZE = "9Kb" and addr_width = 10) else + (ADDR & "1111") when (BRAM_SIZE = "9Kb" and addr_width = 9 ) else + ADDR when (BRAM_SIZE = "18Kb" and addr_width = 14 ) else + (ADDR & '1') when (BRAM_SIZE = "18Kb" and addr_width = 13 ) else + (ADDR & "11") when (BRAM_SIZE = "18Kb" and addr_width = 12) else + (ADDR & "111") when (BRAM_SIZE = "18Kb" and addr_width = 11 ) else + (ADDR & "1111") when (BRAM_SIZE = "18Kb" and addr_width = 10 ) else + (ADDR & "11111") when (BRAM_SIZE = "18Kb" and addr_width = 9 ) else + (others => '1'); + end generate adgen3; + adgen4 : if ( (BRAM_SIZE = "9Kb" and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36) and (READ_WIDTH > 18 and READ_WIDTH <= 36)) or + (BRAM_SIZE = "18Kb" and (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72) and (READ_WIDTH > 36 and READ_WIDTH <= 72)) ) generate + aa : addra_pattern <= (ADDR & '0' & "1111") when (BRAM_SIZE = "9Kb") else + (ADDR & '0' & "11111") when (BRAM_SIZE = "18Kb") else + (others => '1'); + + ab : addrb_pattern <= (ADDR & '1' & "1111") when (BRAM_SIZE = "9Kb") else + (ADDR & '1' & "11111") when (BRAM_SIZE = "18Kb") else + (others => '1'); + end generate adgen4; + end generate adr_st; -- end s14 + + di1_v5: if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + di_m1 : if ((BRAM_SIZE = "18Kb" and WRITE_WIDTH <= 36) or (BRAM_SIZE = "36Kb" and WRITE_WIDTH <= 72)) generate + begin + di1 : if (write_p = TRUE and read_p = true) generate + + di11 : if (WRITE_WIDTH >= 71 or WRITE_WIDTH = 35 or WRITE_WIDTH = 36 or WRITE_WIDTH <= 32) generate + i1 : for i in 0 to we_width-1 generate + di_pattern((i*8)+7 downto (i*8)) <= DI(((i*8)+i)+7 downto ((i*8)+i)); + end generate i1; + end generate di11; + + di12 : if (WRITE_WIDTH = 33) generate + di_pattern <= DI(32 downto 9) & DI(7 downto 0); + end generate di12; + + di13 : if (WRITE_WIDTH = 34) generate + di_pattern <= DI(33 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di13; + + di14 : if (WRITE_WIDTH = 65) generate + di_pattern <= DI(64 downto 9) & DI(7 downto 0); + end generate di14; + + di15 : if (WRITE_WIDTH = 66) generate + di_pattern <= DI(65 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di15; + + di16 : if (WRITE_WIDTH = 67) generate + di_pattern <= DI(66 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di16; + + di17 : if (WRITE_WIDTH = 68) generate + di_pattern <= DI(67 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di17; + + di18 : if (WRITE_WIDTH = 69) generate + di_pattern <= DI(68 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di18; + + di19 : if (WRITE_WIDTH = 70) generate + di_pattern <= DI(69 downto 54) & DI(52 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di19; + + + i1p : for j in 1 to wr_widthp generate + dip_pattern(j-1) <= DI((j*8)+j-1); + end generate i1p; + + end generate di1; + di2 : if ((write_p = FALSE and read_p = FALSE) and ( ((READ_WIDTH = WRITE_WIDTH) or (READ_WIDTH/WRITE_WIDTH = 2) or (valid_width = TRUE))) ) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di2; + di3 : if ((READ_WIDTH = 1 and WRITE_WIDTH = 2) or (READ_WIDTH = 2 and WRITE_WIDTH = 4) or (READ_WIDTH = 4 and WRITE_WIDTH = 8) or (READ_WIDTH = 8 and WRITE_WIDTH = 16) or (READ_WIDTH = 16 and WRITE_WIDTH = 32) or (READ_WIDTH = 32 and WRITE_WIDTH = 64 )) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di3; + di4 : if ( (read_p = FALSE and write_p = FALSE) and (WRITE_WIDTH/READ_WIDTH = 2)) generate + di_pattern(READ_WIDTH-1 downto 0) <= DI(READ_WIDTH-1 downto 0); + di_pattern (read_double-1 downto READ_WIDTH) <= DI(read_double-1 downto READ_WIDTH); + end generate di4; + end generate di_m1; + end generate di1_v5; + -- begin s10 + di1_st : if (DEVICE = "SPARTAN6") generate + begin + di_m2 : if ((BRAM_SIZE = "9Kb" and WRITE_WIDTH <= 36) or (BRAM_SIZE = "18Kb" and WRITE_WIDTH <= 72)) generate + begin + di110 : if (write_p = TRUE and read_p = TRUE ) generate + + di111 : if (WRITE_WIDTH >= 71 or WRITE_WIDTH = 35 or WRITE_WIDTH = 36 or WRITE_WIDTH <= 32) generate + i11 : for i in 0 to we_width-1 generate + di_pattern((i*8)+7 downto (i*8)) <= DI(((i*8)+i)+7 downto ((i*8)+i)); + end generate i11; + end generate di111; + + di121 : if (WRITE_WIDTH = 33) generate + di_pattern <= DI(32 downto 9) & DI(7 downto 0); + end generate di121; + + di131 : if (WRITE_WIDTH = 34) generate + di_pattern <= DI(33 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di131; + + di141 : if (WRITE_WIDTH = 65) generate + di_pattern <= DI(64 downto 9) & DI(7 downto 0); + end generate di141; + + di151 : if (WRITE_WIDTH = 66) generate + di_pattern <= DI(65 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di151; + + di161 : if (WRITE_WIDTH = 67) generate + di_pattern <= DI(66 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di161; + + di171 : if (WRITE_WIDTH = 68) generate + di_pattern <= DI(67 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di171; + + di181 : if (WRITE_WIDTH = 69) generate + di_pattern <= DI(68 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di181; + + di191 : if (WRITE_WIDTH = 70) generate + di_pattern <= DI(69 downto 54) & DI(52 downto 45) & DI(43 downto 36) & DI(34 downto 27) & DI(25 downto 18) & DI(16 downto 9) & DI(7 downto 0); + end generate di191; + + + i1p1 : for j in 1 to wr_widthp generate + dip_pattern(j-1) <= DI((j*8)+j-1); + end generate i1p1; + + end generate di110; + di12 : if ((write_p = FALSE and read_p = FALSE) and ( ((READ_WIDTH = WRITE_WIDTH) or (READ_WIDTH/WRITE_WIDTH = 2) or (valid_width = TRUE))) ) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di12; + di13 : if ((READ_WIDTH = 1 and WRITE_WIDTH = 2) or (READ_WIDTH = 2 and WRITE_WIDTH = 4) or (READ_WIDTH = 4 and WRITE_WIDTH = 8) or (READ_WIDTH = 8 and WRITE_WIDTH = 16) or (READ_WIDTH = 16 and WRITE_WIDTH = 32) or (READ_WIDTH = 32 and WRITE_WIDTH = 64 )) generate + di_pattern(fin_wr_width-1 downto 0) <= DI(fin_wr_width-1 downto 0); + end generate di13; + di14 : if ( (read_p = FALSE and write_p = FALSE) and (WRITE_WIDTH/READ_WIDTH = 2)) generate + di_pattern(READ_WIDTH-1 downto 0) <= DI(READ_WIDTH-1 downto 0); + di_pattern (read_double-1 downto READ_WIDTH) <= DI(read_double-1 downto READ_WIDTH); + end generate di14; + end generate di_m2; + end generate di1_st; -- end s10 + + dogen : if ( ((DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") and ((BRAM_SIZE = "18Kb" and READ_WIDTH <= 36) or (BRAM_SIZE = "36Kb" and READ_WIDTH <= 72)) ) or ((DEVICE ="SPARTAN6") and ((BRAM_SIZE = "9Kb" and READ_WIDTH <= 36) or (BRAM_SIZE = "18Kb" and READ_WIDTH <= 72)) ) ) generate + do11 : if (read_p = TRUE and write_p = TRUE) generate + + do110 : if (READ_WIDTH >= 71 or READ_WIDTH = 35 or READ_WIDTH = 36 or READ_WIDTH <= 32) generate + o1 : for i1 in 0 to rd_byte_width-1 generate + DO(((i1*8)+i1)+7 downto ((i1*8)+i1)) <= do_pattern((i1*8)+7 downto (i1*8)); + end generate o1; + end generate do110; + + do111 : if (READ_WIDTH = 33) generate + DO(32 downto 9) <= do_pattern(31 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do111; + + do112 : if (READ_WIDTH = 34) generate + DO(33 downto 18) <= do_pattern(31 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do112; + + do113 : if (READ_WIDTH = 65) generate + DO(64 downto 9) <= do_pattern(63 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do113; + + do114 : if (READ_WIDTH = 66) generate + DO(65 downto 18) <= do_pattern(63 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do114; + + do115 : if (READ_WIDTH = 67) generate + DO(66 downto 27) <= do_pattern(63 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do115; + + do116 : if (READ_WIDTH = 68) generate + DO(67 downto 36) <= do_pattern(63 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do116; + + do117 : if (READ_WIDTH = 69) generate + DO(68 downto 45) <= do_pattern(63 downto 40); + DO(43 downto 36) <= do_pattern(39 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do117; + + do118 : if (READ_WIDTH = 70) generate + DO(69 downto 54) <= do_pattern(63 downto 48); + DO(52 downto 45) <= do_pattern(47 downto 40); + DO(43 downto 36) <= do_pattern(39 downto 32); + DO(34 downto 27) <= do_pattern(31 downto 24); + DO(25 downto 18) <= do_pattern(23 downto 16); + DO(16 downto 9) <= do_pattern(15 downto 8); + DO(7 downto 0) <= do_pattern(7 downto 0); + end generate do118; + + o1p : for j1 in 1 to rd_widthp generate + DO((j1*8)+j1-1) <= dop_pattern(j1-1); + end generate o1p; + + end generate do11; + do121 : if ( (read_p = FALSE and write_p = FALSE) and ( (READ_WIDTH = WRITE_WIDTH) or (WRITE_WIDTH/READ_WIDTH =2) or (valid_width = TRUE) ) ) generate + DO <= ( do_pattern(fin_rd_width-1 downto 0) ); + end generate do121; + do12 : if ((READ_WIDTH = 2 and WRITE_WIDTH = 1) or (READ_WIDTH = 4 and WRITE_WIDTH = 2) or (READ_WIDTH = 8 and WRITE_WIDTH = 4) or (READ_WIDTH = 16 and WRITE_WIDTH = 8) or (READ_WIDTH = 32 and WRITE_WIDTH = 16) or (READ_WIDTH = 64 and WRITE_WIDTH = 32 )) generate + DO <= ( do_pattern(fin_rd_width-1 downto 0) ); + end generate do12; + do3 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH = 3)) generate + -- write width 3 + DO <= ( do_pattern((4+(WRITE_WIDTH-1)) downto 4) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do3; + do47 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH > 4 and WRITE_WIDTH <= 7)) generate + -- write width between 4 and 7 + DO <= ( do_pattern((8+(WRITE_WIDTH-1)) downto 8) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do47; + do815 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and(WRITE_WIDTH > 9 and WRITE_WIDTH <= 15)) generate + -- write width between 8 and 15 + DO <= ( do_pattern((16+(WRITE_WIDTH-1)) downto 16) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do815; + do1831 : if ((read_p = FALSE and write_p = FALSE) and (READ_WIDTH/WRITE_WIDTH = 2) and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 31)) generate + -- write width between 18 and 31 + DO <= ( do_pattern((32+(WRITE_WIDTH-1)) downto 32) & do_pattern((WRITE_WIDTH-1) downto 0) ); + end generate do1831; + + end generate dogen; + + we1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + w1 : we_pattern <= (WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 1 ) else + WE when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + (WE & WE & WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 1 ) else + (WE & WE) when (BRAM_SIZE = "36Kb" and we_width = 2 ) else + WE when (BRAM_SIZE = "36Kb" and we_width = 4 ) else + WE; + end generate we1; + -- begin s14 + we2 : if (DEVICE = "SPARTAN6") generate + w1 : we_pattern <= (WE & WE) when (BRAM_SIZE = "9Kb" and we_width = 1 ) else + WE when (BRAM_SIZE = "9Kb" and we_width = 2 ) else + (WE & WE & WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 1 ) else + (WE & WE) when (BRAM_SIZE = "18Kb" and we_width = 2 ) else + WE when (BRAM_SIZE = "18Kb" and we_width = 4 ) else + WE; + end generate we2; + -- end s14 + r1 : rstram_pattern <= RST; + r2 : rstreg_pattern <= RST when (DO_REG = 1) else '0'; + + -- begin generate virtex5 + ramb_v5 : if DEVICE ="VIRTEX5" generate + ramb18_sin : if (BRAM_SIZE = "18Kb" and READ_WIDTH <= 18 and WRITE_WIDTH <= 18) generate + begin + + ram18 : RAMB18 + generic map( + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + READ_WIDTH_A => rd_width, + SIM_COLLISION_CHECK => "NONE", + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_WIDTH_A => wr_width + ) + port map ( + ADDRA => addr_pattern, + ADDRB => "00000000000000", + CLKA => CLK, + CLKB => '0', + DIA => di_pattern, + DIB => X"0000", + DIPA => dip_pattern, + DIPB => "00", + ENA => EN, + ENB => '0', + SSRA => RST, + SSRB => '0', + WEA => we_pattern, + WEB => "00", + DOA => do_pattern, + DOB => OPEN, + DOPA => dop_pattern, + DOPB => OPEN, + REGCEA => REGCE, + REGCEB => '0' + ); + + end generate ramb18_sin; + ramb18_sin_1 : if (BRAM_SIZE = "18Kb" and (READ_WIDTH > 18 and READ_WIDTH <= 36) and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36)) generate + begin + + ram18_1 : RAMB18 + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + READ_WIDTH_A => 18, + READ_WIDTH_B => 18, + SIM_COLLISION_CHECK => "NONE", + SIM_MODE => SIM_MODE, + SRVAL_A => srval_a_pattern , + SRVAL_B => srval_b_pattern , + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_A => 18, + WRITE_WIDTH_B => 18 + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLK, + CLKB => CLK, + DIA => di_pattern(31 downto 16), + DIB => di_pattern(15 downto 0), + DIPA => dip_pattern(3 downto 2), + DIPB => dip_pattern(1 downto 0), + ENA => EN, + ENB => EN, + SSRA => RST, + SSRB => RST, + WEA => we_pattern(3 downto 2) , + WEB => we_pattern(1 downto 0), + DOA => do_pattern(31 downto 16), + DOB => do_pattern(15 downto 0), + DOPA => dop_pattern(3 downto 2), + DOPB => dop_pattern(1 downto 0), + REGCEA => REGCE, + REGCEB => REGCE + ); + + end generate ramb18_sin_1; + ramb36_sin : if (BRAM_SIZE = "36Kb" and READ_WIDTH <= 36 and WRITE_WIDTH <= 36) generate + begin + ram36 : RAMB36 + generic map ( + + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + READ_WIDTH_A => rd_width, + SIM_COLLISION_CHECK => "NONE", + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_WIDTH_A => wr_width + + ) + port map ( + ADDRA => addr_pattern, + ADDRB => X"0000", + CLKA => CLK, + CLKB => '0', + DIA => di_pattern, + DIB => X"00000000", + DIPA => dip_pattern, + DIPB => "0000", + ENA => EN, + ENB => '0', + SSRA => RST, + SSRB => '0', + WEA => we_pattern, + WEB => "0000", + DOA => do_pattern, + DOB => OPEN, + DOPA => dop_pattern, + DOPB => OPEN, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => '0', + CASCADEINLATB => '0', + CASCADEINREGA => '0', + CASCADEINREGB => '0', + REGCEA => REGCE, + REGCEB => '0' + ); + end generate ramb36_sin; + ramb36_sin_1 : if (BRAM_SIZE = "36Kb" and (READ_WIDTH > 36 and READ_WIDTH <= 72) and (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72)) generate + begin + ram36_1 : RAMB36 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + READ_WIDTH_A => 36, + READ_WIDTH_B => 36, + SIM_COLLISION_CHECK => "NONE", + SIM_MODE => SIM_MODE, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_A => 36, + WRITE_WIDTH_B => 36 + + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLK, + CLKB => CLK, + DIA => di_pattern(63 downto 32), + DIB => di_pattern(31 downto 0), + DIPA => dip_pattern(7 downto 4), + DIPB => dip_pattern(3 downto 0), + ENA => EN, + ENB => EN, + SSRA => RST, + SSRB => RST, + WEA => we_pattern(7 downto 4), + WEB => we_pattern(3 downto 0), + DOA => do_pattern(63 downto 32), + DOB => do_pattern(31 downto 0), + DOPA => dop_pattern(7 downto 4), + DOPB => dop_pattern(3 downto 0), + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => '0', + CASCADEINLATB => '0', + CASCADEINREGA => '0', + CASCADEINREGB => '0', + REGCEA => REGCE, + REGCEB => REGCE + ); + end generate ramb36_sin_1; + end generate ramb_v5; + -- end generate virtex5 + -- begin generate virtex6 +ramb_bl : if (DEVICE ="VIRTEX6" or DEVICE = "7SERIES") generate + ramb18_sin_bl : if (BRAM_SIZE = "18Kb" and READ_WIDTH <= 18 and WRITE_WIDTH <= 18) generate + begin + + ram18_bl : RAMB18E1 + generic map( + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => rd_width, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_WIDTH_A => wr_width + ) + port map ( + ADDRARDADDR => addr_pattern, + ADDRBWRADDR => "00000000000000", + CLKARDCLK => CLK, + CLKBWRCLK => '0', + DIADI => di_pattern, + DIBDI => X"0000", + DIPADIP => dip_pattern, + DIPBDIP => "00", + ENARDEN => EN, + ENBWREN => '0', + RSTRAMARSTRAM => rstram_pattern, + RSTREGARSTREG => rstreg_pattern, + RSTRAMB => '0', + RSTREGB => '0', + WEA => we_pattern, + WEBWE => "0000", + DOADO => do_pattern, + DOBDO => OPEN, + DOPADOP => dop_pattern, + DOPBDOP => OPEN, + REGCEAREGCE => REGCE, + REGCEB => '0' + ); + + end generate ramb18_sin_bl; + ramb18_sin_bl_1 : if (BRAM_SIZE = "18Kb" and (READ_WIDTH > 18 and READ_WIDTH <= 36) and (WRITE_WIDTH > 18 and WRITE_WIDTH <= 36)) generate + begin + + ram18_bl_1 : RAMB18E1 + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => 18, + READ_WIDTH_B => 18, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern , + SRVAL_B => srval_b_pattern , + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_A => 18, + WRITE_WIDTH_B => 18 + ) + port map ( + ADDRARDADDR => addra_pattern, + ADDRBWRADDR => addrb_pattern, + CLKARDCLK => CLK, + CLKBWRCLK => CLK, + DIADI => di_pattern(31 downto 16), + DIBDI => di_pattern(15 downto 0), + DIPADIP => dip_pattern(3 downto 2), + DIPBDIP => dip_pattern(1 downto 0), + ENARDEN => EN, + ENBWREN => EN, + RSTRAMARSTRAM => rstram_pattern, + RSTREGARSTREG => rstreg_pattern, + RSTRAMB => rstram_pattern, + RSTREGB => rstreg_pattern, + WEA => we_pattern(3 downto 2), + WEBWE => we_pattern, + DOADO => do_pattern(31 downto 16), + DOBDO => do_pattern(15 downto 0), + DOPADOP => dop_pattern(3 downto 2), + DOPBDOP => dop_pattern(1 downto 0), + REGCEAREGCE => REGCE, + REGCEB => REGCE + ); + + end generate ramb18_sin_bl_1; + + ramb36_sin_bl : if (BRAM_SIZE = "36Kb" and READ_WIDTH <= 36 and WRITE_WIDTH <= 36) generate + begin + ram36_bl : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => rd_width, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE, + WRITE_WIDTH_A => wr_width + + ) + port map ( + ADDRARDADDR => addr_pattern, + ADDRBWRADDR => X"0000", + CLKARDCLK => CLK, + CLKBWRCLK => '0', + DIADI => di_pattern, + DIBDI => X"00000000", + DIPADIP => dip_pattern, + DIPBDIP => "0000", + ENARDEN => EN, + ENBWREN => '0', + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RSTRAMARSTRAM => rstram_pattern, + RSTREGARSTREG => rstreg_pattern, + RSTRAMB => '0', + RSTREGB => '0', + WEA => we_pattern, + WEBWE => "00000000", + DOADO => do_pattern, + DOBDO => OPEN, + DOPADOP => dop_pattern, + DOPBDOP => OPEN, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + CASCADEINA => '0', + CASCADEINB => '0', + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN, + SBITERR => OPEN, + REGCEAREGCE => REGCE, + REGCEB => '0' + ); + end generate ramb36_sin_bl; + ramb36_sin_bl_1 : if (BRAM_SIZE = "36Kb" and (READ_WIDTH > 36 and READ_WIDTH <= 72) and (WRITE_WIDTH > 36 and WRITE_WIDTH <= 72)) generate + begin + ram36_bl_1 : RAMB36E1 + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => 36, + READ_WIDTH_B => 36, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => sim_device_dp, + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE, + WRITE_WIDTH_A => 36, + WRITE_WIDTH_B => 36 + + ) + port map ( + ADDRARDADDR => addra_pattern, + ADDRBWRADDR => addrb_pattern, + CLKARDCLK => CLK, + CLKBWRCLK => CLK, + DIADI => di_pattern(63 downto 32), + DIBDI => di_pattern(31 downto 0), + DIPADIP => dip_pattern(7 downto 4), + DIPBDIP => dip_pattern(3 downto 0), + ENARDEN => EN, + ENBWREN => EN, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RSTRAMARSTRAM => rstram_pattern, + RSTREGARSTREG => rstreg_pattern, + RSTRAMB => rstram_pattern, + RSTREGB => rstreg_pattern, + WEA => we_pattern(7 downto 4), + WEBWE => we_pattern, + DOADO => do_pattern(63 downto 32), + DOBDO => do_pattern(31 downto 0), + DOPADOP => dop_pattern(7 downto 4), + DOPBDOP => dop_pattern(3 downto 0), + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + CASCADEINA => '0', + CASCADEINB => '0', + DBITERR => OPEN, + ECCPARITY => OPEN, + RDADDRECC => OPEN, + SBITERR => OPEN, + REGCEAREGCE => REGCE, + REGCEB => REGCE + ); + end generate ramb36_sin_bl_1; + + end generate ramb_bl; + -- end generate virtex6 + -- begin generate spartan6 + ramb_st : if DEVICE = "SPARTAN6" generate + ramb9_sin_st : if (BRAM_SIZE = "9Kb" and (READ_WIDTH = WRITE_WIDTH) and (READ_WIDTH <= 18)) generate + begin + + ram9_st : RAMB8BWER + generic map( + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INIT_FILE => INIT_FILE, + DATA_WIDTH_A => wr_width, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE + ) + port map ( + ADDRAWRADDR => addr_pattern, + ADDRBRDADDR => "0000000000000", + CLKAWRCLK => CLK, + CLKBRDCLK => '0', + DIADI => di_pattern, + DIBDI => X"0000", + DIPADIP => dip_pattern, + DIPBDIP => "00", + ENAWREN => EN, + ENBRDEN => '0', + REGCEA => REGCE, + REGCEBREGCE => '0', + RSTA => RST, + RSTBRST => '0', + WEAWEL => we_pattern, + WEBWEU => "00", + DOADO => do_pattern, + DOBDO => OPEN, + DOPADOP => dop_pattern, + DOPBDOP => OPEN + ); + + end generate ramb9_sin_st; + ramb9_sin_st_1 : if (BRAM_SIZE = "9Kb" and (READ_WIDTH = WRITE_WIDTH) and (READ_WIDTH > 18 and READ_WIDTH <= 36)) generate + begin + + ram9_st : RAMB8BWER + generic map( + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INIT_FILE => INIT_FILE, + DATA_WIDTH_A => 18, + DATA_WIDTH_B => 18, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => srval_a_pattern , + SRVAL_B => srval_b_pattern , + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE + ) + port map ( + ADDRAWRADDR => addra_pattern, + ADDRBRDADDR => addrb_pattern, + CLKAWRCLK => CLK, + CLKBRDCLK => CLK, + DIADI => di_pattern(31 downto 16), + DIBDI => di_pattern(15 downto 0), + DIPADIP => dip_pattern(3 downto 2), + DIPBDIP => dip_pattern(1 downto 0), + ENAWREN => EN, + ENBRDEN => EN, + REGCEA => REGCE, + REGCEBREGCE => REGCE, + RSTA => RST, + RSTBRST => RST, + WEAWEL => we_pattern(3 downto 2), + WEBWEU => we_pattern(1 downto 0), + DOADO => do_pattern(31 downto 16), + DOBDO => do_pattern(15 downto 0), + DOPADOP => dop_pattern(3 downto 2), + DOPBDOP => dop_pattern(1 downto 0) + ); + + end generate ramb9_sin_st_1; + ramb18_sin_st : if (BRAM_SIZE = "18Kb" and (READ_WIDTH = WRITE_WIDTH) and (READ_WIDTH <= 36)) generate + begin + ram18_st : RAMB16BWER + generic map ( + + DOA_REG => DO_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init, read_p, write_p, READ_WIDTH, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => "SPARTAN6", + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval, read_p, write_p, READ_WIDTH, init_srval_width_size), + DATA_WIDTH_A => rd_width, + WRITE_MODE_A => WRITE_MODE + + ) + port map ( + ADDRA => addr_pattern, + ADDRB => "00000000000000", + CLKA => CLK, + CLKB => '0', + DIA => di_pattern, + DIB => X"00000000", + DIPA => dip_pattern, + DIPB => "0000", + ENA => EN, + ENB => '0', + REGCEA => REGCE, + REGCEB => '0', + RSTA => RST, + RSTB => '0', + WEA => we_pattern, + WEB => "0000", + DOA => do_pattern, + DOB => OPEN, + DOPA => dop_pattern, + DOPB => OPEN + ); + end generate ramb18_sin_st; + ramb18_sin_st_1 : if (BRAM_SIZE = "18Kb" and (READ_WIDTH = WRITE_WIDTH) and (READ_WIDTH > 36 and READ_WIDTH <= 72)) generate + begin + ram18_st_1 : RAMB16BWER + generic map ( + + DOA_REG => DO_REG, + DOB_REG => DO_REG, + INIT_A => init_a_pattern, + INIT_B => init_b_pattern, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => "NONE", + SIM_DEVICE => "SPARTAN6", + SRVAL_A => srval_a_pattern, + SRVAL_B => srval_b_pattern, + DATA_WIDTH_A => 36, + DATA_WIDTH_B => 36, + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE + + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLK, + CLKB => CLK, + DIA => di_pattern(63 downto 32), + DIB => di_pattern(31 downto 0), + DIPA => dip_pattern(7 downto 4), + DIPB => dip_pattern(3 downto 0), + ENA => EN, + ENB => EN, + REGCEA => REGCE, + REGCEB => REGCE, + RSTA => RST, + RSTB => RST, + WEA => we_pattern(7 downto 4), + WEB => we_pattern(3 downto 0), + DOA => do_pattern(63 downto 32), + DOB => do_pattern(31 downto 0), + DOPA => dop_pattern(7 downto 4), + DOPB => dop_pattern(3 downto 0) + ); + end generate ramb18_sin_st_1; + end generate ramb_st; + -- end generate spartan6 +end bram_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_TDP_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_TDP_MACRO.vhd new file mode 100644 index 0000000..ec13223 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/BRAM_TDP_MACRO.vhd @@ -0,0 +1,2665 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 14.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for True Dual Port Block RAM +-- /___/ /\ Filename : BRAM_TDP_MACRO.vhd +-- \ \ / \ Timestamp : Wed April 11 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 04/11/08 - Initial version. +-- 05/25/11 - 607722 - Reset output latch for DO_REG=1 +-- 10/26/11 - 624543 - Fix DO for assymetric widths, drc to check for read,write widths equal or ratio of 2. +-- 11/30/11 - 636062 - Fix drc and do +-- 01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking. +-- 04/24/12 - 657517 - fix for write_width = 2* read_width +-- 11/01/12 - 679413 - pass INIT_FILE to Spartan6 BRAM +-- 09/29/14 - Update DI and DO for parity intersperse every byte (CR 773917). +-- End Revision + +----- CELL BRAM_TDP_MACRO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library unisim; +use unisim.VCOMPONENTS.all; +library STD; +use STD.TEXTIO.ALL; + + +entity BRAM_TDP_MACRO is +generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH_A : integer := 1; + READ_WIDTH_B : integer := 1; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; -- This parameter is valid only for Virtex5 + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 1; + WRITE_WIDTH_B : integer := 1 + + ); +port ( + + DOA : out std_logic_vector(READ_WIDTH_A-1 downto 0); + DOB : out std_logic_vector(READ_WIDTH_B-1 downto 0); + + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(WRITE_WIDTH_A-1 downto 0); + DIB : in std_logic_vector(WRITE_WIDTH_B-1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + + ); +end BRAM_TDP_MACRO; + +architecture bram_V of BRAM_TDP_MACRO is + + function GetDIAWidth ( + wr_widtha : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case wr_widtha is + when 0 => func_width := 1; + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". This attribute must atleast be equal to 1. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s1 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s1 + else + func_width := 32; + end if; + when others => if(func_bram_size = "18Kb" or func_bram_size = "9Kb") then + func_width := 16; + else + func_width := 32; + end if; + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s2 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s2 + end if; + end case; + else + func_width := 32; + end if; + return func_width; + end; + + function GetDIBWidth ( + wr_widthb : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case wr_widthb is + when 0 => func_width := 1; + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_B : ") ); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". This attribute must atleast be equal to 1 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_B : ") ); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s3 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_B : ") ); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s3 + else + func_width := 32; + end if; + when others => if(func_bram_size = "18Kb" or func_bram_size = "9Kb") then + func_width := 16; + else + func_width := 32; + end if; + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s4 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute WRITE_WIDTH_A : ") ); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s4 + end if; + + end case; + else + func_width := 32; + end if; + return func_width; + end; + + function GetDOAWidth ( + rd_widtha : in integer; + func_bram_size : in string; + device : in string; + wr_widtha : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + -- begin s26 + if(DEVICE = "SPARTAN6") then + if(rd_widtha /= wr_widtha) then + write( Message, STRING'("WRITE_WIDTH_A and READ_WIDTH_A must be equal. ") ); + write ( Message, WRITE_WIDTH_A); + write ( Message, READ_WIDTH_A); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; -- end s26 + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((rd_widtha /= wr_widtha) and (rd_widtha/wr_widtha /=2) and (wr_widtha/rd_widtha /=2) and ( (rd_widtha /= 1 and rd_widtha /= 2 and rd_widtha /= 4 and rd_widtha /= 8 and rd_widtha /= 9 and rd_widtha /= 16 and rd_widtha /= 18 and rd_widtha /= 32 and rd_widtha /= 36) or (wr_widtha /= 1 and wr_widtha /= 2 and wr_widtha /= 4 and wr_widtha /= 8 and wr_widtha /= 9 and wr_widtha /= 16 and wr_widtha /= 18 and wr_widtha /= 32 and wr_widtha /= 36)) ) then + write( Message, STRING'("Illegal values of Attributes READ_WIDTH_A, WRITE_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write ( Message, STRING'(" and ")); + write ( Message, WRITE_WIDTH_A); + write( Message, STRING'(". To use BRAM_TDP_MACRO. One of the following conditions must be true- 1. READ_WIDTH must be equal to WRITE_WIDTH 2. If assymetric, READ_WIDTH and WRITE_WIDTH must have a ratio of 2. 3. If assymetric, READ_WIDTH and WRITE_WIDTH should have values 1, 2, 4, 8, 9, 16, 18, 32, 36.")); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + case rd_widtha is + when 0 => func_width := 1; + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES")) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s5 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s5 + else + func_width := 32; + end if; + when others => if(func_bram_size = "18Kb" or func_bram_size = "9Kb") then + func_width := 16; + else + func_width := 32; + end if; + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s6 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_A : ") ); + write ( Message, READ_WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s6 + end if; + end case; + else + func_width := 32; + end if; + return func_width; + end; + + function GetDOBWidth ( + rd_widthb : in integer; + func_bram_size : in string; + device : in string; + wr_widthb : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + -- begin s27 + if(DEVICE = "SPARTAN6") then + if(rd_widthb /= wr_widthb) then + write( Message, STRING'("WRITE_WIDTH_B and READ_WIDTH_B must be equal. ") ); + write ( Message, WRITE_WIDTH_B); + write ( Message, READ_WIDTH_B); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; -- end s27 + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if((rd_widthb /= wr_widthb) and (rd_widthb/wr_widthb /= 2) and (wr_widthb/rd_widthb /= 2) and ((rd_widthb /= 1 and rd_widthb /= 2 and rd_widthb /= 4 and rd_widthb /= 8 and rd_widthb /= 9 and rd_widthb /= 16 and rd_widthb /= 18 and rd_widthb /= 32 and rd_widthb /= 36 ) or (wr_widthb /= 1 and wr_widthb /= 2 and wr_widthb /= 4 and wr_widthb /= 8 and wr_widthb /= 9 and wr_widthb /= 16 and wr_widthb /= 18 and wr_widthb /= 32 and wr_widthb /= 36)) ) then + write( Message, STRING'("Illegal values of Attributes READ_WIDTH_B, WRITE_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write ( Message, STRING'(" and ")); + write ( Message, WRITE_WIDTH_B); + write( Message, STRING'(". To use BRAM_TDP_MACRO. One of the following conditions must be true- 1. READ_WIDTH must be equal to WRITE_WIDTH 2. If assymetric, READ_WIDTH and WRITE_WIDTH must have a ratio of 2. 3. If assymetric, READ_WIDTH and WRITE_WIDTH should have values 1, 2, 4, 8, 9, 16, 18, 32, 36.") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + case rd_widthb is + when 0 => func_width := 1; + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write( Message, STRING'(". This attribute must atleast be equal to 1 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => if (func_bram_size /= "36Kb" and (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES")) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s7 + elsif (func_bram_size /= "18Kb" and (DEVICE = "SPARTAN6") ) then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute for BRAM_SIZE 9Kb are ") ); + write( Message, STRING'(" 1 to 18 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s7 + else + func_width := 32; + end if; + when others => if(func_bram_size = "18Kb" or func_bram_size = "9Kb") then + func_width := 16; + else + func_width := 32; + end if; + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + -- begin s8 + elsif(DEVICE = "SPARTAN6") then + write( Message, STRING'("Illegal value of Attribute READ_WIDTH_B : ") ); + write ( Message, READ_WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 for BRAM_SIZE of 9Kb and ") ); + write( Message, STRING'(" 1 to 36 for BRAM_SIZE of 18Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); -- end s8 + end if; + end case; + else + func_width := 32; + end if; + return func_width; + end; + function GetD_Width ( + width : in integer; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case width is + when 0 => func_width := 0; + when 1 => func_width := 1; + when 2 => func_width := 2; + when 3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 9; + when 10 to 18 => func_width := 18; + when 19 to 36 => func_width := 36; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetDPWidth ( + width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when others => func_width := 0; + end case; + else + func_width := 0; + end if; + return func_width; + end; + function GetLeastWidthA ( + wr_width_a : in integer; + rd_width_a : in integer + ) return integer is + variable func_least_width : integer; + begin + if (wr_width_a <= rd_width_a) then + func_least_width := wr_width_a; + else + func_least_width := rd_width_a; + end if; + return func_least_width; + end; + + function GetLeastWidthB ( + wr_width_b : in integer; + rd_width_b : in integer + ) return integer is + variable func_least_width : integer; + begin + if (wr_width_b <= rd_width_b) then + func_least_width := wr_width_b; + else + func_least_width := rd_width_b; + end if; + return func_least_width; + end; + + function GetADDRWidth ( + least_width : in integer; + func_bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + case least_width is + when 1 => if (func_bram_size = "9Kb") then + func_width := 13; + elsif (func_bram_size = "18Kb") then + func_width := 14; + else + func_width := 15; + end if; + when 2 => if (func_bram_size = "9Kb") then + func_width := 12; + elsif (func_bram_size = "18Kb") then + func_width := 13; + else + func_width := 14; + end if; + when 3|4 => if (func_bram_size = "9Kb") then + func_width := 11; + elsif (func_bram_size = "18Kb") then + func_width := 12; + else + func_width := 13; + end if; + when 5|6|7|8|9 => if (func_bram_size = "9Kb") then + func_width := 10; + elsif (func_bram_size = "18Kb") then + func_width := 11; + else + func_width := 12; + end if; + when 10 to 18 => if (func_bram_size = "9Kb") then + func_width := 9; + elsif (func_bram_size = "18Kb") then + func_width := 10; + else + func_width := 11; + end if; + when 19 to 36 => if (func_bram_size = "36Kb") then + func_width := 10; + elsif (func_bram_size = "18Kb") then + func_width := 9; + else + func_width := 9; + end if; + when others => func_width := 15; + end case; + else + func_width := 15; + end if; + return func_width; + end; + + function GetWEWidth ( + bram_size : in string; + device : in string; + wr_width : in integer + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if bram_size= "18Kb"then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + else + func_width := 2; + end if; + elsif bram_size = "36Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; + end if; + -- begin s9 + elsif(DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + else + func_width := 2; + end if; + elsif bram_size = "18Kb" then + if wr_width <= 9 then + func_width := 1; + elsif wr_width > 9 and wr_width <= 18 then + func_width := 2; + elsif wr_width > 18 and wr_width <= 36 then + func_width := 4; + else + func_width := 4; + end if; + end if; -- end s9 + else + func_width := 4; + end if; + return func_width; + end; + + function GetMaxADDRSize ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if bram_size = "9Kb" then + func_width := 13; + elsif bram_size = "18Kb" then + func_width := 14; + elsif bram_size = "36Kb" then + func_width := 16; + else + func_width := 16; + end if; + else + func_width := 16; + end if; + return func_width; + end; + + function GetMaxDataSize ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "9Kb") then + func_width := 16; + elsif bram_size = "36Kb" then + func_width := 32; + else + func_width := 32; + end if; + -- begin s11 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + func_width := 16; + elsif bram_size = "18Kb" then + func_width := 32; + else + func_width := 32; + end if; -- end s11 + else + func_width := 32; + end if; + return func_width; + end; + + function GetMaxDataPSize ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "9Kb") then + func_width := 2; + elsif bram_size = "36Kb" then + func_width := 4; + else + func_width := 4; + end if; + -- begin s12 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + func_width := 2; + elsif bram_size = "18Kb" then + func_width := 4; + else + func_width := 4; + end if; -- end s12 + else + func_width := 4; + end if; + return func_width; + end; + + function GetMaxWESize ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "9Kb") then + func_width := 2; + elsif bram_size = "36Kb" then + func_width := 4; + else + func_width := 4; + end if; + -- begin s13 + elsif (DEVICE = "SPARTAN6") then + if bram_size = "9Kb" then + func_width := 2; + elsif bram_size = "18Kb" then + func_width := 4; + else + func_width := 4; + end if; -- end s13 + else + func_width := 4; + end if; + return func_width; + end; + + function GetMaxWESize_bl ( + bram_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if bram_size = "18Kb" then + func_width := 4; + elsif bram_size = "36Kb" then + func_width := 8; + else + func_width := 8; + end if; + return func_width; + end; + function GetFinalWidth ( + width : in integer + ) return integer is + variable func_least_width : integer; + begin + if (width = 0) then + func_least_width := 1; + else + func_least_width := width; + end if; + return func_least_width; + end; + + function GetBRAMSize ( + bram_size : in string; + device : in string + ) return boolean is + variable bram_val : boolean; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ( DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (bram_size = "18Kb" or bram_size = "36Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 18Kb, 36Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; + -- begin s14 + if (DEVICE = "SPARTAN6") then + if(bram_size = "9Kb" or bram_size = "18Kb") then + bram_val := TRUE; + else + bram_val := FALSE; + write( Message, STRING'("Illegal value of Attribute BRAM_SIZE : ") ); + write ( Message, BRAM_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 9Kb, 18Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + end if; -- end s14 + return bram_val; + end; + + function Get_P ( + wd : in integer; + device : in string + ) return boolean is + variable wp : boolean; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if wd = 9 or wd = 17 or wd = 18 or wd = 33 or wd = 34 or wd = 35 or wd = 36 then + wp := TRUE; + else + wp := FALSE; + end if; + else + wp := FALSE; + end if; + return wp; + end; + + function CheckParity ( + wp_a, wp_b, rp_a, rp_b : in boolean; + device : in string + ) return boolean is + variable Message : LINE; + variable check : boolean; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + if ( (wp_a = FALSE and wp_b = FALSE and rp_a = FALSE and rp_b = FALSE) or (wp_a = FALSE and wp_b = TRUE and rp_a = TRUE and rp_b = FALSE) or (wp_a = TRUE and wp_b = FALSE and rp_a = TRUE and rp_b = FALSE) or (wp_a = FALSE and wp_b = TRUE and rp_a = FALSE and rp_b = TRUE) or (wp_a = TRUE and wp_b = FALSE and rp_a = FALSE and rp_b = TRUE) or (wp_a = TRUE and wp_b = TRUE and rp_a = FALSE and rp_b = TRUE) or (wp_a = TRUE and wp_b = TRUE and rp_a = TRUE and rp_b = FALSE) or (wp_a = TRUE and wp_b = FALSE and rp_a = TRUE and rp_b = TRUE) or (wp_a = FALSE and wp_b = TRUE and rp_a = TRUE and rp_b = TRUE) or (wp_a = TRUE and wp_b = TRUE and rp_a = TRUE and rp_b = TRUE) ) then + check := FALSE; + elsif(wp_a = FALSE and wp_b = TRUE and rp_a = FALSE and rp_b = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("WRITE_WIDTH_B on BRAM_TDP_MACRO is set to ") ); + write( Message, WRITE_WIDTH_B); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = TRUE and wp_b = FALSE and rp_a = FALSE and rp_b = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("WRITE_WIDTH_A on BRAM_TDP_MACRO is set to ") ); + write( Message, WRITE_WIDTH_A); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = TRUE and wp_b = TRUE and rp_a = FALSE and rp_b = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("WRITE_WIDTH_A on BRAM_TDP_MACRO is set to ") ); + write( Message, WRITE_WIDTH_A); + write( Message, STRING'(" and WRITE_WIDTH_B on BRAM_TDP_MACRO is set to ") ); + write( Message, WRITE_WIDTH_B); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = FALSE and wp_b = FALSE and rp_a = TRUE and rp_b = FALSE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("READ_WIDTH_A on BRAM_TDP_MACRO is set to ") ); + write( Message, READ_WIDTH_A); + write( Message, STRING'(". The parity bit(s) have not been written and hence cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = FALSE and wp_b = FALSE and rp_a = FALSE and rp_b = TRUE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("READ_WIDTH_B on BRAM_TDP_MACRO is set to ") ); + write( Message, READ_WIDTH_B); + write( Message, STRING'(". The parity bit(s) have not been written and hence cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + elsif(wp_a = FALSE and wp_b = FALSE and rp_a = TRUE and rp_b = TRUE) then + write( Message, STRING'("Port Width Mismatch : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("READ_WIDTH_A on BRAM_TDP_MACRO is set to ") ); + write( Message, READ_WIDTH_A); + write( Message, STRING'(" and READ_WIDTH_B on BRAM_TDP_MACRO is set to ") ); + write( Message, READ_WIDTH_B); + write( Message, STRING'(". The parity bit(s) cannot be read") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Warning; + DEALLOCATE (Message); + end if; + end if; + return check; + end; + + function GetSIMDev ( + device : in string + ) return string is + begin + if(DEVICE = "VIRTEX6") then + return "VIRTEX6"; + else + return "7SERIES"; + end if; + end; + + function GetValWidth_A ( + rd_widtha : in integer; + wr_widtha : in integer + ) return boolean is + begin + if ((rd_widtha = 1 or rd_widtha = 2 or rd_widtha = 4 or rd_widtha = 8 or rd_widtha = 9 or rd_widtha = 16 or rd_widtha = 18 or rd_widtha = 32 or rd_widtha = 36 ) and (wr_widtha = 1 or wr_widtha = 2 or wr_widtha = 4 or wr_widtha = 8 or wr_widtha = 9 or wr_widtha = 16 or wr_widtha = 18 or wr_widtha = 32 or wr_widtha = 36 )) then + return TRUE; + else + return FALSE; + end if; + end; + + function GetValWidth_B ( + rd_widthb : in integer; + wr_widthb : in integer + ) return boolean is + begin + if ((rd_widthb = 1 or rd_widthb = 2 or rd_widthb = 4 or rd_widthb = 8 or rd_widthb = 9 or rd_widthb = 16 or rd_widthb = 18 or rd_widthb = 32 or rd_widthb = 36) and (wr_widthb = 1 or wr_widthb = 2 or wr_widthb = 4 or wr_widthb = 8 or wr_widthb = 9 or wr_widthb = 16 or wr_widthb = 18 or wr_widthb = 32 or wr_widthb = 36)) then + return TRUE; + else + return FALSE; + end if; + end; + + function CheckWEAWidth ( + wr_width : in integer; + wea_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if ( wr_width <= 9 and wea_vec /= 1) then + write( Message, STRING'("WEA port width incorrectly set for WRITE_WIDTH_A : ") ); + write( Message, WRITE_WIDTH_A); + write( Message, STRING'(". WEA port width must be of width 1 (0 downto 0) . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 9 and wr_width <= 18) and wea_vec /= 2) then + write( Message, STRING'("WEA port width incorrectly set for WRITE_WIDTH_A : ") ); + write( Message, WRITE_WIDTH_A); + write( Message, STRING'(". WEA port width must be of width 2 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 18 and wr_width <= 36) and wea_vec /= 4) then + write( Message, STRING'("WEA port width incorrectly set for WRITE_WIDTH_A : ") ); + write( Message, WRITE_WIDTH_A); + write( Message, STRING'(". WEA port width must be of width 4 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + end; +function CheckWEBWidth ( + wr_width : in integer; + web_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if ( wr_width <= 9 and web_vec /= 1) then + write( Message, STRING'("WEB port width incorrectly set for WRITE_WIDTH_B : ") ); + write( Message, WRITE_WIDTH_B); + write( Message, STRING'(". WEB port width must be of width 1 (0 downto 0) . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 9 and wr_width <= 18) and web_vec /= 2) then + write( Message, STRING'("WEB port width incorrectly set for WRITE_WIDTH_B : ") ); + write( Message, WRITE_WIDTH_B); + write( Message, STRING'(". WEB port width must be of width 2 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ( (wr_width > 18 and wr_width <= 36) and web_vec /= 4) then + write( Message, STRING'("WEB port width incorrectly set for WRITE_WIDTH_B : ") ); + write( Message, WRITE_WIDTH_B); + write( Message, STRING'(". WEB port width must be of width 4 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + end; + +function CheckADDRAWidth ( + least_width : in integer; + func_bram_size : in string; + device : in string; + addra_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if (func_bram_size = "9Kb") then + if (least_width = 1 and addra_vec /= 13) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addra_vec /= 12) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addra_vec /= 11) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addra_vec /= 10) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addra_vec /= 9) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "18Kb") then + if (least_width = 1 and addra_vec /= 14) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addra_vec /= 13) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addra_vec /= 12) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addra_vec /= 11) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addra_vec /= 10) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 18 and least_width <= 36) and addra_vec /= 9) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "36Kb") then + if (least_width = 1 and addra_vec /= 15) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 15 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addra_vec /= 14) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addra_vec /= 13) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addra_vec /= 12) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addra_vec /= 11) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 18 and least_width <= 36) and addra_vec /= 10) then + write( Message, STRING'("ADDRA port width incorrectly set. ") ); + write( Message, STRING'(". ADDRA port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + else + return TRUE; + end if; + end; + + function CheckADDRBWidth ( + least_width : in integer; + func_bram_size : in string; + device : in string; + addrb_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if (func_bram_size = "9Kb") then + if (least_width = 1 and addrb_vec /= 13) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addrb_vec /= 12) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addrb_vec /= 11) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addrb_vec /= 10) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addrb_vec /= 9) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "18Kb") then + if (least_width = 1 and addrb_vec /= 14) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addrb_vec /= 13) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addrb_vec /= 12) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addrb_vec /= 11) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addrb_vec /= 10) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 18 and least_width <= 36) and addrb_vec /= 9) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 9 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + elsif (func_bram_size = "36Kb") then + if (least_width = 1 and addrb_vec /= 15) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 15 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif (least_width = 2 and addrb_vec /= 14) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 14 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 2 and least_width <= 4) and addrb_vec /= 13) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 13 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 4 and least_width <= 9) and addrb_vec /= 12) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 12 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 9 and least_width <= 18) and addrb_vec /= 11) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 11 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + elsif ((least_width > 18 and least_width <= 36) and addrb_vec /= 10) then + write( Message, STRING'("ADDRB port width incorrectly set. ") ); + write( Message, STRING'(". ADDRB port width must be of width 10 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return FALSE; + else + return TRUE; + end if; + else + return TRUE; + end if; + end; + + + function Get_Parity_Width ( + wd : in integer + ) return integer is + variable wp : integer; + begin + if (wd = 9 or wd = 17 or wd = 33) then + wp := 1; + elsif (wd = 18 or wd = 34) then + wp := 2; + elsif (wd = 35) then + wp := 3; + elsif (wd = 36) then + wp := 4; + else + wp := 4; + end if; + return wp; + end; + + + function Pad_INIT_SRVAL ( + func_in_init_srval : in bit_vector; + func_init_srval_width_size : in integer) + return bit_vector is variable func_paded_init_srval : bit_vector(0 to func_init_srval_width_size-1) := (others=>'0'); + variable func_padded_width : integer; + begin + + if (func_in_init_srval'length > func_init_srval_width_size) then + func_padded_width := func_init_srval_width_size; + else + func_padded_width := func_in_init_srval'length; + end if; + + for i in 0 to func_padded_width-1 loop + func_paded_init_srval(((func_init_srval_width_size-1) - (func_padded_width-1)) + i) := func_in_init_srval(i); + end loop; + + return func_paded_init_srval; + end; + + + function Get_INIT_SRVAL_Width ( + func_bram_size : in string; + func_device : in string) + return integer is variable init_srval_width : integer; + begin + if(bram_size = "36Kb") then + init_srval_width := 36; + elsif(bram_size = "18Kb") then + if (func_device = "SPARTAN6") then + init_srval_width := 36; + else + init_srval_width := 20; + end if; + elsif (bram_size = "9Kb") then + init_srval_width := 20; + else + init_srval_width := 36; + end if; + + return init_srval_width; + end; + + + function INIT_SRVAL_parity_byte ( + in_init_srval : in bit_vector; + readp : in boolean; + writep : in boolean; + read_widthp : in integer; + init_srval_width : in integer) + return bit_vector is variable out_init_srval : bit_vector(0 to in_init_srval'length-1); + begin + + if (readp = TRUE and writep = TRUE) then + + if (read_widthp = 9) then + if (init_srval_width = 20) then + out_init_srval := "00000000000" & in_init_srval(11) & in_init_srval(12 to 19); + else + out_init_srval := "000000000000000000000000000" & in_init_srval(27) & in_init_srval(28 to 35); + end if; + elsif (read_widthp = 17) then + if (init_srval_width = 20) then + out_init_srval := "000" & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + else + out_init_srval := "0000000000000000000" & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + end if; + elsif (read_widthp = 18) then + if (init_srval_width = 20) then + out_init_srval := "00" & in_init_srval(2) & in_init_srval(11) & in_init_srval(3 to 10) & in_init_srval(12 to 19); + else + out_init_srval := "000000000000000000" & in_init_srval(18) & in_init_srval(27) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + end if; + elsif (read_widthp = 33) then + out_init_srval := "000" & in_init_srval(27) & in_init_srval(3 to 26) & in_init_srval(28 to 35); + elsif (read_widthp = 34) then + out_init_srval := "00" & in_init_srval(18) & in_init_srval(27) & in_init_srval(2 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + elsif (read_widthp = 35) then + out_init_srval := '0' & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + elsif (read_widthp = 36) then + out_init_srval := in_init_srval(0) & in_init_srval(9) & in_init_srval(18) & in_init_srval(27) & in_init_srval(1 to 8) & in_init_srval(10 to 17) & in_init_srval(19 to 26) & in_init_srval(28 to 35); + else + out_init_srval := in_init_srval; + end if; + + else + out_init_srval := in_init_srval; + end if; + + return out_init_srval; + + end; + + + constant bram_size_val : boolean := GetBRAMSize(BRAM_SIZE, DEVICE); + constant write_a_p : boolean := Get_P(WRITE_WIDTH_A, DEVICE); + constant write_b_p : boolean := Get_P(WRITE_WIDTH_B, DEVICE); + constant read_a_p : boolean := Get_P(READ_WIDTH_A, DEVICE); + constant read_b_p : boolean := Get_P(READ_WIDTH_B, DEVICE); + constant dia_width : integer := GetDIAWidth(WRITE_WIDTH_A, BRAM_SIZE, DEVICE); + constant dib_width : integer := GetDIBWidth(WRITE_WIDTH_B, BRAM_SIZE, DEVICE); + constant dipa_width : integer := GetDPWidth(WRITE_WIDTH_A, BRAM_SIZE, DEVICE); + constant dipb_width : integer := GetDPWidth(WRITE_WIDTH_B, BRAM_SIZE, DEVICE); + constant doa_width : integer := GetDOAWidth(READ_WIDTH_A, BRAM_SIZE, DEVICE, WRITE_WIDTH_A); + constant dob_width : integer := GetDOBWidth(READ_WIDTH_B, BRAM_SIZE, DEVICE, WRITE_WIDTH_B); + constant dopa_width : integer := GetDPWidth(READ_WIDTH_A, BRAM_SIZE, DEVICE); + constant dopb_width : integer := GetDPWidth(READ_WIDTH_B, BRAM_SIZE, DEVICE); + constant wr_a_width : integer := GetD_Width (WRITE_WIDTH_A, DEVICE); + constant wr_b_width : integer := GetD_Width (WRITE_WIDTH_B, DEVICE); + constant rd_a_width : integer := GetD_Width (READ_WIDTH_A, DEVICE); + constant rd_b_width : integer := GetD_Width (READ_WIDTH_B, DEVICE); + constant check_p : boolean := CheckParity(write_a_p, write_b_p, read_a_p, read_b_p, DEVICE); + constant least_width_A : integer := GetLeastWidthA(dia_width, doa_width); + constant least_width_B : integer := GetLeastWidthB(dib_width, dob_width); + constant addra_width : integer := GetADDRWidth(least_width_A, BRAM_SIZE, DEVICE); + constant addrb_width : integer := GetADDRWidth(least_width_B, BRAM_SIZE, DEVICE); + constant wea_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, WRITE_WIDTH_A); + constant web_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, WRITE_WIDTH_B); + constant rda_byte_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, READ_WIDTH_A); + constant rdb_byte_width : integer := GetWEWidth(BRAM_SIZE, DEVICE, READ_WIDTH_B); + constant fin_rda_width : integer := GetFinalWidth(READ_WIDTH_A); + constant fin_rdb_width : integer := GetFinalWidth(READ_WIDTH_B); + constant fin_wra_width : integer := GetFinalWidth(WRITE_WIDTH_A); + constant fin_wrb_width : integer := GetFinalWidth(WRITE_WIDTH_B); + constant sim_device_dp : string := GetSIMDev(DEVICE); + constant valid_width_a : boolean := GetValWidth_A(READ_WIDTH_A,WRITE_WIDTH_A); + constant valid_width_b : boolean := GetValWidth_B(READ_WIDTH_B,WRITE_WIDTH_B); + constant wealeng : integer := WEA'length; + constant webleng : integer := WEB'length; + constant addraleng : integer := ADDRA'length; + constant addrbleng : integer := ADDRB'length; + constant checkwea : boolean := CheckWEAWidth(WRITE_WIDTH_A, wealeng); + constant checkweb : boolean := CheckWEBWidth(WRITE_WIDTH_B, webleng); + constant checkaddra : boolean := CheckADDRAWidth(least_width_A, BRAM_SIZE, DEVICE, addraleng); + constant checkaddrb : boolean := CheckADDRBWidth(least_width_B, BRAM_SIZE, DEVICE, addrbleng); + + constant max_addr_width : integer := GetMaxADDRSize(BRAM_SIZE, DEVICE); + constant max_data_width : integer := GetMaxDataSize(BRAM_SIZE, DEVICE); + constant max_datap_width : integer := GetMaxDataPSize(BRAM_SIZE, DEVICE); + constant max_we_width : integer := GetMaxWESize(BRAM_SIZE, DEVICE); + constant max_web_width_bl : integer := GetMaxWESize_bl(BRAM_SIZE, DEVICE); + + constant reada_double : integer := (2*READ_WIDTH_A); + constant readb_double : integer := (2*READ_WIDTH_B); + + constant init_srval_width_size : integer := Get_INIT_SRVAL_Width(BRAM_SIZE, DEVICE); + constant padded_init_a : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(INIT_A, init_srval_width_size); + constant padded_init_b : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(INIT_B, init_srval_width_size); + constant padded_srval_a : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(SRVAL_A, init_srval_width_size); + constant padded_srval_b : bit_vector(0 to init_srval_width_size-1) := Pad_INIT_SRVAL(SRVAL_B, init_srval_width_size); + constant wra_widthp : integer := Get_Parity_Width(WRITE_WIDTH_A); + constant wrb_widthp : integer := Get_Parity_Width(WRITE_WIDTH_B); + constant rda_widthp : integer := Get_Parity_Width(READ_WIDTH_A); + constant rdb_widthp : integer := Get_Parity_Width(READ_WIDTH_B); + + signal addra_pattern : std_logic_vector(max_addr_width-1 downto 0) := (others=> '0'); + signal addrb_pattern : std_logic_vector(max_addr_width-1 downto 0) := (others=> '0'); + + signal dia_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal dib_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal dipa_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal dipb_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal doa_pattern : std_logic_vector(max_data_width-1 downto 0); + signal dob_pattern : std_logic_vector(max_data_width-1 downto 0); + signal dopa_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal dopb_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal wea_pattern : std_logic_vector(max_we_width-1 downto 0) := (others=>'0'); + signal web_pattern : std_logic_vector(max_we_width-1 downto 0) := (others=>'0'); + signal web_pattern_bl : std_logic_vector(max_web_width_bl-1 downto 0) := (others=>'0'); + + signal rstrama_pattern : std_logic := '0'; + signal rstramb_pattern : std_logic := '0'; + signal rstrega_pattern : std_logic := '0'; + signal rstregb_pattern : std_logic := '0'; + +begin + + a1 : addra_pattern <= + -- begin s15 + ADDRA when (BRAM_SIZE = "9Kb" and addra_width = 13 ) else + (ADDRA & '1') when (BRAM_SIZE = "9Kb" and addra_width = 12 ) else + (ADDRA & "11") when (BRAM_SIZE = "9Kb" and addra_width = 11 ) else + (ADDRA & "111") when (BRAM_SIZE = "9Kb" and addra_width = 10 ) else + (ADDRA & "1111") when (BRAM_SIZE = "9Kb" and addra_width = 9) else -- end s15 + ADDRA when (BRAM_SIZE = "18Kb" and addra_width = 14 ) else + (ADDRA & '1') when (BRAM_SIZE = "18Kb" and addra_width = 13 ) else + (ADDRA & "11") when (BRAM_SIZE = "18Kb" and addra_width = 12 ) else + (ADDRA & "111") when (BRAM_SIZE = "18Kb" and addra_width = 11 ) else + (ADDRA & "1111") when (BRAM_SIZE = "18Kb" and addra_width = 10 ) else + (ADDRA & "11111") when (BRAM_SIZE = "18Kb" and addra_width = 9 ) else + ADDRA when (BRAM_SIZE = "36Kb" and addra_width = 16 ) else + ('1' & ADDRA) when (BRAM_SIZE = "36Kb" and addra_width = 15 ) else + ('1' & ADDRA & '1') when (BRAM_SIZE = "36Kb" and addra_width = 14 ) else + ('1' & ADDRA & "11") when (BRAM_SIZE = "36Kb" and addra_width = 13) else + ('1' & ADDRA & "111") when (BRAM_SIZE = "36Kb" and addra_width = 12 ) else + ('1' & ADDRA & "1111") when (BRAM_SIZE = "36Kb" and addra_width = 11 ) else + ('1' & ADDRA & "11111") when (BRAM_SIZE = "36Kb" and addra_width = 10 ) else + ADDRA; + a2 : addrb_pattern <= + -- begin s16 + ADDRB when (BRAM_SIZE = "9Kb" and addrb_width = 13 ) else + (ADDRB & '1') when (BRAM_SIZE = "9Kb" and addrb_width = 12 ) else + (ADDRB & "11") when (BRAM_SIZE = "9Kb" and addrb_width = 11 ) else + (ADDRB & "111") when (BRAM_SIZE = "9Kb" and addrb_width = 10 ) else + (ADDRB & "1111") when (BRAM_SIZE = "9Kb" and addrb_width = 9 ) else -- end s16 + ADDRB when (BRAM_SIZE = "18Kb" and addrb_width = 14 ) else + (ADDRB & '1') when (BRAM_SIZE = "18Kb" and addrb_width = 13 ) else + (ADDRB & "11") when (BRAM_SIZE = "18Kb" and addrb_width = 12 ) else + (ADDRB & "111") when (BRAM_SIZE = "18Kb" and addrb_width = 11 ) else + (ADDRB & "1111") when (BRAM_SIZE = "18Kb" and addrb_width = 10 ) else + (ADDRB & "11111") when (BRAM_SIZE = "18Kb" and addrb_width = 9 ) else + ADDRB when (BRAM_SIZE = "36Kb" and addrb_width = 16 ) else + ('1' & ADDRB) when (BRAM_SIZE = "36Kb" and addrb_width = 15 ) else + ('1' & ADDRB & '1') when (BRAM_SIZE = "36Kb" and addrb_width = 14 ) else + ('1' & ADDRB & "11") when (BRAM_SIZE = "36Kb" and addrb_width = 13 ) else + ('1' & ADDRB & "111") when (BRAM_SIZE = "36Kb" and addrb_width = 12 ) else + ('1' & ADDRB & "1111") when (BRAM_SIZE = "36Kb" and addrb_width = 11 ) else + ('1' & ADDRB & "11111") when (BRAM_SIZE = "36Kb" and addrb_width = 10 ) else + ADDRB; + + + dia1_v5 : if ( ((DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") and ((BRAM_SIZE = "18Kb" and WRITE_WIDTH_A <= 18) or (BRAM_SIZE = "36Kb" and WRITE_WIDTH_A <= 36))) or ( (DEVICE = "SPARTAN6") and ((BRAM_SIZE = "9Kb" and WRITE_WIDTH_A <= 18) or (BRAM_SIZE = "18Kb" and WRITE_WIDTH_A <= 36) ) ) ) generate + begin + dia1 : if (write_a_p = TRUE and read_a_p = TRUE) generate + + dia11 : if (WRITE_WIDTH_A = 33) generate + dia_pattern <= DIA(32 downto 9) & DIA(7 downto 0); + end generate dia11; + + dia12 : if (WRITE_WIDTH_A = 34) generate + dia_pattern <= DIA(33 downto 18) & DIA(16 downto 9) & DIA(7 downto 0); + end generate dia12; + + dia13 : if (WRITE_WIDTH_A = 35 or WRITE_WIDTH_A = 36 or WRITE_WIDTH_A <= 32) generate + ia1 : for i in 0 to wea_width-1 generate + dia_pattern((i*8)+7 downto (i*8)) <= DIA(((i*8)+i)+7 downto ((i*8)+i)); + end generate ia1; + end generate dia13; + + ia1p : for j in 1 to wra_widthp generate + dipa_pattern(j-1) <= DIA((j*8)+j-1); + end generate ia1p; + + end generate dia1; + dia2 : if ( (read_a_p = FALSE and write_a_p = FALSE) and ((READ_WIDTH_A = WRITE_WIDTH_A) or (READ_WIDTH_A/WRITE_WIDTH_A = 2) or (valid_width_a = TRUE)) ) generate + dia_pattern(fin_wra_width-1 downto 0) <= DIA(fin_wra_width-1 downto 0); + end generate dia2; + dia3 : if ((READ_WIDTH_A = 1 and WRITE_WIDTH_A = 2) or (READ_WIDTH_A = 2 and WRITE_WIDTH_A = 4) or (READ_WIDTH_A = 4 and WRITE_WIDTH_A = 8) or (READ_WIDTH_A = 8 and WRITE_WIDTH_A = 16) or (READ_WIDTH_A = 16 and WRITE_WIDTH_A = 32) or (READ_WIDTH_A = 32 and WRITE_WIDTH_A = 64 )) generate + dia_pattern(fin_wra_width-1 downto 0) <= DIA(fin_wra_width-1 downto 0); + end generate dia3; + dia4 : if ( (read_a_p = FALSE and write_a_p = FALSE) and (WRITE_WIDTH_A/READ_WIDTH_A = 2)) generate + dia_pattern(READ_WIDTH_A-1 downto 0) <= DIA(READ_WIDTH_A-1 downto 0); + dia_pattern (reada_double-1 downto READ_WIDTH_A) <= DIA(reada_double-1 downto READ_WIDTH_A); + end generate dia4; + end generate dia1_v5; + -- begin s17 + + dib1_v5 : if ( ((DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") and ((BRAM_SIZE = "18Kb" and WRITE_WIDTH_B <= 18) or (BRAM_SIZE = "36Kb" and WRITE_WIDTH_B <= 36))) or ( (DEVICE = "SPARTAN6") and ((BRAM_SIZE = "9Kb" and WRITE_WIDTH_B <= 18) or (BRAM_SIZE = "18Kb" and WRITE_WIDTH_B <= 36) ) ) ) generate + begin + dib1 : if (write_b_p = TRUE and read_b_p = TRUE) generate + + dib11 : if (WRITE_WIDTH_B = 33) generate + dib_pattern <= DIB(32 downto 9) & DIB(7 downto 0); + end generate dib11; + + dib12 : if (WRITE_WIDTH_B = 34) generate + dib_pattern <= DIB(33 downto 18) & DIB(16 downto 9) & DIB(7 downto 0); + end generate dib12; + + dib13 : if (WRITE_WIDTH_B = 35 or WRITE_WIDTH_B = 36 or WRITE_WIDTH_B <= 32) generate + ib1 : for i in 0 to web_width-1 generate + dib_pattern((i*8)+7 downto (i*8)) <= DIB(((i*8)+i)+7 downto ((i*8)+i)); + end generate ib1; + end generate dib13; + + ib1p : for j in 1 to wrb_widthp generate + dipb_pattern(j-1) <= DIB((j*8)+j-1); + end generate ib1p; + + end generate dib1; + dib2 : if ( (read_b_p = FALSE and write_b_p = FALSE) and ((READ_WIDTH_B = WRITE_WIDTH_B) or (READ_WIDTH_B/WRITE_WIDTH_B = 2) or (valid_width_b = TRUE)) ) generate + dib_pattern(fin_wrb_width-1 downto 0) <= DIB(fin_wrb_width-1 downto 0); + end generate dib2; + dib3 : if ((READ_WIDTH_B = 1 and WRITE_WIDTH_B = 2) or (READ_WIDTH_B = 2 and WRITE_WIDTH_B = 4) or (READ_WIDTH_B = 4 and WRITE_WIDTH_B = 8) or (READ_WIDTH_B = 8 and WRITE_WIDTH_B = 16) or (READ_WIDTH_B = 16 and WRITE_WIDTH_B = 32) or (READ_WIDTH_B = 32 and WRITE_WIDTH_A = 64 )) generate + dib_pattern(fin_wrb_width-1 downto 0) <= DIB(fin_wrb_width-1 downto 0); + end generate dib3; + dib4 : if ( (read_b_p = FALSE and write_b_p = FALSE) and (WRITE_WIDTH_B/READ_WIDTH_B = 2)) generate + dib_pattern(READ_WIDTH_B-1 downto 0) <= DIB(READ_WIDTH_B-1 downto 0); + dib_pattern (readb_double-1 downto READ_WIDTH_B) <= DIB(readb_double-1 downto READ_WIDTH_B); + end generate dib4; + end generate dib1_v5; + + + doagen : if ( ((DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") and ((BRAM_SIZE = "18Kb" and READ_WIDTH_A <= 18) or (BRAM_SIZE = "36Kb" and READ_WIDTH_A <= 36)) ) or ((DEVICE ="SPARTAN6") and ((BRAM_SIZE = "9Kb" and READ_WIDTH_A <= 18) or (BRAM_SIZE = "18Kb" and READ_WIDTH_A <= 36)) ) ) generate + doa11 : if (read_a_p = TRUE and write_a_p = TRUE) generate + + doa111 : if (READ_WIDTH_A = 33) generate + DOA(32 downto 9) <= doa_pattern(31 downto 8); + DOA(7 downto 0) <= doa_pattern(7 downto 0); + end generate doa111; + + doa112 : if (READ_WIDTH_A = 34) generate + DOA(33 downto 18) <= doa_pattern(31 downto 16); + DOA(16 downto 9) <= doa_pattern(15 downto 8); + DOA(7 downto 0) <= doa_pattern(7 downto 0); + end generate doa112; + + doa113 : if (READ_WIDTH_A = 35 or READ_WIDTH_A = 36 or READ_WIDTH_A <= 32) generate + oa1 : for i1 in 0 to rda_byte_width-1 generate + DOA(((i1*8)+i1)+7 downto ((i1*8)+i1)) <= doa_pattern((i1*8)+7 downto (i1*8)); + end generate oa1; + end generate doa113; + + oa1p : for j1 in 1 to rda_widthp generate + DOA((j1*8)+j1-1) <= dopa_pattern(j1-1); + end generate oa1p; + + end generate doa11; + doa121 : if ( (read_a_p = FALSE and write_a_p = FALSE) and ( (READ_WIDTH_A = WRITE_WIDTH_A) or (WRITE_WIDTH_A/READ_WIDTH_A = 2) or (valid_width_a = TRUE) )) generate + DOA <= ( doa_pattern(fin_rda_width-1 downto 0) ); + end generate doa121; + doa12 : if ((READ_WIDTH_A = 2 and WRITE_WIDTH_A = 1) or (READ_WIDTH_A = 4 and WRITE_WIDTH_A = 2) or (READ_WIDTH_A = 8 and WRITE_WIDTH_A = 4) or (READ_WIDTH_A = 16 and WRITE_WIDTH_A = 8) or (READ_WIDTH_A = 32 and WRITE_WIDTH_A = 16) or (READ_WIDTH_A = 64 and WRITE_WIDTH_A = 32 )) generate + DOA <= ( doa_pattern(fin_rda_width-1 downto 0) ); + end generate doa12; + doa3 : if ((read_a_p = FALSE and write_a_p = FALSE) and (READ_WIDTH_A/WRITE_WIDTH_A = 2) and (WRITE_WIDTH_A = 3)) generate + -- write width 3 + DOA <= ( doa_pattern((4+(WRITE_WIDTH_A-1)) downto 4) & doa_pattern((WRITE_WIDTH_A-1) downto 0) ); + end generate doa3; + doa47 : if ((read_a_p = FALSE and write_a_p = FALSE) and (READ_WIDTH_A/WRITE_WIDTH_A = 2) and (WRITE_WIDTH_A > 4 and WRITE_WIDTH_A < 8)) generate + -- write width between 4 and 7 + DOA <= ( doa_pattern((8+(WRITE_WIDTH_A-1)) downto 8) & doa_pattern((WRITE_WIDTH_A-1) downto 0) ); + end generate doa47; + doa815 : if ((read_a_p = FALSE and write_a_p = FALSE) and (READ_WIDTH_A/WRITE_WIDTH_A = 2) and (WRITE_WIDTH_A > 8 and WRITE_WIDTH_A < 16) ) generate + -- write width between 8 and 15 + DOA <= ( doa_pattern((16+(WRITE_WIDTH_A-1)) downto 16) & doa_pattern((WRITE_WIDTH_A-1) downto 0) ); + end generate doa815; + + end generate doagen; + + dobgen : if ( ((DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") and ((BRAM_SIZE = "18Kb" and READ_WIDTH_B <= 18) or (BRAM_SIZE = "36Kb" and READ_WIDTH_B <= 36)) ) or ((DEVICE ="SPARTAN6") and ((BRAM_SIZE = "9Kb" and READ_WIDTH_B <= 18) or (BRAM_SIZE = "18Kb" and READ_WIDTH_B <= 36)) ) ) generate + dob11 : if (read_b_p = TRUE and write_b_p = TRUE) generate + + dob111 : if (READ_WIDTH_B = 33) generate + DOB(32 downto 9) <= dob_pattern(31 downto 8); + DOB(7 downto 0) <= dob_pattern(7 downto 0); + end generate dob111; + + dob112 : if (READ_WIDTH_B = 34) generate + DOB(33 downto 18) <= dob_pattern(31 downto 16); + DOB(16 downto 9) <= dob_pattern(15 downto 8); + DOB(7 downto 0) <= dob_pattern(7 downto 0); + end generate dob112; + + dob113 : if (READ_WIDTH_B = 35 or READ_WIDTH_B = 36 or READ_WIDTH_B <= 32) generate + ob1 : for i1 in 0 to rdb_byte_width-1 generate + DOB(((i1*8)+i1)+7 downto ((i1*8)+i1)) <= dob_pattern((i1*8)+7 downto (i1*8)); + end generate ob1; + end generate dob113; + + ob1p : for j1 in 1 to rdb_widthp generate + DOB((j1*8)+j1-1) <= dopb_pattern(j1-1); + end generate ob1p; + + end generate dob11; + dob121 : if ( (read_b_p = FALSE and write_b_p = FALSE ) and ((READ_WIDTH_B = WRITE_WIDTH_B) or (WRITE_WIDTH_B/READ_WIDTH_B = 2) or (valid_width_b = TRUE) )) generate + DOB <= ( dob_pattern(fin_rdb_width-1 downto 0) ); + end generate dob121; + dob12 : if ((READ_WIDTH_B = 2 and WRITE_WIDTH_B = 1) or (READ_WIDTH_B = 4 and WRITE_WIDTH_B = 2) or (READ_WIDTH_B = 8 and WRITE_WIDTH_B = 4) or (READ_WIDTH_B = 16 and WRITE_WIDTH_B = 8) or (READ_WIDTH_B = 32 and WRITE_WIDTH_B = 16) or (READ_WIDTH_B = 64 and WRITE_WIDTH_A = 32 )) generate + DOB <= ( dob_pattern(fin_rdb_width-1 downto 0) ); + end generate dob12; + dob3 : if ( (read_b_p = FALSE and write_b_p = FALSE ) and (READ_WIDTH_B/WRITE_WIDTH_B = 2) and (WRITE_WIDTH_B = 3)) generate + -- write width 3 + DOB <= ( dob_pattern((4+(WRITE_WIDTH_B-1)) downto 4) & dob_pattern((WRITE_WIDTH_B-1) downto 0) ); + end generate dob3; + dob47 : if ( (read_b_p = FALSE and write_b_p = FALSE ) and (READ_WIDTH_B/WRITE_WIDTH_B = 2) and (WRITE_WIDTH_B > 4 and WRITE_WIDTH_B < 8)) generate + DOB <= ( dob_pattern((8+(WRITE_WIDTH_B-1)) downto 8) & dob_pattern((WRITE_WIDTH_B-1) downto 0) ); + end generate dob47; + dob815 : if ( (read_b_p = FALSE and write_b_p = FALSE ) and (WRITE_WIDTH_B > 8 and WRITE_WIDTH_B < 16) and (READ_WIDTH_B/WRITE_WIDTH_B =2) ) generate + -- write width between 8 and 15 + DOB <= ( dob_pattern((16+(WRITE_WIDTH_B-1)) downto 16) & dob_pattern((WRITE_WIDTH_B-1) downto 0) ); + end generate dob815; + + end generate dobgen; + + + + wea1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + w1 : wea_pattern <= (WEA & WEA) when (BRAM_SIZE = "18Kb" and wea_width = 1 ) else + WEA when (BRAM_SIZE = "18Kb" and wea_width = 2 ) else + (WEA & WEA & WEA & WEA) when (BRAM_SIZE = "36Kb" and wea_width = 1 ) else + (WEA & WEA) when (BRAM_SIZE = "36Kb" and wea_width = 2 ) else + WEA when (BRAM_SIZE = "36Kb" and wea_width = 4 ) else + WEA; + end generate wea1; + -- begin s26 + wea2 : if (DEVICE = "SPARTAN6") generate + w2 : wea_pattern <= (WEA & WEA) when (BRAM_SIZE = "9Kb" and wea_width = 1 ) else + WEA when (BRAM_SIZE = "9Kb" and wea_width = 2 ) else + (WEA & WEA & WEA & WEA) when (BRAM_SIZE = "18Kb" and wea_width = 1 ) else + (WEA & WEA) when (BRAM_SIZE = "18Kb" and wea_width = 2 ) else + WEA when (BRAM_SIZE = "18Kb" and wea_width = 4 ) else + WEA; + end generate wea2; + -- end s26 + web1 : if (DEVICE = "VIRTEX5") generate + web1 : web_pattern <= (WEB & WEB) when (BRAM_SIZE = "18Kb" and web_width = 1 ) else + WEB when (BRAM_SIZE = "18Kb" and web_width = 2 ) else + (WEB & WEB & WEB & WEB) when (BRAM_SIZE = "36Kb" and web_width = 1 ) else + (WEB & WEB) when (BRAM_SIZE = "36Kb" and web_width = 2 ) else + WEB when (BRAM_SIZE = "36Kb" and web_width = 4 ) else + WEB; + end generate web1; + -- begin s27 + web2 : if (DEVICE = "SPARTAN6") generate + web2 : web_pattern <= (WEB & WEB) when (BRAM_SIZE = "9Kb" and web_width = 1 ) else + WEB when (BRAM_SIZE = "9Kb" and web_width = 2 ) else + (WEB & WEB & WEB & WEB) when (BRAM_SIZE = "18Kb" and web_width = 1 ) else + (WEB & WEB) when (BRAM_SIZE = "18Kb" and web_width = 2 ) else + WEB when (BRAM_SIZE = "18Kb" and web_width = 4 ) else + WEB; + end generate web2; + -- end s27 + web_bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + web1 : web_pattern_bl <= ("00" & WEB & WEB) when (BRAM_SIZE = "18Kb" and web_width = 1 ) else + ("00" & WEB) when (BRAM_SIZE = "18Kb" and web_width = 2 ) else + ("0000" & WEB & WEB & WEB & WEB) when (BRAM_SIZE = "36Kb" and web_width = 1) else + ("0000" & WEB & WEB) when (BRAM_SIZE = "36Kb" and web_width = 2 ) else + ("0000" & WEB) when (BRAM_SIZE = "36Kb" and web_width = 4 ) else + ("0000"& WEB); + end generate web_bl; + + r1 : rstrama_pattern <= RSTA; + r2 : rstramb_pattern <= RSTB; + r3 : rstrega_pattern <= RSTA when (DOA_REG = 1) else '0'; + r4 : rstregb_pattern <= RSTB when (DOB_REG = 1) else '0'; + + + -- begin generate virtex5 + ramb_v5 : if DEVICE = "VIRTEX5" generate + ramb18_dp : if BRAM_SIZE = "18Kb" generate + begin + + ram18 : RAMB18 + generic map( + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + READ_WIDTH_A => rd_a_width, + READ_WIDTH_B => rd_b_width, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => wr_a_width, + WRITE_WIDTH_B => wr_b_width + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLKA, + CLKB => CLKB, + DIA => dia_pattern, + DIB => dib_pattern, + DIPA => dipa_pattern, + DIPB => dipb_pattern, + ENA => ENA, + ENB => ENB, + SSRA => RSTA, + SSRB => RSTB, + WEA => wea_pattern, + WEB => web_pattern, + DOA => doa_pattern, + DOB => dob_pattern, + DOPA => dopa_pattern, + DOPB => dopb_pattern, + REGCEA => REGCEA, + REGCEB => REGCEB + ); + + end generate ramb18_dp; + + ramb36_dp : if BRAM_SIZE = "36Kb" generate + begin + ram36 : RAMB36 + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + READ_WIDTH_A => rd_a_width, + READ_WIDTH_B => rd_b_width, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => wr_a_width, + WRITE_WIDTH_B => wr_b_width + + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLKA, + CLKB => CLKB, + DIA => dia_pattern, + DIB => dib_pattern, + DIPA => dipa_pattern, + DIPB => dipb_pattern, + ENA => ENA, + ENB => ENB, + SSRA => RSTA, + SSRB => RSTB, + WEA => wea_pattern, + WEB => web_pattern, + DOA => doa_pattern, + DOB => dob_pattern, + DOPA => dopa_pattern, + DOPB => dopb_pattern, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => '0', + CASCADEINLATB => '0', + CASCADEINREGA => '0', + CASCADEINREGB => '0', + REGCEA => REGCEA, + REGCEB => REGCEB + ); + end generate ramb36_dp; + + end generate ramb_v5; + -- end generate virtex5 + -- begin generate virtex6 + ramb_bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + ramb18_dp_bl : if BRAM_SIZE = "18Kb" generate + begin + + ram18_bl : RAMB18E1 + generic map( + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + RAM_MODE => "TDP", + READ_WIDTH_A => rd_a_width, + READ_WIDTH_B => rd_b_width, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => wr_a_width, + WRITE_WIDTH_B => wr_b_width + ) + port map ( + ADDRARDADDR => addra_pattern, + ADDRBWRADDR => addrb_pattern, + CLKARDCLK => CLKA, + CLKBWRCLK => CLKB, + DIADI => dia_pattern, + DIBDI => dib_pattern, + DIPADIP => dipa_pattern, + DIPBDIP => dipb_pattern, + ENARDEN => ENA, + ENBWREN => ENB, + REGCEAREGCE => REGCEA, + REGCEB => REGCEB, + RSTRAMARSTRAM => rstrama_pattern, + RSTREGARSTREG => rstrega_pattern, + RSTRAMB => rstramb_pattern, + RSTREGB => rstregb_pattern, + WEA => wea_pattern, + WEBWE => web_pattern_bl , + DOADO => doa_pattern, + DOBDO => dob_pattern, + DOPADOP => dopa_pattern, + DOPBDOP => dopb_pattern + ); + + end generate ramb18_dp_bl; + + ramb36_dp_bl : if BRAM_SIZE = "36Kb" generate + begin + ram36_bl : RAMB36E1 + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_FILE => INIT_FILE, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => sim_device_dp, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + READ_WIDTH_A => rd_a_width, + READ_WIDTH_B => rd_b_width, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => wr_a_width, + WRITE_WIDTH_B => wr_b_width + + ) + port map ( + ADDRARDADDR => addra_pattern, + ADDRBWRADDR => addrb_pattern, + CASCADEINA => '0', + CASCADEINB => '0', + CLKARDCLK => CLKA, + CLKBWRCLK => CLKB, + DIADI => dia_pattern, + DIBDI => dib_pattern, + DIPADIP => dipa_pattern, + DIPBDIP => dipb_pattern, + ENARDEN => ENA, + ENBWREN => ENB, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + REGCEAREGCE => REGCEA, + REGCEB => REGCEB, + RSTRAMARSTRAM => rstrama_pattern, + RSTREGARSTREG => rstrega_pattern, + RSTRAMB => rstramb_pattern, + RSTREGB => rstregb_pattern, + WEA => wea_pattern, + WEBWE => web_pattern_bl, + CASCADEOUTA => OPEN, + CASCADEOUTB => OPEN, + DBITERR => OPEN, + DOADO => doa_pattern, + DOBDO => dob_pattern, + DOPADOP => dopa_pattern, + DOPBDOP => dopb_pattern, + ECCPARITY => OPEN, + RDADDRECC => OPEN, + SBITERR => OPEN + ); + end generate ramb36_dp_bl; + + end generate ramb_bl; + -- end generate virtex6 + -- begin generate spartan6 + +ramb_st : if DEVICE = "SPARTAN6" generate + ramb9_dp_st : if BRAM_SIZE = "9Kb" generate + begin + + ram9_st : RAMB8BWER + generic map( + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INIT_FILE => INIT_FILE, + DATA_WIDTH_A => rd_a_width, + DATA_WIDTH_B => rd_b_width, + RAM_MODE => "TDP", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) + port map ( + ADDRAWRADDR => addra_pattern, + ADDRBRDADDR => addrb_pattern, + CLKAWRCLK => CLKA, + CLKBRDCLK => CLKB, + DIADI => dia_pattern, + DIBDI => dib_pattern, + DIPADIP => dipa_pattern, + DIPBDIP => dipb_pattern, + ENAWREN => ENA, + ENBRDEN => ENB, + REGCEA => REGCEA, + REGCEBREGCE => REGCEB, + RSTA => RSTA, + RSTBRST => RSTB, + WEAWEL => wea_pattern, + WEBWEU => web_pattern , + DOADO => doa_pattern, + DOBDO => dob_pattern, + DOPADOP => dopa_pattern, + DOPBDOP => dopb_pattern + ); + + end generate ramb9_dp_st; + + ramb18_dp_st : if BRAM_SIZE = "18Kb" generate + begin + ram18_st : RAMB16BWER + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_SRVAL_parity_byte(padded_init_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + INIT_B => INIT_SRVAL_parity_byte(padded_init_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_DEVICE => "SPARTAN6", + SRVAL_A => INIT_SRVAL_parity_byte(padded_srval_a, read_a_p, write_a_p, READ_WIDTH_A, init_srval_width_size), + SRVAL_B => INIT_SRVAL_parity_byte(padded_srval_b, read_b_p, write_b_p, READ_WIDTH_B, init_srval_width_size), + DATA_WIDTH_A => rd_a_width, + DATA_WIDTH_B => rd_b_width, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + + ) + port map ( + ADDRA => addra_pattern, + ADDRB => addrb_pattern, + CLKA => CLKA, + CLKB => CLKB, + DIA => dia_pattern, + DIB => dib_pattern, + DIPA => dipa_pattern, + DIPB => dipb_pattern, + ENA => ENA, + ENB => ENB, + REGCEA => REGCEA, + REGCEB => REGCEB, + RSTA => RSTA, + RSTB => RSTB, + WEA => wea_pattern, + WEB => web_pattern, + DOA => doa_pattern, + DOB => dob_pattern, + DOPA => dopa_pattern, + DOPB => dopb_pattern + ); + end generate ramb18_dp_st; + + end generate ramb_st; + -- end generate spartan6 + +end bram_V; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_LOAD_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_LOAD_MACRO.vhd new file mode 100644 index 0000000..b868f32 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_LOAD_MACRO.vhd @@ -0,0 +1,329 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2008 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : COUNTER_LOAD_MACRO.vhd +-- \ \ / \ Timestamp : Fri April 18 2008 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 04/18/08 - Initial version. +-- End Revision + +----- CELL COUNTER_LOAD_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + +entity COUNTER_LOAD_MACRO is + generic ( + COUNT_BY : std_logic_vector := X"000000000001"; + DEVICE : string := "VIRTEX5"; + STYLE : string := "AUTO"; + WIDTH_DATA : integer := 48 + ); + + port ( + Q : out std_logic_vector(WIDTH_DATA-1 downto 0); + CE : in std_logic; + CLK : in std_logic; + DIRECTION : in std_logic; + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_DATA-1 downto 0); + RST : in std_logic + ); +end entity COUNTER_LOAD_MACRO; + +architecture counter of COUNTER_LOAD_MACRO is + + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckStyle ( + style : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (style = "AUTO" or style = "DSP" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute STYLE : ") ); + write ( Message, STYLE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" AUTO, DSP ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidth ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 48 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_DATA : ") ); + write ( Message, WIDTH_DATA); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 48 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + + function GetOPMODE_IN ( + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_width := 7; + elsif (DEVICE = "SPARTAN6") then + func_width := 8; + else + func_width := 8; + end if; + return func_width; + end; + + constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE); + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkStyle : boolean := CheckStyle(STYLE); + constant ChkWidth : boolean := CheckWidth(WIDTH_DATA); + +--Signal Declarations: + signal OPMODE_IN : std_logic_vector((OPMODE_WIDTH-1) downto 0); + signal ALUMODE_IN : std_logic_vector(3 downto 0); + signal CNTR_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal COUNT_BY_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal LOAD_DATA_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal D_INST : std_logic_vector(17 downto 0) := "000000000000000000"; + + +-- Architecture Section: instantiation +begin + + v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + OPMODE_IN <= ("01" & LOAD & "00" & (not LOAD) & (not LOAD) ); + end generate v; + + s : if (DEVICE = "SPARTAN6") generate + OPMODE_IN <= (not DIRECTION) & (not DIRECTION) & "001" & LOAD & "11"; + end generate s; + + Q <= CNTR_OUT(WIDTH_DATA-1 downto 0); + + load1 : if (WIDTH_DATA = 48) generate + begin + LOAD_DATA_IN <= LOAD_DATA; + end generate load1; + load2 : if (WIDTH_DATA < 48) generate + begin + l1: for i in 47 downto WIDTH_DATA generate + LOAD_DATA_IN(i) <= '0'; + end generate; + LOAD_DATA_IN(WIDTH_DATA-1 downto 0) <= LOAD_DATA; + end generate load2; + + ALUMODE_IN <= "00" & (not DIRECTION) & (not DIRECTION); + COUNT_BY_IN <= COUNT_BY; + + D_INST <= "000000" & COUNT_BY_IN(47 downto 36); + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + begin + DSP48E_1: DSP48E + generic map ( + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => CNTR_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => COUNT_BY_IN(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => COUNT_BY_IN(17 downto 0), + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => '0', + CEA2 => CE, + CEALUMODE => CE, + CEB1 => '0', + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => '0', + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); +end generate v5; + -- end generate virtex5 + -- begin generate virtex6 +bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_2: DSP48E1 + generic map ( + DREG => 0, + ADREG => 0, + MREG => 0, + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => CNTR_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => COUNT_BY_IN(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => COUNT_BY_IN(17 downto 0), + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => '0', + CEA2 => CE, + CEAD => '0', + CEALUMODE => CE, + CEB1 => '0', + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => '0', + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); +end generate bl; + -- end generate virtex6 + -- begin generate spartan6 + st : if DEVICE = "SPARTAN6" generate + begin + DSP48E_3: DSP48A1 + port map ( + BCOUT => open, + CARRYOUT => open, + CARRYOUTF => open, + M => open, + P => CNTR_OUT, + PCOUT => open, + A => COUNT_BY_IN(35 downto 18), + B => COUNT_BY_IN(17 downto 0), + C => LOAD_DATA_IN, + CARRYIN => '0', + CEA => CE, + CEB => CE, + CEC => CE, + CECARRYIN => CE, + CED => CE, + CEM => '0', + CEOPMODE => CE, + CEP => CE, + CLK => CLK, + D => D_INST, + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTB => RST, + RSTC => RST, + RSTCARRYIN => RST, + RSTD => RST, + RSTM => RST, + RSTOPMODE => RST, + RSTP => RST + ); + end generate st; + -- end generate spartan6 + +end counter; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_TC_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_TC_MACRO.vhd new file mode 100644 index 0000000..afb5675 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_TC_MACRO.vhd @@ -0,0 +1,301 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : COUNTER_TC_MACRO.vhd +-- \ \ / \ Timestamp : Fri April 18 2008 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 06/08/08 - Initial version. +-- 01/04/12 - Fix for CR 639887 +-- End Revision + +----- CELL COUNTER_TC_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + +entity COUNTER_TC_MACRO is + generic ( + COUNT_BY : std_logic_vector := X"000000000001"; + DEVICE : string := "VIRTEX5"; + DIRECTION : string := "UP"; + RESET_UPON_TC : string := "FALSE"; + STYLE : string := "AUTO"; + TC_VALUE : std_logic_vector := X"000000000000"; + WIDTH_DATA : integer := 48 + ); + + port ( + Q : out std_logic_vector(WIDTH_DATA-1 downto 0); + TC : out std_logic; + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end entity COUNTER_TC_MACRO; + +architecture count of COUNTER_TC_MACRO is + + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckStyle ( + style : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (style = "AUTO" or style = "DSP" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute STYLE : ") ); + write ( Message, STYLE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" AUTO, DSP ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidth ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 48 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_DATA : ") ); + write ( Message, WIDTH_DATA); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 48 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + + function CheckReset ( + reset : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (reset = "TRUE" or reset = "FALSE" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute RESET_UPON_TC : ") ); + write ( Message, STYLE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" TRUE or FALSE ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + + function GetDirection ( + dir : in string + ) return std_logic is + variable func_val : std_logic; + variable Message : LINE; + begin + if (DIRECTION = "UP") then + func_val := '0'; + elsif (DIRECTION = "DOWN") then + func_val := '1'; + else + write( Message, STRING'("Illegal value of Attribute DIRECTION : ") ); + write ( Message, DIRECTION); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" UP or DOWN ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + + +--Signal Declarations: + + signal ALUMODE_IN : std_logic_vector(3 downto 0); + signal OPMODE_IN : std_logic_vector(6 downto 0); + signal CNTR_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal COUNT_BY_INP : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal Q_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal TC_INT : std_logic; + + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkStyle : boolean := CheckStyle(STYLE); + constant ChkWidth : boolean := CheckWidth(WIDTH_DATA); + constant ChkReset : boolean := CheckReset(RESET_UPON_TC); + constant ADD_SUB : std_logic := GetDirection(DIRECTION); + +-- Architecture Section: instantiation +begin + + t1 : TC_INT <= '1' when ( CNTR_OUT = (TC_VALUE -1) and RST = '0') else '0'; + t2 : TC <= '1' when ( CNTR_OUT = TC_VALUE and RST = '0') else '0'; + op : OPMODE_IN <= ('0' & (not TC_INT) & "000" & (not TC_INT) & (not TC_INT) ) when (RESET_UPON_TC = "TRUE") else "0100011"; + Q <= Q_IN(WIDTH_DATA-1 downto 0) when (RST = '1' or (RESET_UPON_TC = "TRUE" and CNTR_OUT = (TC_VALUE+1))) else CNTR_OUT(WIDTH_DATA-1 downto 0); + + ALUMODE_IN <= "00" & ADD_SUB & ADD_SUB; + COUNT_BY_INP <= COUNT_BY; + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + begin + DSP48E_1: DSP48E + generic map ( + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => CNTR_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => COUNT_BY_INP(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => COUNT_BY_INP(17 downto 0), + BCIN => "000000000000000000", + C => "000000000000000000000000000000000000000000000000", + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => '0', + CEA2 => CE, + CEALUMODE => CE, + CEB1 => '0', + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => '0', + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); +end generate v5; + -- end generate virtex5 + -- begin generate virtex6 +bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_2: DSP48E1 + generic map ( + DREG => 0, + ADREG => 0, + MREG => 0, + USE_MULT => "NONE") + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => CNTR_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => COUNT_BY_INP(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => COUNT_BY_INP(17 downto 0), + BCIN => "000000000000000000", + C => "000000000000000000000000000000000000000000000000", + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => '0', + CEA2 => CE, + CEAD => '0', + CEALUMODE => CE, + CEB1 => '0', + CEB2 => CE, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => '0', + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); +end generate bl; + -- end generate virtex6 +end count; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/EQ_COMPARE_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/EQ_COMPARE_MACRO.vhd new file mode 100644 index 0000000..983be7a --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/EQ_COMPARE_MACRO.vhd @@ -0,0 +1,368 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2015 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 2015.3 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : EQ_COMPARE_MACRO.vhd +-- \ \ / \ +-- \___\/\___\ +-- +-- Revision: +-- 04/04/08 - Initial version. +-- 04/09/15 - 852167 - align with verilog +-- End Revision + +----- CELL EQ_COMPARE_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + +entity EQ_COMPARE_MACRO is + generic ( + DEVICE : string := "VIRTEX6"; + LATENCY : integer := 2; + MASK : bit_vector := X"000000000000"; + SEL_MASK : string := "MASK"; + SEL_PATTERN : string := "DYNAMIC_PATTERN"; + STATIC_PATTERN : bit_vector := X"000000000000"; + WIDTH : integer := 48 + ); + + port ( + Q : out std_logic; + CE : in std_logic; + CLK : in std_logic; + DATA_IN : in std_logic_vector(WIDTH-1 downto 0); + DYNAMIC_PATTERN : in std_logic_vector(WIDTH-1 downto 0); + RST : in std_logic + ); +end entity EQ_COMPARE_MACRO; + +architecture compare of EQ_COMPARE_MACRO is + + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetSelPattern ( + sel_pat : in string + ) return string is + variable Message : LINE; + begin + if (sel_pat = "STATIC_PATTERN") then + return "PATTERN"; + elsif (sel_pat = "DYNAMIC_PATTERN") then + return "C"; + else + write( Message, STRING'("Illegal value of Attribute SEL_PATTERN : ") ); + write ( Message, SEL_PATTERN); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" STATIC_PATTERN, DYNAMIC_PATTERN ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return "PATTERN"; + end if; + end; + function GetSelMask ( + sel_mas : in string + ) return string is + variable Message : LINE; + begin + if (sel_mas = "MASK" ) then + return "MASK"; + elsif (sel_mas = "DYNAMIC_PATTERN") then + return "C"; + else + write( Message, STRING'("Illegal value of Attribute SEL_MASK : ") ); + write ( Message, SEL_MASK); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" MASK, DYNAMIC_PATTERN ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return "MASK"; + end if; + end; + function CheckWidth ( + width : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (width > 0 and width <= 48 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH : ") ); + write ( Message, WIDTH); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 48 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetABREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 ) then + func_width := 1; + elsif (LATENCY = 3 ) then + func_width := 2; + else + func_width := 0; + end if; + return func_width; + end; + function GetCREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 2 or LATENCY = 3 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetQREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3) then + func_width := 1; + elsif (LATENCY = 0) then + func_width := 0; + else + func_width := 0; + write( Message, STRING'("Illegal value of Attribute LATENCY : ") ); + write ( Message, LATENCY); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 0 to 3 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_width; + end; + + +--Signal Declarations: + + signal DYNAMIC_PATTERN_INP : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal DATA_INP : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal CEA1_IN : std_logic; + signal CEA2_IN : std_logic; + signal CEB1_IN : std_logic; + signal CEB2_IN : std_logic; + + constant AREG_IN : integer := GetABREG_IN(LATENCY); + constant BREG_IN : integer := GetABREG_IN(LATENCY); + constant CREG_IN : integer := GetCREG_IN(LATENCY); + constant QREG : integer := GetQREG_IN(LATENCY); + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant SEL_PATTERN_IN : string := GetSelPattern(SEL_PATTERN); + constant SEL_MASK_IN : string := GetSelMask(SEL_MASK); + constant ChkWidth : boolean := CheckWidth(WIDTH); + +-- Architecture Section: instantiation +begin + + CEA1_IN <= CE when (AREG_IN = 2) else '0'; + CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0'; + CEB1_IN <= CE when (BREG_IN = 2) else '0'; + CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0'; + + inps1 : if (WIDTH = 48) generate + begin + DATA_INP <= DATA_IN; + DYNAMIC_PATTERN_INP <= DYNAMIC_PATTERN; + end generate inps1; + inps2 : if (WIDTH < 48) generate + begin + i1: for i in 47 downto WIDTH generate + DATA_INP(i) <= '0'; + DYNAMIC_PATTERN_INP(i) <= '0'; + end generate; + DATA_INP(WIDTH-1 downto 0) <= DATA_IN(WIDTH-1 downto 0); + DYNAMIC_PATTERN_INP(WIDTH-1 downto 0) <= DYNAMIC_PATTERN(WIDTH-1 downto 0); + end generate inps2; + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + begin + DSP48E_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + CREG => CREG_IN, + MASK => MASK, + PATTERN => STATIC_PATTERN, + PREG => QREG, + SEL_MASK => SEL_MASK_IN, + SEL_PATTERN => SEL_PATTERN_IN, + USE_MULT => "NONE", + USE_PATTERN_DETECT => "PATDET" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => open, + PATTERNBDETECT => open, + PATTERNDETECT => Q, + PCOUT => open, + UNDERFLOW => open, + A => DATA_INP(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => DATA_INP(17 downto 0), + BCIN => "000000000000000000", + C => DYNAMIC_PATTERN_INP, + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => '0', + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => "0000011", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); +end generate v5; + -- end generate virtex5 + -- begin generate virtex6 +bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_2: DSP48E1 + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + ADREG => 0, + BCASCREG => BREG_IN, + BREG => BREG_IN, + CREG => CREG_IN, + DREG => 0, + MREG => 0, + MASK => MASK, + PATTERN => STATIC_PATTERN, + PREG => QREG, + SEL_MASK => SEL_MASK_IN, + SEL_PATTERN => SEL_PATTERN_IN, + USE_MULT => "NONE", + USE_PATTERN_DETECT => "PATDET" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => open, + PATTERNBDETECT => open, + PATTERNDETECT => Q, + PCOUT => open, + UNDERFLOW => open, + A => DATA_INP(47 downto 18), + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => DATA_INP(17 downto 0), + BCIN => "000000000000000000", + C => DYNAMIC_PATTERN_INP, + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEAD => '0', + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => '0', + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => "0000011", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); +end generate bl; + -- end generate virtex6 + +end compare; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_DUALCLOCK_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_DUALCLOCK_MACRO.vhd new file mode 100644 index 0000000..a9eaa4f --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_DUALCLOCK_MACRO.vhd @@ -0,0 +1,930 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for FIFO +-- /___/ /\ Filename : FIFO_DUALCLOCK_MACRO.vhd +-- \ \ / \ Timestamp : Fri April 18 2008 10:43:59 PST 2006 +-- \___\/\___\ +-- +-- Revision: +-- 04/04/08 - Initial version. +-- 08/09/11 - Fixed CR 620349 +-- 01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking. +-- End Revision + +----- CELL FIFO_DUALCLOCK_MACRO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library unimacro; +use unimacro.VCOMPONENTS.all; + +library STD; +use STD.TEXTIO.ALL; + +entity FIFO_DUALCLOCK_MACRO is + + generic ( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DEVICE : string := "VIRTEX5"; + FIFO_SIZE : string := "18Kb"; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6 + SRVAL : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6 + SIM_MODE : string := "SAFE" -- This parameter is valid only for Virtex5 + ); + port( + ALMOSTEMPTY : out std_logic; + ALMOSTFULL : out std_logic; + DO : out std_logic_vector(DATA_WIDTH-1 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + RDCOUNT : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + RDERR : out std_logic; + WRCOUNT : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + WRERR : out std_logic; + + DI : in std_logic_vector(DATA_WIDTH-1 downto 0); + RDCLK : in std_logic; + RDEN : in std_logic; + RST : in std_logic; + WRCLK : in std_logic; + WREN : in std_logic + ); + + end entity FIFO_DUALCLOCK_MACRO; + + architecture fifo_V of FIFO_DUALCLOCK_MACRO is + + function GetDWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 0|1|2|3|4 => func_width := 4; + if(d_width = 0) then + write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => func_width := 32; + when 37 to 72 => if(func_fifo_size = "18Kb") then + write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". Legal values of this attribute for FIFO_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + else + func_width := 64; + end if; + when others => write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for FIFO_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 72 for FIFO_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + func_width := 64; + end case; + else + func_width := 64; + end if; + return func_width; + end; + function GetD_Size ( + d_size : in integer; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_size is + when 0|1|2|3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 9; + when 10 to 18 => func_width := 18; + when 19 to 36 => func_width := 36; + when 37 to 72 => func_width := 72; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetDIPWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 0; + end case; + else + func_width := 0; + end if; + return func_width; + end; + function GetDOPWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetCOUNTWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(fifo_size = "18Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 12; + when 5|6|7|8|9 => func_width := 11; + when 10 to 18 => func_width := 10; + when 19 to 36 => func_width := 9; + when others => func_width := 12; + end case; + elsif(fifo_size = "36Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 13; + when 5|6|7|8|9 => func_width := 12; + when 10 to 18 => func_width := 11; + when 19 to 36 => func_width := 10; + when 37 to 72 => func_width := 9; + when others => func_width := 13; + end case; + end if; + else + func_width := 13; + end if; + return func_width; + end; + + function GetMaxDWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 16; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 64; + else + func_width := 64; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 64; + else + func_width := 64; + end if; -- end b1 + else + func_width := 64; + end if; + return func_width; + end; + function GetMaxDPWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 2; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 8; + else + func_width := 8; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 8; + else + func_width := 8; + end if; -- end b2 + + else + func_width := 8; + end if; + return func_width; + end; + function GetFinalWidth ( + d_width : in integer + ) return integer is + variable func_least_width : integer; + begin + if (d_width = 0) then + func_least_width := 1; + else + func_least_width := d_width; + end if; + return func_least_width; + end; + function GetMaxCOUNTWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 12; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 9; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 13; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 9; + else + func_width := 13; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 12; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 13; + else + func_width := 13; + end if; -- end b3 + else + func_width := 13; + end if; + return func_width; + end; + + function GetFIFOSize ( + fifo_size : in string; + device : in string + ) return boolean is + variable fifo_val : boolean; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if fifo_size = "18Kb" or fifo_size = "36Kb" then + fifo_val := TRUE; + else + fifo_val := FALSE; + write( Message, STRING'("Illegal value of Attribute FIFO_SIZE : ") ); + write ( Message, FIFO_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 18Kb or 36Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + else + fifo_val := FALSE; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Allowed values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return fifo_val; + end; + + function GetD_P ( + dw : in integer; + device : in string + ) return boolean is + variable dp : boolean; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then + dp := TRUE; + else + dp := FALSE; + end if; + else + dp := FALSE; + end if; + return dp; + end; + + function GetSIMDev ( + device : in string + ) return string is + begin + if(DEVICE = "VIRTEX6") then + return "VIRTEX6"; + else + return "7SERIES"; + end if; + end; + + function CheckRDCOUNT ( + d_width : in integer; + fifo_size : in string; + device : in string; + rd_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if(fifo_size = "18Kb") then + if ((d_width > 0 and d_width <= 4) and rd_vec /= 12) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >4 and d_width <= 9) and rd_vec /= 11) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and rd_vec /= 10) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >19 and d_width <=36) and rd_vec /= 9) then + write( Message, STRING'(" .RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + elsif(fifo_size = "36Kb") then + if ((d_width > 0 and d_width <= 4) and rd_vec /= 13) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 13 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width > 4 and d_width <= 9) and rd_vec /= 12) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and rd_vec /= 11) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >18 and d_width <=36) and rd_vec /= 10) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >36 and d_width <=72) and rd_vec /= 9) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + else + return true; + end if; + end; + + function CheckWRCOUNT ( + d_width : in integer; + fifo_size : in string; + device : in string; + wr_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if(fifo_size = "18Kb") then + if ((d_width > 0 and d_width <= 4) and wr_vec /= 12) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >4 and d_width <= 9) and wr_vec /= 11) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and wr_vec /= 10) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >19 and d_width <=36) and wr_vec /= 9) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + elsif(fifo_size = "36Kb") then + if ((d_width > 0 and d_width <= 4) and wr_vec /= 13) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 13 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width > 4 and d_width <= 9) and wr_vec /= 12) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and wr_vec /= 11) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >18 and d_width <=36) and wr_vec /= 10) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >36 and d_width <=72) and wr_vec /= 9) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + else + return true; + end if; + end; + + constant fifo_size_val : boolean := GetFIFOSize(FIFO_SIZE, DEVICE); + constant data_p : boolean := GetD_P(DATA_WIDTH, DEVICE); + constant count_width : integer := GetCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant d_width : integer := GetDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant d_size : integer := GetD_Size(DATA_WIDTH, DEVICE); + constant dip_width : integer := GetDIPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant dop_width : integer := GetDOPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant fin_width : integer := GetFinalWidth(DATA_WIDTH); + constant sim_device_dp : string := GetSIMDev(DEVICE); + constant rdctleng : integer := RDCOUNT'length; + constant wrctleng : integer := WRCOUNT'length; + constant checkrdct : boolean := CheckRDCount(DATA_WIDTH, FIFO_SIZE, DEVICE, rdctleng); + constant checkwrct : boolean := CheckWRCount(DATA_WIDTH, FIFO_SIZE, DEVICE, wrctleng); + + constant max_data_width : integer := GetMaxDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant max_datap_width : integer := GetMaxDPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant max_count_width : integer := GetMaxCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + + signal di_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal do_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal dip_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal dop_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal rdcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0'); + signal wrcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0'); + + + begin + di1v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + digen1 : if (data_p = TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + dip_pattern(dip_width-1 downto 0) <= DI(fin_width-1 downto d_width) ; + di_pattern (d_width-1 downto 0) <= DI(d_width-1 downto 0); + end generate digen1; + end generate di1v5; + + di2v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + digen2 : if (data_p = FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + di_pattern(fin_width-1 downto 0) <= DI(fin_width-1 downto 0); + end generate digen2; + end generate di2v5; + + do1v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + dogen1 : if (data_p= TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + DO <= (dop_pattern(dop_width-1 downto 0) & do_pattern(d_width-1 downto 0)); + end generate dogen1; + end generate do1v5; + + do2v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + dogen2 : if (data_p= FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + DO <= do_pattern(fin_width-1 downto 0); + end generate dogen2; + end generate do2v5; + + RDCOUNT <= rdcount_pattern(count_width-1 downto 0); + WRCOUNT <= wrcount_pattern(count_width-1 downto 0); + + -- begin generate virtex5 + v5 : if (DEVICE = "VIRTEX5") generate + fifo_18_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <=18 ) generate + begin + fifo_18_inst : FIFO18 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + RST => RST, + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_18_inst; + + fifo_18_36_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate + begin + fifo_18_36_inst : fifo18_36 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DO_REG => 1, + EN_SYN => FALSE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + RST => RST, + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_18_36_inst; + + fifo_36_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate + begin + fifo_36_inst : FIFO36 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + RST => RST, + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_36_inst; + + fifo_36_72_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate + begin + fifo_36_72_inst : fifo36_72 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DO_REG => 1, + EN_SYN => FALSE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + RST => RST, + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_36_72_inst; + end generate v5; + -- end generate virtex5 + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + fifo_18_inst_bl : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <= 18 ) generate + begin + fifo_18_bl : FIFO18E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIFO_MODE => "FIFO18", + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + INIT => INIT(0 to 35), + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL(0 to 35) + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + REGCE => '1', + RST => RST, + RSTREG => '1', + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_18_inst_bl; + fifo_18_inst_bl_1 : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate + begin + fifo_18_bl_1 : FIFO18E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIFO_MODE => "FIFO18_36", + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + INIT => INIT(0 to 35), + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL(0 to 35) + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => RDCLK, + RDEN => RDEN, + REGCE => '1', + RST => RST, + RSTREG => '1', + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_18_inst_bl_1; + fifo_36_inst_bl : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate + begin + fifo_36_bl : FIFO36E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIFO_MODE => "FIFO36", + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + INIT => INIT, + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => RDCLK, + RDEN => RDEN, + REGCE => '1', + RST => RST, + RSTREG => '1', + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_36_inst_bl; + fifo_36_inst_bl_1 : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate + begin + fifo_36_bl_1 : FIFO36E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => 1, + EN_SYN => FALSE, + FIFO_MODE => "FIFO36_72", + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH, + INIT => INIT, + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => RDCLK, + RDEN => RDEN, + REGCE => '1', + RST => RST, + RSTREG => '1', + WRCLK => WRCLK, + WREN => WREN + ); + end generate fifo_36_inst_bl_1; + + end generate bl; + -- end generate virtex6 + + end fifo_V; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_SYNC_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_SYNC_MACRO.vhd new file mode 100644 index 0000000..e80bd56 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_SYNC_MACRO.vhd @@ -0,0 +1,934 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2007 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for FIFO +-- /___/ /\ Filename : FIFO_SYNC_MACRO.vhd +-- \ \ / \ Timestamp : Fri April 18 2008 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 04/04/08 - Initial version. +-- 01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking. +-- 03/16/12 - fix for 7series +-- End Revision + +----- CELL FIFO_SYNC_MACRO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library unimacro; +use unimacro.VCOMPONENTS.all; + +library STD; +use STD.TEXTIO.ALL; + +entity FIFO_SYNC_MACRO is + + generic ( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + FIFO_SIZE : string := "18Kb"; + INIT : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6 + SRVAL : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6 + SIM_MODE : string := "SAFE" -- This parameter is valid only for Virtex5 + ); + port( + ALMOSTEMPTY : out std_logic; + ALMOSTFULL : out std_logic; + DO : out std_logic_vector(DATA_WIDTH-1 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + RDCOUNT : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + RDERR : out std_logic; + WRCOUNT : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + WRERR : out std_logic; + + CLK : in std_logic; + DI : in std_logic_vector(DATA_WIDTH-1 downto 0); + RDEN : in std_logic; + RST : in std_logic; + WREN : in std_logic + ); + + end entity FIFO_SYNC_MACRO; + + architecture fifo_V of FIFO_SYNC_MACRO is + + function GetDWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 0|1|2|3|4 => func_width := 4; + if(d_width = 0) then + write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". This attribute must atleast be equal to 1 . ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + when 5|6|7|8|9 => func_width := 8; + when 10 to 18 => func_width := 16; + when 19 to 36 => func_width := 32; + when 37 to 72 => if(func_fifo_size = "18Kb") then + write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". Legal values of this attribute for FIFO_SIZE 18Kb are ") ); + write( Message, STRING'(" 1 to 36 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + else + func_width := 64; + end if; + when others => write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") ); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 36 for FIFO_SIZE of 18Kb and ") ); + write( Message, STRING'(" 1 to 72 for FIFO_SIZE of 36Kb .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + func_width := 64; + end case; + else + func_width := 64; + end if; + return func_width; + end; + function GetD_Size ( + d_size : in integer; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_size is + when 0|1|2|3|4 => func_width := 4; + when 5|6|7|8|9 => func_width := 9; + when 10 to 18 => func_width := 18; + when 19 to 36 => func_width := 36; + when 37 to 72 => func_width := 72; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetDIPWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 0; + end case; + else + func_width := 0; + end if; + return func_width; + end; + function GetDOPWidth ( + d_width : in integer; + func_fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + case d_width is + when 9 => func_width := 1; + when 17 => func_width := 1; + when 18 => func_width := 2; + when 33 => func_width := 1; + when 34 => func_width := 2; + when 35 => func_width := 3; + when 36 => func_width := 4; + when 65 => func_width := 1; + when 66 => func_width := 2; + when 67 => func_width := 3; + when 68 => func_width := 4; + when 69 => func_width := 5; + when 70 => func_width := 6; + when 71 => func_width := 7; + when 72 => func_width := 8; + when others => func_width := 1; + end case; + else + func_width := 1; + end if; + return func_width; + end; + + function GetCOUNTWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if(fifo_size = "18Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 12; + when 5|6|7|8|9 => func_width := 11; + when 10 to 18 => func_width := 10; + when 19 to 36 => func_width := 9; + when others => func_width := 12; + end case; + elsif(fifo_size = "36Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 13; + when 5|6|7|8|9 => func_width := 12; + when 10 to 18 => func_width := 11; + when 19 to 36 => func_width := 10; + when 37 to 72 => func_width := 9; + when others => func_width := 13; + end case; + end if; + else + func_width := 13; + end if; + return func_width; + end; + + function GetMaxDWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 16; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 64; + else + func_width := 64; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 32; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 64; + else + func_width := 64; + end if; -- end b1 + else + func_width := 64; + end if; + return func_width; + end; + function GetMaxDPWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 2; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 8; + else + func_width := 8; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 4; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 8; + else + func_width := 8; + end if; -- end b2 + else + func_width := 8; + end if; + return func_width; + end; + function GetFinalWidth ( + d_width : in integer + ) return integer is + variable func_least_width : integer; + begin + if (d_width = 0) then + func_least_width := 1; + else + func_least_width := d_width; + end if; + return func_least_width; + end; + function GetMaxCOUNTWidth ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(DEVICE = "VIRTEX5") then + if (fifo_size = "18Kb" and d_width <= 18 ) then + func_width := 12; + elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then + func_width := 9; + elsif (fifo_size = "36Kb" and d_width <= 36 ) then + func_width := 13; + elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then + func_width := 9; + else + func_width := 13; + end if; + elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (fifo_size = "18Kb" and d_width <= 36 ) then + func_width := 12; + elsif (fifo_size = "36Kb" and d_width <= 72 ) then + func_width := 13; + else + func_width := 13; + end if; -- end b3 + else + func_width := 13; + end if; + return func_width; + end; + + function GetFIFOSize ( + fifo_size : in string; + device : in string + ) return boolean is + variable fifo_val : boolean; + variable Message : LINE; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if fifo_size = "18Kb" or fifo_size = "36Kb" then + fifo_val := TRUE; + else + fifo_val := FALSE; + write( Message, STRING'("Illegal value of Attribute FIFO_SIZE : ") ); + write ( Message, FIFO_SIZE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 18Kb or 36Kb ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + else + fifo_val := FALSE; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Allowed values of this attribute is ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return fifo_val; + end; + + function GetD_P ( + dw : in integer; + device : in string + ) return boolean is + variable dp : boolean; + begin + if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then + dp := TRUE; + else + dp := FALSE; + end if; + else + dp := FALSE; + end if; + return dp; + end; + + function GetSIMDev ( + device : in string + ) return string is + begin + if(DEVICE = "VIRTEX6") then + return "VIRTEX6"; + else + return "7SERIES"; + end if; + end; + + function CheckRDCOUNT ( + d_width : in integer; + fifo_size : in string; + device : in string; + rd_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if(fifo_size = "18Kb") then + if ((d_width > 0 and d_width <= 4) and rd_vec /= 12) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >4 and d_width <= 9) and rd_vec /= 11) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and rd_vec /= 10) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >19 and d_width <=36) and rd_vec /= 9) then + write( Message, STRING'(" .RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + elsif(fifo_size = "36Kb") then + if ((d_width > 0 and d_width <= 4) and rd_vec /= 13) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 13 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width > 4 and d_width <= 9) and rd_vec /= 12) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and rd_vec /= 11) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >18 and d_width <=36) and rd_vec /= 10) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >36 and d_width <=72) and rd_vec /= 9) then + write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .RDCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + else + return true; + end if; + end; + + function CheckWRCOUNT ( + d_width : in integer; + fifo_size : in string; + device : in string; + wr_vec : in integer + ) return boolean is + variable Message : LINE; + begin + if(fifo_size = "18Kb") then + if ((d_width > 0 and d_width <= 4) and wr_vec /= 12) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >4 and d_width <= 9) and wr_vec /= 11) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and wr_vec /= 10) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >19 and d_width <=36) and wr_vec /= 9) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + elsif(fifo_size = "36Kb") then + if ((d_width > 0 and d_width <= 4) and wr_vec /= 13) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 13 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width > 4 and d_width <= 9) and wr_vec /= 12) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 12 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >=10 and d_width <=18) and wr_vec /= 11) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 11 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >18 and d_width <=36) and wr_vec /= 10) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 10 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + elsif ((d_width >36 and d_width <=72) and wr_vec /= 9) then + write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") ); + write( Message, DATA_WIDTH); + write( Message, STRING'(" .WRCOUNT must be of width 9 .") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + return false; + else + return true; + end if; + else + return true; + end if; + end; + + constant fifo_size_val : boolean := GetFIFOSize(FIFO_SIZE, DEVICE); + constant data_p : boolean := GetD_P(DATA_WIDTH, DEVICE); + constant count_width : integer := GetCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant d_width : integer := GetDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant d_size : integer := GetD_Size(DATA_WIDTH, DEVICE); + constant dip_width : integer := GetDIPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant dop_width : integer := GetDOPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant fin_width : integer := GetFinalWidth(DATA_WIDTH); + constant sim_device_dp : string := GetSIMDev(DEVICE); + constant rdctleng : integer := RDCOUNT'length; + constant wrctleng : integer := WRCOUNT'length; + constant checkrdct : boolean := CheckRDCOUNT(DATA_WIDTH, FIFO_SIZE, DEVICE, rdctleng); + constant checkwrct : boolean := CheckWRCOUNT(DATA_WIDTH, FIFO_SIZE, DEVICE, wrctleng); + + + constant max_data_width : integer := GetMaxDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant max_datap_width : integer := GetMaxDPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + constant max_count_width : integer := GetMaxCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE); + + signal di_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal do_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0'); + signal dip_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal dop_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0'); + signal rdcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0'); + signal wrcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0'); + signal regce_pattern : std_logic := '0'; + signal rstreg_pattern : std_logic := '0'; + + begin + di1v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + digen1 : if (data_p = TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + dip_pattern(dip_width-1 downto 0) <= DI(fin_width-1 downto d_width) ; + di_pattern (d_width-1 downto 0) <= DI(d_width-1 downto 0); + end generate digen1; + end generate di1v5; + + di2v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + digen2 : if (data_p = FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + di_pattern(fin_width-1 downto 0) <= DI(fin_width-1 downto 0); + end generate digen2; + end generate di2v5; + + do1v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + dogen1 : if (data_p= TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + DO <= (dop_pattern(dop_width-1 downto 0) & do_pattern(d_width-1 downto 0)); + end generate dogen1; + end generate do1v5; + + do2v5 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + dogen2 : if (data_p= FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate + begin + DO <= do_pattern(fin_width-1 downto 0); + end generate dogen2; + end generate do2v5; + + RDCOUNT <= rdcount_pattern(count_width-1 downto 0); + WRCOUNT <= wrcount_pattern(count_width-1 downto 0); + regce_pattern <= '1' when (DO_REG = 1) else '0'; + rstreg_pattern <= '1' when (DO_REG = 1) else '0'; + + -- begin generate virtex5 + v5 : if (DEVICE = "VIRTEX5") generate + fifo_18_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <=18 ) generate + begin + fifo_18_inst : FIFO18 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIRST_WORD_FALL_THROUGH => FALSE, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + RST => RST, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_18_inst; + + fifo_18_36_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate + begin + fifo_18_36_inst : fifo18_36 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIRST_WORD_FALL_THROUGH => FALSE, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + RST => RST, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_18_36_inst; + + fifo_36_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate + begin + fifo_36_inst : FIFO36 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIRST_WORD_FALL_THROUGH => FALSE, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + RST => RST, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_36_inst; + + fifo_36_72_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate + begin + fifo_36_72_inst : fifo36_72 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIRST_WORD_FALL_THROUGH => FALSE, + SIM_MODE => SIM_MODE + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + RST => RST, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_36_72_inst; + end generate v5; + -- end generate virtex5 + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + fifo_18_inst_bl : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <= 18 ) generate + begin + fifo_18_bl : FIFO18E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIFO_MODE => "FIFO18", + FIRST_WORD_FALL_THROUGH => FALSE, + INIT => INIT(0 to 35), + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL(0 to 35) + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + REGCE => regce_pattern, + RST => RST, + RSTREG => rstreg_pattern, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_18_inst_bl; + fifo_18_inst_bl_1 : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate + begin + fifo_18_bl_1 : FIFO18E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIFO_MODE => "FIFO18_36", + FIRST_WORD_FALL_THROUGH => FALSE, + INIT => INIT(0 to 35), + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL(0 to 35) + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DO => do_pattern, + DOP => dop_pattern, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + RDCLK => CLK, + RDEN => RDEN, + REGCE => regce_pattern, + RST => RST, + RSTREG => rstreg_pattern, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_18_inst_bl_1; + + fifo_36_inst_bl : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate + begin + fifo_36_bl : FIFO36E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIFO_MODE => "FIFO36", + FIRST_WORD_FALL_THROUGH => FALSE, + INIT => INIT, + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => CLK, + RDEN => RDEN, + REGCE => regce_pattern, + RST => RST, + RSTREG => rstreg_pattern, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_36_inst_bl; + fifo_36_inst_bl_1 : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate + begin + fifo_36_bl_1 : FIFO36E1 + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => d_size, + DO_REG => DO_REG, + EN_SYN => TRUE, + FIFO_MODE => "FIFO36_72", + FIRST_WORD_FALL_THROUGH => FALSE, + INIT => INIT, + SIM_DEVICE => sim_device_dp, + SRVAL => SRVAL + ) + port map ( + ALMOSTEMPTY => ALMOSTEMPTY, + ALMOSTFULL => ALMOSTFULL, + DBITERR => OPEN, + DO => do_pattern, + DOP => dop_pattern, + ECCPARITY => OPEN, + EMPTY => EMPTY, + FULL => FULL, + RDCOUNT => rdcount_pattern, + RDERR => RDERR, + SBITERR => OPEN, + WRCOUNT => wrcount_pattern, + WRERR => WRERR, + DI => di_pattern, + DIP => dip_pattern, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => CLK, + RDEN => RDEN, + REGCE => regce_pattern, + RST => RST, + RSTREG => rstreg_pattern, + WRCLK => CLK, + WREN => WREN + ); + end generate fifo_36_inst_bl_1; + + + end generate bl; + -- end generate virtex6 + + end fifo_V; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/MACC_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/MACC_MACRO.vhd new file mode 100644 index 0000000..f888dd6 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/MACC_MACRO.vhd @@ -0,0 +1,558 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2015 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 2015.3 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : MACC_MACRO.vhd +-- \ \ / \ +-- \___\/\___\ +-- +-- Revision: +-- 06/06/08 - Initial version. +-- 04/09/15 - 852167 - align with verilog +-- End Revision + +----- CELL MACC_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + + +entity MACC_MACRO is + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 3; + WIDTH_A : integer := 25; + WIDTH_B : integer := 18; + WIDTH_P : integer := 48 + ); + + port ( + P : out std_logic_vector(WIDTH_P-1 downto 0); + A : in std_logic_vector(WIDTH_A-1 downto 0); + ADDSUB : in std_logic; + B : in std_logic_vector(WIDTH_B-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_P-1 downto 0); + RST : in std_logic + ); +end entity MACC_MACRO; + +architecture macc of MACC_MACRO is + + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidthA ( + widtha : in integer; + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (widtha > 0 and widtha <= 25) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") ); + write ( Message, WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 25 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- begin s1 + else + if (DEVICE = "SPARTAN6" and (widtha > 0 and widtha <= 18)) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") ); + write ( Message, WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- end s1 + end if; + return func_val; + end; + function CheckWidthB ( + widthb : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (widthb > 0 and widthb <= 18 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_B : ") ); + write ( Message, WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetWidthA ( + device : in string + ) return integer is + variable func_val : integer; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_val := 25; + else + func_val := 18; + end if; + return func_val; + end; + function GetABREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3) then + func_width := 1; + elsif (LATENCY = 4 ) then + func_width := 2; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG1_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG0_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + + function GetMREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetPREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + else + func_width := 0; + write( Message, STRING'("Illegal value of Attribute LATENCY : ") ); + write ( Message, LATENCY); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 4 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_width; + end; + function GetOPMODE_IN ( + device : in string + ) return integer is + variable func_width : integer; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_width := 7; + elsif (DEVICE = "SPARTAN6") then + func_width := 8; + else + func_width := 8; + end if; + return func_width; + end; + + +--Signal Declarations: + + + constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE); + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkWidthA : boolean := CheckWidthA(WIDTH_A, DEVICE); + constant ChkWidthB : boolean := CheckWidthB(WIDTH_B); + constant MaxWidthA : integer := GetWidthA(DEVICE); + constant AREG_IN : integer := GetABREG_IN(LATENCY); + constant BREG_IN : integer := GetABREG_IN(LATENCY); + constant A0REG_IN : integer := GetABREG0_IN(LATENCY); + constant B0REG_IN : integer := GetABREG0_IN(LATENCY); + constant A1REG_IN : integer := GetABREG1_IN(LATENCY); + constant B1REG_IN : integer := GetABREG1_IN(LATENCY); + constant MREG_IN : integer := GetMREG_IN(LATENCY); + constant PREG_IN : integer := GetPREG_IN(LATENCY); + + signal A_INP : std_logic_vector(24 downto 0) := "0000000000000000000000000"; + signal A_IN : std_logic_vector(29 downto 0) := "000000000000000000000000000000"; + signal B_IN : std_logic_vector(17 downto 0) := "000000000000000000"; + signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal LOAD_DATA_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal OPMODE_IN : std_logic_vector((OPMODE_WIDTH-1) downto 0); + signal ALUMODE_IN : std_logic_vector(3 downto 0); + + signal CEA1_IN : std_logic; + signal CEA2_IN : std_logic; + signal CEB1_IN : std_logic; + signal CEB2_IN : std_logic; + + + +-- Architecture Section: instantiation +begin + + CEA1_IN <= CE when (AREG_IN = 2) else '0'; + CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0'; + CEB1_IN <= CE when (BREG_IN = 2) else '0'; + CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0'; + + ALUMODE_IN <= "00" & (not (ADDSUB)) & (not (ADDSUB)); + + v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + OPMODE_IN <= "01" & LOAD & "0101"; + end generate v; + + s : if (DEVICE = "SPARTAN6") generate + OPMODE_IN <= (not (ADDSUB)) & (not (ADDSUB)) & "001" & LOAD & "01"; + end generate s; + + load1 : if (WIDTH_P = 48) generate + begin + LOAD_DATA_IN <= LOAD_DATA; + end generate load1; + load2 : if (WIDTH_P < 48) generate + begin + l1: for i in 47 downto WIDTH_P generate + LOAD_DATA_IN(i) <= '0'; + end generate; + LOAD_DATA_IN(WIDTH_P-1 downto 0) <= LOAD_DATA; + end generate load2; + + multa : if (WIDTH_A = MaxWidthA) generate + begin + A_INP((MaxWidthA-1) downto 0) <= A; + A_IN <= "00000" & A_INP; + end generate multa; + multb : if (WIDTH_B = 18) generate + begin + B_IN <= B; + end generate multb; + multas : if (WIDTH_A < MaxWidthA) generate + begin + sa: for i in (MaxWidthA-1) downto WIDTH_A generate + A_INP(i) <= A((WIDTH_A-1)); + end generate; + A_INP(WIDTH_A-1 downto 0) <= A; + A_IN <= "00000" & A_INP; + end generate multas; + multbs : if (WIDTH_B < 18) generate + begin + sb: for i in 17 downto WIDTH_B generate + B_IN(i) <= B((WIDTH_B-1)); + end generate; + B_IN(WIDTH_B-1 downto 0) <= B; + end generate multbs; + + P <= RESULT_OUT(WIDTH_P-1 downto 0); + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + v5_1 : if ((LATENCY >= 0) and (LATENCY <= 2)) generate + begin + DSP48E_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN, + USE_MULT => "MULT" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_IN, + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => B_IN, + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN, + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => CE, + CEMULTCARRYIN => CE, + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => OPMODE_IN(6 downto 0), + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); + end generate v5_1; + v5_2 : if ((LATENCY =3) or (LATENCY = 4)) generate + begin + DSP48E_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN, + USE_MULT => "MULT_S" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_IN, + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => B_IN, + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN, + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => CE, + CEMULTCARRYIN => CE, + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => OPMODE_IN(6 downto 0), + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); + end generate v5_2; + end generate v5; + -- end generate virtex5 + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_2: DSP48E1 + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_IN, + ACIN => "000000000000000000000000000000", + ALUMODE => ALUMODE_IN, + B => B_IN, + BCIN => "000000000000000000", + C => LOAD_DATA_IN, + CARRYCASCIN => '0', + CARRYIN => CARRYIN, + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEAD => '0', + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => CE, + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => OPMODE_IN(6 downto 0), + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); + end generate bl; + -- end generate virtex6 + -- begin generate spartan6 + st : if DEVICE = "SPARTAN6" generate + begin + DSP48E_3: DSP48A1 + generic map ( + A0REG => A0REG_IN, + A1REG => A1REG_IN, + B0REG => B0REG_IN, + B1REG => B1REG_IN, + MREG => MREG_IN, + PREG => PREG_IN + ) + port map ( + BCOUT => open, + CARRYOUT => open, + CARRYOUTF => open, + M => open, + P => RESULT_OUT, + PCOUT => open, + A => A_IN(17 downto 0), + B => B_IN, + C => LOAD_DATA_IN, + CARRYIN => CARRYIN, + CEA => CE, + CEB => CE, + CEC => CE, + CECARRYIN => CE, + CED => CE, + CEM => CE, + CEOPMODE => CE, + CEP => CE, + CLK => CLK, + D => "000000000000000000", + OPMODE => OPMODE_IN, + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTB => RST, + RSTC => RST, + RSTCARRYIN => RST, + RSTD => RST, + RSTM => RST, + RSTOPMODE => RST, + RSTP => RST + ); + end generate st; + -- end generate spartan6 +end macc; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/MULT_MACRO.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/MULT_MACRO.vhd new file mode 100644 index 0000000..7f5a104 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/MULT_MACRO.vhd @@ -0,0 +1,561 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2008 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 14.1 +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Macro for DSP48 +-- /___/ /\ Filename : MULT_MACRO.vhd +-- \ \ / \ Timestamp : Fri June 06 2008 10:43:59 PST 2008 +-- \___\/\___\ +-- +-- Revision: +-- 06/06/08 - Initial version. +-- 05/22/12 - 660408 - fix for latency 3 and 4 +-- End Revision + +----- CELL MULT_MACRO ----- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library STD; +use STD.TEXTIO.ALL; + + +entity MULT_MACRO is + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 3; + STYLE : string := "DSP"; + WIDTH_A : integer := 18; + WIDTH_B : integer := 18 + ); + + port ( + P : out std_logic_vector((WIDTH_A+WIDTH_B)-1 downto 0); + A : in std_logic_vector(WIDTH_A-1 downto 0); + B : in std_logic_vector(WIDTH_B-1 downto 0); + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end entity MULT_MACRO; + +architecture mult of MULT_MACRO is + + function CheckDevice ( + device : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute DEVICE : ") ); + write ( Message, DEVICE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckStyle ( + style : in string + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (style = "AUTO" or style = "DSP" ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute STYLE : ") ); + write ( Message, STYLE); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" AUTO, DSP ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function CheckWidthA ( + widtha : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + if (widtha > 0 and widtha <= 25) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") ); + write ( Message, WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 25 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- begin s1 + else + if (DEVICE = "SPARTAN6" and widtha > 0 and widtha <= 18) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") ); + write ( Message, WIDTH_A); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + -- end s1 + end if; + return func_val; + end; + function CheckWidthB ( + widthb : in integer + ) return boolean is + variable func_val : boolean; + variable Message : LINE; + begin + if (widthb > 0 and widthb <= 18 ) then + func_val := true; + else + func_val := false; + write( Message, STRING'("Illegal value of Attribute WIDTH_B : ") ); + write ( Message, WIDTH_B); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 1 to 18 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetWidthA ( + device : in string + ) return integer is + variable func_val : integer; + variable Message : LINE; + + begin + if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then + func_val := 25; + else + func_val := 18; + DEALLOCATE (Message); + end if; + return func_val; + end; + function GetABREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3) then + func_width := 1; + elsif (LATENCY = 4 ) then + func_width := 2; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG1_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetABREG0_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 4) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetPREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + begin + if (LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + else + func_width := 0; + end if; + return func_width; + end; + function GetMREG_IN ( + latency : in integer + ) return integer is + variable func_width : integer; + variable Message : LINE; + begin + if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then + func_width := 1; + elsif (LATENCY = 0) then + func_width := 0; + else + func_width := 0; + write( Message, STRING'("Illegal value of Attribute LATENCY : ") ); + write ( Message, LATENCY); + write( Message, STRING'(". Legal values of this attribute are ") ); + write( Message, STRING'(" 0 to 4 ") ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + return func_width; + end; + + + +--Signal Declarations: + + signal A_IN : std_logic_vector(24 downto 0) := "0000000000000000000000000"; + signal A_INP : std_logic_vector(29 downto 0) := "000000000000000000000000000000"; + signal A_INST : std_logic_vector(17 downto 0) := "000000000000000000"; + signal B_IN : std_logic_vector(17 downto 0) := "000000000000000000"; + signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal RESULT_OUTST : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + signal CEA1_IN : std_logic; + signal CEA2_IN : std_logic; + signal CEB1_IN : std_logic; + signal CEB2_IN : std_logic; + + constant ChkDevice : boolean := CheckDevice(DEVICE); + constant ChkStyle : boolean := CheckStyle(STYLE); + constant ChkWidthA : boolean := CheckWidthA(WIDTH_A); + constant ChkWidthB : boolean := CheckWidthB(WIDTH_B); + constant MaxWidthA : integer := GetWidthA(DEVICE); + constant AREG_IN : integer := GetABREG_IN(LATENCY); + constant BREG_IN : integer := GetABREG_IN(LATENCY); + constant A0REG_IN : integer := GetABREG0_IN(LATENCY); + constant B0REG_IN : integer := GetABREG0_IN(LATENCY); + constant A1REG_IN : integer := GetABREG1_IN(LATENCY); + constant B1REG_IN : integer := GetABREG1_IN(LATENCY); + constant MREG_IN : integer := GetMREG_IN(LATENCY); + constant PREG_IN : integer := GetPREG_IN(LATENCY); + +-- Architecture Section: instantiation +begin + + CEA1_IN <= CE when (AREG_IN = 2) else '0'; + CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0'; + CEB1_IN <= CE when (BREG_IN = 2) else '0'; + CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0'; + + multa : if (WIDTH_A = MaxWidthA) generate + begin + + ga1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + A_IN(MaxWidthA-1 downto 0) <= A; + end generate ga1; + ga2 : if (DEVICE = "SPARTAN6") generate + A_INST(MaxWidthA-1 downto 0) <= A; + end generate ga2; + end generate multa; + multb : if (WIDTH_B = 18) generate + begin + B_IN <= B; + end generate multb; + multas : if (WIDTH_A < MaxWidthA) generate + begin + g1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + A_IN((MaxWidthA-1) downto (MaxWidthA-WIDTH_A)) <= A; + g3 : for i in ((MaxWidthA-1)-WIDTH_A) downto 0 generate + A_IN(i) <= '0'; + end generate g3; + end generate g1; + -- begin s2 + g2 : if (DEVICE = "SPARTAN6") generate + A_INST((MaxWidthA-1) downto (MaxWidthA-WIDTH_A)) <= A; + g4 : for i in ((MaxWidthA-1)-WIDTH_A) downto 0 generate + A_INST(i) <= '0'; + end generate g4; + end generate g2; + -- end s2 + end generate multas; + multbs : if (WIDTH_B < 18) generate + begin + sb: for i in (17-WIDTH_B) downto 0 generate + B_IN(i) <= '0'; + end generate; + B_IN(17 downto (18-(WIDTH_B))) <= B; + end generate multbs; + + A_INP <= "00000" & A_IN ; + + p1: if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + P <= RESULT_OUT(42 downto (42- ((WIDTH_A+WIDTH_B)-1))); + end generate p1; + -- begin s2 + p2: if (DEVICE = "SPARTAN6") generate + P <= RESULT_OUTST(35 downto (35- ((WIDTH_A+WIDTH_B)-1))); + end generate p2; + -- end s2 + + -- begin generate virtex5 + v5 : if DEVICE = "VIRTEX5" generate + v5_1 : if LATENCY = 0 generate + begin + DSP48E_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN, + USE_MULT => "MULT" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_INP, + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => B_IN, + BCIN => "000000000000000000", + C => "000000000000000000000000000000000000000000000000", + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => CE, + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => "0000101", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); + end generate v5_1; + v5_2 : if LATENCY > 0 generate + begin + DSP48E_1: DSP48E + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + BCASCREG => BREG_IN, + BREG => BREG_IN, + MREG => MREG_IN, + PREG => PREG_IN, + USE_MULT => "MULT_S" + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_INP, + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => B_IN, + BCIN => "000000000000000000", + C => "000000000000000000000000000000000000000000000000", + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CEM => CE, + CEMULTCARRYIN => '0', + CEP => CE, + CLK => CLK, + MULTSIGNIN => '0', + OPMODE => "0000101", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTM => RST, + RSTP => RST + ); + end generate v5_2; + end generate v5; + -- end generate virtex5 + -- begin generate virtex6 + bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate + begin + DSP48E_2: DSP48E1 + generic map ( + ACASCREG => AREG_IN, + AREG => AREG_IN, + ADREG => 0, + BCASCREG => BREG_IN, + BREG => BREG_IN, + DREG => 0, + MREG => MREG_IN, + PREG => PREG_IN + ) + port map ( + ACOUT => open, + BCOUT => open, + CARRYCASCOUT => open, + CARRYOUT => open, + MULTSIGNOUT => open, + OVERFLOW => open, + P => RESULT_OUT, + PATTERNBDETECT => open, + PATTERNDETECT => open, + PCOUT => open, + UNDERFLOW => open, + A => A_INP, + ACIN => "000000000000000000000000000000", + ALUMODE => "0000", + B => B_IN, + BCIN => "000000000000000000", + C => "000000000000000000000000000000000000000000000000", + CARRYCASCIN => '0', + CARRYIN => '0', + CARRYINSEL => "000", + CEA1 => CEA1_IN, + CEA2 => CEA2_IN, + CEAD => '0', + CEALUMODE => CE, + CEB1 => CEB1_IN, + CEB2 => CEB2_IN, + CEC => CE, + CECARRYIN => CE, + CECTRL => CE, + CED => '0', + CEINMODE => '0', + CEM => CE, + CEP => CE, + CLK => CLK, + D => "0000000000000000000000000", + INMODE => "00000", + MULTSIGNIN => '0', + OPMODE => "0000101", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTALLCARRYIN => RST, + RSTALUMODE => RST, + RSTB => RST, + RSTC => RST, + RSTCTRL => RST, + RSTD => RST, + RSTINMODE => RST, + RSTM => RST, + RSTP => RST + ); + end generate bl; + -- end generate virtex6 + -- begin generate spartan6 + st : if DEVICE = "SPARTAN6" generate + begin + DSP48E_3: DSP48A1 + generic map ( + A0REG => A0REG_IN, + A1REG => A1REG_IN, + B0REG => B0REG_IN, + B1REG => B1REG_IN, + MREG => MREG_IN, + PREG => PREG_IN + ) + port map ( + BCOUT => open, + CARRYOUT => open, + CARRYOUTF => open, + --M => RESULT_OUTST, + M => open, + P => RESULT_OUTST, + PCOUT => open, + A => A_INST, + B => B_IN, + C => "000000000000000000000000000000000000000000000000", + CARRYIN => '0', + CEA => CE, + CEB => CE, + CEC => CE, + CECARRYIN => CE, + CED => CE, + CEM => CE, + CEOPMODE => CE, + CEP => CE, + CLK => CLK, + D => "000000000000000000", + OPMODE => "00000001", + PCIN => "000000000000000000000000000000000000000000000000", + RSTA => RST, + RSTB => RST, + RSTC => RST, + RSTCARRYIN => RST, + RSTD => RST, + RSTM => RST, + RSTOPMODE => RST, + RSTP => RST + ); + end generate st; + -- end generate spartan6 + +end mult; + + + diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/unimacro_VCOMP.vhd b/resources/dide-lsp/static/vhdl_std_lib/unimacro/unimacro_VCOMP.vhd new file mode 100644 index 0000000..d059627 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/unimacro_VCOMP.vhd @@ -0,0 +1,802 @@ +--************************************************************** +-- Copyright (c) 2008 Xilinx, Inc. All rights reserved. +-- File Name : unimacro_VCOMP.vhd +-- Library : unisim +-- Release : 11.1 +-- Entity Count : 12 +-- Time : Fri Mar 2 10:51:46 2012 +-- Generated by : gencomp.pl +--************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package VCOMPONENTS is + + FUNCTION xil_UNM_GCW ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer; + +-- START COMPONENT +----- component ADDMACC_MACRO ----- +component ADDMACC_MACRO + generic ( + DEVICE : string := "VIRTEX6"; + LATENCY : integer := 4; + WIDTH_MULTIPLIER : integer := 18; + WIDTH_PREADD : integer := 25; + WIDTH_PRODUCT : integer := 48 + ); + port ( + PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0); + MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0); + PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0); + PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0); + RST : in std_logic + ); +end component; + +----- component ADDSUB_MACRO ----- +component ADDSUB_MACRO + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 2; + MODEL_TYPE : integer := 0; + STYLE : string := "DSP"; + VERBOSITY : integer := 0; + WIDTH : integer := 48; + WIDTH_B : integer := 48; + WIDTH_RESULT : integer := 48 + ); + port ( + CARRYOUT : out std_logic; + RESULT : out std_logic_vector(WIDTH-1 downto 0); + A : in std_logic_vector(WIDTH-1 downto 0); + ADD_SUB : in std_logic; + B : in std_logic_vector(WIDTH-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end component; + +----- component BRAM_SDP_MACRO ----- +component BRAM_SDP_MACRO + generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000"; + WRITE_MODE : string := "WRITE_FIRST"; + WRITE_WIDTH : integer := 0 + ); + port ( + DO : out std_logic_vector(READ_WIDTH-1 downto 0); + DI : in std_logic_vector(WRITE_WIDTH-1 downto 0); + RDADDR : in std_logic_vector; + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + RST : in std_ulogic; + WE : in std_logic_vector; + WRADDR : in std_logic_vector; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; + +----- component BRAM_SINGLE_MACRO ----- +component BRAM_SINGLE_MACRO + generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH : integer := 1; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000"; + WRITE_MODE : string := "WRITE_FIRST"; + WRITE_WIDTH : integer := 1 + ); + port ( + DO : out std_logic_vector(READ_WIDTH-1 downto 0); + ADDR : in std_logic_vector; + CLK : in std_ulogic; + DI : in std_logic_vector(WRITE_WIDTH-1 downto 0); + EN : in std_ulogic; + REGCE : in std_ulogic; + RST : in std_ulogic; + WE : in std_logic_vector + ); +end component; + +----- component BRAM_TDP_MACRO ----- +component BRAM_TDP_MACRO + generic ( + BRAM_SIZE : string := "18Kb"; + DEVICE : string := "VIRTEX5"; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + READ_WIDTH_A : integer := 1; + READ_WIDTH_B : integer := 1; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 1; + WRITE_WIDTH_B : integer := 1 + ); + port ( + DOA : out std_logic_vector(READ_WIDTH_A-1 downto 0); + DOB : out std_logic_vector(READ_WIDTH_B-1 downto 0); + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(WRITE_WIDTH_A-1 downto 0); + DIB : in std_logic_vector(WRITE_WIDTH_B-1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + ); +end component; + +----- component COUNTER_LOAD_MACRO ----- +component COUNTER_LOAD_MACRO + generic ( + COUNT_BY : std_logic_vector := X"000000000001"; + DEVICE : string := "VIRTEX5"; + STYLE : string := "AUTO"; + WIDTH_DATA : integer := 48 + ); + port ( + Q : out std_logic_vector(WIDTH_DATA-1 downto 0); + CE : in std_logic; + CLK : in std_logic; + DIRECTION : in std_logic; + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_DATA-1 downto 0); + RST : in std_logic + ); +end component; + +----- component COUNTER_TC_MACRO ----- +component COUNTER_TC_MACRO + generic ( + COUNT_BY : std_logic_vector := X"000000000001"; + DEVICE : string := "VIRTEX5"; + DIRECTION : string := "UP"; + RESET_UPON_TC : string := "FALSE"; + STYLE : string := "AUTO"; + TC_VALUE : std_logic_vector := X"000000000000"; + WIDTH_DATA : integer := 48 + ); + port ( + Q : out std_logic_vector(WIDTH_DATA-1 downto 0); + TC : out std_logic; + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end component; + +----- component EQ_COMPARE_MACRO ----- +component EQ_COMPARE_MACRO + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 2; + MASK : bit_vector := X"000000000000"; + SEL_MASK : string := "MASK"; + SEL_PATTERN : string := "DYNAMIC_PATTERN"; + STATIC_PATTERN : bit_vector := X"000000000000"; + WIDTH : integer := 48 + ); + port ( + Q : out std_logic; + CE : in std_logic; + CLK : in std_logic; + DATA_IN : in std_logic_vector(WIDTH-1 downto 0); + DYNAMIC_PATTERN : in std_logic_vector(WIDTH-1 downto 0); + RST : in std_logic + ); +end component; + +----- component FIFO_DUALCLOCK_MACRO ----- +component FIFO_DUALCLOCK_MACRO + generic ( + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DEVICE : string := "VIRTEX5"; + FIFO_SIZE : string := "18Kb"; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + ); + port ( + ALMOSTEMPTY : out std_logic; + ALMOSTFULL : out std_logic; + DO : out std_logic_vector(DATA_WIDTH-1 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + RDCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + RDERR : out std_logic; + WRCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + WRERR : out std_logic; + DI : in std_logic_vector(DATA_WIDTH-1 downto 0); + RDCLK : in std_logic; + RDEN : in std_logic; + RST : in std_logic; + WRCLK : in std_logic; + WREN : in std_logic + ); +end component; + +----- component FIFO_SYNC_MACRO ----- +component FIFO_SYNC_MACRO + generic ( + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DEVICE : string := "VIRTEX5"; + DO_REG : integer := 0; + FIFO_SIZE : string := "18Kb"; + INIT : bit_vector := X"000000000000000000"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + ); + port ( + ALMOSTEMPTY : out std_logic; + ALMOSTFULL : out std_logic; + DO : out std_logic_vector(DATA_WIDTH-1 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + RDCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + RDERR : out std_logic; + WRCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0); + WRERR : out std_logic; + CLK : in std_logic; + DI : in std_logic_vector(DATA_WIDTH-1 downto 0); + RDEN : in std_logic; + RST : in std_logic; + WREN : in std_logic + ); +end component; + +----- component MACC_MACRO ----- +component MACC_MACRO + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 3; + WIDTH_A : integer := 25; + WIDTH_B : integer := 18; + WIDTH_P : integer := 48 + ); + port ( + P : out std_logic_vector(WIDTH_P-1 downto 0); + A : in std_logic_vector(WIDTH_A-1 downto 0); + ADDSUB : in std_logic; + B : in std_logic_vector(WIDTH_B-1 downto 0); + CARRYIN : in std_logic; + CE : in std_logic; + CLK : in std_logic; + LOAD : in std_logic; + LOAD_DATA : in std_logic_vector(WIDTH_P-1 downto 0); + RST : in std_logic + ); +end component; + +----- component MULT_MACRO ----- +component MULT_MACRO + generic ( + DEVICE : string := "VIRTEX5"; + LATENCY : integer := 3; + STYLE : string := "DSP"; + WIDTH_A : integer := 18; + WIDTH_B : integer := 18 + ); + port ( + P : out std_logic_vector((WIDTH_A+WIDTH_B)-1 downto 0); + A : in std_logic_vector(WIDTH_A-1 downto 0); + B : in std_logic_vector(WIDTH_B-1 downto 0); + CE : in std_logic; + CLK : in std_logic; + RST : in std_logic + ); +end component; + +-- END COMPONENT + +end VCOMPONENTS; + +package body VCOMPONENTS is + + FUNCTION xil_UNM_GCW ( + d_width : in integer; + fifo_size : in string; + device : in string + ) return integer is + variable func_width : integer; + begin + if(device = "VIRTEX5" or device = "VIRTEX6" or device = "7SERIES") then + if(fifo_size = "18Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 12; + when 5|6|7|8|9 => func_width := 11; + when 10 to 18 => func_width := 10; + when 19 to 36 => func_width := 9; + when others => func_width := 12; + end case; + elsif(fifo_size = "36Kb") then + case d_width is + when 0|1|2|3|4 => func_width := 13; + when 5|6|7|8|9 => func_width := 12; + when 10 to 18 => func_width := 11; + when 19 to 36 => func_width := 10; + when 37 to 72 => func_width := 9; + when others => func_width := 13; + end case; + end if; + else + func_width := 13; + end if; + return func_width; + end; + +end VCOMPONENTS; diff --git a/resources/dide-lsp/static/vhdl_std_lib/unimacro/vhdl_analyze_order b/resources/dide-lsp/static/vhdl_std_lib/unimacro/vhdl_analyze_order new file mode 100644 index 0000000..e13ec99 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/unimacro/vhdl_analyze_order @@ -0,0 +1,13 @@ +unimacro_VCOMP.vhd +ADDMACC_MACRO.vhd +ADDSUB_MACRO.vhd +BRAM_SDP_MACRO.vhd +BRAM_SINGLE_MACRO.vhd +BRAM_TDP_MACRO.vhd +COUNTER_LOAD_MACRO.vhd +COUNTER_TC_MACRO.vhd +EQ_COMPARE_MACRO.vhd +FIFO_DUALCLOCK_MACRO.vhd +FIFO_SYNC_MACRO.vhd +MACC_MACRO.vhd +MULT_MACRO.vhd diff --git a/resources/dide-lsp/static/vhdl_std_lib/vhdl_ls.toml b/resources/dide-lsp/static/vhdl_std_lib/vhdl_ls.toml new file mode 100644 index 0000000..61d9957 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vhdl_ls.toml @@ -0,0 +1,7 @@ +[libraries] + +std.files = ['std/*.vhd'] +std.is_third_party = true + +ieee.files = ['ieee_2008/*.vhdl', 'synopsys/*.vhd', 'vital2000/*.vhdl', 'unifast/primitive/*.vhd', 'unifast/secureip/*.vhd', 'unimacro/*.vhd'] +ieee.is_third_party = true \ No newline at end of file diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_b.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_b.vhdl new file mode 100644 index 0000000..39bb38a --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_b.vhdl @@ -0,0 +1,7151 @@ +-- ---------------------------------------------------------------------------- +-- Title : Standard VITAL Memory Package +-- : +-- Library : Vital_Memory +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : Ekambaram Balaji, LSI Logic Corporation +-- : Jose De Castro, Consultant +-- : Prakash Bare, GDA Technologies +-- : William Yam, LSI Logic Corporation +-- : Dennis Brophy, Model Technology +-- : +-- Purpose : This packages defines standard types, constants, functions +-- : and procedures for use in developing ASIC memory models. +-- : +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Ver:|Auth:| Date:| Changes Made: +-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal +-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme +-- 0.3 | jdc |090297| Extensive updates for TAG review (functional) +-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable +-- | | | Added interface of VitalMemoryCrossPorts() & +-- | | | VitalMemoryViolation(). +-- 0.5 | jdc |092997| Completed naming changes thoughout package body. +-- | | | Testing with simgle port test model looks ok. +-- 0.6 | jdc |121797| Major updates to the packages: +-- | | | - Implement VitalMemoryCrossPorts() +-- | | | - Use new VitalAddressValueType +-- | | | - Use new VitalCrossPortModeType enum +-- | | | - Overloading without SamePort args +-- | | | - Honor erroneous address values +-- | | | - Honor ports disabled with 'Z' +-- | | | - Implement implicit read 'M' table symbol +-- | | | - Cleanup buses to use (H DOWNTO L) +-- | | | - Message control via MsgOn,HeaderMsg,PortName +-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases +-- 0.7 | jdc |052698| Bug fixes to the packages: +-- | | | - Fix failure with negative Address values +-- | | | - Added debug messages for VMT table search +-- | | | - Remove 'S' for action column (only 's') +-- | | | - Remove 's' for response column (only 'S') +-- | | | - Remove 'X' for action and response columns +-- 0.8 | jdc |061298| Implemented VitalMemoryViolation() +-- | | | - Minimal functionality violation tables +-- | | | - Missing: +-- | | | - Cannot handle wide violation variables +-- | | | - Cannot handle sub-word cases +-- | | | Fixed IIC version of MemoryMatch +-- | | | Fixed 'M' vs 'm' switched on debug output +-- | | | TO BE DONE: +-- | | | - Implement 'd' corrupting a single bit +-- | | | - Implement 'D' corrupting a single bit +-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType +-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType +-- 0.11|eb/sc|081798| Added overloaded function interface for +-- | | | VitalDeclareMemory +-- 0.14| jdc |113198| Merging of memory functionality and version +-- | | | 1.4 9/17/98 of timing package from Prakash +-- 0.15| jdc |120198| Major development of VMV functionality +-- 0.16| jdc |120298| Complete VMV functionlality for initial testing +-- | | | - New ViolationTableCorruptMask() procedure +-- | | | - New MemoryTableCorruptMask() procedure +-- | | | - HandleMemoryAction(): +-- | | | - Removed DataOutBus bogus output +-- | | | - Replaced DataOutTmp with DataInTmp +-- | | | - Added CorruptMask input handling +-- | | | - Implemented 'd','D' using CorruptMask +-- | | | - CorruptMask on 'd','C','L','D','E' +-- | | | - CorruptMask ignored on 'c','l','e' +-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT +-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT +-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit +-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit +-- | | | - HandleDataAction(): +-- | | | - Added CorruptMask input handling +-- | | | - Implemented 'd','D' using CorruptMask +-- | | | - CorruptMask on 'd','C','L','D','E' +-- | | | - CorruptMask ignored on 'l','e' +-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT +-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT +-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit +-- | | | - Changed 'L','D','E' to use HighBit, LowBit +-- | | | - MemoryTableLookUp(): +-- | | | - Added MsgOn table debug output +-- | | | - Uses new MemoryTableCorruptMask() +-- | | | - ViolationTableLookUp(): +-- | | | - Uses new ViolationTableCorruptMask() +-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType, +-- | | | VitalMemoryViolationTableType data +-- | | | types but not used yet (need to discuss) +-- | | | - Added overload for VitalMemoryViolation() +-- | | | which does not have array flags +-- | | | - Bug fixes for VMV functionality: +-- | | | - ViolationTableLookUp() not handling '-' in +-- | | | scalar violation matching +-- | | | - VitalMemoryViolation() now normalizes +-- | | | VFlagArrayTmp'LEFT as LSB before calling +-- | | | ViolationTableLookUp() for proper scanning +-- | | | - ViolationTableCorruptMask() had to remove +-- | | | normalization of CorruptMaskTmp and +-- | | | ViolMaskTmp for proper MSB:LSB corruption +-- | | | - HandleMemoryAction(), HandleDataAction() +-- | | | - Removed 'D','E' since not being used +-- | | | - Use XOR instead of OR for corrupt masks +-- | | | - Now 'd' is sensitive to HighBit, LowBit +-- | | | - Fixed LowBit overflow in bit writeable case +-- | | | - MemoryTableCorruptMask() +-- | | | - ViolationTableCorruptMask() +-- | | | - VitalMemoryTable() +-- | | | - VitalMemoryCrossPorts() +-- | | | - Fixed VitalMemoryViolation() failing on +-- | | | error AddressValue from earlier VMT() +-- | | | - Minor cleanup of code formatting +-- 0.18| jdc |032599| - In VitalDeclareMemory() +-- | | | - Added BinaryLoadFile formal arg and +-- | | | modified LoadMemory() to handle bin +-- | | | - Added NOCHANGE to VitalPortFlagType +-- | | | - For VitalCrossPortModeType +-- | | | - Added CpContention enum +-- | | | - In HandleDataAction() +-- | | | - Set PortFlag := NOCHANGE for 'S' +-- | | | - In HandleMemoryAction() +-- | | | - Set PortFlag := NOCHANGE for 's' +-- | | | - In VitalMemoryTable() and +-- | | | VitalMemoryViolation() +-- | | | - Honor PortFlag = NOCHANGE returned +-- | | | from HandleMemoryAction() +-- | | | - In VitalMemoryCrossPorts() +-- | | | - Fixed Address = AddressJ for all +-- | | | conditions of DoWrCont & DoCpRead +-- | | | - Handle CpContention like WrContOnly +-- | | | under CpReadOnly conditions, with +-- | | | associated memory message changes +-- | | | - Handle PortFlag = NOCHANGE like +-- | | | PortFlag = READ for actions +-- | | | - Modeling change: +-- | | | - Need to init PortFlag every delta +-- | | | PortFlag_A := (OTHES => UNDEF); +-- | | | - Updated InternalTimingCheck code +-- 0.19| jdc |042599| - Fixes for bit-writeable cases +-- | | | - Check PortFlag after HandleDataAction +-- | | | in VitalMemoryViolation() +-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash +-- | | | and Willian: +-- | | | VitalMemorySchedulePathDelay() +-- | | | VitalMemoryExpandPortFlag() +-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums, +-- | | | added new CpReadAndReadContention. +-- | | | - Fixed VitalMemoryCrossPorts() parameter +-- | | | SamePortFlag to INOUT so that it can +-- | | | set CORRUPT or READ value. +-- | | | - Fixed VitalMemoryTable() where PortFlag +-- | | | setting by HandleDataAction() is being +-- | | | ignored when HandleMemoryAction() sets +-- | | | PortFlagTmp to NOCHANGE. +-- | | | - Fixed VitalMemoryViolation() to set +-- | | | all bits of PortFlag when violating. +-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData +-- | | | checks whether the previous state is HIGHZ. +-- | | | If yes then portFlag should be NOCHANGE +-- | | | for VMPD to ignore IORetain corruption. +-- | | | The idea is that the first Z should be +-- | | | propagated but later ones should be ignored. +-- | | | +-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99 +-- | | | - Changed VitalPortFlagType to record of +-- | | | new VitalPortStateType to hold current, +-- | | | previous values and separate disable. +-- | | | Also created VitalDefaultPortFlag const. +-- | | | Removed usage of PortFlag NOCHANGE +-- | | | - VitalMemoryTable() changes: +-- | | | Optimized return when all curr = prev +-- | | | AddressValue is now INOUT to optimize +-- | | | Transfer PF.MemoryCurrent to MemoryPrevious +-- | | | Transfer PF.DataCurrent to DataPrevious +-- | | | Reset PF.OutputDisable to FALSE +-- | | | Expects PortFlag init in declaration +-- | | | No need to init PortFlag every delta +-- | | | - VitalMemorySchedulePathDelay() changes: +-- | | | Initialize with VitalDefaultPortFlag +-- | | | Check PortFlag.OutputDisable +-- | | | - HandleMemoryAction() changes: +-- | | | Set value of PortFlag.MemoryCurrent +-- | | | Never set PortFlag.OutputDisable +-- | | | - HandleDataAction() changes: +-- | | | Set value of PortFlag.DataCurrent +-- | | | Set PortFlag.DataCurrent for HIGHZ +-- | | | - VitalMemoryCrossPorts() changes: +-- | | | Check/set value of PF.MemoryCurrent +-- | | | Check value of PF.OutputDisable +-- | | | - VitalMemoryViolation() changes: +-- | | | Fixed bug - not reading inout PF value +-- | | | Clean up setting of PortFlag +-- 0.24| jdc |100899| - Modified update of PF.OutputDisable +-- | | | to correctly accomodate 2P1W1R case: +-- | | | the read port should not exhibit +-- | | | IO retain corrupt when reading +-- | | | addr unrelated to addr being written. +-- 0.25| jdc |100999| - VitalMemoryViolation() change: +-- | | | Fixed bug with RDNWR mode incorrectly +-- | | | updating the PF.OutputDisable +-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change: +-- | | | Fixed bugs with update of PF +-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change: +-- | | | Added DoRdWrCont message (ErrMcpRdWrCo, +-- | | | Memory cross port read/write data only +-- | | | contention) +-- | | | - VitalMemoryTable() change: +-- | | | Set PF.OutputDisable := TRUE for the +-- | | | optimized cases. +-- 0.28| pb |112399| - Added 8 VMPD procedures for vector +-- | | | PathCondition support. Now the total +-- | | | number of overloadings for VMPD is 24. +-- | | | - Number of overloadings for SetupHold +-- | | | procedures increased to 5. Scalar violations +-- | | | are not supported anymore. Vector checkEnabled +-- | | | support is provided through the new overloading +-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction() +-- | | | Reinstated 'D' and 'E' actions but +-- | | | with new PortFlagType +-- | | | - Updated file handling syntax, must compile +-- | | | with -93 syntax now. +-- 0.30| jdc |022300| - Formated for 80 column max width +-- ---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.Vital_Timing.all; +USE IEEE.Vital_Primitives.all; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +-- ---------------------------------------------------------------------------- +PACKAGE BODY Vital_Memory IS + +-- ---------------------------------------------------------------------------- +-- Timing Section +-- ---------------------------------------------------------------------------- + +FILE LogFile : TEXT OPEN write_mode IS "delayLog"; +FILE Output : TEXT OPEN write_mode IS "STD_OUTPUT"; + +-- Added for turning off the debug msg.. +CONSTANT PrintDebugMsg : STD_ULOGIC := '0'; + -- '0' - don't print in STD OUTPUT + -- '1' - print in STD OUTPUT + +-- Type and constant definitions for type conversion. +TYPE MVL9_TO_CHAR_TBL IS ARRAY (STD_ULOGIC) OF character; + +--constant MVL9_to_char: MVL9_TO_CHAR_TBL := "UX01ZWLH-"; +CONSTANT MVL9_to_char: MVL9_TO_CHAR_TBL := "XX01ZX010"; + +-- ---------------------------------------------------------------------------- +-- STD_LOGIC WRITE UTILITIES +-- ---------------------------------------------------------------------------- +PROCEDURE WRITE( + l : INOUT line; + val : IN std_logic_vector; + justify : IN side := right; + field : IN width := 0 +) IS + VARIABLE invect : std_logic_vector(val'LENGTH DOWNTO 1); + VARIABLE ins : STRING(val'LENGTH DOWNTO 1); +BEGIN + invect := val; + FOR I IN invect'length DOWNTO 1 LOOP + ins(I) := MVL9_to_char(invect(I)); + END LOOP; + WRITE(L, ins, justify, field); +END; + +PROCEDURE WRITE( + l : INOUT line; + val : IN std_ulogic; + justify : IN side := right; + field : in width := 0 +) IS + VARIABLE ins : CHARACTER; +BEGIN + ins := MVL9_to_char(val); + WRITE(L, ins, justify, field); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE DelayValue( + InputTime : IN TIME ; + outline : INOUT LINE +) IS + CONSTANT header : STRING := "TIME'HIGH"; +BEGIN + IF(InputTime = TIME'HIGH) THEN + WRITE(outline, header); + ELSE + WRITE(outline, InputTime); + END IF; +END DelayValue; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintScheduleDataArray ( + ScheduleDataArray : IN VitalMemoryScheduleDataVectorType +) IS + VARIABLE outline1 : LINE; + VARIABLE outline2 : LINE; + VARIABLE value : TIME; + CONSTANT empty : STRING := " "; + CONSTANT header1 : STRING := "i Age PropDly RetainDly"; + CONSTANT header2 : STRING := "i Sc.Value Output Lastvalue Sc.Time"; +BEGIN + WRITE (outline1, empty); + WRITE (outline1, NOW); + outline2 := outline1; + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITE (outline1, header1); + outline2 := outline1; + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + FOR i IN ScheduleDataArray'RANGE LOOP + WRITE (outline1, i ); + WRITE (outline1, empty); + DelayValue(ScheduleDataArray(i).InputAge, outline1); + WRITE (outline1, empty); + DelayValue(ScheduleDataArray(i).PropDelay, outline1); + WRITE (outline1, empty); + DelayValue(ScheduleDataArray(i).OutputRetainDelay, outline1); + outline2 := outline1; + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + END LOOP; + WRITE (outline1, header2); + outline2 := outline1; + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + FOR i IN ScheduleDataArray'RANGE LOOP + WRITE (outline1, i ); + WRITE (outline1, empty); + WRITE (outline1, ScheduleDataArray(i).ScheduleValue); + WRITE (outline1, empty); + WRITE (outline1, ScheduleDataArray(i).OutputData); + WRITE (outline1, empty); + WRITE (outline1, ScheduleDataArray(i).LastOutputValue ); + WRITE (outline1, empty); + DelayValue(ScheduleDataArray(i).ScheduleTime, outline1); + outline2 := outline1; + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + END LOOP; + WRITE (outline1, empty); + WRITE (outline2, empty); + WRITELINE (LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (Output, outline2); + END IF; +END PrintScheduleDataArray; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintArcType ( + ArcType : IN VitalMemoryArcType +) IS + VARIABLE outline1, outline2 : LINE; + CONSTANT empty : STRING := " "; + CONSTANT cross : STRING := "CrossArc"; + CONSTANT para : STRING := "ParallelArc"; + CONSTANT sub : STRING := "SubWordArc"; + CONSTANT Header1 : STRING := "Path considered @ "; + CONSTANT Header2 : STRING := " is "; +BEGIN + WRITELINE (LogFile, outline1); + WRITE (outline1, header1); + WRITE (outline1, NOW); + WRITE (outline1, empty); + WRITE (outline1, header2); + WRITE (outline1, empty); + case ArcType is + WHEN CrossArc => + WRITE (outline1, cross); + WHEN ParallelArc => + WRITE (outline1, para); + WHEN SubwordArc => + WRITE (outline1, sub); + END CASE; + outline2 := outline1 ; + -- Appears on STD OUT + IF (PrintDebugMsg = '1') THEN + WRITELINE (Output, outline1); + END IF; + WRITELINE (LogFile, outline2); +END PrintArcType; + +-- ---------------------------------------------------------------------------- +-- This returns the value picked from the delay array +-- ---------------------------------------------------------------------------- +PROCEDURE PrintDelay ( + outbitpos : IN INTEGER; + InputArrayLow : IN INTEGER; + InputArrayHigh : IN INTEGER; + debugprop : IN VitalTimeArrayT; + debugretain : IN VitalTimeArrayT +) IS + VARIABLE outline1 : LINE; + VARIABLE outline2 : LINE; + VARIABLE outline3 : LINE; + VARIABLE outline4 : LINE; + VARIABLE outline5 : LINE; + VARIABLE outline6 : LINE; + CONSTANT empty : STRING := " "; + CONSTANT empty5 : STRING := " "; + CONSTANT header1 : STRING := "Prop. delays : "; + CONSTANT header2 : STRING := "Retain delays : "; + CONSTANT header3 : STRING := "output bit : "; +BEGIN + WRITE(outline1, header3); + WRITE(outline1, outbitpos); + outline2 := outline1; + WRITELINE(LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE(output, outline2); + END IF; + WRITE(outline1, header1); + WRITE (outline1, empty5); + FOR i IN InputArrayHigh DOWNTO InputArrayLow LOOP + DelayValue(debugprop(i), outline1); + WRITE(outline1, empty); + END LOOP; + outline2 := outline1; + WRITELINE(LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE(output, outline2); + END IF; + WRITE(outline1, header2); + WRITE (outline1, empty5); + FOR i in InputArrayHigh DOWNTO InputArrayLow LOOP + DelayValue(debugretain(i), outline1); + WRITE(outline1, empty); + END LOOP; + outline2 := outline1; + WRITELINE(LogFile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE(output, outline2); + END IF; +END PrintDelay; + +-- ---------------------------------------------------------------------------- +PROCEDURE DebugMsg1 IS + CONSTANT header1:STRING:= "******************************************"; + CONSTANT header2 :STRING:="Entering the process because of an i/p change"; + variable outline1, outline2 : LINE; +BEGIN + WRITE(outline1, header1); + outline2 := outline1; + WRITELINE (Logfile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITE(outline1, header2); + outline2 := outline1; + WRITELINE (Logfile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITE(outline1, header1); + outline2 := outline1; + WRITELINE (Logfile, outline1); + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; +END DebugMsg1; + +-- ---------------------------------------------------------------------------- +PROCEDURE ScheduleDebugMsg IS + CONSTANT header1 : STRING := "******************************************"; + CONSTANT header2 : STRING := "Finished executing all the procedures"; + VARIABLE outline1 : LINE; + VARIABLE outline2 : LINE; +BEGIN + WRITE(outline1, header1); + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); + WRITE(outline1, header2); + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); + WRITE(outline1, header1); + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); +END ScheduleDebugMsg; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintInputName( + InputSignalName : IN STRING +) IS + VARIABLE outline1 : LINE; + VARIABLE outline2 : LINE; + CONSTANT header1 : STRING := "***Changing input is "; + CONSTANT header2 : STRING := "("; + CONSTANT header3 : STRING := ")"; + CONSTANT header4 : STRING := "****"; + CONSTANT header5 : STRING := "******************************************"; + CONSTANT header6 : STRING:="Entering the process because of an i/p change"; + CONSTANT empty : STRING := " "; +BEGIN + WRITE(outline1, header5); + outline2 := outline1; + WRITELINE (output, outline1); + WRITELINE (Logfile, outline2); + WRITE(outline1, header6); + outline2 := outline1; + WRITELINE (output, outline1); + WRITELINE (Logfile, outline2); + WRITE(outline1, header5); + outline2 := outline1; + WRITELINE (output, outline1); + WRITELINE (Logfile, outline2); + WRITE(outline1, header1); + WRITE(outline1, InputSignalName); + WRITE(outline1, empty); + WRITE(outline1, now); + WRITE(outline1, empty); + WRITE(outline1, header4); + WRITELINE (output, outline1); + WRITELINE (Logfile, outline2); +END PrintInputName; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintInputChangeTime( + ChangeTimeArray : IN VitalTimeArrayT +) IS + VARIABLE outline1 : LINE; + VARIABLE outline2 : LINE; + CONSTANT header5 : STRING := "*************************************"; + CONSTANT header6 : STRING:="ChangeTime Array : "; + CONSTANT empty : STRING := " "; +BEGIN + WRITE(outline1, header5); + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); + WRITE(outline1, header6); + FOR i in ChangeTimeArray'range LOOP + WRITE(outline1, ChangeTimeArray(i)); + WRITE(outline1, empty); + END LOOP; + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); + WRITE(outline1, header5); + outline2 := outline1; + IF (PrintDebugMsg = '1') THEN + WRITELINE (output, outline2); + END IF; + WRITELINE (Logfile, outline1); +END PrintInputChangeTime; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintInputChangeTime( + ChangeTime : IN Time +) IS + VARIABLE ChangeTimeArray : VitalTimeArrayT(0 DOWNTO 0); +BEGIN + ChangeTimeArray(0) := ChangeTime; + PrintInputChangeTime(ChangeTimeArray); +END PrintInputChangeTime; + +-- ---------------------------------------------------------------------------- +-- for debug purpose +CONSTANT MaxNoInputBits : INTEGER := 1000; + +TYPE VitalMemoryDelayType IS RECORD + PropDelay : TIME; + OutputRetainDelay : TIME; +END RECORD; + +-- ---------------------------------------------------------------------------- +-- PROCEDURE: IntToStr +-- +-- PARAMETERS: InputInt - Integer to be converted to String. +-- ResultStr - String buffer for converted Integer +-- AppendPos - Position in buffer to place result +-- +-- DESCRIPTION: This procedure is used to convert an input integer +-- into a string representation. The converted string +-- may be placed at a specific position in the result +-- buffer. +-- +-- ---------------------------------------------------------------------------- + +PROCEDURE IntToStr ( + InputInt : IN INTEGER ; + ResultStr : INOUT STRING ( 1 TO 256) ; + AppendPos : INOUT NATURAL +) IS + -- Look-up table. Given an int, we can get the character. + TYPE integer_table_type IS ARRAY (0 TO 9) OF CHARACTER ; + CONSTANT integer_table : integer_table_type := + ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ; + -- Local variables used in this function. + VARIABLE inpVal : INTEGER := inputInt ; + VARIABLE divisor : INTEGER := 10 ; + VARIABLE tmpStrIndex : INTEGER := 1 ; + VARIABLE tmpStr : STRING ( 1 TO 256 ) ; +BEGIN + IF ( inpVal = 0 ) THEN + tmpStr(tmpStrIndex) := integer_table ( 0 ) ; + tmpStrIndex := tmpStrIndex + 1 ; + ELSE + WHILE ( inpVal > 0 ) LOOP + tmpStr(tmpStrIndex) := integer_table (inpVal mod divisor); + tmpStrIndex := tmpStrIndex + 1 ; + inpVal := inpVal / divisor ; + END LOOP ; + END IF ; + IF (appendPos /= 1 ) THEN + resultStr(appendPos) := ',' ; + appendPos := appendPos + 1 ; + END IF ; + + FOR i IN tmpStrIndex-1 DOWNTO 1 LOOP + resultStr(appendPos) := tmpStr(i) ; + appendPos := appendPos + 1 ; + END LOOP ; +END IntToStr ; + +-- ---------------------------------------------------------------------------- +TYPE CheckType IS ( + SetupCheck, + HoldCheck, + RecoveryCheck, + RemovalCheck, + PulseWidCheck, + PeriodCheck +); + +TYPE CheckInfoType IS RECORD + Violation : BOOLEAN; + CheckKind : CheckType; + ObsTime : TIME; + ExpTime : TIME; + DetTime : TIME; + State : X01; +END RECORD; + +TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER; +TYPE HiLoStrType IS ARRAY (std_ulogic RANGE 'X' TO '1') OF STRING(1 TO 4); + +CONSTANT LogicCvtTable : LogicCvtTableType + := ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); +CONSTANT HiLoStr : HiLoStrType := (" X ", " Low", "High" ); + +TYPE EdgeSymbolMatchType IS ARRAY (X01,X01,VitalEdgeSymbolType) OF BOOLEAN; + +-- last value, present value, edge symbol +CONSTANT EdgeSymbolMatch : EdgeSymbolMatchType := + ( + 'X' => + ( 'X'=>( OTHERS => FALSE), + '0'=>('N'|'F'|'v'|'E'|'D'|'*' => TRUE, OTHERS => FALSE ), + '1'=>('P'|'R'|'^'|'E'|'A'|'*' => TRUE, OTHERS => FALSE ) + ), + '0' => + ( 'X'=>( 'r'|'p'|'R'|'A'|'*' => TRUE, OTHERS => FALSE ), + '0'=>( OTHERS => FALSE ), + '1'=>( '/'|'P'|'p'|'R'|'*' => TRUE, OTHERS => FALSE ) + ), + '1' => + ( 'X'=>( 'f'|'n'|'F'|'D'|'*' => TRUE, OTHERS => FALSE ), + '0'=>( '\'|'N'|'n'|'F'|'*' => TRUE, OTHERS => FALSE ), + '1'=>( OTHERS => FALSE ) + ) + ); + +-- ---------------------------------------------------------------------------- +FUNCTION Minimum ( + CONSTANT t1, t2 : IN TIME +) RETURN TIME IS +BEGIN + IF (t1 < t2) THEN RETURN (t1); ELSE RETURN (t2); END IF; +END Minimum; + +-- ---------------------------------------------------------------------------- +FUNCTION Maximum ( + CONSTANT t1, t2 : IN TIME +) RETURN TIME IS +BEGIN + IF (t1 < t2) THEN RETURN (t2); ELSE RETURN (t1); END IF; +END Maximum; + +-- ---------------------------------------------------------------------------- +-- FUNCTION: VitalMemoryCalcDelay +-- Description: Select Transition dependent Delay. +-- Used internally by VitalMemorySelectDelay. +-- ---------------------------------------------------------------------------- +FUNCTION VitalMemoryCalcDelay ( + CONSTANT NewVal : IN STD_ULOGIC := 'X'; + CONSTANT OldVal : IN STD_ULOGIC := 'X'; + CONSTANT Delay : IN VitalDelayType01ZX +) RETURN VitalMemoryDelayType IS + VARIABLE Result : VitalMemoryDelayType; +BEGIN + CASE Oldval IS + WHEN '0' | 'L' => + CASE Newval IS + WHEN '0' | 'L' => + Result.PropDelay := Delay(tr10); + WHEN '1' | 'H' => + Result.PropDelay := Delay(tr01); + WHEN 'Z' => + Result.PropDelay := Delay(tr0Z); + WHEN OTHERS => + Result.PropDelay := Minimum(Delay(tr01), Delay(tr0Z)); + END CASE; + Result.OutputRetainDelay := Delay(tr0X); + WHEN '1' | 'H' => + CASE Newval IS + WHEN '0' | 'L' => + Result.PropDelay := Delay(tr10); + WHEN '1' | 'H' => + Result.PropDelay := Delay(tr01); + WHEN 'Z' => + Result.PropDelay := Delay(tr1Z); + WHEN OTHERS => + Result.PropDelay := Minimum(Delay(tr10), Delay(tr1Z)); + END CASE; + Result.OutputRetainDelay := Delay(tr1X); + WHEN 'Z' => + CASE Newval IS + WHEN '0' | 'L' => + Result.PropDelay := Delay(trZ0); + WHEN '1' | 'H' => + Result.PropDelay := Delay(trZ1); + WHEN 'Z' => + Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z)); + WHEN OTHERS => + Result.PropDelay := Minimum(Delay(trZ1), Delay(trZ0)); + END CASE; + Result.OutputRetainDelay := Delay(trZX); + WHEN OTHERS => + CASE Newval IS + WHEN '0' | 'L' => + Result.PropDelay := Maximum(Delay(tr10), Delay(trZ0)); + WHEN '1' | 'H' => + Result.PropDelay := Maximum(Delay(tr01), Delay(trZ1)); + WHEN 'Z' => + Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z)); + WHEN OTHERS => + Result.PropDelay := Maximum(Delay(tr10), Delay(tr01)); + END CASE; + Result.OutputRetainDelay := Minimum(Delay(tr1X), Delay(tr0X)); + END CASE; + RETURN Result; +END VitalMemoryCalcDelay; + +-- ---------------------------------------------------------------------------- +FUNCTION VitalMemoryCalcDelay ( + CONSTANT NewVal : IN STD_ULOGIC := 'X'; + CONSTANT OldVal : IN STD_ULOGIC := 'X'; + CONSTANT Delay : IN VitalDelayType01Z +) RETURN VitalMemoryDelayType IS + VARIABLE Result : VitalMemoryDelayType; +BEGIN +CASE Oldval IS + WHEN '0' | 'L' => + CASE Newval IS + WHEN '0' | 'L' => Result.PropDelay := Delay(tr10); + WHEN '1' | 'H' => Result.PropDelay := Delay(tr01); + WHEN OTHERS => + Result.PropDelay := Minimum(Delay(tr01), Delay(tr10)); + END CASE; + Result.OutputRetainDelay := Delay(tr0Z); + WHEN '1' | 'H' => + CASE Newval IS + WHEN '0' | 'L' => Result.PropDelay := Delay(tr10); + WHEN '1' | 'H' => Result.PropDelay := Delay(tr01); + WHEN OTHERS => + Result.PropDelay := Minimum(Delay(tr10), Delay(tr01)); + END CASE; + Result.OutputRetainDelay := Delay(tr1Z); + WHEN OTHERS => + Result.PropDelay := Maximum(Delay(tr10),Delay(tr01)); + Result.OutputRetainDelay := Minimum(Delay(tr1Z),Delay(tr0Z)); + END CASE; + RETURN Result; +END VitalMemoryCalcDelay; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryUpdateInputChangeTime ( + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + VARIABLE NumBitsPerSubword : INTEGER +) IS + VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0); + VARIABLE InSignalNorm : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0); + VARIABLE ChangeTimeNorm : VitalTimeArrayT(InputSignal'LENGTH-1 downto 0); + VARIABLE BitsPerWord : INTEGER; +BEGIN + LastInputValue := InputSignal'LAST_VALUE; + IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN + BitsPerWord := InputSignal'LENGTH; + ELSE + BitsPerWord := NumBitsPerSubword; + END IF; + + FOR i IN InSignalNorm'RANGE LOOP + IF (InSignalNorm(i) /= LastInputValue(i)) THEN + ChangeTimeNorm(i/BitsPerWord) := NOW - InputSignal'LAST_EVENT; + ELSE + ChangeTimeNorm(i/BitsPerWord) := InputChangeTimeArray(i); + END IF; + END LOOP; + + FOR i IN ChangeTimeNorm'RANGE LOOP + ChangeTimeNorm(i) := ChangeTimeNorm(i/BitsPerword); + END LOOP; + + InputChangeTimeArray := ChangeTimeNorm; + + -- for debug purpose only + PrintInputChangeTime(InputChangeTimeArray); +END VitalMemoryUpdateInputChangeTime; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryUpdateInputChangeTime +-- Description: Time since previous event for each bit of the input +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryUpdateInputChangeTime ( + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR +) IS + VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'RANGE) ; +BEGIN + LastInputValue := InputSignal'LAST_VALUE; + FOR i IN InputSignal'RANGE LOOP + IF (InputSignal(i) /= LastInputValue(i)) THEN + InputChangeTimeArray(i) := NOW - InputSignal'LAST_EVENT; + END IF; + END LOOP; + -- for debug purpose only + PrintInputChangeTime(InputChangeTimeArray); +END VitalMemoryUpdateInputChangeTime; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryUpdateInputChangeTime ( + VARIABLE InputChangeTime : INOUT TIME; + SIGNAL InputSignal : IN STD_ULOGIC +) IS +BEGIN + InputChangeTime := NOW - InputSignal'LAST_EVENT; + -- for debug purpose only + PrintInputChangeTime(InputChangeTime); +END VitalMemoryUpdateInputChangeTime; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryExpandPortFlag ( + CONSTANT PortFlag : IN VitalPortFlagVectorType; + CONSTANT NumBitsPerSubword : IN INTEGER; + VARIABLE ExpandedPortFlag : OUT VitalPortFlagVectorType +) IS + VARIABLE PortFlagNorm : VitalPortFlagVectorType( + PortFlag'LENGTH-1 downto 0) := PortFlag; + VARIABLE ExpandedPortFlagNorm : VitalPortFlagVectorType( + ExpandedPortFlag'LENGTH-1 downto 0); + VARIABLE SubwordIndex : INTEGER; +BEGIN + FOR Index IN INTEGER RANGE 0 to ExpandedPortFlag'LENGTH-1 LOOP + IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN + SubwordIndex := 0; + ELSE + SubwordIndex := Index / NumBitsPerSubword; + END IF; + ExpandedPortFlagNorm(Index) := PortFlagNorm(SubWordIndex); + END LOOP; + ExpandedPortFlag := ExpandedPortFlagNorm; +END VitalMemoryExpandPortFlag; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemorySelectDelay +-- Description : Select Propagation Delay. Used internally by +-- VitalMemoryAddPathDelay. +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- VitalDelayArrayType01ZX +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySelectDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE InputChangeTimeArray : IN VitalTimeArrayT; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN +) IS + VARIABLE InputArrayLow : INTEGER := 0; + VARIABLE InputArrayHigh : INTEGER := 0; + VARIABLE DelayArrayIndex : INTEGER := 0; + VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword; + VARIABLE NewValue : STD_ULOGIC; + VARIABLE OldValue : STD_ULOGIC; + VARIABLE OutputLength : INTEGER := 0; + VARIABLE OutArrayIndex : INTEGER; + VARIABLE PropDelay : TIME; + VARIABLE RetainDelay : TIME; + VARIABLE CurPropDelay : TIME; + VARIABLE CurRetainDelay : TIME; + VARIABLE InputAge : TIME; + VARIABLE CurInputAge : TIME; + VARIABLE InputChangeTimeNorm : VitalTimeArrayT( + InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray; + VARIABLE DelayArrayNorm : VitalDelayArrayType01ZX( + PathDelayArray'LENGTH-1 downto 0):= PathDelayArray; + VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType + (ScheduleDataArray'LENGTH-1 downto 0):= ScheduleDataArray; + + -- for debug purpose + VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0); + VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0); + +BEGIN + + -- for debug purpose + PrintArcType(ArcType); + + OutputLength := ScheduleDataArray'LENGTH; + FOR OutBitPos IN 0 to (OutputLength -1) LOOP + NEXT WHEN PathConditionArray(OutBitPos) = FALSE; + + NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue + = ScheduleDataArrayNorm(OutBitPos).OutputData) AND + (ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND + (OutputRetainFlag = FALSE )); + + NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData; + OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue; + PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay; + InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge; + RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay; + NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord; + + CASE ArcType IS + WHEN ParallelArc => + InputArrayLow := OutBitPos; + InputArrayHigh := OutBitPos; + DelayArrayIndex := OutBitPos; + WHEN CrossArc => + InputArrayLow := 0; + InputArrayHigh := InputChangeTimeArray'LENGTH - 1 ; + DelayArrayIndex := OutBitPos; + WHEN SubwordArc => + InputArrayLow := OutBitPos / NumBitsPerSubWord; + InputArrayHigh := OutBitPos / NumBitsPerSubWord; + DelayArrayIndex := OutBitPos + + (OutputLength * (OutBitPos / NumBitsPerSubWord)); + END CASE; + + FOR i IN InputArrayLow TO InputArrayHigh LOOP + (CurPropDelay,CurRetainDelay) := + VitalMemoryCalcDelay ( + NewValue, OldValue, DelayArrayNorm(DelayArrayIndex) + ); + IF (OutputRetainFlag = FALSE) THEN + CurRetainDelay := TIME'HIGH; + END IF; + + -- for debug purpose + debugprop(i) := CurPropDelay; + debugretain(i) := CurRetainDelay; + + IF ArcType = CrossArc THEN + DelayArrayIndex := DelayArrayIndex + OutputLength; + END IF; + + -- If there is one input change at a time, then choose the + -- delay from that input. If there is simultaneous input + -- change, then choose the minimum of propagation delays + + IF (InputChangeTimeNorm(i) < 0 ns)THEN + CurInputAge := TIME'HIGH; + ELSE + CurInputAge := NOW - InputChangeTimeNorm(i); + END IF; + + IF (CurInputAge < InputAge)THEN + PropDelay := CurPropDelay; + RetainDelay := CurRetainDelay; + InputAge := CurInputAge; + ELSIF (CurInputAge = InputAge)THEN + IF (CurPropDelay < PropDelay) THEN + PropDelay := CurPropDelay; + END IF; + IF (OutputRetainFlag = TRUE) THEN + IF (CurRetainDelay < RetainDelay) THEN + RetainDelay := CurRetainDelay; + END IF; + END IF; + END IF; + END LOOP; + + -- Store it back to data strucutre + ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay; + ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay; + ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge; + + -- for debug purpose + PrintDelay(outbitPos,InputArrayLow, InputArrayHigh, + debugprop, debugretain); + END LOOP; + + ScheduleDataArray := ScheduleDataArrayNorm; + +END VitalMemorySelectDelay; + +-- ---------------------------------------------------------------------------- +-- VitalDelayArrayType01Z +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySelectDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE InputChangeTimeArray : IN VitalTimeArrayT; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN +) IS + VARIABLE InputArrayLow : INTEGER := 0; + VARIABLE InputArrayHigh : INTEGER := 0; + VARIABLE DelayArrayIndex : INTEGER := 0; + VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword; + VARIABLE NewValue : STD_ULOGIC; + VARIABLE OldValue : STD_ULOGIC; + VARIABLE OutputLength : INTEGER := 0; + VARIABLE OutArrayIndex : INTEGER; + VARIABLE PropDelay : TIME; + VARIABLE RetainDelay : TIME; + VARIABLE CurPropDelay : TIME; + VARIABLE CurRetainDelay : TIME; + VARIABLE InputAge : TIME; + VARIABLE CurInputAge : TIME; + VARIABLE InputChangeTimeNorm : VitalTimeArrayT( + InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray; + VARIABLE DelayArrayNorm : VitalDelayArrayType01Z( + PathDelayArray'LENGTH-1 downto 0):= PathDelayArray; + VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType + (ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray; + + -- for debug purpose + VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0); + VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0); +BEGIN + + -- for debug purpose + PrintArcType(ArcType); + + OutputLength := ScheduleDataArray'LENGTH; + FOR OutBitPos IN 0 to (OutputLength -1) LOOP + NEXT WHEN PathConditionArray(OutBitPos) = FALSE; + + NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue + = ScheduleDataArrayNorm(OutBitPos).OutputData) AND + (ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND + (OutputRetainFlag = FALSE)); + + NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData; + OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue; + PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay; + InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge; + RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay; + NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord; + + CASE ArcType IS + WHEN ParallelArc => + InputArrayLow := OutBitPos; + InputArrayHigh := OutBitPos; + DelayArrayIndex := OutBitPos; + WHEN CrossArc => + InputArrayLow := 0; + InputArrayHigh := InputChangeTimeArray'LENGTH-1; + DelayArrayIndex := OutBitPos; + WHEN SubwordArc => + InputArrayLow := OutBitPos / NumBitsPerSubWord; + InputArrayHigh := OutBitPos / NumBitsPerSubWord; + DelayArrayIndex := OutBitPos + + (OutputLength * (OutBitPos / NumBitsPerSubWord)); + END CASE; + + FOR i IN InputArrayLow TO InputArrayHigh LOOP + (CurPropDelay, CurRetainDelay) := + VitalMemoryCalcDelay ( + NewValue, OldValue, DelayArrayNorm(DelayArrayIndex) + ); + IF (OutputRetainFlag = FALSE) THEN + CurRetainDelay := TIME'HIGH; + END IF; + + -- for debug purpose + debugprop(i) := CurPropDelay; + debugretain(i) := CurRetainDelay; + + IF (ArcType = CrossArc) THEN + DelayArrayIndex := DelayArrayIndex + OutputLength; + END IF; + + -- If there is one input change at a time, then choose the + -- delay from that input. If there is simultaneous input + -- change, then choose the minimum of propagation delays + + IF (InputChangeTimeNorm(i) < 0 ns) THEN + CurInputAge := TIME'HIGH; + ELSE + CurInputAge := NOW - InputChangeTimeNorm(i); + END IF; + + IF (CurInputAge < InputAge) THEN + PropDelay := CurPropDelay; + RetainDelay := CurRetainDelay; + InputAge := CurInputAge; + ELSIF (CurInputAge = InputAge) THEN + IF (CurPropDelay < PropDelay) THEN + PropDelay := CurPropDelay; + END IF; + IF (OutputRetainFlag = TRUE) THEN + IF (CurRetainDelay < RetainDelay) THEN + RetainDelay := CurRetainDelay; + END IF; + END IF; + END IF; + END LOOP; + + -- Store it back to data strucutre + ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay; + ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay; + ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge; + + -- for debug purpose + PrintDelay(outbitPos, InputArrayLow, InputArrayHigh, + debugprop, debugretain); + END LOOP; + + ScheduleDataArray := ScheduleDataArrayNorm; + +END VitalMemorySelectDelay; + +-- ---------------------------------------------------------------------------- +-- VitalDelayArrayType01 +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySelectDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE InputChangeTimeArray : IN VitalTimeArrayT; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType; + CONSTANT PathConditionArray : IN VitalBoolArrayT +) IS + VARIABLE CurPathDelay : VitalMemoryDelayType; + VARIABLE InputArrayLow : INTEGER := 0; + VARIABLE InputArrayHigh : INTEGER := 0; + VARIABLE DelayArrayIndex : INTEGER := 0; + VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword; + VARIABLE NewValue : STD_ULOGIC; + VARIABLE OldValue : STD_ULOGIC; + VARIABLE OutputLength : INTEGER := 0; + VARIABLE OutArrayIndex : INTEGER; + VARIABLE PropDelay : TIME; + VARIABLE CurPropDelay : TIME; + VARIABLE InputAge : TIME; + VARIABLE CurInputAge : TIME; + VARIABLE InputChangeTimeNorm : VitalTimeArrayT( + InputChangeTimeArray'LENGTH-1 downto 0):= InputChangeTimeArray; + VARIABLE DelayArrayNorm : VitalDelayArrayType01( + PathDelayArray'LENGTH-1 downto 0):= PathDelayArray; + VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType + (ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray; + + -- for debug purpose + VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0); + VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0); +BEGIN + + -- for debug purpose + PrintArcType(ArcType); + + OutputLength := ScheduleDataArray'LENGTH; + FOR OutBitPos IN 0 to (OutputLength -1) LOOP + NEXT WHEN PathConditionArray(OutBitPos) = FALSE; + + NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue + = ScheduleDataArrayNorm(OutBitPos).OutputData) AND + (ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW)); + + NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData; + OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue; + PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay; + InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge; + NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord; + + CASE ArcType IS + WHEN ParallelArc => + InputArrayLow := OutBitPos; + InputArrayHigh := OutBitPos; + DelayArrayIndex := OutBitPos; + WHEN CrossArc => + InputArrayLow := 0; + InputArrayHigh := InputChangeTimeArray'LENGTH-1; + DelayArrayIndex := OutBitPos; + WHEN SubwordArc => + InputArrayLow := OutBitPos / NumBitsPerSubWord; + InputArrayHigh := OutBitPos / NumBitsPerSubWord; + DelayArrayIndex := OutBitPos + + (OutputLength * (OutBitPos / NumBitsPerSubWord)); + END CASE; + + FOR i IN InputArrayLow TO InputArrayHigh LOOP + CurPropDelay:= VitalCalcDelay (NewValue, + OldValue, DelayArrayNorm(DelayArrayIndex)); + + -- for debug purpose + debugprop(i) := CurPropDelay; + debugretain(i) := TIME'HIGH; + + IF (ArcType = CrossArc) THEN + DelayArrayIndex := DelayArrayIndex + OutputLength; + END IF; + + -- If there is one input change at a time, then choose the + -- delay from that input. If there is simultaneous input + -- change, then choose the minimum of propagation delays + + IF (InputChangeTimeNorm(i) < 0 ns) THEN + CurInputAge := TIME'HIGH; + ELSE + CurInputAge := NOW - InputChangeTimeNorm(i); + END IF; + IF (CurInputAge < InputAge) THEN + PropDelay := CurPropDelay; + InputAge := CurInputAge; + ELSIF (CurInputAge = InputAge) THEN + IF (CurPropDelay < PropDelay) THEN + PropDelay := CurPropDelay; + END IF; + END IF; + END LOOP; + + -- Store it back to data strucutre + ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay; + ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge; + + -- for debug purpose + PrintDelay(outbitPos, InputArrayLow, InputArrayHigh, + debugprop, debugretain); + END LOOP; + + ScheduleDataArray := ScheduleDataArrayNorm; + +END VitalMemorySelectDelay; + +-- ---------------------------------------------------------------------------- +-- VitalDelayArrayType +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySelectDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE InputChangeTimeArray : IN VitalTimeArrayT; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType; + CONSTANT PathConditionArray : IN VitalBoolArrayT +) IS + VARIABLE InputArrayLow : INTEGER := 0; + VARIABLE InputArrayHigh : INTEGER := 0; + VARIABLE DelayArrayIndex : INTEGER := 0; + VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword; + VARIABLE NewValue : STD_ULOGIC; + VARIABLE OldValue : STD_ULOGIC; + VARIABLE OutputLength : INTEGER := 0; + VARIABLE OutArrayIndex : INTEGER; + VARIABLE PropDelay : TIME; + VARIABLE CurPropDelay : TIME; + VARIABLE InputAge : TIME; + VARIABLE CurInputAge : TIME; + VARIABLE InputChangeTimeNorm : VitalTimeArrayT( + InputChangeTimeArray'LENGTH-1 downto 0) := InputChangeTimeArray; + VARIABLE DelayArrayNorm : VitalDelayArrayType( + PathDelayArray'LENGTH-1 downto 0) := PathDelayArray; + VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType + (ScheduleDataArray'LENGTH-1 downto 0) := ScheduleDataArray; + + -- for debug purpose + VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0); + VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0); +BEGIN + + -- for debug purpose + PrintArcType(ArcType); + + OutputLength := ScheduleDataArray'LENGTH; + FOR OutBitPos IN 0 to (OutputLength -1) LOOP + NEXT WHEN PathConditionArray(OutBitPos) = FALSE; + + NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue + = ScheduleDataArrayNorm(OutBitPos).OutputData) AND + (ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW)); + + NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData; + OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue; + PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay; + InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge; + NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord; + + CASE ArcType IS + WHEN ParallelArc => + InputArrayLow := OutBitPos; + InputArrayHigh := OutBitPos; + DelayArrayIndex := OutBitPos; + WHEN CrossArc => + InputArrayLow := 0; + InputArrayHigh := InputChangeTimeArray'LENGTH-1; + DelayArrayIndex := OutBitPos; + WHEN SubwordArc => + InputArrayLow := OutBitPos / NumBitsPerSubWord; + InputArrayHigh := OutBitPos / NumBitsPerSubWord; + DelayArrayIndex := OutBitPos + + (OutputLength * (OutBitPos / NumBitsPerSubWord)); + END CASE; + + FOR i IN InputArrayLow TO InputArrayHigh LOOP + CurPropDelay := VitalCalcDelay (NewValue, + OldValue, DelayArrayNorm(DelayArrayIndex)); + + -- for debug purpose + debugprop(i) := CurPropDelay; + debugretain(i) := TIME'HIGH; + + IF (ArcType = CrossArc) THEN + DelayArrayIndex := DelayArrayIndex + OutputLength; + END IF; + + -- If there is one input change at a time, then choose the + -- delay from that input. If there is simultaneous input + -- change, then choose the minimum of propagation delays + + IF (InputChangeTimeNorm(i) < 0 ns) THEN + CurInputAge := TIME'HIGH; + ELSE + CurInputAge := NOW - InputChangeTimeNorm(i); + END IF; + + IF (CurInputAge < InputAge) THEN + PropDelay := CurPropDelay; + InputAge := CurInputAge; + ELSIF (CurInputAge = InputAge) THEN + IF (CurPropDelay < PropDelay) THEN + PropDelay := CurPropDelay; + END IF; + END IF; + END LOOP; + + -- Store it back to data strucutre + ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay; + ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge; + + -- for debug purpose + PrintDelay(outbitPos, InputArrayLow, InputArrayHigh, + debugprop, debugretain); + END LOOP; + + ScheduleDataArray := ScheduleDataArrayNorm; + +END VitalMemorySelectDelay; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryInitPathDelay +-- Description: To initialize Schedule Data structure for an +-- output. +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryInitPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR; + CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword +) IS +BEGIN + -- Initialize the ScheduleData Structure. + FOR i IN OutputDataArray'RANGE LOOP + ScheduleDataArray(i).OutputData := OutputDataArray(i); + ScheduleDataArray(i).PropDelay := TIME'HIGH; + ScheduleDataArray(i).OutputRetainDelay := TIME'HIGH; + ScheduleDataArray(i).InputAge := TIME'HIGH; + ScheduleDataArray(i).NumBitsPerSubWord := NumBitsPerSubWord; + + -- Update LastOutputValue of Output if the Output has + -- already been scheduled. + IF ((ScheduleDataArray(i).ScheduleValue /= OutputDataArray(i)) AND + (ScheduleDataArray(i).ScheduleTime <= NOW)) THEN + ScheduleDataArray(i).LastOutputValue + := ScheduleDataArray(i).ScheduleValue; + END IF; + END LOOP; + + -- for debug purpose + DebugMsg1; + PrintScheduleDataArray(ScheduleDataArray); + +END VitalMemoryInitPathDelay; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryInitPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + VARIABLE OutputData : IN STD_ULOGIC +) IS + VARIABLE ScheduledataArray: VitalMemoryScheduleDataVectorType + (0 downto 0); + VARIABLE OutputDataArray : STD_LOGIC_VECTOR(0 downto 0); +BEGIN + ScheduledataArray(0) := ScheduleData; + OutputDataArray(0) := OutputData; + VitalMemoryInitPathDelay ( + ScheduleDataArray => ScheduleDataArray, + OutputDataArray => OutputDataArray, + NumBitsPerSubWord => DefaultNumBitsPerSubword + ); + + -- for debug purpose + DebugMsg1; + PrintScheduleDataArray( ScheduleDataArray); + +END VitalMemoryInitPathDelay; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryAddPathDelay +-- Description: Declare a path for one scalar/vector input to +-- the output for which Schedule Data has been +-- initialized previously. +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- #1 +-- DelayType - VitalMemoryDelayType +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelay : IN VitalDelayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathDelayArray : VitalDelayArrayType(0 downto 0); + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + PathDelayArray(0) := PathDelay; + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #2 +-- DelayType - VitalMemoryDelayType +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray + ); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #3 +-- DelayType - VitalMemoryDelayType +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR Mem400 + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #4 +-- DelayType - VitalMemoryDelayType +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + + ScheduleDataArray(0) := ScheduleData; + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #5 +-- DelayType - VitalMemoryDelayType +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #6 +-- DelayType - VitalMemoryDelayType +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT +) IS + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400; + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #7 +-- DelayType - VitalMemoryDelayType01 +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelay : IN VitalDelayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathDelayArray : VitalDelayArrayType01(0 downto 0); + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + PathDelayArray(0) := PathDelay; + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #8 +-- DelayType - VitalMemoryDelayType01 +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #9 +-- DelayType - VitalMemoryDelayType01 +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400; + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #10 +-- DelayType - VitalMemoryDelayType01 +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray: INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +)IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #11 +-- DelayType - VitalMemoryDelayType01 +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +) IS + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #12 +-- DelayType - VitalMemoryDelayType01 +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT +) IS + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400; + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #13 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelay : IN VitalDelayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathDelayArray : VitalDelayArrayType01Z(0 downto 0); + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + PathDelayArray(0) := PathDelay; + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #14 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); + +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #15 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0); + VARIABLE PathConditionArrayExp : VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #16 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + NumBitsPerSubword := ScheduleDataArray(0).NumBitsPerSubword; + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, + InputSignal, + NumBitsPerSubword + ); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #17 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword; + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, + InputSignal, + NumBitsPerSubword + ); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #18 +-- DelayType - VitalMemoryDelayType01Z +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS +VARIABLE NumBitsPerSubword : INTEGER; +VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0); +VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, InputSignal, + NumBitsPerSubword); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #19 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelay : IN VitalDelayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE PathDelayArray : VitalDelayArrayType01ZX(0 downto 0); + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + PathDelayArray(0) := PathDelay; + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #20 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #21 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTime : INOUT TIME; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +) IS + VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400; + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal); + InputChangeTimeArray(0) := InputChangeTime; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #22 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS + VARIABLE ScheduleDataArray : + VitalMemoryScheduleDataVectorType(0 downto 0); + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0); +BEGIN + PathConditionArray(0) := PathCondition; + ScheduleDataArray(0) := ScheduleData; + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword; + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, InputSignal, + NumBitsPerSubword); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #23 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArray : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + FOR i IN PathConditionArray'RANGE LOOP + PathConditionArray(i) := PathCondition; + END LOOP; + + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword; + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, InputSignal, + NumBitsPerSubword); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArray, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- #24 +-- DelayType - VitalMemoryDelayType01XZ +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +) IS + VARIABLE NumBitsPerSubword : INTEGER; + VARIABLE PathConditionArrayNorm : + VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400; + VARIABLE PathConditionArrayExp : + VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0); +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword; + FOR i IN PathConditionArrayExp'RANGE LOOP + PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword); + END LOOP; + + IF (OutputRetainBehavior = WordCorrupt AND + ArcType = ParallelArc AND + OutputRetainFlag = TRUE) THEN + VitalMemoryUpdateInputChangeTime( + InputChangeTimeArray, InputSignal, + NumBitsPerSubword); + ELSE + VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal); + END IF; + + VitalMemorySelectDelay( + ScheduleDataArray, InputChangeTimeArray, + OutputSignalName, PathDelayArray, + ArcType, PathConditionArrayExp, OutputRetainFlag); +END VitalMemoryAddPathDelay; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemorySchedulePathDelay +-- Description: Schedule Output after Propagation Delay selected +-- by checking all the paths added thru' +-- VitalMemoryAddPathDelay. +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag; + CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap; + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType +) IS + VARIABLE Age : TIME; + VARIABLE PropDelay : TIME; + VARIABLE RetainDelay : TIME; + VARIABLE Data : STD_ULOGIC; +BEGIN + IF (PortFlag.OutputDisable /= TRUE) THEN + FOR i IN ScheduleDataArray'RANGE LOOP + PropDelay := ScheduleDataArray(i).PropDelay; + RetainDelay := ScheduleDataArray(i).OutputRetainDelay; + + NEXT WHEN PropDelay = TIME'HIGH; + + Age := ScheduleDataArray(i).InputAge; + Data := ScheduleDataArray(i).OutputData; + + IF (Age < RetainDelay and RetainDelay < PropDelay) THEN + OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age); + END IF; + + IF (Age <= PropDelay) THEN + OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age); + ScheduleDataArray(i).ScheduleValue := Data; + ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age; + END IF; + END LOOP; + END IF; + + -- for debug purpose + PrintScheduleDataArray(ScheduleDataArray); + + -- for debug purpose + ScheduleDebugMsg; +END VitalMemorySchedulePathDelay; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemorySchedulePathDelay +-- Description: Schedule Output after Propagation Delay selected +-- by checking all the paths added thru' +-- VitalMemoryAddPathDelay. +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING :=""; + CONSTANT PortFlag : IN VitalPortFlagVectorType; + CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap; + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType +) IS + VARIABLE Age : TIME; + VARIABLE PropDelay : TIME; + VARIABLE RetainDelay : TIME; + VARIABLE Data : STD_ULOGIC; + VARIABLE ExpandedPortFlag : + VitalPortFlagVectorType(ScheduleDataArray'RANGE); + VARIABLE NumBitsPerSubword : INTEGER; +BEGIN + NumBitsPerSubword := + ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword; + VitalMemoryExpandPortFlag( PortFlag, NumBitsPerSubword, ExpandedPortFlag ); + FOR i IN ScheduleDataArray'RANGE LOOP + NEXT WHEN ExpandedPortFlag(i).OutputDisable = TRUE; + + PropDelay := ScheduleDataArray(i).PropDelay; + RetainDelay := ScheduleDataArray(i).OutputRetainDelay; + + NEXT WHEN PropDelay = TIME'HIGH; + + Age := ScheduleDataArray(i).InputAge; + Data := ScheduleDataArray(i).OutputData; + + IF (Age < RetainDelay and RetainDelay < PropDelay) THEN + OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age); + END IF; + + IF (Age <= PropDelay) THEN + OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age); + ScheduleDataArray(i).ScheduleValue := Data; + ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age; + END IF; + END LOOP; + + -- for debug purpose + PrintScheduleDataArray(ScheduleDataArray); + + -- for debug purpose + ScheduleDebugMsg; +END VitalMemorySchedulePathDelay; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT STD_ULOGIC; + CONSTANT OutputSignalName: IN STRING :=""; + CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType +) IS + VARIABLE Age : TIME; + VARIABLE PropDelay : TIME; + VARIABLE RetainDelay : TIME; + VARIABLE Data : STD_ULOGIC; + VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType (0 downto 0); +BEGIN + IF (PortFlag.OutputDisable /= TRUE) THEN + ScheduledataArray(0) := ScheduleData; + PropDelay := ScheduleDataArray(0).PropDelay; + RetainDelay := ScheduleDataArray(0).OutputRetainDelay; + Age := ScheduleDataArray(0).InputAge; + Data := ScheduleDataArray(0).OutputData; + + IF (Age < RetainDelay and RetainDelay < PropDelay) THEN + OutSignal <= TRANSPORT 'X' AFTER (RetainDelay - Age); + END IF; + + IF (Age <= PropDelay and PropDelay /= TIME'HIGH) THEN + OutSignal <= TRANSPORT OutputMap(Data) AFTER (PropDelay - Age); + ScheduleDataArray(0).ScheduleValue := Data; + ScheduleDataArray(0).ScheduleTime := NOW + PropDelay - Age; + END IF; + END IF; + + -- for debug purpose + PrintScheduleDataArray(ScheduleDataArray); + + -- for debug purpose + ScheduleDebugMsg; + +END VitalMemorySchedulePathDelay; + +-- ---------------------------------------------------------------------------- +-- Procedure : InternalTimingCheck +-- ---------------------------------------------------------------------------- +PROCEDURE InternalTimingCheck ( + CONSTANT TestSignal : IN std_ulogic; + CONSTANT RefSignal : IN std_ulogic; + CONSTANT TestDelay : IN TIME := 0 ns; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + VARIABLE RefTime : IN TIME; + VARIABLE RefEdge : IN BOOLEAN; + VARIABLE TestTime : IN TIME; + VARIABLE TestEvent : IN BOOLEAN; + VARIABLE SetupEn : INOUT BOOLEAN; + VARIABLE HoldEn : INOUT BOOLEAN; + VARIABLE CheckInfo : INOUT CheckInfoType; + CONSTANT MsgOn : IN BOOLEAN +) IS + VARIABLE bias : TIME; + VARIABLE actualObsTime : TIME; + VARIABLE BC : TIME; + VARIABLE Message :LINE; +BEGIN + -- Check SETUP constraint + IF (RefEdge) THEN + IF (SetupEn) THEN + CheckInfo.ObsTime := RefTime - TestTime; + CheckInfo.State := To_X01(TestSignal); + CASE CheckInfo.State IS + WHEN '0' => + CheckInfo.ExpTime := SetupLow; + -- start of new code IR245-246 + BC := HoldHigh; + -- end of new code IR245-246 + WHEN '1' => + CheckInfo.ExpTime := SetupHigh; + -- start of new code IR245-246 + BC := HoldLow; + -- end of new code IR245-246 + WHEN 'X' => + CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow); + -- start of new code IR245-246 + BC := Maximum(HoldHigh,HoldLow); + -- end of new code IR245-246 + END CASE; + -- added the second condition for IR 245-246 + CheckInfo.Violation := + ((CheckInfo.ObsTime < CheckInfo.ExpTime) + AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns)))); + -- start of new code IR245-246 + IF (CheckInfo.ExpTime = 0 ns) THEN + CheckInfo.CheckKind := HoldCheck; + ELSE + CheckInfo.CheckKind := SetupCheck; + END IF; + -- end of new code IR245-246 + SetupEn := FALSE; + ELSE + CheckInfo.Violation := FALSE; + END IF; + + -- Check HOLD constraint + ELSIF (TestEvent) THEN + IF HoldEn THEN + CheckInfo.ObsTime := TestTime - RefTime; + CheckInfo.State := To_X01(TestSignal); + CASE CheckInfo.State IS + WHEN '0' => + CheckInfo.ExpTime := HoldHigh; + -- new code for unnamed IR + CheckInfo.State := '1'; + -- start of new code IR245-246 + BC := SetupLow; + -- end of new code IR245-246 + WHEN '1' => + CheckInfo.ExpTime := HoldLow; + -- new code for unnamed IR + CheckInfo.State := '0'; + -- start of new code IR245-246 + BC := SetupHigh; + -- end of new code IR245-246 + WHEN 'X' => + CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow); + -- start of new code IR245-246 + BC := Maximum(SetupHigh,SetupLow); + -- end of new code IR245-246 + END CASE; + -- added the second condition for IR 245-246 + CheckInfo.Violation := + ((CheckInfo.ObsTime < CheckInfo.ExpTime) + AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns)))); + -- start of new code IR245-246 + IF (CheckInfo.ExpTime = 0 ns) THEN + CheckInfo.CheckKind := SetupCheck; + ELSE + CheckInfo.CheckKind := HoldCheck; + END IF; + -- end of new code IR245-246 + HoldEn := NOT CheckInfo.Violation; + ELSE + CheckInfo.Violation := FALSE; + END IF; + ELSE + CheckInfo.Violation := FALSE; + END IF; + + -- Adjust report values to account for internal model delays + -- Note: TestDelay, RefDelay, TestTime, RefTime are non-negative + -- Note: bias may be negative or positive + IF MsgOn AND CheckInfo.Violation THEN + -- modified the code for correct reporting of violation in case of + -- order of signals being reversed because of internal delays + -- new variable + actualObsTime := (TestTime-TestDelay)-(RefTime-RefDelay); + bias := TestDelay - RefDelay; + IF (actualObsTime < 0 ns) THEN -- It should be a setup check + IF ( CheckInfo.CheckKind = HoldCheck) THEN + CheckInfo.CheckKind := SetupCheck; + CASE CheckInfo.State IS + WHEN '0' => CheckInfo.ExpTime := SetupLow; + WHEN '1' => CheckInfo.ExpTime := SetupHigh; + WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow); + END CASE; + END IF; + CheckInfo.ObsTime := -actualObsTime; + CheckInfo.ExpTime := CheckInfo.ExpTime + bias; + CheckInfo.DetTime := RefTime - RefDelay; + ELSE -- It should be a hold check + IF (CheckInfo.CheckKind = SetupCheck) THEN + CheckInfo.CheckKind := HoldCheck; + CASE CheckInfo.State IS + WHEN '0' => + CheckInfo.ExpTime := HoldHigh; + CheckInfo.State := '1'; + WHEN '1' => + CheckInfo.ExpTime := HoldLow; + CheckInfo.State := '0'; + WHEN 'X' => + CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow); + END CASE; + END IF; + CheckInfo.ObsTime := actualObsTime; + CheckInfo.ExpTime := CheckInfo.ExpTime - bias; + CheckInfo.DetTime := TestTime - TestDelay; + END IF; + END IF; +END InternalTimingCheck; + + +-- ---------------------------------------------------------------------------- +-- Setup and Hold Time Check Routine +-- ---------------------------------------------------------------------------- +PROCEDURE TimingArrayIndex ( + SIGNAL InputSignal : IN Std_logic_vector; + CONSTANT ArrayIndexNorm : IN INTEGER; + VARIABLE Index : OUT INTEGER +) IS +BEGIN + IF (InputSignal'LEFT > InputSignal'RIGHT) THEN + Index := ArrayIndexNorm + InputSignal'RIGHT; + ELSE + Index := InputSignal'RIGHT - ArrayIndexNorm; + END IF; +END TimingArrayIndex; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryReportViolation ( + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT CheckInfo : IN CheckInfoType; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + VARIABLE Message : LINE; +BEGIN + IF (NOT CheckInfo.Violation) THEN + RETURN; + END IF; + Write ( Message, HeaderMsg ); + CASE CheckInfo.CheckKind IS + WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") ); + WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") ); + WHEN RecoveryCheck => Write ( Message, STRING'(" RECOVERY ") ); + WHEN RemovalCheck => Write ( Message, STRING'(" REMOVAL ") ); + WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH ")); + WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") ); + END CASE; + Write ( Message, HiLoStr(CheckInfo.State) ); + Write ( Message, STRING'(" VIOLATION ON ") ); + Write ( Message, TestSignalName ); + IF (RefSignalName'LENGTH > 0) THEN + Write ( Message, STRING'(" WITH RESPECT TO ") ); + Write ( Message, RefSignalName ); + END IF; + Write ( Message, ';' & LF ); + Write ( Message, STRING'(" Expected := ") ); + Write ( Message, CheckInfo.ExpTime); + Write ( Message, STRING'("; Observed := ") ); + Write ( Message, CheckInfo.ObsTime); + Write ( Message, STRING'("; At : ") ); + Write ( Message, CheckInfo.DetTime); + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + DEALLOCATE (Message); +END VitalMemoryReportViolation; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryReportViolation ( + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT TestArrayIndex : IN INTEGER; + CONSTANT RefArrayIndex : IN INTEGER; + SIGNAL TestSignal : IN std_logic_vector; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT CheckInfo : IN CheckInfoType; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + VARIABLE Message : LINE; + VARIABLE i, j : INTEGER; +BEGIN + IF (NOT CheckInfo.Violation) THEN + RETURN; + END IF; + + Write ( Message, HeaderMsg ); + CASE CheckInfo.CheckKind IS + WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") ); + WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") ); + WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH ")); + WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") ); + WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") ); + END CASE; + Write ( Message, HiLoStr(CheckInfo.State) ); + Write ( Message, STRING'(" VIOLATION ON ") ); + Write ( Message, TestSignalName ); + TimingArrayIndex(TestSignal, TestArrayIndex, i); + CASE MsgFormat IS + WHEN Scalar => + NULL; + WHEN VectorEnum => + Write ( Message, '_'); + Write ( Message, i); + WHEN Vector => + Write ( Message, '('); + Write ( Message, i); + Write ( Message, ')'); + END CASE; + + IF (RefSignalName'LENGTH > 0) THEN + Write ( Message, STRING'(" WITH RESPECT TO ") ); + Write ( Message, RefSignalName ); + END IF; + + IF(RefSignal'LENGTH > 0) THEN + TimingArrayIndex(RefSignal, RefArrayIndex, j); + CASE MsgFormat IS + WHEN Scalar => + NULL; + WHEN VectorEnum => + Write ( Message, '_'); + Write ( Message, j); + WHEN Vector => + Write ( Message, '('); + Write ( Message, j); + Write ( Message, ')'); + END CASE; + END IF; + + Write ( Message, ';' & LF ); + Write ( Message, STRING'(" Expected := ") ); + Write ( Message, CheckInfo.ExpTime); + Write ( Message, STRING'("; Observed := ") ); + Write ( Message, CheckInfo.ObsTime); + Write ( Message, STRING'("; At : ") ); + Write ( Message, CheckInfo.DetTime); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); +END VitalMemoryReportViolation; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryReportViolation ( + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT TestArrayIndex : IN INTEGER; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT CheckInfo : IN CheckInfoType; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + VARIABLE Message : LINE; +BEGIN + IF (NOT CheckInfo.Violation) THEN + RETURN; + END IF; + + Write ( Message, HeaderMsg ); + CASE CheckInfo.CheckKind IS + WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") ); + WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") ); + WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH ")); + WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") ); + WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") ); + END CASE; + + Write ( Message, HiLoStr(CheckInfo.State) ); + Write ( Message, STRING'(" VIOLATION ON ") ); + Write ( Message, TestSignalName ); + + CASE MsgFormat IS + WHEN Scalar => + NULL; + WHEN VectorEnum => + Write ( Message, '_'); + Write ( Message, TestArrayIndex); + WHEN Vector => + Write ( Message, '('); + Write ( Message, TestArrayIndex); + Write ( Message, ')'); + END CASE; + + IF (RefSignalName'LENGTH > 0) THEN + Write ( Message, STRING'(" WITH RESPECT TO ") ); + Write ( Message, RefSignalName ); + END IF; + + Write ( Message, ';' & LF ); + Write ( Message, STRING'(" Expected := ") ); + Write ( Message, CheckInfo.ExpTime); + Write ( Message, STRING'("; Observed := ") ); + Write ( Message, CheckInfo.ObsTime); + Write ( Message, STRING'("; At : ") ); + Write ( Message, CheckInfo.DetTime); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); +END VitalMemoryReportViolation; + +-- ---------------------------------------------------------------------------- +FUNCTION VitalMemoryTimingDataInit +RETURN VitalMemoryTimingDataType IS +BEGIN + RETURN (FALSE, 'X', 0 ns, FALSE, 'X', 0 ns, FALSE, + NULL, NULL, NULL, NULL, NULL, NULL); +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalSetupHoldCheck +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayType; + CONSTANT SetupLow : IN VitalDelayType; + CONSTANT HoldHigh : IN VitalDelayType; + CONSTANT HoldLow : IN VitalDelayType; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE CheckEnScalar : BOOLEAN := FALSE; + VARIABLE ViolationInt : X01ArrayT(CheckEnabled'RANGE); + VARIABLE RefEdge : BOOLEAN; + VARIABLE TestEvent : BOOLEAN; + VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay); + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLast := To_X01(TestSignal); + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF (RefEdge) THEN + TimingData.RefTime := NOW; + --TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE); + --IR252 3/23/98 + TimingData.SetupEn := TimingData.SetupEn AND EnableSetupOnRef; + TimingData.HoldEn := EnableHoldOnRef; + END IF; + + -- Detect test (data) changes and record the time of the last change + TestEvent := TimingData.TestLast /= To_X01Z(TestSignal); + TimingData.TestLast := To_X01Z(TestSignal); + IF TestEvent THEN + TimingData.SetupEn := EnableSetupOnTest ; --IR252 3/23/98 + TimingData.HoldEn := TimingData.HoldEn AND EnableHoldOnTest ; + --IR252 3/23/98 + TimingData.TestTime := NOW; + END IF; + + FOR i IN CheckEnabled'RANGE LOOP + IF CheckEnabled(i) = TRUE THEN + CheckEnScalar := TRUE; + END IF; + ViolationInt(i) := '0'; + END LOOP; + + IF (CheckEnScalar) THEN + InternalTimingCheck ( + TestSignal => TestSignal, + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh, + SetupLow => SetupLow, + HoldHigh => HoldHigh, + HoldLow => HoldLow, + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTime, + TestEvent => TestEvent, + SetupEn => TimingData.SetupEn, + HoldEn => TimingData.HoldEn, + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, + HeaderMsg, CheckInfo, MsgSeverity ); + END IF; + IF (XOn) THEN + FOR i IN CheckEnabled'RANGE LOOP + IF CheckEnabled(i) = TRUE THEN + ViolationInt(i) := 'X'; + END IF; + END LOOP; + END IF; + END IF; + END IF; + Violation := ViolationInt; +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : BOOLEAN; + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE); + TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE); + TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + FOR i IN TestSignal'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignal(i)); + END LOOP; + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF (RefEdge) THEN + TimingData.RefTime := NOW; + --TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE); + --IR252 3/23/98 + FOR i IN TestSignal'RANGE LOOP + TimingData.SetupEnA(i) + := TimingData.SetupEnA(i) AND EnableSetupOnRef; + TimingData.HoldEnA(i) := EnableHoldOnRef; + END LOOP; + END IF; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignal'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignal(i)); + IF TestEvent(i) THEN + TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98 + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ; + --IR252 3/23/98 + TimingData.TestTimeA(i) := NOW; + --TimingData.SetupEnA(i) := TRUE; + TimingData.TestTime := NOW; + END IF; + END LOOP; + + FOR i IN TestSignal'RANGE LOOP + Violation(i) := '0'; + + IF (CheckEnabled) THEN + TestDly := Maximum(0 ns, TestDelay(i)); + InternalTimingCheck ( + TestSignal => TestSignal(i), + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh(i), + SetupLow => SetupLow(i), + HoldHigh => HoldHigh(i), + HoldLow => HoldLow(i), + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(i), + HoldEn => TimingData.HoldEnA(i), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i , + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; + IF (XOn) THEN + Violation(i) := 'X'; + END IF; + END IF; + END IF; + END LOOP; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE ViolationInt : X01ArrayT(TestSignal'RANGE); + VARIABLE ViolationIntNorm: X01ArrayT(TestSignal'LENGTH-1 downto 0); + VARIABLE ViolationNorm : X01ArrayT(Violation'LENGTH-1 downto 0); + VARIABLE CheckEnInt : VitalBoolArrayT(TestSignal'RANGE); + VARIABLE CheckEnIntNorm : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0); + VARIABLE CheckEnScalar : BOOLEAN := FALSE; --Mem IR 401 + VARIABLE CheckEnabledNorm: VitalBoolArrayT(CheckEnabled'LENGTH-1 downto 0); + VARIABLE RefEdge : BOOLEAN; + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE); + TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE); + TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + FOR i IN TestSignal'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignal(i)); + END LOOP; + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF RefEdge THEN + TimingData.RefTime := NOW; + --TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE); + --IR252 3/23/98 + FOR i IN TestSignal'RANGE LOOP + TimingData.SetupEnA(i) + := TimingData.SetupEnA(i) AND EnableSetupOnRef; + TimingData.HoldEnA(i) := EnableHoldOnRef; + END LOOP; + END IF; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignal'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignal(i)); + IF TestEvent(i) THEN + TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98 + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ; + --IR252 3/23/98 + TimingData.TestTimeA(i) := NOW; + --TimingData.SetupEnA(i) := TRUE; + TimingData.TestTime := NOW; + END IF; + END LOOP; + + IF ArcType = CrossArc THEN + CheckEnScalar := FALSE; + FOR i IN CheckEnabled'RANGE LOOP + IF CheckEnabled(i) = TRUE THEN + CheckEnScalar := TRUE; + END IF; + END LOOP; + FOR i IN CheckEnInt'RANGE LOOP + CheckEnInt(i) := CheckEnScalar; + END LOOP; + ELSE + FOR i IN CheckEnIntNorm'RANGE LOOP + CheckEnIntNorm(i) := CheckEnabledNorm(i / NumBitsPerSubWord ); + END LOOP; + CheckEnInt := CheckEnIntNorm; + END IF; + + FOR i IN TestSignal'RANGE LOOP + ViolationInt(i) := '0'; + + IF (CheckEnInt(i)) THEN + TestDly := Maximum(0 ns, TestDelay(i)); + InternalTimingCheck ( + TestSignal => TestSignal(i), + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh(i), + SetupLow => SetupLow(i), + HoldHigh => HoldHigh(i), + HoldLow => HoldLow(i), + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(i), + HoldEn => TimingData.HoldEnA(i), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i , + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; + IF (XOn) THEN + ViolationInt(i) := 'X'; + END IF; + END IF; + END IF; + END LOOP; + + IF (ViolationInt'LENGTH = Violation'LENGTH) THEN + Violation := ViolationInt; + ELSE + ViolationIntNorm := ViolationInt; + FOR i IN ViolationNorm'RANGE LOOP + ViolationNorm(i) := '0'; + END LOOP; + FOR i IN ViolationIntNorm'RANGE LOOP + IF (ViolationIntNorm(i) = 'X') THEN + ViolationNorm(i / NumBitsPerSubWord) := 'X'; + END IF; + END LOOP; + Violation := ViolationNorm; + END IF; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArraytype; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0); + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME; + VARIABLE bias : TIME; + VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH; + VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH; + VARIABLE NumChecks : NATURAL; + + VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0); + VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0); + + VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0) + := TestSignal; + VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0) + := TestDelay; + VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0) + := RefSignal; + VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0) + := RefDelay; + VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0) + := SetupHigh; + VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0) + := SetupLow; + VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0) + := HoldHigh; + VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0) + := HoldLow; + + VARIABLE RefBitLow : NATURAL; + VARIABLE RefBitHigh : NATURAL; + VARIABLE EnArrayIndex : NATURAL; + VARIABLE TimingArrayIndex: NATURAL; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0); + TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0); + TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0); + TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0); + IF (ArcType = CrossArc) THEN + NumChecks := RefSignal'LENGTH * TestSignal'LENGTH; + ELSE + NumChecks := TestSignal'LENGTH; + END IF; + TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + + FOR i IN TestSignalNorm'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignalNorm(i)); + END LOOP; + + FOR i IN RefSignalNorm'RANGE LOOP + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + END LOOP; + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + FOR i IN RefSignalNorm'RANGE LOOP + RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i), + To_X01(RefSignalNorm(i)), RefTransition); + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + IF (RefEdge(i)) THEN + TimingData.RefTimeA(i) := NOW; + END IF; + END LOOP; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignalNorm'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i)); + IF (TestEvent(i)) THEN + TimingData.TestTimeA(i) := NOW; + END IF; + END LOOP; + + FOR i IN ViolationTest'RANGE LOOP + ViolationTest(i) := '0'; + END LOOP; + FOR i IN ViolationRef'RANGE LOOP + ViolationRef(i) := '0'; + END LOOP; + + FOR i IN TestSignalNorm'RANGE LOOP + IF (ArcType = CrossArc) THEN + FOR j IN RefSignalNorm'RANGE LOOP + IF (TestEvent(i)) THEN + --TimingData.SetupEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest; + TimingData.HoldEnA(i*NumRefBits+j) + := TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest; + END IF; + IF (RefEdge(j)) THEN + --TimingData.HoldEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef; + TimingData.SetupEnA(i*NumRefBits+j) + := TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef; + END IF; + END LOOP; + RefBitLow := 0; + RefBitHigh := NumRefBits-1; + TimingArrayIndex := i; + ELSE + IF ArcType = SubwordArc THEN + RefBitLow := i / NumBitsPerSubWord; + TimingArrayIndex := i + NumTestBits * RefBitLow; + ELSE + RefBitLow := i; + TimingArrayIndex := i; + END IF; + RefBitHigh := RefBitLow; + IF TestEvent(i) THEN + --TimingData.SetupEnA(i) := TRUE; + --IR252 + TimingData.SetupEnA(i) := EnableSetupOnTest; + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest; + END IF; + IF RefEdge(RefBitLow) THEN + --TimingData.HoldEnA(i) := TRUE; + --IR252 + TimingData.HoldEnA(i) := EnableHoldOnRef; + TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef; + END IF; + END IF; + + EnArrayIndex := i; + FOR j IN RefBitLow to RefBitHigh LOOP + + IF (CheckEnabled) THEN + TestDly := Maximum(0 ns, TestDelayNorm(i)); + RefDly := Maximum(0 ns, RefDelayNorm(j)); + + InternalTimingCheck ( + TestSignal => TestSignalNorm(i), + RefSignal => RefSignalNorm(j), + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHighNorm(TimingArrayIndex), + SetupLow => SetupLowNorm(TimingArrayIndex), + HoldHigh => HoldHighNorm(TimingArrayIndex), + HoldLow => HoldLowNorm(TimingArrayIndex), + RefTime => TimingData.RefTimeA(j), + RefEdge => RefEdge(j), + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(EnArrayIndex), + HoldEn => TimingData.HoldEnA(EnArrayIndex), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF (CheckInfo.Violation) THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j, + TestSignal, RefSignal, HeaderMsg, CheckInfo, + MsgFormat, MsgSeverity ); + END IF; + IF (XOn) THEN + ViolationTest(i) := 'X'; + ViolationRef(j) := 'X'; + END IF; + END IF; + END IF; + + TimingArrayIndex := TimingArrayIndex + NumRefBits; + EnArrayIndex := EnArrayIndex + NumRefBits; + + END LOOP; + END LOOP; + + IF (ArcType = CrossArc) THEN + Violation := ViolationRef; + ELSE + IF (Violation'LENGTH = ViolationRef'LENGTH) THEN + Violation := ViolationRef; + ELSE + Violation := ViolationTest; + END IF; + END IF; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArraytype; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0); + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME; + VARIABLE bias : TIME; + VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH; + VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH; + VARIABLE NumChecks : NATURAL; + + VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0); + VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0); + + VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0) + := TestSignal; + VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0) + := TestDelay; + VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0) + := RefSignal; + VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0) + := RefDelay; + VARIABLE CheckEnNorm : VitalBoolArrayT(NumRefBits-1 downto 0) + := CheckEnabled; + VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0) + := SetupHigh; + VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0) + := SetupLow; + VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0) + := HoldHigh; + VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0) + := HoldLow; + + VARIABLE RefBitLow : NATURAL; + VARIABLE RefBitHigh : NATURAL; + VARIABLE EnArrayIndex : NATURAL; + VARIABLE TimingArrayIndex: NATURAL; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0); + TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0); + TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0); + TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0); + IF ArcType = CrossArc THEN + NumChecks := RefSignal'LENGTH * TestSignal'LENGTH; + ELSE + NumChecks := TestSignal'LENGTH; + END IF; + TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + + FOR i IN TestSignalNorm'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignalNorm(i)); + END LOOP; + + FOR i IN RefSignalNorm'RANGE LOOP + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + END LOOP; + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + FOR i IN RefSignalNorm'RANGE LOOP + RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i), + To_X01(RefSignalNorm(i)), RefTransition); + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + IF RefEdge(i) THEN + TimingData.RefTimeA(i) := NOW; + END IF; + END LOOP; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignalNorm'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i)); + IF TestEvent(i) THEN + TimingData.TestTimeA(i) := NOW; + END IF; + END LOOP; + + FOR i IN ViolationTest'RANGE LOOP + ViolationTest(i) := '0'; + END LOOP; + FOR i IN ViolationRef'RANGE LOOP + ViolationRef(i) := '0'; + END LOOP; + + FOR i IN TestSignalNorm'RANGE LOOP + IF (ArcType = CrossArc) THEN + FOR j IN RefSignalNorm'RANGE LOOP + IF (TestEvent(i)) THEN + --TimingData.SetupEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest; + TimingData.HoldEnA(i*NumRefBits+j) + := TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest; + END IF; + IF (RefEdge(j)) THEN + --TimingData.HoldEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef; + TimingData.SetupEnA(i*NumRefBits+j) + := TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef; + END IF; + END LOOP; + RefBitLow := 0; + RefBitHigh := NumRefBits-1; + TimingArrayIndex := i; + ELSE + IF (ArcType = SubwordArc) THEN + RefBitLow := i / NumBitsPerSubWord; + TimingArrayIndex := i + NumTestBits * RefBitLow; + ELSE + RefBitLow := i; + TimingArrayIndex := i; + END IF; + RefBitHigh := RefBitLow; + IF (TestEvent(i)) THEN + --TimingData.SetupEnA(i) := TRUE; + --IR252 + TimingData.SetupEnA(i) := EnableSetupOnTest; + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest; + END IF; + IF (RefEdge(RefBitLow)) THEN + --TimingData.HoldEnA(i) := TRUE; + --IR252 + TimingData.HoldEnA(i) := EnableHoldOnRef; + TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef; + END IF; + END IF; + + EnArrayIndex := i; + FOR j IN RefBitLow to RefBitHigh LOOP + IF (CheckEnNorm(j)) THEN + TestDly := Maximum(0 ns, TestDelayNorm(i)); + RefDly := Maximum(0 ns, RefDelayNorm(j)); + + InternalTimingCheck ( + TestSignal => TestSignalNorm(i), + RefSignal => RefSignalNorm(j), + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHighNorm(TimingArrayIndex), + SetupLow => SetupLowNorm(TimingArrayIndex), + HoldHigh => HoldHighNorm(TimingArrayIndex), + HoldLow => HoldLowNorm(TimingArrayIndex), + RefTime => TimingData.RefTimeA(j), + RefEdge => RefEdge(j), + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(EnArrayIndex), + HoldEn => TimingData.HoldEnA(EnArrayIndex), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF (CheckInfo.Violation) THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j, + TestSignal, RefSignal, HeaderMsg, CheckInfo, + MsgFormat, MsgSeverity ); + END IF; + + IF (XOn) THEN + ViolationTest(i) := 'X'; + ViolationRef(j) := 'X'; + END IF; + END IF; + END IF; + + TimingArrayIndex := TimingArrayIndex + NumRefBits; + EnArrayIndex := EnArrayIndex + NumRefBits; + END LOOP; + END LOOP; + + IF (ArcType = CrossArc) THEN + Violation := ViolationRef; + ELSE + IF (Violation'LENGTH = ViolationRef'LENGTH) THEN + Violation := ViolationRef; + ELSE + Violation := ViolationTest; + END IF; + END IF; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +-- scalar violations not needed +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : BOOLEAN; + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; + +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE); + TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE); + TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + FOR i IN TestSignal'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignal(i)); + END LOOP; + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF (RefEdge) THEN + TimingData.RefTime := NOW; + --TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE); + --IR252 3/23/98 + FOR i IN TestSignal'RANGE LOOP + TimingData.SetupEnA(i) + := TimingData.SetupEnA(i) AND EnableSetupOnRef; + TimingData.HoldEnA(i) := EnableHoldOnRef; + END LOOP; + END IF; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignal'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignal(i)); + IF TestEvent(i) THEN + TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98 + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ; + --IR252 3/23/98 + TimingData.TestTimeA(i) := NOW; + --TimingData.SetupEnA(i) := TRUE; + TimingData.TestTime := NOW; + END IF; + END LOOP; + + Violation := '0'; + FOR i IN TestSignal'RANGE LOOP + IF (CheckEnabled) THEN + TestDly := Maximum(0 ns, TestDelay(i)); + InternalTimingCheck ( + TestSignal => TestSignal(i), + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh(i), + SetupLow => SetupLow(i), + HoldHigh => HoldHigh(i), + HoldLow => HoldLow(i), + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(i), + HoldEn => TimingData.HoldEnA(i), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i , + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; + IF (XOn) THEN + Violation := 'X'; + END IF; + END IF; + END IF; + END LOOP; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArraytype; + CONSTANT SetupHigh : IN VitalDelayArraytype; + CONSTANT SetupLow : IN VitalDelayArraytype; + CONSTANT HoldHigh : IN VitalDelayArraytype; + CONSTANT HoldLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + --IR252 3/23/98 + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0); + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0); + VARIABLE TestDly : TIME; + VARIABLE RefDly : TIME; + VARIABLE bias : TIME; + VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH; + VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH; + VARIABLE NumChecks : NATURAL; + + VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0) + := TestSignal; + VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0) + := TestDelay; + VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0) + := RefSignal; + VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0) + := RefDelay; + VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0) + := SetupHigh; + VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0) + := SetupLow; + VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0) + := HoldHigh; + VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0) + := HoldLow; + + VARIABLE RefBitLow : NATURAL; + VARIABLE RefBitHigh : NATURAL; + VARIABLE EnArrayIndex : NATURAL; + VARIABLE TimingArrayIndex: NATURAL; +BEGIN + + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0); + TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0); + TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0); + TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0); + IF (ArcType = CrossArc) THEN + NumChecks := RefSignal'LENGTH * TestSignal'LENGTH; + ELSE + NumChecks := TestSignal'LENGTH; + END IF; + TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0); + + FOR i IN TestSignalNorm'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignalNorm(i)); + END LOOP; + + FOR i IN RefSignalNorm'RANGE LOOP + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + END LOOP; + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + FOR i IN RefSignalNorm'RANGE LOOP + RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i), + To_X01(RefSignalNorm(i)), RefTransition); + TimingData.RefLastA(i) := To_X01(RefSignalNorm(i)); + IF (RefEdge(i)) THEN + TimingData.RefTimeA(i) := NOW; + END IF; + END LOOP; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignalNorm'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i)); + IF (TestEvent(i)) THEN + TimingData.TestTimeA(i) := NOW; + END IF; + END LOOP; + + FOR i IN TestSignalNorm'RANGE LOOP + IF (ArcType = CrossArc) THEN + FOR j IN RefSignalNorm'RANGE LOOP + IF (TestEvent(i)) THEN + --TimingData.SetupEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest; + TimingData.HoldEnA(i*NumRefBits+j) + := TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest; + END IF; + IF (RefEdge(j)) THEN + --TimingData.HoldEnA(i*NumRefBits+j) := TRUE; + --IR252 + TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef; + TimingData.SetupEnA(i*NumRefBits+j) + := TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef; + END IF; + END LOOP; + RefBitLow := 0; + RefBitHigh := NumRefBits-1; + TimingArrayIndex := i; + ELSE + IF (ArcType = SubwordArc) THEN + RefBitLow := i / NumBitsPerSubWord; + TimingArrayIndex := i + NumTestBits * RefBitLow; + ELSE + RefBitLow := i; + TimingArrayIndex := i; + END IF; + RefBitHigh := RefBitLow; + IF (TestEvent(i)) THEN + --TimingData.SetupEnA(i) := TRUE; + --IR252 + TimingData.SetupEnA(i) := EnableSetupOnTest; + TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest; + END IF; + IF (RefEdge(RefBitLow)) THEN + --TimingData.HoldEnA(i) := TRUE; + --IR252 + TimingData.HoldEnA(i) := EnableHoldOnRef; + TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef; + END IF; + END IF; + + EnArrayIndex := i; + Violation := '0'; + FOR j IN RefBitLow to RefBitHigh LOOP + + IF (CheckEnabled) THEN + TestDly := Maximum(0 ns, TestDelayNorm(i)); + RefDly := Maximum(0 ns, RefDelayNorm(j)); + + InternalTimingCheck ( + TestSignal => TestSignalNorm(i), + RefSignal => RefSignalNorm(j), + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHighNorm(TimingArrayIndex), + SetupLow => SetupLowNorm(TimingArrayIndex), + HoldHigh => HoldHighNorm(TimingArrayIndex), + HoldLow => HoldLowNorm(TimingArrayIndex), + RefTime => TimingData.RefTimeA(j), + RefEdge => RefEdge(j), + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(EnArrayIndex), + HoldEn => TimingData.HoldEnA(EnArrayIndex), + CheckInfo => CheckInfo, + MsgOn => MsgOn + ); + + -- Report any detected violations and set return violation flag + IF (CheckInfo.Violation) THEN + IF (MsgOn) THEN + VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j, + TestSignal, RefSignal, HeaderMsg, CheckInfo, + MsgFormat, MsgSeverity ); + END IF; + + IF (XOn) THEN + Violation := 'X'; + END IF; + END IF; + END IF; + + TimingArrayIndex := TimingArrayIndex + NumRefBits; + EnArrayIndex := EnArrayIndex + NumRefBits; + + END LOOP; + END LOOP; + +END VitalMemorySetupHoldCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryPeriodPulseCheck ( + VARIABLE Violation : OUT X01; + VARIABLE PeriodData : INOUT VitalPeriodDataArrayType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + CONSTANT Period : IN VitalDelayArraytype; + CONSTANT PulseWidthHigh : IN VitalDelayArraytype; + CONSTANT PulseWidthLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType +) IS + VARIABLE TestDly : VitalDelayType; + VARIABLE CheckInfo : CheckInfoType; + VARIABLE PeriodObs : VitalDelayType; + VARIABLE PulseTest : BOOLEAN; + VARIABLE PeriodTest: BOOLEAN; + VARIABLE TestValue : X01; +BEGIN + + -- Initialize for no violation + Violation := '0'; --MEM IR 402 + + FOR i IN TestSignal'RANGE LOOP + TestDly := Maximum(0 ns, TestDelay(i)); + TestValue := To_X01(TestSignal(i)); + + IF (PeriodData(i).NotFirstFlag = FALSE) THEN + PeriodData(i).Rise := -Maximum(Period(i), + Maximum(PulseWidthHigh(i),PulseWidthLow(i))); + PeriodData(i).Fall := -Maximum(Period(i), + Maximum(PulseWidthHigh(i),PulseWidthLow(i))); + PeriodData(i).Last := TestValue; + PeriodData(i).NotFirstFlag := TRUE; + END IF; + + -- Initialize for no violation + -- Violation := '0'; --Mem IR 402 + + -- No violation possible if no test signal change + NEXT WHEN (PeriodData(i).Last = TestValue); + + -- record starting pulse times + IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN + -- Compute period times, then record the High Rise Time + PeriodObs := NOW - PeriodData(i).Rise; + PeriodData(i).Rise := NOW; + PeriodTest := TRUE; + ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN + -- Compute period times, then record the Low Fall Time + PeriodObs := NOW - PeriodData(i).Fall; + PeriodData(i).Fall := NOW; + PeriodTest := TRUE; + ELSE + PeriodTest := FALSE; + END IF; + + -- do checks on pulse ends + IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData(i).Fall; + CheckInfo.ExpTime := PulseWidthLow(i); + PulseTest := TRUE; + ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData(i).Rise; + CheckInfo.ExpTime := PulseWidthHigh(i); + PulseTest := TRUE; + ELSE + PulseTest := FALSE; + END IF; + + IF (PulseTest AND CheckEnabled) THEN + -- Verify Pulse Width [ignore 1st edge] + IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN + IF (XOn) THEN + Violation := 'X'; + END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PulseWidCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := PeriodData(i).Last; + VitalMemoryReportViolation (TestSignalName, "", i, + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + IF (PeriodTest AND CheckEnabled) THEN + -- Verify the Period [ignore 1st edge] + CheckInfo.ObsTime := PeriodObs; + CheckInfo.ExpTime := Period(i); + IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN + IF (XOn) THEN + Violation := 'X'; + END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PeriodCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := TestValue; + VitalMemoryReportViolation (TestSignalName, "", i, + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + PeriodData(i).Last := TestValue; + END LOOP; + +END VitalMemoryPeriodPulseCheck; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryPeriodPulseCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE PeriodData : INOUT VitalPeriodDataArrayType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArraytype; + CONSTANT Period : IN VitalDelayArraytype; + CONSTANT PulseWidthHigh : IN VitalDelayArraytype; + CONSTANT PulseWidthLow : IN VitalDelayArraytype; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType +)IS + VARIABLE TestDly : VitalDelayType; + VARIABLE CheckInfo : CheckInfoType; + VARIABLE PeriodObs : VitalDelayType; + VARIABLE PulseTest : BOOLEAN; + VARIABLE PeriodTest: BOOLEAN; + VARIABLE TestValue : X01; +BEGIN + + FOR i IN TestSignal'RANGE LOOP + TestDly := Maximum(0 ns, TestDelay(i)); + TestValue := To_X01(TestSignal(i)); + + IF (PeriodData(i).NotFirstFlag = FALSE) THEN + PeriodData(i).Rise := -Maximum(Period(i), + Maximum(PulseWidthHigh(i),PulseWidthLow(i))); + PeriodData(i).Fall := -Maximum(Period(i), + Maximum(PulseWidthHigh(i),PulseWidthLow(i))); + PeriodData(i).Last := TestValue; + PeriodData(i).NotFirstFlag := TRUE; + END IF; + + -- Initialize for no violation + Violation(i) := '0'; + + -- No violation possible if no test signal change + NEXT WHEN (PeriodData(i).Last = TestValue); + + -- record starting pulse times + IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN + -- Compute period times, then record the High Rise Time + PeriodObs := NOW - PeriodData(i).Rise; + PeriodData(i).Rise := NOW; + PeriodTest := TRUE; + ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN + -- Compute period times, then record the Low Fall Time + PeriodObs := NOW - PeriodData(i).Fall; + PeriodData(i).Fall := NOW; + PeriodTest := TRUE; + ELSE + PeriodTest := FALSE; + END IF; + + -- do checks on pulse ends + IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData(i).Fall; + CheckInfo.ExpTime := PulseWidthLow(i); + PulseTest := TRUE; + ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData(i).Rise; + CheckInfo.ExpTime := PulseWidthHigh(i); + PulseTest := TRUE; + ELSE + PulseTest := FALSE; + END IF; + + IF (PulseTest AND CheckEnabled) THEN + -- Verify Pulse Width [ignore 1st edge] + IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN + IF (XOn) THEN + Violation(i) := 'X'; + END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PulseWidCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := PeriodData(i).Last; + VitalMemoryReportViolation (TestSignalName, "", i, + HeaderMsg, CheckInfo, MsgFormat, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + IF (PeriodTest AND CheckEnabled) THEN + -- Verify the Period [ignore 1st edge] + CheckInfo.ObsTime := PeriodObs; + CheckInfo.ExpTime := Period(i); + IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN + IF (XOn) THEN + Violation(i) := 'X'; + END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PeriodCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := TestValue; + VitalMemoryReportViolation (TestSignalName, "", i, + HeaderMsg, CheckInfo, MsgFOrmat, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + PeriodData(i).Last := TestValue; + END LOOP; + +END VitalMemoryPeriodPulseCheck; + +-- ---------------------------------------------------------------------------- +-- Functionality Section +-- ---------------------------------------------------------------------------- + +-- Look-up table. Given an int, we can get the 4-bit bit_vector. +TYPE HexToBitvTableType IS ARRAY (NATURAL RANGE <>) OF + std_logic_vector(3 DOWNTO 0) ; + +CONSTANT HexToBitvTable : HexToBitvTableType (0 TO 15) := + ( + "0000", "0001", "0010", "0011", + "0100", "0101", "0110", "0111", + "1000", "1001", "1010", "1011", + "1100", "1101", "1110", "1111" + ) ; + +-- ---------------------------------------------------------------------------- +-- Misc Utilities Local Utilities +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- Procedure: IsSpace +-- Parameters: ch -- input character +-- Description: Returns TRUE or FALSE depending on the input character +-- being white space or not. +-- ---------------------------------------------------------------------------- +FUNCTION IsSpace (ch : character) +RETURN boolean IS +BEGIN + RETURN ((ch = ' ') OR (ch = CR) OR (ch = HT) OR (ch = NUL)); +END IsSpace; + +-- ---------------------------------------------------------------------------- +-- Procedure: LenOfString +-- Parameters: Str -- input string +-- Description: Returns the NATURAL length of the input string. +-- as terminated by the first NUL character. +-- ---------------------------------------------------------------------------- +FUNCTION LenOfString (Str : STRING) +RETURN NATURAL IS + VARIABLE StrRight : NATURAL; +BEGIN + StrRight := Str'RIGHT; + FOR i IN Str'RANGE LOOP + IF (Str(i) = NUL) THEN + StrRight := i - 1; + EXIT; + END IF; + END LOOP; + RETURN (StrRight); +END LenOfString; + +-- ---------------------------------------------------------------------------- +-- Procedure: HexToInt +-- Parameters: Hex -- input character or string +-- Description: Converts input character or string interpreted as a +-- hexadecimal representation to integer value. +-- ---------------------------------------------------------------------------- +FUNCTION HexToInt(Hex : CHARACTER) RETURN INTEGER IS + CONSTANT HexChars : STRING := "0123456789ABCDEFabcdef"; + CONSTANT XHiChar : CHARACTER := 'X'; + CONSTANT XLoChar : CHARACTER := 'x'; +BEGIN + IF (Hex = XLoChar OR Hex = XHiChar) THEN + RETURN (23); + END IF; + FOR i IN 1 TO 16 LOOP + IF(Hex = HexChars(i)) THEN + RETURN (i-1); + END IF; + END LOOP; + FOR i IN 17 TO 22 LOOP + IF (Hex = HexChars(i)) THEN + RETURN (i-7); + END IF; + END LOOP; + ASSERT FALSE REPORT + "Invalid character received by HexToInt function" + SEVERITY WARNING; + RETURN (0); +END HexToInt; + +-- ---------------------------------------------------------------------------- +FUNCTION HexToInt (Hex : STRING) RETURN INTEGER IS + VARIABLE Value : INTEGER := 0; + VARIABLE Length : INTEGER; +BEGIN + Length := LenOfString(hex); + IF (Length > 8) THEN + ASSERT FALSE REPORT + "Invalid string length received by HexToInt function" + SEVERITY WARNING; + ELSE + FOR i IN 1 TO Length LOOP + Value := Value + HexToInt(Hex(i)) * 16 ** (Length - i); + END LOOP; + END IF; + RETURN (Value); +END HexToInt; + +-- ---------------------------------------------------------------------------- +-- Procedure: HexToBitv +-- Parameters: Hex -- Input hex string +-- Description: Converts input hex string to a std_logic_vector +-- ---------------------------------------------------------------------------- +FUNCTION HexToBitv( + Hex : STRING +) RETURN std_logic_vector is + VARIABLE Index : INTEGER := 0 ; + VARIABLE ValHexToInt : INTEGER ; + VARIABLE BitsPerHex : INTEGER := 4 ; -- Denotes no. of bits per hex char. + VARIABLE HexLen : NATURAL := (BitsPerHex * LenOfString(Hex)) ; + VARIABLE TableVal : std_logic_vector(3 DOWNTO 0) ; + VARIABLE Result : std_logic_vector(HexLen-1 DOWNTO 0) ; +BEGIN + -- Assign 4-bit wide bit vector to result directly from a look-up table. + Index := 0 ; + WHILE ( Index < HexLen ) LOOP + ValHexToInt := HexToInt( Hex((HexLen - Index)/BitsPerHex ) ); + IF ( ValHexToInt = 23 ) THEN + TableVal := "XXXX"; + ELSE + -- Look up from the table. + TableVal := HexToBitvTable( ValHexToInt ) ; + END IF; + -- Assign now. + Result(Index+3 DOWNTO Index) := TableVal ; + -- Get ready for next block of 4-bits. + Index := Index + 4 ; + END LOOP ; + RETURN Result ; +END HexToBitv ; + +-- ---------------------------------------------------------------------------- +-- Procedure: BinToBitv +-- Parameters: Bin -- Input bin string +-- Description: Converts input bin string to a std_logic_vector +-- ---------------------------------------------------------------------------- +FUNCTION BinToBitv( + Bin : STRING +) RETURN std_logic_vector is + VARIABLE Index : INTEGER := 0 ; + VARIABLE Length : NATURAL := LenOfString(Bin); + VARIABLE BitVal : std_ulogic; + VARIABLE Result : std_logic_vector(Length-1 DOWNTO 0) ; +BEGIN + Index := 0 ; + WHILE ( Index < Length ) LOOP + IF (Bin(Length-Index) = '0') THEN + BitVal := '0'; + ELSIF (Bin(Length-Index) = '1') THEN + BitVal := '1'; + ELSE + BitVal := 'X'; + END IF ; + -- Assign now. + Result(Index) := BitVal ; + Index := Index + 1 ; + END LOOP ; + RETURN Result ; +END BinToBitv ; + +-- ---------------------------------------------------------------------------- +-- For Memory Table Modeling +-- ---------------------------------------------------------------------------- + +TYPE To_MemoryCharType IS ARRAY (VitalMemorySymbolType) OF CHARACTER; +CONSTANT To_MemoryChar : To_MemoryCharType := + ( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v', + 'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S', + 'g', 'u', 'i', 'G', 'U', 'I', + 'w', 's', + 'c', 'l', 'd', 'e', 'C', 'L', + 'M', 'm', 't' ); + +TYPE ValidMemoryTableInputType IS ARRAY (VitalMemorySymbolType) OF BOOLEAN; +CONSTANT ValidMemoryTableInput : ValidMemoryTableInputType := + -- '/', '\', 'P', 'N', 'r', 'f', + ( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, + -- 'p', 'n', 'R', 'F', '^', 'v', + TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, + -- 'E', 'A', 'D', '*', + TRUE, TRUE, TRUE, TRUE, + -- 'X', '0', '1', '-', 'B', 'Z', + TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, + -- 'S', + TRUE, + -- 'g', 'u', 'i', 'G', 'U', 'I', + FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, + -- 'w', 's', + FALSE, FALSE, + -- 'c', 'l', 'd', 'e', 'C', 'L', + FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, + -- 'M', 'm', 't' + FALSE, FALSE, FALSE); + +TYPE MemoryTableMatchType IS ARRAY (X01,X01,VitalMemorySymbolType) OF BOOLEAN; +-- last value, present value, table symbol +CONSTANT MemoryTableMatch : MemoryTableMatchType := ( + ( -- X (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + -- g u i G U I + -- w s + -- c l d e, C L + -- m t + ( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( FALSE,FALSE,FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, FALSE,TRUE, + TRUE, FALSE,TRUE, TRUE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( FALSE,FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,TRUE, FALSE,TRUE, FALSE, + TRUE, TRUE, FALSE,TRUE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE) + ), + + (-- 0 (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + -- g u i G U I + -- w s + -- c l d e, C L + -- m t + ( FALSE,FALSE,FALSE,FALSE,TRUE, FALSE, + TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE) + ), + + (-- 1 (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + -- g u i G U I + -- w s + -- c l d e, C L + -- m t + ( FALSE,FALSE,FALSE,FALSE,FALSE,TRUE , + FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,TRUE, TRUE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE), + ( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE) + ) + ); + + +-- ---------------------------------------------------------------------------- +-- Error Message Types and Tables +-- ---------------------------------------------------------------------------- + +TYPE VitalMemoryErrorType IS ( + ErrGoodAddr, -- 'g' Good address (no transition) + ErrUnknAddr, -- 'u' 'X' levels in address (no transition) + ErrInvaAddr, -- 'i' Invalid address (no transition) + ErrGoodTrAddr, -- 'G' Good address (with transition) + ErrUnknTrAddr, -- 'U' 'X' levels in address (with transition) + ErrInvaTrAddr, -- 'I' Invalid address (with transition) + ErrWrDatMem, -- 'w' Writing data to memory + ErrNoChgMem, -- 's' Retaining previous memory contents + ErrCrAllMem, -- 'c' Corrupting entire memory with 'X' + ErrCrWrdMem, -- 'l' Corrupting a word in memory with 'X' + ErrCrBitMem, -- 'd' Corrupting a single bit in memory with 'X' + ErrCrDatMem, -- 'e' Corrupting a word with 'X' based on data in + ErrCrAllSubMem,-- 'C' Corrupting a sub-word entire memory with 'X' + ErrCrWrdSubMem,-- 'L' Corrupting a sub-word in memory with 'X' + ErrCrBitSubMem,-- 'D' Corrupting a single bit of a memory sub-word with 'X' + ErrCrDatSubMem,-- 'E' Corrupting a sub-word with 'X' based on data in + ErrCrWrdOut, -- 'l' Corrupting data out with 'X' + ErrCrBitOut, -- 'd' Corrupting a single bit of data out with 'X' + ErrCrDatOut, -- 'e' Corrupting data out with 'X' based on data in + ErrCrWrdSubOut,-- 'L' Corrupting data out sub-word with 'X' + ErrCrBitSubOut,-- 'D' Corrupting a single bit of data out sub-word with 'X' + ErrCrDatSubOut,-- 'E' Corrupting data out sub-word with 'X' based on data in + ErrImplOut, -- 'M' Implicit read from memory to data out + ErrReadOut, -- 'm' Reading data from memory to data out + ErrAssgOut, -- 't' Transferring from data in to data out + ErrAsgXOut, -- 'X' Assigning unknown level to data out + ErrAsg0Out, -- '0' Assigning low level to data out + ErrAsg1Out, -- '1' Assigning high level to data out + ErrAsgZOut, -- 'Z' Assigning high impedence to data out + ErrAsgSOut, -- 'S' Keeping data out at steady value + ErrAsgXMem, -- 'X' Assigning unknown level to memory location + ErrAsg0Mem, -- '0' Assigning low level to memory location + ErrAsg1Mem, -- '1' Assigning high level to memory location + ErrAsgZMem, -- 'Z' Assigning high impedence to memory location + ErrDefMemAct, -- No memory table match, using default action + ErrInitMem, -- Initialize memory contents + ErrMcpWrCont, -- Memory cross port to same port write contention + ErrMcpCpCont, -- Memory cross port read/write data/memory contention + ErrMcpCpRead, -- Memory cross port read to same port + ErrMcpRdWrCo, -- Memory cross port read/write data only contention + ErrMcpCpWrCont,-- Memory cross port to cross port write contention + ErrUnknMemDo, -- Unknown memory action + ErrUnknDatDo, -- Unknown data action + ErrUnknSymbol, -- Illegal memory symbol + ErrLdIlgArg, + ErrLdAddrRng, + ErrLdMemInfo, + ErrLdFileEmpty, + ErrPrintString +); + +TYPE VitalMemoryErrorSeverityType IS +ARRAY (VitalMemoryErrorType) OF SEVERITY_LEVEL; +CONSTANT VitalMemoryErrorSeverity : + VitalMemoryErrorSeverityType := ( + ErrGoodAddr => NOTE, + ErrUnknAddr => WARNING, + ErrInvaAddr => WARNING, + ErrGoodTrAddr => NOTE, + ErrUnknTrAddr => WARNING, + ErrInvaTrAddr => WARNING, + ErrWrDatMem => NOTE, + ErrNoChgMem => NOTE, + ErrCrAllMem => WARNING, + ErrCrWrdMem => WARNING, + ErrCrBitMem => WARNING, + ErrCrDatMem => WARNING, + ErrCrAllSubMem => WARNING, + ErrCrWrdSubMem => WARNING, + ErrCrBitSubMem => WARNING, + ErrCrDatSubMem => WARNING, + ErrCrWrdOut => WARNING, + ErrCrBitOut => WARNING, + ErrCrDatOut => WARNING, + ErrCrWrdSubOut => WARNING, + ErrCrBitSubOut => WARNING, + ErrCrDatSubOut => WARNING, + ErrImplOut => NOTE, + ErrReadOut => NOTE, + ErrAssgOut => NOTE, + ErrAsgXOut => NOTE, + ErrAsg0Out => NOTE, + ErrAsg1Out => NOTE, + ErrAsgZOut => NOTE, + ErrAsgSOut => NOTE, + ErrAsgXMem => NOTE, + ErrAsg0Mem => NOTE, + ErrAsg1Mem => NOTE, + ErrAsgZMem => NOTE, + ErrDefMemAct => NOTE, + ErrInitMem => NOTE, + ErrMcpWrCont => WARNING, + ErrMcpCpCont => WARNING, + ErrMcpCpRead => WARNING, + ErrMcpRdWrCo => WARNING, + ErrMcpCpWrCont => WARNING, + ErrUnknMemDo => ERROR, + ErrUnknDatDo => ERROR, + ErrUnknSymbol => ERROR, + ErrLdIlgArg => ERROR, + ErrLdAddrRng => WARNING, + ErrLdMemInfo => NOTE, + ErrLdFileEmpty => ERROR, + ErrPrintString => WARNING + ); + +-- ---------------------------------------------------------------------------- +CONSTANT MsgGoodAddr : STRING + := "Good address (no transition)"; +CONSTANT MsgUnknAddr : STRING + := "Unknown address (no transition)"; +CONSTANT MsgInvaAddr : STRING + := "Invalid address (no transition)"; +CONSTANT MsgGoodTrAddr : STRING + := "Good address (with transition)"; +CONSTANT MsgUnknTrAddr : STRING + := "Unknown address (with transition)"; +CONSTANT MsgInvaTrAddr : STRING + := "Invalid address (with transition)"; +CONSTANT MsgNoChgMem : STRING + := "Retaining previous memory contents"; +CONSTANT MsgWrDatMem : STRING + := "Writing data to memory"; +CONSTANT MsgCrAllMem : STRING + := "Corrupting entire memory with 'X'"; +CONSTANT MsgCrWrdMem : STRING + := "Corrupting a word in memory with 'X'"; +CONSTANT MsgCrBitMem : STRING + := "Corrupting a single bit in memory with 'X'"; +CONSTANT MsgCrDatMem : STRING + := "Corrupting a word with 'X' based on data in"; +CONSTANT MsgCrAllSubMem : STRING + := "Corrupting a sub-word entire memory with 'X'"; +CONSTANT MsgCrWrdSubMem : STRING + := "Corrupting a sub-word in memory with 'X'"; +CONSTANT MsgCrBitSubMem : STRING + := "Corrupting a single bit of a sub-word with 'X'"; +CONSTANT MsgCrDatSubMem : STRING + := "Corrupting a sub-word with 'X' based on data in"; +CONSTANT MsgCrWrdOut : STRING + := "Corrupting data out with 'X'"; +CONSTANT MsgCrBitOut : STRING + := "Corrupting a single bit of data out with 'X'"; +CONSTANT MsgCrDatOut : STRING + := "Corrupting data out with 'X' based on data in"; +CONSTANT MsgCrWrdSubOut : STRING + := "Corrupting data out sub-word with 'X'"; +CONSTANT MsgCrBitSubOut : STRING + := "Corrupting a single bit of data out sub-word with 'X'"; +CONSTANT MsgCrDatSubOut : STRING + := "Corrupting data out sub-word with 'X' based on data in"; +CONSTANT MsgImplOut : STRING + := "Implicit read from memory to data out"; +CONSTANT MsgReadOut : STRING + := "Reading data from memory to data out"; +CONSTANT MsgAssgOut : STRING + := "Transferring from data in to data out"; +CONSTANT MsgAsgXOut : STRING + := "Assigning unknown level to data out"; +CONSTANT MsgAsg0Out : STRING + := "Assigning low level to data out"; +CONSTANT MsgAsg1Out : STRING + := "Assigning high level to data out"; +CONSTANT MsgAsgZOut : STRING + := "Assigning high impedance to data out"; +CONSTANT MsgAsgSOut : STRING + := "Keeping data out at steady value"; +CONSTANT MsgAsgXMem : STRING + := "Assigning unknown level to memory location"; +CONSTANT MsgAsg0Mem : STRING + := "Assigning low level to memory location"; +CONSTANT MsgAsg1Mem : STRING + := "Assigning high level to memory location"; +CONSTANT MsgAsgZMem : STRING + := "Assigning high impedance to memory location"; +CONSTANT MsgDefMemAct : STRING + := "No memory table match, using default action"; +CONSTANT MsgInitMem : STRING + := "Initializing memory contents"; +CONSTANT MsgMcpWrCont : STRING + := "Same port write contention"; +CONSTANT MsgMcpCpCont : STRING + := "Cross port read/write data/memory contention"; +CONSTANT MsgMcpCpRead : STRING + := "Cross port read to same port"; +CONSTANT MsgMcpRdWrCo : STRING + := "Cross port read/write data only contention"; +CONSTANT MsgMcpCpWrCont : STRING + := "Cross port write contention"; +CONSTANT MsgUnknMemDo : STRING + := "Unknown memory action"; +CONSTANT MsgUnknDatDo : STRING + := "Unknown data action"; +CONSTANT MsgUnknSymbol : STRING + := "Illegal memory symbol"; + +CONSTANT MsgLdIlgArg : STRING + := "Illegal bit arguments while loading memory."; +CONSTANT MsgLdMemInfo : STRING + := "Loading data from the file into memory."; +CONSTANT MsgLdAddrRng : STRING + := "Address out of range while loading memory."; +CONSTANT MsgLdFileEmpty : STRING + := "Memory load file is empty."; +CONSTANT MsgPrintString : STRING + := ""; + +CONSTANT MsgUnknown : STRING + := "Unknown error message."; + +CONSTANT MsgVMT : STRING + := "VitalMemoryTable"; +CONSTANT MsgVMV : STRING + := "VitalMemoryViolation"; +CONSTANT MsgVDM : STRING + := "VitalDeclareMemory"; +CONSTANT MsgVMCP : STRING + := "VitalMemoryCrossPorts"; + +-- ---------------------------------------------------------------------------- +-- LOCAL Utilities +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- Procedure: MemoryMessage +-- Parameters: ErrorId -- Input error code +-- Description: This function looks up the input error code and returns +-- the string value of the associated message. +-- ---------------------------------------------------------------------------- + +FUNCTION MemoryMessage ( + CONSTANT ErrorId : IN VitalMemoryErrorType +) RETURN STRING IS +BEGIN + CASE ErrorId IS + WHEN ErrGoodAddr => RETURN MsgGoodAddr ; + WHEN ErrUnknAddr => RETURN MsgUnknAddr ; + WHEN ErrInvaAddr => RETURN MsgInvaAddr ; + WHEN ErrGoodTrAddr => RETURN MsgGoodTrAddr ; + WHEN ErrUnknTrAddr => RETURN MsgUnknTrAddr ; + WHEN ErrInvaTrAddr => RETURN MsgInvaTrAddr ; + WHEN ErrWrDatMem => RETURN MsgWrDatMem ; + WHEN ErrNoChgMem => RETURN MsgNoChgMem ; + WHEN ErrCrAllMem => RETURN MsgCrAllMem ; + WHEN ErrCrWrdMem => RETURN MsgCrWrdMem ; + WHEN ErrCrBitMem => RETURN MsgCrBitMem ; + WHEN ErrCrDatMem => RETURN MsgCrDatMem ; + WHEN ErrCrAllSubMem => RETURN MsgCrAllSubMem; + WHEN ErrCrWrdSubMem => RETURN MsgCrWrdSubMem; + WHEN ErrCrBitSubMem => RETURN MsgCrBitSubMem; + WHEN ErrCrDatSubMem => RETURN MsgCrDatSubMem; + WHEN ErrCrWrdOut => RETURN MsgCrWrdOut ; + WHEN ErrCrBitOut => RETURN MsgCrBitOut ; + WHEN ErrCrDatOut => RETURN MsgCrDatOut ; + WHEN ErrCrWrdSubOut => RETURN MsgCrWrdSubOut; + WHEN ErrCrBitSubOut => RETURN MsgCrBitSubOut; + WHEN ErrCrDatSubOut => RETURN MsgCrDatSubOut; + WHEN ErrImplOut => RETURN MsgImplOut ; + WHEN ErrReadOut => RETURN MsgReadOut ; + WHEN ErrAssgOut => RETURN MsgAssgOut ; + WHEN ErrAsgXOut => RETURN MsgAsgXOut ; + WHEN ErrAsg0Out => RETURN MsgAsg0Out ; + WHEN ErrAsg1Out => RETURN MsgAsg1Out ; + WHEN ErrAsgZOut => RETURN MsgAsgZOut ; + WHEN ErrAsgSOut => RETURN MsgAsgSOut ; + WHEN ErrAsgXMem => RETURN MsgAsgXMem ; + WHEN ErrAsg0Mem => RETURN MsgAsg0Mem ; + WHEN ErrAsg1Mem => RETURN MsgAsg1Mem ; + WHEN ErrAsgZMem => RETURN MsgAsgZMem ; + WHEN ErrDefMemAct => RETURN MsgDefMemAct ; + WHEN ErrInitMem => RETURN MsgInitMem ; + WHEN ErrMcpWrCont => RETURN MsgMcpWrCont ; + WHEN ErrMcpCpCont => RETURN MsgMcpCpCont ; + WHEN ErrMcpCpRead => RETURN MsgMcpCpRead ; + WHEN ErrMcpRdWrCo => RETURN MsgMcpRdWrCo ; + WHEN ErrMcpCpWrCont => RETURN MsgMcpCpWrCont; + WHEN ErrUnknMemDo => RETURN MsgUnknMemDo ; + WHEN ErrUnknDatDo => RETURN MsgUnknDatDo ; + WHEN ErrUnknSymbol => RETURN MsgUnknSymbol ; + WHEN ErrLdIlgArg => RETURN MsgLdIlgArg ; + WHEN ErrLdAddrRng => RETURN MsgLdAddrRng ; + WHEN ErrLdMemInfo => RETURN MsgLdMemInfo ; + WHEN ErrLdFileEmpty => RETURN MsgLdFileEmpty; + WHEN ErrPrintString => RETURN MsgPrintString; + WHEN OTHERS => RETURN MsgUnknown ; + END CASE; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: PrintMemoryMessage +-- Parameters: Routine -- String identifying the calling routine +-- ErrorId -- Input error code for message lookup +-- Info -- Output string or character +-- InfoStr -- Additional output string +-- Info1 -- Additional output integer +-- Info2 -- Additional output integer +-- Info3 -- Additional output integer +-- Description: This procedure prints out a memory status message +-- given the input error id and other status information. +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType +) IS +BEGIN + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT Info : IN STRING +) IS +BEGIN + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT Info1 : IN STRING; + CONSTANT Info2 : IN STRING +) IS +BEGIN + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info1 & " " & Info2 + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT Info : IN CHARACTER +) IS +BEGIN + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT InfoStr : IN STRING; + CONSTANT Info1 : IN NATURAL +) IS + VARIABLE TmpStr : STRING ( 1 TO 256 ) ; + VARIABLE TmpInt : INTEGER := 1; +BEGIN + IntToStr(Info1,TmpStr,TmpInt); + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT InfoStr : IN STRING; + CONSTANT Info1 : IN NATURAL; + CONSTANT Info2 : IN NATURAL +) IS + VARIABLE TmpStr : STRING ( 1 TO 256 ) ; + VARIABLE TmpInt : INTEGER := 1; +BEGIN + IntToStr(Info1,TmpStr,TmpInt); + IntToStr(Info2,TmpStr,TmpInt); + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalMemoryErrorType; + CONSTANT InfoStr : IN STRING; + CONSTANT Info1 : IN NATURAL; + CONSTANT Info2 : IN NATURAL; + CONSTANT Info3 : IN NATURAL +) IS + VARIABLE TmpStr : STRING ( 1 TO 256 ) ; + VARIABLE TmpInt : INTEGER := 1; +BEGIN + IntToStr(Info1,TmpStr,TmpInt); + IntToStr(Info2,TmpStr,TmpInt); + IntToStr(Info3,TmpStr,TmpInt); + ASSERT FALSE + REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr + SEVERITY VitalMemoryErrorSeverity(ErrorId); +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE PrintMemoryMessage ( + CONSTANT Routine : IN STRING; + CONSTANT Table : IN VitalMemoryTableType; + CONSTANT Index : IN INTEGER; + CONSTANT InfoStr : IN STRING +) IS + CONSTANT TableEntries : INTEGER := Table'LENGTH(1); + CONSTANT TableWidth : INTEGER := Table'LENGTH(2); + VARIABLE TmpStr : STRING ( 1 TO 256 ) ; + VARIABLE TmpInt : INTEGER := 1; +BEGIN + IF (Index < 0 AND Index > TableEntries-1) THEN + ASSERT FALSE + REPORT Routine & ": Memory table search failure" + SEVERITY ERROR; + END IF; + ColLoop: + FOR i IN 0 TO TableWidth-1 LOOP + IF (i >= 64) THEN + TmpStr(TmpInt) := '.'; + TmpInt := TmpInt + 1; + TmpStr(TmpInt) := '.'; + TmpInt := TmpInt + 1; + TmpStr(TmpInt) := '.'; + TmpInt := TmpInt + 1; + EXIT ColLoop; + END IF; + TmpStr(TmpInt) := '''; + TmpInt := TmpInt + 1; + TmpStr(TmpInt) := To_MemoryChar(Table(Index,i)); + TmpInt := TmpInt + 1; + TmpStr(TmpInt) := '''; + TmpInt := TmpInt + 1; + IF (i < TableWidth-1) THEN + TmpStr(TmpInt) := ','; + TmpInt := TmpInt + 1; + END IF; + END LOOP; + ASSERT FALSE + REPORT Routine & ": Port=" & InfoStr & " TableRow=" & TmpStr + SEVERITY NOTE; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: DecodeAddress +-- Parameters: Address - Converted address. +-- AddrFlag - Flag to indicte address match +-- MemoryData - Information about memory characteristics +-- PrevAddressBus - Previous input address value +-- AddressBus - Input address value. +-- Description: This procedure is used for transforming a valid +-- address value to an integer in order to access memory. +-- It performs address bound checking as well. +-- Sets Address to -1 for unknowns +-- Sets Address to -2 for out of range +-- ---------------------------------------------------------------------------- + +PROCEDURE DecodeAddress ( + VARIABLE Address : INOUT INTEGER; + VARIABLE AddrFlag : INOUT VitalMemorySymbolType; + VARIABLE MemoryData : IN VitalMemoryDataType; + CONSTANT PrevAddressBus : IN std_logic_vector; + CONSTANT AddressBus : IN std_logic_vector +) IS + VARIABLE Power : NATURAL; + VARIABLE AddrUnkn : BOOLEAN; +BEGIN + Power := 0; + AddrUnkn := FALSE; + -- It is assumed that always Address'LEFT represents the Most significant bit. + FOR i IN AddressBus'RANGE LOOP + Power := Power * 2; + IF (AddressBus(i) /= '1' AND AddressBus(i) /= '0') THEN + AddrUnkn := TRUE; + Power := 0; + EXIT; + ELSIF (AddressBus(i) = '1') THEN + Power := Power + 1; + END IF; + END LOOP; + Address := Power; + AddrFlag := 'g'; + IF (AddrUnkn) THEN + AddrFlag := 'u'; -- unknown addr + Address := -1; + END IF; + IF ( Power > (MemoryData.NoOfWords - 1)) THEN + AddrFlag := 'i'; -- invalid addr + Address := -2; + END IF; + IF (PrevAddressBus /= AddressBus) THEN + CASE AddrFlag IS + WHEN 'g' => AddrFlag := 'G'; + WHEN 'u' => AddrFlag := 'U'; + WHEN 'i' => AddrFlag := 'I'; + WHEN OTHERS => + ASSERT FALSE REPORT + "DecodeAddress: Internal error. [AddrFlag]=" + & To_MemoryChar(AddrFlag) + SEVERITY ERROR; + END CASE; + END IF; +END DecodeAddress; + +-- ---------------------------------------------------------------------------- +-- Procedure: DecodeData +-- Parameters: DataFlag - Flag to indicte data match +-- PrevDataInBus - Previous input data value +-- DataInBus - Input data value. +-- HighBit - High bit offset value. +-- LowBit - Low bit offset value. +-- Description: This procedure is used for interpreting the input data +-- as a data flag for subsequent table matching. +-- ---------------------------------------------------------------------------- +PROCEDURE DecodeData ( + VARIABLE DataFlag : INOUT VitalMemorySymbolType; + CONSTANT PrevDataInBus : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT HighBit : IN NATURAL; + CONSTANT LowBit : IN NATURAL +) IS + VARIABLE DataUnkn : BOOLEAN := FALSE; +BEGIN + FOR i IN LowBit TO HighBit LOOP + IF DataInBus(i) /= '1' AND DataInBus(i) /= '0' THEN + DataUnkn := TRUE; + EXIT; + END IF; + END LOOP; + DataFlag := 'g'; + IF (DataUnkn) THEN + DataFlag := 'u'; -- unknown addr + END IF; + IF (PrevDataInBus(HighBit DOWNTO LowBit) /= + DataInBus(HighBit DOWNTO LowBit)) THEN + CASE DataFlag IS + WHEN 'g' => DataFlag := 'G'; + WHEN 'u' => DataFlag := 'U'; + WHEN OTHERS => + ASSERT FALSE REPORT + "DecodeData: Internal error. [DataFlag]=" + & To_MemoryChar(DataFlag) + SEVERITY ERROR; + END CASE; + END IF; +END DecodeData; + +-- ---------------------------------------------------------------------------- +-- Procedure: WriteMemory +-- Parameters: MemoryPtr - Pointer to the memory array. +-- DataInBus - Input Data to be written. +-- Address - Address of the memory location. +-- BitPosition - Position of bit in memory location. +-- HighBit - High bit offset value. +-- LowBit - Low bit offset value. +-- Description: This procedure is used to write to a memory location +-- on a bit/byte/word basis. +-- The high bit and low bit offset are used for byte write +-- operations.These parameters specify the data byte for write. +-- In the case of word write the complete memory word is used. +-- This procedure is overloaded for bit,byte and word write +-- memory operations.The number of parameters may vary. +-- ---------------------------------------------------------------------------- +PROCEDURE WriteMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT HighBit : IN NATURAL; + CONSTANT LowBit : IN NATURAL +) IS + VARIABLE TmpData : std_logic_vector(DataInBus'LENGTH - 1 DOWNTO 0); +BEGIN + -- Address bound checking. + IF ( Address < 0 OR Address > (MemoryPtr.NoOfWords - 1)) THEN + PrintMemoryMessage ( "WriteMemory", ErrPrintString, + "Aborting write operation as address is out of range.") ; + RETURN; + END IF; + TmpData := To_UX01(DataInBus); + FOR i in LowBit to HighBit LOOP + MemoryPtr.MemoryArrayPtr(Address).all(i) := TmpData(i); + END LOOP; +END WriteMemory; + +-- ---------------------------------------------------------------------------- +PROCEDURE WriteMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT BitPosition : IN NATURAL +) IS + VARIABLE HighBit : NATURAL; + VARIABLE LowBit : NATURAL; +BEGIN + HighBit := BitPosition; + LowBit := BitPosition; + WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit); +END WriteMemory; + +-- ---------------------------------------------------------------------------- +PROCEDURE WriteMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT Address : IN INTEGER +) IS + VARIABLE HighBit : NATURAL; + VARIABLE LowBit : NATURAL; +BEGIN + HighBit := MemoryPtr.NoOfBitsPerWord - 1; + LowBit := 0; + WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit); +END WriteMemory; + +-- ---------------------------------------------------------------------------- +-- Procedure: ReadMemory +-- Parameters: MemoryPtr - Pointer to the memory array. +-- DataOut - Output Data to be read in this. +-- Address - Address of the memory location. +-- BitPosition - Position of bit in memory location. +-- HighBit - High bit offset value. +-- LowBit - Low bit offset value. +-- Description: This procedure is used to read from a memory location +-- on a bit/byte/word basis. +-- The high bit and low bit offset are used for byte write +-- operations.These parameters specify the data byte for +-- read.In the case of word write the complete memory word +-- is used.This procedure is overloaded for bit,byte and +-- word write memory operations.The number of parameters +-- may vary. +-- ---------------------------------------------------------------------------- +PROCEDURE ReadMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + VARIABLE DataOut : OUT std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT HighBit : IN NATURAL; + CONSTANT LowBit : IN NATURAL +) IS + VARIABLE DataOutTmp : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0); + VARIABLE length : NATURAL := (HighBit - LowBit + 1); +BEGIN + -- Address bound checking. + IF ( Address > (MemoryPtr.NoOfWords - 1)) THEN + PrintMemoryMessage ( + "ReadMemory",ErrInvaAddr, + "[Address,NoOfWords]=",Address,MemoryPtr.NoOfWords + ); + FOR i in LowBit to HighBit LOOP + DataOutTmp(i) := 'X'; + END LOOP; + ELSE + FOR i in LowBit to HighBit LOOP + DataOutTmp(i) := MemoryPtr.MemoryArrayPtr (Address).all(i); + END LOOP; + END IF; + DataOut := DataOutTmp; +END ReadMemory; + +-- ---------------------------------------------------------------------------- +PROCEDURE ReadMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + VARIABLE DataOut : OUT std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT BitPosition : IN NATURAL +) IS + VARIABLE HighBit : NATURAL; + VARIABLE LowBit : NATURAL; +BEGIN + HighBit := BitPosition; + LowBit := BitPosition; + ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit); +END ReadMemory; + +-- ---------------------------------------------------------------------------- +PROCEDURE ReadMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + VARIABLE DataOut : OUT std_logic_vector; + CONSTANT Address : IN INTEGER +) IS + VARIABLE HighBit : NATURAL; + VARIABLE LowBit : NATURAL; +BEGIN + HighBit := MemoryPtr.NoOfBitsPerWord - 1; + LowBit := 0; + ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit); +END ReadMemory; + + +-- ---------------------------------------------------------------------------- +-- Procedure: LoadMemory +-- Parameters: MemoryPtr - Pointer to the memory array. +-- FileName - Name of the output file. +-- HighBit - High bit offset value. +-- LowBit - Low bit offset value. +-- Description: This procedure is used to load the contents of the memory +-- from a specified input file. +-- The high bit and low bit offset are used so that same task +-- can be used for all bit/byte/word write operations. +-- In the case of a bit write RAM the HighBit and LowBit have +-- the same value. +-- This procedure is overloaded for word write operations. +-- ---------------------------------------------------------------------------- +PROCEDURE LoadMemory ( + VARIABLE MemoryPtr : INOUT VitalMemoryDataType; + CONSTANT FileName : IN STRING; + CONSTANT BinaryFile : IN BOOLEAN := FALSE +) IS + FILE Fptr : TEXT OPEN read_mode IS FileName; + VARIABLE OneLine : LINE; + VARIABLE Ignore : CHARACTER; + VARIABLE Index : NATURAL := 1; + VARIABLE LineNo : NATURAL := 0; + VARIABLE Address : INTEGER := 0; + VARIABLE DataInBus : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0); + VARIABLE AddrStr : STRING(1 TO 80) ; + VARIABLE DataInStr : STRING(1 TO 255) ; +BEGIN + IF (ENDFILE(fptr)) THEN + PrintMemoryMessage (MsgVDM, ErrLdFileEmpty, + "[FileName]="&FileName); + RETURN; + END IF ; + PrintMemoryMessage ( + MsgVDM,ErrLdMemInfo, "[FileName]="&FileName + ); + WHILE (NOT ENDFILE(fptr)) LOOP + ReadLine(Fptr, OneLine); + LineNo := LineNo + 1 ; + -- First ignoring leading spaces. + WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP + READ (OneLine, Ignore) ; -- Ignoring the space character. + END LOOP ; + -- Note that, by now oneline has been "stripped" of its leading spaces. + IF ( OneLine(1) = '@' ) THEN + READ (OneLine, Ignore); -- Ignore the '@' character and read the string. + -- Now strip off spaces, if any, between '@' and Address string. + WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP + READ (OneLine, Ignore) ; -- Ignoring the space character. + END LOOP ; + -- Now get the string which represents the address into string variable. + Index := 1; + WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP + READ(OneLine, AddrStr(Index)); + Index := Index + 1; + END LOOP ; + AddrStr(Index) := NUL; + -- Now convert the hex string into a hex integer + Address := HexToInt(AddrStr) ; + ELSE + IF ( LineNo /= 1 ) THEN + Address := Address + 1; + END IF; + END IF ; + IF ( Address > (MemoryPtr.NoOfWords - 1) ) THEN + PrintMemoryMessage (MsgVDM, ErrLdAddrRng, + "[Address,lineno]=", Address, LineNo) ; + EXIT ; + END IF; + -- Now strip off spaces, between Address string and DataInBus string. + WHILE (OneLine'LENGTH /= 0 AND IsSpace(OneLine(1))) LOOP + READ (OneLine, Ignore) ; -- Ignoring the space character. + END LOOP ; + Index := 1; + WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP + READ(OneLine, DataInStr(Index)); + Index := Index + 1; + END LOOP ; + DataInStr(Index) := NUL; + IF (BinaryFile) THEN + DataInBus := BinToBitv (DataInStr); + ELSE + DataInBus := HexToBitv (DataInStr); + END IF ; + WriteMemory (MemoryPtr, DataInBus, Address); + END LOOP ; +END LoadMemory; + +-- ---------------------------------------------------------------------------- +-- Procedure: MemoryMatch +-- Parameters: Symbol - Symbol from memory table +-- TestFlag - Interpreted data or address symbol +-- In2 - input from VitalMemoryTable procedure +-- to memory table +-- In2LastValue - Previous value of input +-- Err - TRUE if symbol is not a valid input symbol +-- ReturnValue - TRUE if match occurred +-- Description: This procedure sets ReturnValue to true if in2 matches +-- symbol (from the memory table). If symbol is an edge +-- value edge is set to true and in2 and in2LastValue are +-- checked against symbol. Err is set to true if symbol +-- is an invalid value for the input portion of the memory +-- table. +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryMatch ( + CONSTANT Symbol : IN VitalMemorySymbolType; + CONSTANT In2 : IN std_ulogic; + CONSTANT In2LastValue : IN std_ulogic; + VARIABLE Err : OUT BOOLEAN; + VARIABLE ReturnValue : OUT BOOLEAN +) IS +BEGIN + IF (NOT ValidMemoryTableInput(Symbol) ) THEN + PrintMemoryMessage(MsgVMT,ErrUnknSymbol,To_MemoryChar(Symbol)); + Err := TRUE; + ReturnValue := FALSE; + ELSE + ReturnValue := MemoryTableMatch(To_X01(In2LastValue), To_X01(In2), Symbol); + Err := FALSE; + END IF; +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryMatch ( + CONSTANT Symbol : IN VitalMemorySymbolType; + CONSTANT TestFlag : IN VitalMemorySymbolType; + VARIABLE Err : OUT BOOLEAN; + VARIABLE ReturnValue : OUT BOOLEAN +) IS +BEGIN + Err := FALSE; + ReturnValue := FALSE; + CASE Symbol IS + WHEN 'g'|'u'|'i'|'G'|'U'|'I'|'-'|'*'|'S' => + IF (Symbol = TestFlag) THEN + ReturnValue := TRUE; + ELSE + CASE Symbol IS + WHEN '-' => + ReturnValue := TRUE; + Err := FALSE; + WHEN '*' => + IF (TestFlag = 'G' OR + TestFlag = 'U' OR + TestFlag = 'I') THEN + ReturnValue := TRUE; + Err := FALSE; + END IF; + WHEN 'S' => + IF (TestFlag = 'g' OR + TestFlag = 'u' OR + TestFlag = 'i') THEN + ReturnValue := TRUE; + Err := FALSE; + END IF; + WHEN OTHERS => + ReturnValue := FALSE; + END CASE; + END IF; + WHEN OTHERS => + Err := TRUE; + RETURN; + END CASE; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: MemoryTableCorruptMask +-- Description: Compute memory and data corruption masks for memory table +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryTableCorruptMask ( + VARIABLE CorruptMask : OUT std_logic_vector; + CONSTANT Action : IN VitalMemorySymbolType; + CONSTANT EnableIndex : IN INTEGER; + CONSTANT BitsPerWord : IN INTEGER; + CONSTANT BitsPerSubWord : IN INTEGER; + CONSTANT BitsPerEnable : IN INTEGER +) IS + VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE) + := (OTHERS => '0'); + VARIABLE ViolFlAryPosn : INTEGER; + VARIABLE HighBit : INTEGER; + VARIABLE LowBit : INTEGER; +BEGIN + CASE (Action) IS + WHEN 'c'|'l'|'e' => + -- Corrupt whole word + CorruptMaskTmp := (OTHERS => 'X'); + CorruptMask := CorruptMaskTmp; + RETURN; + WHEN 'd'|'C'|'L'|'D'|'E' => + -- Process corruption below + WHEN OTHERS => + -- No data or memory corruption + CorruptMaskTmp := (OTHERS => '0'); + CorruptMask := CorruptMaskTmp; + RETURN; + END CASE; + IF (Action = 'd') THEN + CorruptMaskTmp := (OTHERS => 'X'); + CorruptMask := CorruptMaskTmp; + RETURN; + END IF; + -- Remaining are subword cases 'C', 'L', 'D', 'E' + CorruptMaskTmp := (OTHERS => '0'); + LowBit := 0; + HighBit := BitsPerSubWord-1; + SubWordLoop: + FOR i IN 0 TO BitsPerEnable-1 LOOP + IF (i = EnableIndex) THEN + FOR j IN HighBit TO LowBit LOOP + CorruptMaskTmp(j) := 'X'; + END LOOP; + END IF; + -- Calculate HighBit and LowBit + LowBit := LowBit + BitsPerSubWord; + IF (LowBit > BitsPerWord) THEN + LowBit := BitsPerWord; + END IF; + HighBit := LowBit + BitsPerSubWord; + IF (HighBit > BitsPerWord) THEN + HighBit := BitsPerWord; + ELSE + HighBit := HighBit - 1; + END IF; + END LOOP; + CorruptMask := CorruptMaskTmp; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryTableCorruptMask ( + VARIABLE CorruptMask : OUT std_logic_vector; + CONSTANT Action : IN VitalMemorySymbolType +) IS + VARIABLE CorruptMaskTmp : std_logic_vector (0 TO CorruptMask'LENGTH-1) + := (OTHERS => '0'); + VARIABLE ViolFlAryPosn : INTEGER; + VARIABLE HighBit : INTEGER; + VARIABLE LowBit : INTEGER; +BEGIN + CASE (Action) IS + WHEN 'c'|'l'|'d'|'e'|'C'|'L'|'D'|'E' => + -- Corrupt whole word + CorruptMaskTmp := (OTHERS => 'X'); + CorruptMask := CorruptMaskTmp; + RETURN; + WHEN OTHERS => + -- No data or memory corruption + CorruptMaskTmp := (OTHERS => '0'); + CorruptMask := CorruptMaskTmp; + RETURN; + END CASE; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: MemoryTableCorruptMask +-- Description: Compute memory and data corruption masks for violation table +-- ---------------------------------------------------------------------------- +PROCEDURE ViolationTableCorruptMask ( + VARIABLE CorruptMask : OUT std_logic_vector; + CONSTANT Action : IN VitalMemorySymbolType; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationFlagsArray : IN std_logic_vector; + CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT TableIndex : IN INTEGER; + CONSTANT BitsPerWord : IN INTEGER; + CONSTANT BitsPerSubWord : IN INTEGER; + CONSTANT BitsPerEnable : IN INTEGER +) IS + VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE) + := (OTHERS => '0'); + VARIABLE ViolMaskTmp : std_logic_vector (CorruptMask'RANGE) + := (OTHERS => '0'); + VARIABLE ViolFlAryPosn : INTEGER; + VARIABLE HighBit : INTEGER; + VARIABLE LowBit : INTEGER; + CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH; + CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH; + CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1); + CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2); + CONSTANT DatActionNdx : INTEGER := TableWidth - 1; + CONSTANT MemActionNdx : INTEGER := TableWidth - 2; +BEGIN + CASE (Action) IS + WHEN 'c'|'l'|'e' => + -- Corrupt whole word + CorruptMaskTmp := (OTHERS => 'X'); + CorruptMask := CorruptMaskTmp; + RETURN; + WHEN 'd'|'C'|'L'|'D'|'E' => + -- Process corruption below + WHEN OTHERS => + -- No data or memory corruption + CorruptMaskTmp := (OTHERS => '0'); + CorruptMask := CorruptMaskTmp; + RETURN; + END CASE; + RowLoop: -- Check each element of the ViolationFlags + FOR j IN 0 TO ViolFlagsSize LOOP + IF (j = ViolFlagsSize) THEN + ViolFlAryPosn := 0; + RowLoop2: -- Check relevant elements of the ViolationFlagsArray + FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP + IF (ViolationTable(TableIndex, k + ViolFlagsSize) = 'X') THEN + MaskLoop: -- Set the 'X' bits in the violation mask + FOR m IN INTEGER RANGE 0 TO CorruptMask'LENGTH-1 LOOP + IF (m <= ViolationSizesArray(k)-1) THEN + ViolMaskTmp(m) := ViolMaskTmp(m) XOR + ViolationFlagsArray(ViolFlAryPosn+m); + ELSE + EXIT MaskLoop; + END IF; + END LOOP; + END IF; + ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k); + END LOOP; + ELSE + IF (ViolationTable(TableIndex, j) = 'X') THEN + ViolMaskTmp(0) := ViolMaskTmp(0) XOR ViolationFlags(j); + END IF; + END IF; + END LOOP; + IF (Action = 'd') THEN + CorruptMask := ViolMaskTmp; + RETURN; + END IF; + -- Remaining are subword cases 'C', 'L', 'D', 'E' + CorruptMaskTmp := (OTHERS => '0'); + LowBit := 0; + HighBit := BitsPerSubWord-1; + SubWordLoop: + FOR i IN 0 TO BitsPerEnable-1 LOOP + IF (ViolMaskTmp(i) = 'X') THEN + FOR j IN HighBit TO LowBit LOOP + CorruptMaskTmp(j) := 'X'; + END LOOP; + END IF; + -- Calculate HighBit and LowBit + LowBit := LowBit + BitsPerSubWord; + IF (LowBit > BitsPerWord) THEN + LowBit := BitsPerWord; + END IF; + HighBit := LowBit + BitsPerSubWord; + IF (HighBit > BitsPerWord) THEN + HighBit := BitsPerWord; + ELSE + HighBit := HighBit - 1; + END IF; + END LOOP; + CorruptMask := CorruptMaskTmp; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: MemoryTableLookUp +-- Parameters: MemoryAction - Output memory action to be performed +-- DataAction - Output data action to be performed +-- PrevControls - Previous data in for edge detection +-- PrevEnableBus - Previous enables for edge detection +-- Controls - Agregate of scalar control lines +-- EnableBus - Concatenation of vector control lines +-- EnableIndex - Current slice of vector control lines +-- AddrFlag - Matching symbol from address decoding +-- DataFlag - Matching symbol from data decoding +-- MemoryTable - Input memory action table +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control message output +-- +-- Description: This function is used to find the output of the +-- MemoryTable corresponding to a given set of inputs. +-- +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryTableLookUp ( + VARIABLE MemoryAction : OUT VitalMemorySymbolType; + VARIABLE DataAction : OUT VitalMemorySymbolType; + VARIABLE MemoryCorruptMask : OUT std_logic_vector; + VARIABLE DataCorruptMask : OUT std_logic_vector; + CONSTANT PrevControls : IN std_logic_vector; + CONSTANT Controls : IN std_logic_vector; + CONSTANT AddrFlag : IN VitalMemorySymbolType; + CONSTANT DataFlag : IN VitalMemorySymbolType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + CONSTANT ControlsSize : INTEGER := Controls'LENGTH; + CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1); + CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2); + CONSTANT DatActionNdx : INTEGER := TableWidth - 1; + CONSTANT MemActionNdx : INTEGER := TableWidth - 2; + CONSTANT DataInBusNdx : INTEGER := TableWidth - 3; + CONSTANT AddressBusNdx : INTEGER := TableWidth - 4; + VARIABLE AddrFlagTable : VitalMemorySymbolType; + VARIABLE Match : BOOLEAN; + VARIABLE Err : BOOLEAN := FALSE; + VARIABLE TableAlias : VitalMemoryTableType( + 0 TO TableEntries - 1, + 0 TO TableWidth - 1) + := MemoryTable; +BEGIN + ColLoop: -- Compare each entry in the table + FOR i IN TableAlias'RANGE(1) LOOP + RowLoop: -- Check each element of the Controls + FOR j IN 0 TO ControlsSize LOOP + IF (j = ControlsSize) THEN + -- a match occurred, now check AddrFlag, DataFlag + MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match); + IF (Match) THEN + MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match); + IF (Match) THEN + MemoryTableCorruptMask ( + CorruptMask => MemoryCorruptMask , + Action => TableAlias(i, MemActionNdx) + ); + MemoryTableCorruptMask ( + CorruptMask => DataCorruptMask , + Action => TableAlias(i, DatActionNdx) + ); + -- get the return memory and data actions + MemoryAction := TableAlias(i, MemActionNdx); + DataAction := TableAlias(i, DatActionNdx); + -- DEBUG: The lines below report table search + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMT,TableAlias,i,PortName); + END IF; + -- DEBUG: The lines above report table search + RETURN; + END IF; + END IF; + ELSE + -- Match memory table inputs + MemoryMatch ( TableAlias(i,j), + Controls(j), PrevControls(j), + Err, Match); + END IF; + EXIT RowLoop WHEN NOT(Match); + EXIT ColLoop WHEN Err; + END LOOP RowLoop; + END LOOP ColLoop; + -- no match found, return default action + MemoryAction := 's'; -- no change to memory + DataAction := 'S'; -- no change to dataout + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName); + END IF; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +PROCEDURE MemoryTableLookUp ( + VARIABLE MemoryAction : OUT VitalMemorySymbolType; + VARIABLE DataAction : OUT VitalMemorySymbolType; + VARIABLE MemoryCorruptMask : OUT std_logic_vector; + VARIABLE DataCorruptMask : OUT std_logic_vector; + CONSTANT PrevControls : IN std_logic_vector; + CONSTANT PrevEnableBus : IN std_logic_vector; + CONSTANT Controls : IN std_logic_vector; + CONSTANT EnableBus : IN std_logic_vector; + CONSTANT EnableIndex : IN INTEGER; + CONSTANT BitsPerWord : IN INTEGER; + CONSTANT BitsPerSubWord : IN INTEGER; + CONSTANT BitsPerEnable : IN INTEGER; + CONSTANT AddrFlag : IN VitalMemorySymbolType; + CONSTANT DataFlag : IN VitalMemorySymbolType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + CONSTANT ControlsSize : INTEGER := Controls'LENGTH; + CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1); + CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2); + CONSTANT DatActionNdx : INTEGER := TableWidth - 1; + CONSTANT MemActionNdx : INTEGER := TableWidth - 2; + CONSTANT DataInBusNdx : INTEGER := TableWidth - 3; + CONSTANT AddressBusNdx : INTEGER := TableWidth - 4; + VARIABLE AddrFlagTable : VitalMemorySymbolType; + VARIABLE Match : BOOLEAN; + VARIABLE Err : BOOLEAN := FALSE; + VARIABLE TableAlias : VitalMemoryTableType( + 0 TO TableEntries - 1, + 0 TO TableWidth - 1) + := MemoryTable; +BEGIN + ColLoop: -- Compare each entry in the table + FOR i IN TableAlias'RANGE(1) LOOP + RowLoop: -- Check each element of the Controls + FOR j IN 0 TO ControlsSize LOOP + IF (j = ControlsSize) THEN + -- a match occurred, now check EnableBus, AddrFlag, DataFlag + IF (EnableIndex >= 0) THEN + RowLoop2: -- Check relevant elements of the EnableBus + FOR k IN 0 TO AddressBusNdx - ControlsSize - 1 LOOP + MemoryMatch ( TableAlias(i,k + ControlsSize), + EnableBus(k * BitsPerEnable + EnableIndex), + PrevEnableBus(k * BitsPerEnable + EnableIndex), + Err, Match); + EXIT RowLoop2 WHEN NOT(Match); + END LOOP; + END IF; + IF (Match) THEN + MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match); + IF (Match) THEN + MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match); + IF (Match) THEN + MemoryTableCorruptMask ( + CorruptMask => MemoryCorruptMask , + Action => TableAlias(i, MemActionNdx), + EnableIndex => EnableIndex , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable + ); + MemoryTableCorruptMask ( + CorruptMask => DataCorruptMask , + Action => TableAlias(i, DatActionNdx), + EnableIndex => EnableIndex , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable + ); + -- get the return memory and data actions + MemoryAction := TableAlias(i, MemActionNdx); + DataAction := TableAlias(i, DatActionNdx); + -- DEBUG: The lines below report table search + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMT,TableAlias,i,PortName); + END IF; + -- DEBUG: The lines above report table search + RETURN; + END IF; + END IF; + END IF; + ELSE + -- Match memory table inputs + MemoryMatch ( TableAlias(i,j), + Controls(j), PrevControls(j), + Err, Match); + END IF; + EXIT RowLoop WHEN NOT(Match); + EXIT ColLoop WHEN Err; + END LOOP RowLoop; + END LOOP ColLoop; + -- no match found, return default action + MemoryAction := 's'; -- no change to memory + DataAction := 'S'; -- no change to dataout + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName); + END IF; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: ViolationTableLookUp +-- Parameters: MemoryAction - Output memory action to be performed +-- DataAction - Output data action to be performed +-- TimingDataArray - This is currently not used (comment out) +-- ViolationArray - Aggregation of violation variables +-- ViolationTable - Input memory violation table +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control message output +-- Description: This function is used to find the output of the +-- ViolationTable corresponding to a given set of inputs. +-- ---------------------------------------------------------------------------- +PROCEDURE ViolationTableLookUp ( + VARIABLE MemoryAction : OUT VitalMemorySymbolType; + VARIABLE DataAction : OUT VitalMemorySymbolType; + VARIABLE MemoryCorruptMask : OUT std_logic_vector; + VARIABLE DataCorruptMask : OUT std_logic_vector; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationFlagsArray : IN std_logic_vector; + CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT BitsPerWord : IN INTEGER; + CONSTANT BitsPerSubWord : IN INTEGER; + CONSTANT BitsPerEnable : IN INTEGER; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH; + CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH; + VARIABLE ViolFlAryPosn : INTEGER; + VARIABLE ViolFlAryItem : std_ulogic; + CONSTANT ViolSzArySize : INTEGER := ViolationSizesArray'LENGTH; + CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1); + CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2); + CONSTANT DatActionNdx : INTEGER := TableWidth - 1; + CONSTANT MemActionNdx : INTEGER := TableWidth - 2; + VARIABLE HighBit : NATURAL := 0; + VARIABLE LowBit : NATURAL := 0; + VARIABLE Match : BOOLEAN; + VARIABLE Err : BOOLEAN := FALSE; + VARIABLE TableAlias : VitalMemoryTableType( + 0 TO TableEntries - 1, + 0 TO TableWidth - 1) + := ViolationTable; +BEGIN + ColLoop: -- Compare each entry in the table + FOR i IN TableAlias'RANGE(1) LOOP + RowLoop: -- Check each element of the ViolationFlags + FOR j IN 0 TO ViolFlagsSize LOOP + IF (j = ViolFlagsSize) THEN + ViolFlAryPosn := 0; + RowLoop2: -- Check relevant elements of the ViolationFlagsArray + FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP + ViolFlAryItem := '0'; + SubwordLoop: -- Check for 'X' in ViolationFlagsArray chunk + FOR s IN ViolFlAryPosn TO ViolFlAryPosn+ViolationSizesArray(k)-1 LOOP + IF (ViolationFlagsArray(s) = 'X') THEN + ViolFlAryItem := 'X'; + EXIT SubwordLoop; + END IF; + END LOOP; + MemoryMatch ( TableAlias(i,k + ViolFlagsSize), + ViolFlAryItem,ViolFlAryItem, + Err, Match); + ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k); + EXIT RowLoop2 WHEN NOT(Match); + END LOOP; + IF (Match) THEN + -- Compute memory and data corruption masks + ViolationTableCorruptMask( + CorruptMask => MemoryCorruptMask , + Action => TableAlias(i, MemActionNdx), + ViolationFlags => ViolationFlags , + ViolationFlagsArray => ViolationFlagsArray , + ViolationSizesArray => ViolationSizesArray , + ViolationTable => ViolationTable , + TableIndex => i , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable + ); + ViolationTableCorruptMask( + CorruptMask => DataCorruptMask , + Action => TableAlias(i, DatActionNdx), + ViolationFlags => ViolationFlags , + ViolationFlagsArray => ViolationFlagsArray , + ViolationSizesArray => ViolationSizesArray , + ViolationTable => ViolationTable , + TableIndex => i , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable + ); + -- get the return memory and data actions + MemoryAction := TableAlias(i, MemActionNdx); + DataAction := TableAlias(i, DatActionNdx); + -- DEBUG: The lines below report table search + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMV,TableAlias,i,PortName); + END IF; + -- DEBUG: The lines above report table search + RETURN; + END IF; + ELSE + -- Match violation table inputs + Err := FALSE; + Match := FALSE; + IF (TableAlias(i,j) /= 'X' AND + TableAlias(i,j) /= '0' AND + TableAlias(i,j) /= '-') THEN + Err := TRUE; + ELSIF (TableAlias(i,j) = '-' OR + (TableAlias(i,j) = 'X' AND ViolationFlags(j) = 'X') OR + (TableAlias(i,j) = '0' AND ViolationFlags(j) = '0')) THEN + Match := TRUE; + END IF; + END IF; + EXIT RowLoop WHEN NOT(Match); + EXIT ColLoop WHEN Err; + END LOOP RowLoop; + END LOOP ColLoop; + -- no match found, return default action + MemoryAction := 's'; -- no change to memory + DataAction := 'S'; -- no change to dataout + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMV,ErrDefMemAct,HeaderMsg,PortName); + END IF; + RETURN; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: HandleMemoryAction +-- Parameters: MemoryData - Pointer to memory data structure +-- PortFlag - Indicates read/write mode of port +-- CorruptMask - XOR'ed with DataInBus when corrupting +-- DataInBus - Current data bus in +-- Address - Current address integer +-- HighBit - Current address high bit +-- LowBit - Current address low bit +-- MemoryTable - Input memory action table +-- MemoryAction - Memory action to be performed +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control message output +-- Description: This procedure performs the specified memory action on +-- the input memory data structure. +-- ---------------------------------------------------------------------------- +PROCEDURE HandleMemoryAction ( + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagType; + CONSTANT CorruptMask : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT HighBit : IN NATURAL; + CONSTANT LowBit : IN NATURAL; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT MemoryAction : IN VitalMemorySymbolType; + CONSTANT CallerName : IN STRING; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + VARIABLE DataInTmp : std_logic_vector(DataInBus'RANGE) + := DataInBus; + BEGIN + + -- Handle the memory action + CASE MemoryAction IS + + WHEN 'w' => + -- Writing data to memory + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrWrDatMem,HeaderMsg,PortName); + END IF; + WriteMemory(MemoryData,DataInBus,Address,HighBit,LowBit); + PortFlag.MemoryCurrent := WRITE; + + WHEN 's' => + -- Retaining previous memory contents + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrNoChgMem,HeaderMsg,PortName); + END IF; + -- Set memory current to quiet state + PortFlag.MemoryCurrent := READ; + + WHEN 'c' => + -- Corrupting entire memory with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrAllMem,HeaderMsg,PortName); + END IF; + DataInTmp := (OTHERS => 'X'); + -- No need to CorruptMask + FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP + WriteMemory(MemoryData,DataInTmp,i); + END LOOP; + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'l' => + -- Corrupting a word in memory with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrWrdMem,HeaderMsg,PortName); + END IF; + DataInTmp := (OTHERS => 'X'); + -- No need to CorruptMask + WriteMemory(MemoryData,DataInTmp,Address); + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'd' => + -- Corrupting a single bit in memory with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrBitMem,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataInTmp,Address); + DataInTmp := DataInTmp XOR CorruptMask; + WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit); + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'e' => + -- Corrupting a word with 'X' based on data in + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrDatMem,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataInTmp,Address); + IF (DataInTmp /= DataInBus) THEN + DataInTmp := (OTHERS => 'X'); + -- No need to CorruptMask + WriteMemory(MemoryData,DataInTmp,Address); + END IF; + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'C' => + -- Corrupting a sub-word entire memory with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrAllSubMem,HeaderMsg,PortName); + END IF; + FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP + ReadMemory(MemoryData,DataInTmp,i); + DataInTmp := DataInTmp XOR CorruptMask; + WriteMemory(MemoryData,DataInTmp,i,HighBit,LowBit); + END LOOP; + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'L' => + -- Corrupting a sub-word in memory with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrWrdSubMem,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataInTmp,Address); + DataInTmp := DataInTmp XOR CorruptMask; + WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit); + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'D' => + -- Corrupting a single bit of a memory sub-word with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrBitSubMem,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataInTmp,Address); + DataInTmp := DataInTmp XOR CorruptMask; + WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit); + PortFlag.MemoryCurrent := CORRUPT; + + WHEN 'E' => + -- Corrupting a sub-word with 'X' based on data in + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrDatSubMem,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataInTmp,Address); + IF (DataInBus(HighBit DOWNTO LowBit) /= + DataInTmp(HighBit DOWNTO LowBit)) THEN + DataInTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit); + END IF; + --PortFlag := WRITE; + PortFlag.MemoryCurrent := CORRUPT; + + WHEN '0' => + -- Assigning low level to memory location + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsg0Mem,HeaderMsg,PortName); + END IF; + DataInTmp := (OTHERS => '0'); + WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit); + PortFlag.MemoryCurrent := WRITE; + + WHEN '1' => + -- Assigning high level to memory location + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsg1Mem,HeaderMsg,PortName); + END IF; + DataInTmp := (OTHERS => '1'); + WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit); + PortFlag.MemoryCurrent := WRITE; + + WHEN 'Z' => + -- Assigning high impedence to memory location + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsgZMem,HeaderMsg,PortName); + END IF; + DataInTmp := (OTHERS => 'Z'); + WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit); + PortFlag.MemoryCurrent := WRITE; + + WHEN OTHERS => + -- Unknown memory action + PortFlag.MemoryCurrent := UNDEF; + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrUnknMemDo,HeaderMsg,PortName); + END IF; + + END CASE; + + -- Note: HandleMemoryAction does not change the PortFlag.OutputDisable +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: HandleDataAction +-- Parameters: DataOutBus - Output result of the data action +-- MemoryData - Input pointer to memory data structure +-- PortFlag - Indicates read/write mode of port +-- CorruptMask - XOR'ed with DataInBus when corrupting +-- DataInBus - Current data bus in +-- Address - Current address integer +-- HighBit - Current address high bit +-- LowBit - Current address low bit +-- MemoryTable - Input memory action table +-- DataAction - Data action to be performed +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control message output +-- Description: This procedure performs the specified data action based +-- on the input memory data structure. Checks whether +-- the previous state is HighZ. If yes then portFlag +-- should be NOCHANGE for VMPD to ignore IORetain +-- corruption. The idea is that the first Z should be +-- propagated but later ones should be ignored. +-- ---------------------------------------------------------------------------- +PROCEDURE HandleDataAction ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagType; + CONSTANT CorruptMask : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT Address : IN INTEGER; + CONSTANT HighBit : IN NATURAL; + CONSTANT LowBit : IN NATURAL; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT DataAction : IN VitalMemorySymbolType; + CONSTANT CallerName : IN STRING; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + + VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) + := DataOutBus; + +BEGIN + + -- Handle the data action + CASE DataAction IS + + WHEN 'l' => + -- Corrupting data out with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrWrdOut,HeaderMsg,PortName); + END IF; + DataOutTmp := (OTHERS => 'X'); + -- No need to CorruptMask + PortFlag.DataCurrent := CORRUPT; + + WHEN 'd' => + -- Corrupting a single bit of data out with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrBitOut,HeaderMsg,PortName); + END IF; + DataOutTmp(HighBit DOWNTO LowBit) := + DataOutTmp(HighBit DOWNTO LowBit) XOR + CorruptMask(HighBit DOWNTO LowBit); + PortFlag.DataCurrent := CORRUPT; + + WHEN 'e' => + -- Corrupting data out with 'X' based on data in + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrDatOut,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataOutTmp,Address); + IF (DataOutTmp /= DataInBus) THEN + DataOutTmp := (OTHERS => 'X'); + -- No need to CorruptMask + END IF; + PortFlag.DataCurrent := CORRUPT; + + WHEN 'L' => + -- Corrupting data out sub-word with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrWrdSubOut,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataOutTmp,Address); + DataOutTmp(HighBit DOWNTO LowBit) := + DataOutTmp(HighBit DOWNTO LowBit) XOR + CorruptMask(HighBit DOWNTO LowBit); + PortFlag.DataCurrent := CORRUPT; + + WHEN 'D' => + -- Corrupting a single bit of data out sub-word with 'X' + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrBitSubOut,HeaderMsg,PortName); + END IF; + DataOutTmp(HighBit DOWNTO LowBit) := + DataOutTmp(HighBit DOWNTO LowBit) XOR + CorruptMask(HighBit DOWNTO LowBit); + PortFlag.DataCurrent := CORRUPT; + + WHEN 'E' => + -- Corrupting data out sub-word with 'X' based on data in + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrCrDatSubOut,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataOutTmp,Address); + IF (DataInBus(HighBit DOWNTO LowBit) /= + DataOutTmp(HighBit DOWNTO LowBit)) THEN + DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + -- No need to CorruptMask + END IF; + PortFlag.DataCurrent := CORRUPT; + + WHEN 'M' => + -- Implicit read from memory to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrImplOut,HeaderMsg,PortName); + END IF; + PortFlag.DataCurrent := READ; + + WHEN 'm' => + -- Reading data from memory to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrReadOut,HeaderMsg,PortName); + END IF; + ReadMemory(MemoryData,DataOutTmp,Address); + PortFlag.DataCurrent := READ; + + WHEN 't' => + -- Transferring from data in to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAssgOut,HeaderMsg,PortName); + END IF; + DataOutTmp := DataInBus; + PortFlag.DataCurrent := READ; + + WHEN '0' => + -- Assigning low level to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsg0Out,HeaderMsg,PortName); + END IF; + DataOutTmp := (OTHERS => '0'); + PortFlag.DataCurrent := READ; + + WHEN '1' => + -- Assigning high level to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsg1Out,HeaderMsg,PortName); + END IF; + DataOutTmp := (OTHERS => '1'); + PortFlag.DataCurrent := READ; + + WHEN 'Z' => + -- Assigning high impedence to data out + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsgZOut,HeaderMsg,PortName); + END IF; + DataOutTmp := (OTHERS => 'Z'); + PortFlag.DataCurrent := HIGHZ; + + WHEN 'S' => + -- Keeping data out at steady value + PortFlag.OutputDisable := TRUE; + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrAsgSOut,HeaderMsg,PortName); + END IF; + + WHEN OTHERS => + -- Unknown data action + PortFlag.DataCurrent := UNDEF; + IF (MsgOn) THEN + PrintMemoryMessage(CallerName,ErrUnknDatDo,HeaderMsg,PortName); + END IF; + + END CASE; + + DataOutBus(HighBit DOWNTO LowBit) := DataOutTmp(HighBit DOWNTO LowBit); + +END; + + +-- ---------------------------------------------------------------------------- +-- Memory Table Modeling Primitives +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalDeclareMemory +-- Parameters: NoOfWords - Number of words in the memory +-- NoOfBitsPerWord - Number of bits per word in memory +-- NoOfBitsPerSubWord - Number of bits per sub word +-- MemoryLoadFile - Name of data file to load +-- Description: This function is intended to be used to initialize +-- memory data declarations, i.e. to be executed duing +-- simulation elaboration time. Handles the allocation +-- and initialization of memory for the memory data. +-- Default NoOfBitsPerSubWord is NoOfBitsPerWord. +-- ---------------------------------------------------------------------------- +IMPURE FUNCTION VitalDeclareMemory ( + CONSTANT NoOfWords : IN POSITIVE; + CONSTANT NoOfBitsPerWord : IN POSITIVE; + CONSTANT MemoryLoadFile : IN string := ""; + CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE +) RETURN VitalMemoryDataType IS + VARIABLE MemoryPtr : VitalMemoryDataType; +BEGIN + MemoryPtr := VitalDeclareMemory( + NoOfWords => NoOfWords, + NoOfBitsPerWord => NoOfBitsPerWord, + NoOfBitsPerSubWord => NoOfBitsPerWord, + MemoryLoadFile => MemoryLoadFile, + BinaryLoadFile => BinaryLoadFile + ); + RETURN MemoryPtr; +END; + +-- ---------------------------------------------------------------------------- +IMPURE FUNCTION VitalDeclareMemory ( + CONSTANT NoOfWords : IN POSITIVE; + CONSTANT NoOfBitsPerWord : IN POSITIVE; + CONSTANT NoOfBitsPerSubWord : IN POSITIVE; + CONSTANT MemoryLoadFile : IN string := ""; + CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE +) RETURN VitalMemoryDataType IS + VARIABLE MemoryPtr : VitalMemoryDataType; + VARIABLE BitsPerEnable : NATURAL + := ((NoOfBitsPerWord-1) + /NoOfBitsPerSubWord)+1; +BEGIN + PrintMemoryMessage(MsgVDM,ErrInitMem); + MemoryPtr := new VitalMemoryArrayRecType '( + NoOfWords => NoOfWords, + NoOfBitsPerWord => NoOfBitsPerWord, + NoOfBitsPerSubWord => NoOfBitsPerSubWord, + NoOfBitsPerEnable => BitsPerEnable, + MemoryArrayPtr => NULL + ); + MemoryPtr.MemoryArrayPtr + := new MemoryArrayType (0 to MemoryPtr.NoOfWords - 1); + FOR i IN 0 TO MemoryPtr.NoOfWords - 1 LOOP + MemoryPtr.MemoryArrayPtr(i) + := new MemoryWordType (MemoryPtr.NoOfBitsPerWord - 1 DOWNTO 0); + END LOOP; + IF (MemoryLoadFile /= "") THEN + LoadMemory (MemoryPtr, MemoryLoadFile, BinaryLoadFile); + END IF; + RETURN MemoryPtr; +END; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryTable +-- Parameters: DataOutBus - Output candidate zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- PrevControls - Previous data in for edge detection +-- PrevEnableBus - Previous enables for edge detection +-- PrevDataInBus - Previous data bus for edge detection +-- PrevAddressBus - Previous address bus for edge detection +-- PortFlag - Indicates port operating mode +-- PortFlagArray - Vector form of PortFlag for sub-word +-- Controls - Agregate of scalar control lines +-- EnableBus - Concatenation of vector control lines +-- DataInBus - Input value of data bus in +-- AddressBus - Input value of address bus in +-- AddressValue - Decoded value of the AddressBus +-- MemoryTable - Input memory action table +-- PortType - The type of port (currently not used) +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- MsgSeverity - Control level of message generation +-- Description: This procedure implements the majority of the memory +-- modeling functionality via lookup of the memory action +-- tables and performing the specified actions if matches +-- are found, or the default actions otherwise. The +-- overloadings are provided for the word and sub-word +-- (using the EnableBus and PortFlagArray arguments) addressing +-- cases. +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryTable ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PrevControls : INOUT std_logic_vector; + VARIABLE PrevDataInBus : INOUT std_logic_vector; + VARIABLE PrevAddressBus : INOUT std_logic_vector; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT Controls : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressBus : IN std_logic_vector; + VARIABLE AddressValue : INOUT VitalAddressValueType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType := UNDEF; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + + VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) + := DataOutBus; + VARIABLE MemoryAction : VitalMemorySymbolType; + VARIABLE DataAction : VitalMemorySymbolType; + VARIABLE HighBit : NATURAL := MemoryData.NoOfBitsPerWord-1; + VARIABLE LowBit : NATURAL := 0; + VARIABLE Address : INTEGER := 0; + VARIABLE PortFlagTmp : VitalPortFlagType; + VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr + VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data + VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE); + VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE); + +BEGIN + + -- Optimize for case when all current inputs are same as previous + IF (PrevDataInBus = DataInBus + AND PrevAddressBus = AddressBus + AND PrevControls = Controls + AND PortFlag(0).MemoryCurrent = PortFlag(0).MemoryPrevious + AND PortFlag(0).DataCurrent = PortFlag(0).DataPrevious) THEN + PortFlag(0).OutputDisable := TRUE; + RETURN; + END IF; + + PortFlag(0).DataPrevious := PortFlag(0).DataCurrent; + PortFlag(0).MemoryPrevious := PortFlag(0).MemoryCurrent; + PortFlag(0).OutputDisable := FALSE; + PortFlagTmp := PortFlag(0); + + -- Convert address bus to integer value and table lookup flag + DecodeAddress( + Address => Address , + AddrFlag => AddrFlag , + MemoryData => MemoryData , + PrevAddressBus => PrevAddressBus , + AddressBus => AddressBus + ); + + -- Interpret data bus as a table lookup flag + DecodeData ( + DataFlag => DataFlag , + PrevDataInBus => PrevDataInBus , + DataInBus => DataInBus , + HighBit => HighBit , + LowBit => LowBit + ); + + -- Lookup memory and data actions + MemoryTableLookUp( + MemoryAction => MemoryAction , + DataAction => DataAction , + MemoryCorruptMask => MemCorruptMask , + DataCorruptMask => DatCorruptMask , + PrevControls => PrevControls , + Controls => Controls , + AddrFlag => AddrFlag , + DataFlag => DataFlag , + MemoryTable => MemoryTable , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + -- Handle data action before memory action + -- This allows reading previous memory contents + HandleDataAction( + DataOutBus => DataOutTmp , + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => DatCorruptMask , + DataInBus => DataInBus , + Address => Address , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => MemoryTable , + DataAction => DataAction , + CallerName => MsgVMT , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + HandleMemoryAction( + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => MemCorruptMask , + DataInBus => DataInBus , + Address => Address , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => MemoryTable , + MemoryAction => MemoryAction , + CallerName => MsgVMT , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + -- Set the output PortFlag(0) value + IF (DataAction = 'S') THEN + PortFlagTmp.OutputDisable := TRUE; + END IF; + IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious + AND PortFlagTmp.DataCurrent = HIGHZ) THEN + PortFlagTmp.OutputDisable := TRUE; + END IF; + PortFlag(0) := PortFlagTmp; + + -- Set previous values for subsequent edge detection + PrevControls := Controls; + PrevDataInBus := DataInBus; + PrevAddressBus := AddressBus; + + -- Set the candidate zero delay return value + DataOutBus := DataOutTmp; + + -- Set the output AddressValue for VitalMemoryCrossPorts + AddressValue := Address; + +END VitalMemoryTable; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryTable ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PrevControls : INOUT std_logic_vector; + VARIABLE PrevEnableBus : INOUT std_logic_vector; + VARIABLE PrevDataInBus : INOUT std_logic_vector; + VARIABLE PrevAddressBus : INOUT std_logic_vector; + VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType; + CONSTANT Controls : IN std_logic_vector; + CONSTANT EnableBus : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressBus : IN std_logic_vector; + VARIABLE AddressValue : INOUT VitalAddressValueType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType := UNDEF; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + + VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord; + VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord; + VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable; + VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) + := DataOutBus; + VARIABLE MemoryAction : VitalMemorySymbolType; + VARIABLE DataAction : VitalMemorySymbolType; + VARIABLE HighBit : NATURAL := BitsPerSubWord-1; + VARIABLE LowBit : NATURAL := 0; + VARIABLE Address : INTEGER := 0; + VARIABLE PortFlagTmp : VitalPortFlagType; + VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr + VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data + VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE); + VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE); + +BEGIN + + -- Optimize for case when all current inputs are same as previous + IF (PrevDataInBus = DataInBus + AND PrevAddressBus = AddressBus + AND PrevControls = Controls) THEN + CheckFlags: + FOR i IN 0 TO BitsPerEnable-1 LOOP + IF (PortFlagArray(i).MemoryCurrent /= PortFlagArray(i).MemoryPrevious + OR PortFlagArray(i).DataCurrent /= PortFlagArray(i).DataPrevious) THEN + EXIT CheckFlags; + END IF; + IF (i = BitsPerEnable-1) THEN + FOR j IN 0 TO BitsPerEnable-1 LOOP + PortFlagArray(j).OutputDisable := TRUE; + END LOOP; + RETURN; + END IF; + END LOOP; + END IF; + + -- Convert address bus to integer value and table lookup flag + DecodeAddress( + Address => Address, + AddrFlag => AddrFlag, + MemoryData => MemoryData, + PrevAddressBus => PrevAddressBus, + AddressBus => AddressBus + ); + + -- Perform independent operations for each sub-word + FOR i IN 0 TO BitsPerEnable-1 LOOP + + -- Set the output PortFlag(i) value + PortFlagArray(i).DataPrevious := PortFlagArray(i).DataCurrent; + PortFlagArray(i).MemoryPrevious := PortFlagArray(i).MemoryCurrent; + PortFlagArray(i).OutputDisable := FALSE; + PortFlagTmp := PortFlagArray(i); + + -- Interpret data bus as a table lookup flag + DecodeData ( + DataFlag => DataFlag , + PrevDataInBus => PrevDataInBus , + DataInBus => DataInBus , + HighBit => HighBit , + LowBit => LowBit + ); + + -- Lookup memory and data actions + MemoryTableLookUp( + MemoryAction => MemoryAction , + DataAction => DataAction , + MemoryCorruptMask => MemCorruptMask , + DataCorruptMask => DatCorruptMask , + PrevControls => PrevControls , + PrevEnableBus => PrevEnableBus , + Controls => Controls , + EnableBus => EnableBus , + EnableIndex => i , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable , + AddrFlag => AddrFlag , + DataFlag => DataFlag , + MemoryTable => MemoryTable , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + -- Handle data action before memory action + -- This allows reading previous memory contents + HandleDataAction( + DataOutBus => DataOutTmp , + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => DatCorruptMask , + DataInBus => DataInBus , + Address => Address , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => MemoryTable , + DataAction => DataAction , + CallerName => MsgVMT , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + HandleMemoryAction( + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => MemCorruptMask , + DataInBus => DataInBus , + Address => Address , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => MemoryTable , + MemoryAction => MemoryAction , + CallerName => MsgVMT , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + -- Set the output PortFlag(i) value + IF (DataAction = 'S') THEN + PortFlagTmp.OutputDisable := TRUE; + END IF; + IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious + AND PortFlagTmp.DataCurrent = HIGHZ) THEN + PortFlagTmp.OutputDisable := TRUE; + END IF; + PortFlagArray(i) := PortFlagTmp; + + IF (i < BitsPerEnable-1) THEN + -- Calculate HighBit and LowBit + LowBit := LowBit + BitsPerSubWord; + IF (LowBit > BitsPerWord) THEN + LowBit := BitsPerWord; + END IF; + HighBit := LowBit + BitsPerSubWord; + IF (HighBit > BitsPerWord) THEN + HighBit := BitsPerWord; + ELSE + HighBit := HighBit - 1; + END IF; + END IF; + + END LOOP; + + -- Set previous values for subsequent edge detection + PrevControls := Controls; + PrevEnableBus := EnableBus; + PrevDataInBus := DataInBus; + PrevAddressBus := AddressBus; + + -- Set the candidate zero delay return value + DataOutBus := DataOutTmp; + + -- Set the output AddressValue for VitalMemoryCrossPorts + AddressValue := Address; + +END VitalMemoryTable; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryCrossPorts +-- Parameters: DataOutBus - Output candidate zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- SamePortFlag - Operating mode for same port +-- SamePortAddressValue - Operating modes for cross ports +-- CrossPortAddressArray - Decoded AddressBus for cross ports +-- CrossPortMode - Write contention and crossport read control +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- Description: These procedures control the effect of memory operations +-- on a given port due to operations on other ports in a +-- multi-port memory. +-- This includes data write through when reading and writing +-- to the same address, as well as write contention when +-- there are multiple write to the same address. +-- If addresses do not match then data bus is unchanged. +-- The DataOutBus can be diabled with 'Z' value. +-- If the WritePortFlag is 'CORRUPT', that would mean +-- that the whole memory is corrupted. So, for corrupting +-- the Read port, the Addresses need not be compared. +-- +-- CrossPortMode Enum Description +-- 1. CpRead Allows Cross Port Read Only +-- No contention checking. +-- 2. WriteContention Allows for write contention checks +-- only between multiple write ports +-- 3. ReadWriteContention Allows contention between read and +-- write ports. The action is to corrupt +-- the memory and the output bus. +-- 4. CpReadAndWriteContention Is a combination of 1 & 2 +-- 5. CpReadAndReadContention Allows contention between read and +-- write ports. The action is to corrupt +-- the dataout bus only. The cp read is +-- performed if not contending. +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryCrossPorts ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType; + CONSTANT SamePortAddressValue : IN VitalAddressValueType; + CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType; + CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType; + CONSTANT CrossPortMode : IN VitalCrossPortModeType + := CpReadAndWriteContention; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + + VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord; + VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord; + VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable; + VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) := (OTHERS => 'Z'); + VARIABLE MemoryTmp : std_logic_vector(DataOutBus'RANGE); + VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH; + VARIABLE LowBit : NATURAL := 0; + VARIABLE HighBit : NATURAL := BitsPerSubWord-1; + VARIABLE Address : VitalAddressValueType := SamePortAddressValue; + VARIABLE AddressJ : VitalAddressValueType; + VARIABLE AddressK : VitalAddressValueType; + VARIABLE PortFlagI : VitalPortFlagType; + VARIABLE PortFlagIJ : VitalPortFlagType; + VARIABLE PortFlagIK : VitalPortFlagType; + VARIABLE DoCpRead : BOOLEAN := FALSE; + VARIABLE DoWrCont : BOOLEAN := FALSE; + VARIABLE DoCpCont : BOOLEAN := FALSE; + VARIABLE DoRdWrCont : BOOLEAN := FALSE; + VARIABLE CpWrCont : BOOLEAN := FALSE; + VARIABLE ModeWrCont : BOOLEAN := + (CrossPortMode=WriteContention) OR + (CrossPortMode=CpReadAndWriteContention); + VARIABLE ModeCpRead : BOOLEAN := + (CrossPortMode=CpRead) OR + (CrossPortMode=CpReadAndWriteContention); + VARIABLE ModeCpCont : BOOLEAN := (CrossPortMode=ReadWriteContention); + VARIABLE ModeRdWrCont : BOOLEAN := (CrossPortMode=CpReadAndReadContention); + +BEGIN + + -- Check for disabled port (i.e. OTHERS => 'Z') + IF (DataOutBus = DataOutTmp) THEN + RETURN; + ELSE + DataOutTmp := DataOutBus; + END IF; + + -- Check for error in address + IF (Address < 0) THEN + RETURN; + END IF; + + ReadMemory(MemoryData,MemoryTmp,Address); + + SubWordLoop: -- For each slice of the sub-word I + FOR i IN 0 TO BitsPerEnable-1 LOOP + PortFlagI := SamePortFlag(i); + + -- For each cross port J: check with same port address + FOR j IN 0 TO CrossPorts-1 LOOP + PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable); + AddressJ := CrossPortAddressArray(j); + IF (AddressJ < 0) THEN + NEXT; + END IF; + DoWrCont := (Address = AddressJ) AND + (ModeWrCont = TRUE) AND + ((PortFlagI.MemoryCurrent = WRITE) OR + (PortFlagI.MemoryCurrent = CORRUPT)) AND + ((PortFlagIJ.MemoryCurrent = WRITE) OR + (PortFlagIJ.MemoryCurrent = CORRUPT)) ; + DoCpRead := (Address = AddressJ) AND + (ModeCpRead = TRUE) AND + ((PortFlagI.MemoryCurrent = READ) OR + (PortFlagI.OutputDisable = TRUE)) AND + ((PortFlagIJ.MemoryCurrent = WRITE) OR + (PortFlagIJ.MemoryCurrent = CORRUPT)) ; + DoCpCont := (Address = AddressJ) AND + (ModeCpCont = TRUE) AND + ((PortFlagI.MemoryCurrent = READ) OR + (PortFlagI.OutputDisable = TRUE)) AND + ((PortFlagIJ.MemoryCurrent = WRITE) OR + (PortFlagIJ.MemoryCurrent = CORRUPT)) ; + DoRdWrCont:= (Address = AddressJ) AND + (ModeRdWrCont = TRUE) AND + ((PortFlagI.MemoryCurrent = READ) OR + (PortFlagI.OutputDisable = TRUE)) AND + ((PortFlagIJ.MemoryCurrent = WRITE) OR + (PortFlagIJ.MemoryCurrent = CORRUPT)) ; + IF (DoWrCont OR DoCpCont) THEN + -- Corrupt dataout and memory + MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + SamePortFlag(i).MemoryCurrent := CORRUPT; + SamePortFlag(i).DataCurrent := CORRUPT; + SamePortFlag(i).OutputDisable := FALSE; + EXIT; + END IF; + IF (DoCpRead) THEN + -- Update dataout with memory + DataOutTmp(HighBit DOWNTO LowBit) := + MemoryTmp(HighBit DOWNTO LowBit); + SamePortFlag(i).MemoryCurrent := READ; + SamePortFlag(i).DataCurrent := READ; + SamePortFlag(i).OutputDisable := FALSE; + EXIT; + END IF; + IF (DoRdWrCont) THEN + -- Corrupt dataout only + DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + SamePortFlag(i).DataCurrent := CORRUPT; + SamePortFlag(i).OutputDisable := FALSE; + EXIT; + END IF; + END LOOP; + + IF (i < BitsPerEnable-1) THEN + -- Calculate HighBit and LowBit + LowBit := LowBit + BitsPerSubWord; + IF (LowBit > BitsPerWord) THEN + LowBit := BitsPerWord; + END IF; + HighBit := LowBit + BitsPerSubWord; + IF (HighBit > BitsPerWord) THEN + HighBit := BitsPerWord; + ELSE + HighBit := HighBit - 1; + END IF; + END IF; + + END LOOP; -- SubWordLoop + + DataOutBus := DataOutTmp; + + IF (DoWrCont) THEN + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMCP,ErrMcpWrCont,HeaderMsg,PortName); + END IF; + WriteMemory(MemoryData,MemoryTmp,Address); + END IF; + + IF (DoCpCont) THEN + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMCP,ErrMcpCpCont,HeaderMsg,PortName); + END IF; + WriteMemory(MemoryData,MemoryTmp,Address); + END IF; + + IF (DoCpRead) THEN + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMCP,ErrMcpCpRead,HeaderMsg,PortName); + END IF; + END IF; + + IF (DoRdWrCont) THEN + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMCP,ErrMcpRdWrCo,HeaderMsg,PortName); + END IF; + END IF; + +END VitalMemoryCrossPorts; + +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryCrossPorts ( + VARIABLE MemoryData : INOUT VitalMemoryDataType; + CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType; + CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) IS + + VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord; + VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord; + VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable; + VARIABLE MemoryTmp : std_logic_vector(BitsPerWord-1 DOWNTO 0); + VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH; + VARIABLE LowBit : NATURAL := 0; + VARIABLE HighBit : NATURAL := BitsPerSubWord-1; + VARIABLE AddressJ : VitalAddressValueType; + VARIABLE AddressK : VitalAddressValueType; + VARIABLE PortFlagIJ : VitalPortFlagType; + VARIABLE PortFlagIK : VitalPortFlagType; + VARIABLE CpWrCont : BOOLEAN := FALSE; + +BEGIN + + SubWordLoop: -- For each slice of the sub-word I + FOR i IN 0 TO BitsPerEnable-1 LOOP + + -- For each cross port J: check with each cross port K + FOR j IN 0 TO CrossPorts-1 LOOP + PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable); + AddressJ := CrossPortAddressArray(j); + -- Check for error in address + IF (AddressJ < 0) THEN + NEXT; + END IF; + ReadMemory(MemoryData,MemoryTmp,AddressJ); + -- For each cross port K + FOR k IN 0 TO CrossPorts-1 LOOP + IF (k <= j) THEN + NEXT; + END IF; + PortFlagIK := CrossPortFlagArray(i+k*BitsPerEnable); + AddressK := CrossPortAddressArray(k); + -- Check for error in address + IF (AddressK < 0) THEN + NEXT; + END IF; + CpWrCont := ( (AddressJ = AddressK) AND + (PortFlagIJ.MemoryCurrent = WRITE) AND + (PortFlagIK.MemoryCurrent = WRITE) ) OR + ( (PortFlagIJ.MemoryCurrent = WRITE) AND + (PortFlagIK.MemoryCurrent = CORRUPT) ) OR + ( (PortFlagIJ.MemoryCurrent = CORRUPT) AND + (PortFlagIK.MemoryCurrent = WRITE) ) OR + ( (PortFlagIJ.MemoryCurrent = CORRUPT) AND + (PortFlagIK.MemoryCurrent = CORRUPT) ) ; + IF (CpWrCont) THEN + -- Corrupt memory only + MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X'); + EXIT; + END IF; + END LOOP; -- FOR k IN 0 TO CrossPorts-1 LOOP + IF (CpWrCont = TRUE) THEN + IF (MsgOn) THEN + PrintMemoryMessage(MsgVMCP,ErrMcpCpWrCont,HeaderMsg); + END IF; + WriteMemory(MemoryData,MemoryTmp,AddressJ); + END IF; + END LOOP; -- FOR j IN 0 TO CrossPorts-1 LOOP + + IF (i < BitsPerEnable-1) THEN + -- Calculate HighBit and LowBit + LowBit := LowBit + BitsPerSubWord; + IF (LowBit > BitsPerWord) THEN + LowBit := BitsPerWord; + END IF; + HighBit := LowBit + BitsPerSubWord; + IF (HighBit > BitsPerWord) THEN + HighBit := BitsPerWord; + ELSE + HighBit := HighBit - 1; + END IF; + END IF; + END LOOP; -- SubWordLoop + +END VitalMemoryCrossPorts; + + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryViolation +-- Parameters: DataOutBus - Output zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- PortFlag - Indicates port operating mode +-- TimingDataArray - This is currently not used (comment out) +-- ViolationArray - Aggregation of violation variables +-- DataInBus - Input value of data bus in +-- AddressBus - Input value of address bus in +-- AddressValue - Decoded value of the AddressBus +-- ViolationTable - Input memory violation table +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- MsgSeverity - Control level of message generation +-- Description: This procedure is intended to implement all actions on the +-- memory contents and data out bus as a result of timing viols. +-- It uses the memory action table to perform various corruption +-- policies specified by the user. +-- ---------------------------------------------------------------------------- + +PROCEDURE VitalMemoryViolation ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressValue : IN VitalAddressValueType; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationFlagsArray : IN X01ArrayT; + CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + + VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord; + VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord; + VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable; + VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) + := DataOutBus; + VARIABLE MemoryAction : VitalMemorySymbolType; + VARIABLE DataAction : VitalMemorySymbolType; + -- VMT relies on the corrupt masks so HighBit/LowBit are full word + VARIABLE HighBit : NATURAL := BitsPerWord-1; + VARIABLE LowBit : NATURAL := 0; + VARIABLE PortFlagTmp : VitalPortFlagType; + VARIABLE VFlagArrayTmp : std_logic_vector + (0 TO ViolationFlagsArray'LENGTH-1); + VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE); + VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE); + +BEGIN + + -- Don't do anything if given an error address + IF (AddressValue < 0) THEN + RETURN; + END IF; + + FOR i IN ViolationFlagsArray'RANGE LOOP + VFlagArrayTmp(i) := ViolationFlagsArray(i); + END LOOP; + + -- Lookup memory and data actions + ViolationTableLookUp( + MemoryAction => MemoryAction , + DataAction => DataAction , + MemoryCorruptMask => MemCorruptMask , + DataCorruptMask => DatCorruptMask , + ViolationFlags => ViolationFlags , + ViolationFlagsArray => VFlagArrayTmp , + ViolationSizesArray => ViolationSizesArray , + ViolationTable => ViolationTable , + BitsPerWord => BitsPerWord , + BitsPerSubWord => BitsPerSubWord , + BitsPerEnable => BitsPerEnable , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + + -- Need to read incoming PF value (was not before) + PortFlagTmp := PortFlag(0); + + IF (PortType = READ OR PortType = RDNWR) THEN + -- Handle data action before memory action + -- This allows reading previous memory contents + HandleDataAction( + DataOutBus => DataOutTmp , + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => DatCorruptMask , + DataInBus => DataInBus , + Address => AddressValue , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => ViolationTable , + DataAction => DataAction , + CallerName => MsgVMV , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + END IF; + + IF (PortType = WRITE OR PortType = RDNWR) THEN + HandleMemoryAction( + MemoryData => MemoryData , + PortFlag => PortFlagTmp , + CorruptMask => MemCorruptMask , + DataInBus => DataInBus , + Address => AddressValue , + HighBit => HighBit , + LowBit => LowBit , + MemoryTable => ViolationTable , + MemoryAction => MemoryAction , + CallerName => MsgVMV , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn + ); + END IF; + + -- Check if we need to turn off PF.OutputDisable + IF (DataAction /= 'S') THEN + PortFlagTmp.OutputDisable := FALSE; + -- Set the output PortFlag(0) value + -- Note that all bits of PortFlag get PortFlagTmp + FOR i IN PortFlag'RANGE LOOP + PortFlag(i) := PortFlagTmp; + END LOOP; + END IF; + + -- Set the candidate zero delay return value + DataOutBus := DataOutTmp; + +END; + +PROCEDURE VitalMemoryViolation ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressValue : IN VitalAddressValueType; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) IS + + VARIABLE VFlagArrayTmp : X01ArrayT (0 TO 0); + +BEGIN + + VitalMemoryViolation ( + DataOutBus => DataOutBus , + MemoryData => MemoryData , + PortFlag => PortFlag , + DataInBus => DataInBus , + AddressValue => AddressValue , + ViolationFlags => ViolationFlags , + ViolationFlagsArray => VFlagArrayTmp , + ViolationSizesArray => ( 0 => 0 ) , + ViolationTable => ViolationTable , + PortType => PortType , + PortName => PortName , + HeaderMsg => HeaderMsg , + MsgOn => MsgOn , + MsgSeverity => MsgSeverity + ); + +END; + +END Vital_Memory ; diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_p.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_p.vhdl new file mode 100644 index 0000000..83874f4 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/memory_p.vhdl @@ -0,0 +1,1729 @@ +-- ---------------------------------------------------------------------------- +-- Title : Standard VITAL Memory Package +-- : +-- Library : Vital_Memory +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : Ekambaram Balaji, LSI Logic Corporation +-- : Jose De Castro, Consultant +-- : Prakash Bare, GDA Technologies +-- : William Yam, LSI Logic Corporation +-- : Dennis Brophy, Model Technology +-- : +-- Purpose : This packages defines standard types, constants, functions +-- : and procedures for use in developing ASIC memory models. +-- : +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Ver:|Auth:| Date:| Changes Made: +-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal +-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme +-- 0.3 | jdc |090297| Extensive updates for TAG review (functional) +-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable +-- | | | Added interface of VitalMemoryCrossPorts() & +-- | | | VitalMemoryViolation(). +-- 0.5 | jdc |092997| Completed naming changes thoughout package body. +-- | | | Testing with simgle port test model looks ok. +-- 0.6 | jdc |121797| Major updates to the packages: +-- | | | - Implement VitalMemoryCrossPorts() +-- | | | - Use new VitalAddressValueType +-- | | | - Use new VitalCrossPortModeType enum +-- | | | - Overloading without SamePort args +-- | | | - Honor erroneous address values +-- | | | - Honor ports disabled with 'Z' +-- | | | - Implement implicit read 'M' table symbol +-- | | | - Cleanup buses to use (H DOWNTO L) +-- | | | - Message control via MsgOn,HeaderMsg,PortName +-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases +-- 0.7 | jdc |052698| Bug fixes to the packages: +-- | | | - Fix failure with negative Address values +-- | | | - Added debug messages for VMT table search +-- | | | - Remove 'S' for action column (only 's') +-- | | | - Remove 's' for response column (only 'S') +-- | | | - Remove 'X' for action and response columns +-- 0.8 | jdc |061298| Implemented VitalMemoryViolation() +-- | | | - Minimal functionality violation tables +-- | | | - Missing: +-- | | | - Cannot handle wide violation variables +-- | | | - Cannot handle sub-word cases +-- | | | Fixed IIC version of MemoryMatch +-- | | | Fixed 'M' vs 'm' switched on debug output +-- | | | TO BE DONE: +-- | | | - Implement 'd' corrupting a single bit +-- | | | - Implement 'D' corrupting a single bit +-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType +-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType +-- 0.11|eb/sc|081798| Added overloaded function interface for +-- | | | VitalDeclareMemory +-- 0.14| jdc |113198| Merging of memory functionality and version +-- | | | 1.4 9/17/98 of timing package from Prakash +-- 0.15| jdc |120198| Major development of VMV functionality +-- 0.16| jdc |120298| Complete VMV functionlality for initial testing +-- | | | - New ViolationTableCorruptMask() procedure +-- | | | - New MemoryTableCorruptMask() procedure +-- | | | - HandleMemoryAction(): +-- | | | - Removed DataOutBus bogus output +-- | | | - Replaced DataOutTmp with DataInTmp +-- | | | - Added CorruptMask input handling +-- | | | - Implemented 'd','D' using CorruptMask +-- | | | - CorruptMask on 'd','C','L','D','E' +-- | | | - CorruptMask ignored on 'c','l','e' +-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT +-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT +-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit +-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit +-- | | | - HandleDataAction(): +-- | | | - Added CorruptMask input handling +-- | | | - Implemented 'd','D' using CorruptMask +-- | | | - CorruptMask on 'd','C','L','D','E' +-- | | | - CorruptMask ignored on 'l','e' +-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT +-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT +-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit +-- | | | - Changed 'L','D','E' to use HighBit, LowBit +-- | | | - MemoryTableLookUp(): +-- | | | - Added MsgOn table debug output +-- | | | - Uses new MemoryTableCorruptMask() +-- | | | - ViolationTableLookUp(): +-- | | | - Uses new ViolationTableCorruptMask() +-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType, +-- | | | VitalMemoryViolationTableType data +-- | | | types but not used yet (need to discuss) +-- | | | - Added overload for VitalMemoryViolation() +-- | | | which does not have array flags +-- | | | - Bug fixes for VMV functionality: +-- | | | - ViolationTableLookUp() not handling '-' in +-- | | | scalar violation matching +-- | | | - VitalMemoryViolation() now normalizes +-- | | | VFlagArrayTmp'LEFT as LSB before calling +-- | | | ViolationTableLookUp() for proper scanning +-- | | | - ViolationTableCorruptMask() had to remove +-- | | | normalization of CorruptMaskTmp and +-- | | | ViolMaskTmp for proper MSB:LSB corruption +-- | | | - HandleMemoryAction(), HandleDataAction() +-- | | | - Removed 'D','E' since not being used +-- | | | - Use XOR instead of OR for corrupt masks +-- | | | - Now 'd' is sensitive to HighBit, LowBit +-- | | | - Fixed LowBit overflow in bit writeable case +-- | | | - MemoryTableCorruptMask() +-- | | | - ViolationTableCorruptMask() +-- | | | - VitalMemoryTable() +-- | | | - VitalMemoryCrossPorts() +-- | | | - Fixed VitalMemoryViolation() failing on +-- | | | error AddressValue from earlier VMT() +-- | | | - Minor cleanup of code formatting +-- 0.18| jdc |032599| - In VitalDeclareMemory() +-- | | | - Added BinaryLoadFile formal arg and +-- | | | modified LoadMemory() to handle bin +-- | | | - Added NOCHANGE to VitalPortFlagType +-- | | | - For VitalCrossPortModeType +-- | | | - Added CpContention enum +-- | | | - In HandleDataAction() +-- | | | - Set PortFlag := NOCHANGE for 'S' +-- | | | - In HandleMemoryAction() +-- | | | - Set PortFlag := NOCHANGE for 's' +-- | | | - In VitalMemoryTable() and +-- | | | VitalMemoryViolation() +-- | | | - Honor PortFlag = NOCHANGE returned +-- | | | from HandleMemoryAction() +-- | | | - In VitalMemoryCrossPorts() +-- | | | - Fixed Address = AddressJ for all +-- | | | conditions of DoWrCont & DoCpRead +-- | | | - Handle CpContention like WrContOnly +-- | | | under CpReadOnly conditions, with +-- | | | associated memory message changes +-- | | | - Handle PortFlag = NOCHANGE like +-- | | | PortFlag = READ for actions +-- | | | - Modeling change: +-- | | | - Need to init PortFlag every delta +-- | | | PortFlag_A := (OTHES => UNDEF); +-- | | | - Updated InternalTimingCheck code +-- 0.19| jdc |042599| - Fixes for bit-writeable cases +-- | | | - Check PortFlag after HandleDataAction +-- | | | in VitalMemoryViolation() +-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash +-- | | | and Willian: +-- | | | VitalMemorySchedulePathDelay() +-- | | | VitalMemoryExpandPortFlag() +-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums, +-- | | | added new CpReadAndReadContention. +-- | | | - Fixed VitalMemoryCrossPorts() parameter +-- | | | SamePortFlag to INOUT so that it can +-- | | | set CORRUPT or READ value. +-- | | | - Fixed VitalMemoryTable() where PortFlag +-- | | | setting by HandleDataAction() is being +-- | | | ignored when HandleMemoryAction() sets +-- | | | PortFlagTmp to NOCHANGE. +-- | | | - Fixed VitalMemoryViolation() to set +-- | | | all bits of PortFlag when violating. +-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData +-- | | | checks whether the previous state is HIGHZ. +-- | | | If yes then portFlag should be NOCHANGE +-- | | | for VMPD to ignore IORetain corruption. +-- | | | The idea is that the first Z should be +-- | | | propagated but later ones should be ignored. +-- | | | +-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99 +-- | | | - Changed VitalPortFlagType to record of +-- | | | new VitalPortStateType to hold current, +-- | | | previous values and separate disable. +-- | | | Also created VitalDefaultPortFlag const. +-- | | | Removed usage of PortFlag NOCHANGE +-- | | | - VitalMemoryTable() changes: +-- | | | Optimized return when all curr = prev +-- | | | AddressValue is now INOUT to optimize +-- | | | Transfer PF.MemoryCurrent to MemoryPrevious +-- | | | Transfer PF.DataCurrent to DataPrevious +-- | | | Reset PF.OutputDisable to FALSE +-- | | | Expects PortFlag init in declaration +-- | | | No need to init PortFlag every delta +-- | | | - VitalMemorySchedulePathDelay() changes: +-- | | | Initialize with VitalDefaultPortFlag +-- | | | Check PortFlag.OutputDisable +-- | | | - HandleMemoryAction() changes: +-- | | | Set value of PortFlag.MemoryCurrent +-- | | | Never set PortFlag.OutputDisable +-- | | | - HandleDataAction() changes: +-- | | | Set value of PortFlag.DataCurrent +-- | | | Set PortFlag.DataCurrent for HIGHZ +-- | | | - VitalMemoryCrossPorts() changes: +-- | | | Check/set value of PF.MemoryCurrent +-- | | | Check value of PF.OutputDisable +-- | | | - VitalMemoryViolation() changes: +-- | | | Fixed bug - not reading inout PF value +-- | | | Clean up setting of PortFlag +-- 0.24| jdc |100899| - Modified update of PF.OutputDisable +-- | | | to correctly accomodate 2P1W1R case: +-- | | | the read port should not exhibit +-- | | | IO retain corrupt when reading +-- | | | addr unrelated to addr being written. +-- 0.25| jdc |100999| - VitalMemoryViolation() change: +-- | | | Fixed bug with RDNWR mode incorrectly +-- | | | updating the PF.OutputDisable +-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change: +-- | | | Fixed bugs with update of PF +-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change: +-- | | | Added DoRdWrCont message (ErrMcpRdWrCo, +-- | | | Memory cross port read/write data only +-- | | | contention) +-- | | | - VitalMemoryTable() change: +-- | | | Set PF.OutputDisable := TRUE for the +-- | | | optimized cases. +-- 0.28| pb |112399| - Added 8 VMPD procedures for vector +-- | | | PathCondition support. Now the total +-- | | | number of overloadings for VMPD is 24. +-- | | | - Number of overloadings for SetupHold +-- | | | procedures increased to 5. Scalar violations +-- | | | are not supported anymore. Vector checkEnabled +-- | | | support is provided through the new overloading +-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction() +-- | | | Reinstated 'D' and 'E' actions but +-- | | | with new PortFlagType +-- | | | - Updated file handling syntax, must compile +-- | | | with -93 syntax now. +-- 0.30| jdc |022300| - Formated for 80 column max width +-- ---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.Vital_Timing.ALL; +USE IEEE.Vital_Primitives.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +PACKAGE Vital_Memory IS + +-- ---------------------------------------------------------------------------- +-- Timing Section +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- Types and constants for Memory timing procedures +-- ---------------------------------------------------------------------------- +TYPE VitalMemoryArcType IS (ParallelArc, CrossArc, SubwordArc); +TYPE OutputRetainBehaviorType IS (BitCorrupt, WordCorrupt); +TYPE VitalMemoryMsgFormatType IS (Vector, Scalar, VectorEnum); +TYPE X01ArrayT IS ARRAY (NATURAL RANGE <> ) OF X01; +TYPE X01ArrayPT IS ACCESS X01ArrayT; +TYPE VitalMemoryViolationType IS ACCESS X01ArrayT; +CONSTANT DefaultNumBitsPerSubword : INTEGER := -1; + + +-- Data type storing path delay and schedule information for output bits +TYPE VitalMemoryScheduleDataType IS RECORD + OutputData : std_ulogic; + NumBitsPerSubWord : INTEGER; + ScheduleTime : TIME; + ScheduleValue : std_ulogic; + LastOutputValue : std_ulogic; + PropDelay : TIME; + OutputRetainDelay : TIME; + InputAge : TIME; +END RECORD; + +TYPE VitalMemoryTimingDataType IS RECORD + NotFirstFlag : BOOLEAN; + RefLast : X01; + RefTime : TIME; + HoldEn : BOOLEAN; + TestLast : std_ulogic; + TestTime : TIME; + SetupEn : BOOLEAN; + TestLastA : VitalLogicArrayPT; + TestTimeA : VitalTimeArrayPT; + RefLastA : X01ArrayPT; + RefTimeA : VitalTimeArrayPT; + HoldEnA : VitalBoolArrayPT; + SetupEnA : VitalBoolArrayPT; +END RECORD; + +TYPE VitalPeriodDataArrayType IS ARRAY (NATURAL RANGE <>) OF + VitalPeriodDataType; + +-- Data type storing path delay and schedule information for output +-- vectors +TYPE VitalMemoryScheduleDataVectorType IS ARRAY (NATURAL RANGE <> ) OF + VitalMemoryScheduleDataType; + +-- VitalPortFlagType records runtime mode of port sub-word slices +-- TYPE VitalPortFlagType IS ( +-- UNDEF, +-- READ, +-- WRITE, +-- CORRUPT, +-- HIGHZ, +-- NOCHANGE +-- ); + +-- VitalPortFlagType records runtime mode of port sub-word slices +TYPE VitalPortStateType IS ( + UNDEF, + READ, + WRITE, + CORRUPT, + HIGHZ +); + +TYPE VitalPortFlagType IS RECORD + MemoryCurrent : VitalPortStateType; + MemoryPrevious : VitalPortStateType; + DataCurrent : VitalPortStateType; + DataPrevious : VitalPortStateType; + OutputDisable : BOOLEAN; +END RECORD; + +CONSTANT VitalDefaultPortFlag : VitalPortFlagType := ( + MemoryCurrent => READ, + MemoryPrevious => UNDEF, + DataCurrent => READ, + DataPrevious => UNDEF, + OutputDisable => FALSE +); + +-- VitalPortFlagVectorType to be same width i as enables of a port +-- or j multiples thereof, where j is the number of cross ports +TYPE VitalPortFlagVectorType IS + ARRAY (NATURAL RANGE <>) OF VitalPortFlagType; + +-- ---------------------------------------------------------------------------- +-- Functions : VitalMemory path delay procedures +-- - VitalMemoryInitPathDelay +-- - VitalMemoryAddPathDelay +-- - VitalMemorySchedulePathDelay +-- +-- Description: VitalMemoryInitPathDelay, VitalMemoryAddPathDelay and +-- VitalMemorySchedulePathDelay are Level 1 routines used +-- for selecting the propagation delay paths based on +-- path condition, transition type and delay values and +-- schedule a new output value. +-- +-- Following features are implemented in these procedures: +-- o condition dependent path selection +-- o Transition dependent delay selection +-- o shortest delay path selection from multiple +-- candidate paths +-- o Scheduling of the computed values on the specified +-- signal. +-- o output retain behavior if outputRetain flag is set +-- o output mapping to alternate strengths to model +-- pull-up, pull-down etc. +-- +-- +-- +-- Following is information on overloading of the procedures. +-- +-- VitalMemoryInitPathDelay is overloaded for ScheduleDataArray and +-- OutputDataArray +-- +-- ---------------------------------------------------------------------------- +-- ScheduleDataArray OutputDataArray +-- ---------------------------------------------------------------------------- +-- Scalar Scalar +-- Vector Vector +-- ---------------------------------------------------------------------------- +-- +-- +-- VitalMemoryAddPathDelay is overloaded for ScheduleDataArray, +-- PathDelayArray, InputSignal and delaytype. +-- +-- ---------------------------------------------------------------------------- +-- DelayType InputSignal ScheduleData PathDelay +-- Array Array +-- ---------------------------------------------------------------------------- +-- VitalDelayType Scalar Scalar Scalar +-- VitalDelayType Scalar Vector Vector +-- VitalDelayType Vector Scalar Vector +-- VitalDelayType Vector Vector Vector +-- VitalDelayType01 Scalar Scalar Scalar +-- VitalDelayType01 Scalar Vector Vector +-- VitalDelayType01 Vector Scalar Vector +-- VitalDelayType01 Vector Vector Vector +-- VitalDelayType01Z Scalar Scalar Scalar +-- VitalDelayType01Z Scalar Vector Vector +-- VitalDelayType01Z Vector Scalar Vector +-- VitalDelayType01Z Vector Vector Vector +-- VitalDelayType01XZ Scalar Scalar Scalar +-- VitalDelayType01XZ Scalar Vector Vector +-- VitalDelayType01XZ Vector Scalar Vector +-- VitalDelayType01XZ Vector Vector Vector +-- ---------------------------------------------------------------------------- +-- +-- +-- VitalMemorySchedulePathDelay is overloaded for ScheduleDataArray, +-- and OutSignal +-- +-- ---------------------------------------------------------------------------- +-- OutSignal ScheduleDataArray +-- ---------------------------------------------------------------------------- +-- Scalar Scalar +-- Vector Vector +-- ---------------------------------------------------------------------------- +-- +-- Procedure Declarations: +-- +-- +-- Function : VitalMemoryInitPathDelay +-- +-- Arguments: +-- +-- INOUT Type Description +-- +-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/ +-- ScheduleData VitalMemoryScheduleDataType +-- Internal data variable for +-- storing delay and schedule +-- information for each output bit +-- +-- +-- IN +-- +-- OutputDataArray/ STD_LOGIC_VECTOR/Array containing current output +-- OutputData STD_ULOGIC value +-- +-- +-- NumBitsPerSubWord INTEGER Number of bits per subword. +-- Default value of this argument +-- is DefaultNumBitsPerSubword +-- which is interpreted as no +-- subwords +-- +-- ---------------------------------------------------------------------------- +-- +-- +-- ScheduleDataArray - Vector +-- OutputDataArray - Vector +-- +PROCEDURE VitalMemoryInitPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR; + CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword +); +-- +-- ScheduleDataArray - Scalar +-- OutputDataArray - Scalar +-- +PROCEDURE VitalMemoryInitPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + VARIABLE OutputData : IN STD_ULOGIC +); + +-- ---------------------------------------------------------------------------- +-- +-- Function : VitalMemoryAddPathDelay +-- +-- Arguments +-- +-- INOUT Type Description +-- +-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/ +-- ScheduleData VitalMemoryScheduleDataType +-- Internal data variable for +-- storing delay and schedule +-- information for each output bit +-- +-- InputChangeTimeArray/ VitaltimeArrayT/Time +-- InputChangeTime Holds the time since the last +-- input change +-- +-- IN +-- +-- InputSignal STD_LOGIC_VECTOR +-- STD_ULOGIC/ Array holding the input value +-- +-- OutputSignalName STRING The output signal name +-- +-- PathDelayArray/ VitalDelayArrayType01ZX, +-- PathDelay VitalDelayArrayType01Z, +-- VitalDelayArrayType01, +-- VitalDelayArrayType/ +-- VitalDelayType01ZX, +-- VitalDelayType01Z, +-- VitalDelayType01, +-- VitalDelayType Array of delay values +-- +-- ArcType VitalMemoryArcType +-- Indicates the Path type. This +-- can be SubwordArc, CrossArc or +-- ParallelArc +-- +-- PathCondition BOOLEAN If True, the transition in +-- the corresponding input signal +-- is considered while +-- caluculating the prop. delay +-- else the transition is ignored. +-- +-- OutputRetainFlag BOOLEAN If specified TRUE,output retain +-- (hold) behavior is implemented. +-- +-- ---------------------------------------------------------------------------- +-- +-- #1 +-- DelayType - VitalDelayType +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelay : IN VitalDelayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #2 +-- DelayType - VitalDelayType +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #3 +-- DelayType - VitalDelayType +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT +); + +-- #4 +-- DelayType - VitalDelayType +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #5 +-- DelayType - VitalDelayType +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #6 +-- DelayType - VitalDelayType +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT +); + +-- #7 +-- DelayType - VitalDelayType01 +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelay : IN VitalDelayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #8 +-- DelayType - VitalDelayType01 +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #9 +-- DelayType - VitalDelayType01 +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT +); + +-- #10 +-- DelayType - VitalDelayType01 +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #11 +-- DelayType - VitalDelayType01 +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE +); + +-- #12 +-- DelayType - VitalDelayType01 +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT +); + +-- #13 +-- DelayType - VitalDelayType01Z +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelay : IN VitalDelayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #14 +-- DelayType - VitalDelayType01Z +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #15 +-- DelayType - VitalDelayType01Z +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #16 +-- DelayType - VitalDelayType01Z +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- #17 +-- DelayType - VitalDelayType01Z +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- #18 +-- DelayType - VitalDelayType01Z +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01Z; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- #19 +-- DelayType - VitalDelayType01ZX +-- Input - Scalar +-- Output - Scalar +-- Delay - Scalar +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelay : IN VitalDelayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #20 +-- DelayType - VitalDelayType01ZX +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #21 +-- DelayType - VitalDelayType01ZX +-- Input - Scalar +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_ULOGIC; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTime : INOUT Time; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray: IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE +); + +-- #22 +-- DelayType - VitalDelayType01ZX +-- Input - Vector +-- Output - Scalar +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- #23 +-- DelayType - VitalDelayType01ZX +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Scalar + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathCondition : IN BOOLEAN := TRUE; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- #24 +-- DelayType - VitalDelayType01ZX +-- Input - Vector +-- Output - Vector +-- Delay - Vector +-- Condition - Vector + +PROCEDURE VitalMemoryAddPathDelay ( + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType; + SIGNAL InputSignal : IN STD_LOGIC_VECTOR; + CONSTANT OutputSignalName : IN STRING := ""; + VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT; + CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT PathConditionArray : IN VitalBoolArrayT; + CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE; + CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt +); + +-- ---------------------------------------------------------------------------- +-- +-- Function : VitalMemorySchedulePathDelay +-- +-- Arguments: +-- +-- OUT Type Description +-- OutSignal STD_LOGIC_VECTOR/ The output signal for +-- STD_ULOGIC scheduling +-- +-- IN +-- OutputSignalName STRING The name of the output signal +-- +-- IN +-- PortFlag VitalPortFlagType Port flag variable from +-- functional procedures +-- +-- IN +-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the +-- output can be mapped to +-- alternate strengths to model +-- tri-state devices, pull-ups +-- and pull-downs. +-- +-- INOUT +-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/ +-- ScheduleData VitalMemoryScheduleDataType +-- Internal data variable for +-- storing delay and schedule +-- information for each +-- output bit +-- +-- ---------------------------------------------------------------------------- +-- +-- ScheduleDataArray - Vector +-- OutputSignal - Vector +-- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT std_logic_vector; + CONSTANT OutputSignalName : IN STRING := ""; + CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType +); +-- +-- ScheduleDataArray - Vector +-- OutputSignal - Vector +-- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT std_logic_vector; + CONSTANT OutputSignalName : IN STRING := ""; + CONSTANT PortFlag : IN VitalPortFlagVectorType; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType +); +-- +-- ScheduleDataArray - Scalar +-- OutputSignal - Scalar +-- +PROCEDURE VitalMemorySchedulePathDelay ( + SIGNAL OutSignal : OUT std_ulogic; + CONSTANT OutputSignalName : IN STRING := ""; + CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType +); + +-- ---------------------------------------------------------------------------- +FUNCTION VitalMemoryTimingDataInit RETURN VitalMemoryTimingDataType; + +-- ---------------------------------------------------------------------------- +-- +-- Function Name: VitalMemorySetupHoldCheck +-- +-- Description: The VitalMemorySetupHoldCheck procedure detects a setup or a +-- hold violation on the input test signal with respect +-- to the corresponding input reference signal. The timing +-- constraints are specified through parameters +-- representing the high and low values for the setup and +-- hold values for the setup and hold times. This +-- procedure assumes non-negative values for setup and hold +-- timing constraints. +-- +-- It is assumed that negative timing constraints +-- are handled by internally delaying the test or +-- reference signals. Negative setup times result in +-- a delayed reference signal. Negative hold times +-- result in a delayed test signal. Furthermore, the +-- delays and constraints associated with these and +-- other signals may need to be appropriately +-- adjusted so that all constraint intervals overlap +-- the delayed reference signals and all constraint +-- values (with respect to the delayed signals) are +-- non-negative. +-- +-- This function is overloaded based on the input +-- TestSignal and reference signals. Parallel, Subword and +-- Cross Arc relationships between test and reference +-- signals are supported. +-- +-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX +-- : +-- : -->| error region |<-- +-- : +-- _______________________________ +-- RefSignal \______________________________ +-- : | | | +-- : | -->| |<-- thold +-- : -->| tsetup |<-- +-- +-- Arguments: +-- +-- IN Type Description +-- TestSignal std_logic_vector Value of test signal +-- TestSignalName STRING Name of test signal +-- TestDelay VitalDelayArrayType Model's internal delay associated +-- with TestSignal +-- RefSignal std_ulogic Value of reference signal +-- std_logic_vector +-- RefSignalName STRING Name of reference signal +-- RefDelay TIME Model's internal delay associated +-- VitalDelayArrayType with RefSignal +-- SetupHigh VitalDelayArrayType Absolute minimum time duration +-- before the transition of RefSignal +-- for which transitions of +-- TestSignal are allowed to proceed +-- to the "1" state without causing +-- a setup violation. +-- SetupLow VitalDelayArrayType Absolute minimum time duration +-- before the transition of RefSignal +-- for which transitions of +-- TestSignal are allowed to proceed +-- to the "0" state without causing +-- a setup violation. +-- HoldHigh VitalDelayArrayType Absolute minimum time duration +-- after the transition of RefSignal +-- for which transitions of +-- TestSignal are allowed to +-- proceed to the "1" state without +-- causing a hold violation. +-- HoldLow VitalDelayArrayType Absolute minimum time duration +-- after the transition of RefSignal +-- for which transitions of +-- TestSignal are allowed to +-- proceed to the "0" state without +-- causing a hold violation. +-- CheckEnabled BOOLEAN Check performed if TRUE. +-- RefTransition VitalEdgeSymbolType +-- Reference edge specified. Events +-- on the RefSignal which match the +-- edge spec. are used as reference +-- edges. +-- ArcType VitalMemoryArcType +-- NumBitsPerSubWord INTEGER +-- HeaderMsg STRING String that will accompany any +-- assertion messages produced. +-- XOn BOOLEAN If TRUE, Violation output +-- parameter is set to "X". +-- Otherwise, Violation is always +-- set to "0." +-- MsgOn BOOLEAN If TRUE, set and hold violation +-- message will be generated. +-- Otherwise, no messages are +-- generated, even upon violations. +-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. +-- MsgFormat VitalMemoryMsgFormatType +-- Format of the Test/Reference +-- signals in violation messages. +-- +-- INOUT +-- TimingData VitalMemoryTimingDataType +-- VitalMemorySetupHoldCheck information +-- storage area. This is used +-- internally to detect reference +-- edges and record the time of the +-- last edge. +-- +-- OUT +-- Violation X01 This is the violation flag returned. +-- X01ArrayT Overloaded for array type. +-- +-- +-- ---------------------------------------------------------------------------- + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayType; + CONSTANT SetupLow : IN VitalDelayType; + CONSTANT HoldHigh : IN VitalDelayType; + CONSTANT HoldLow : IN VitalDelayType; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArrayType; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArrayType; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN VitalBoolArrayT; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +--------------- following are not needed -------------------------- + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + +PROCEDURE VitalMemorySetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalMemoryTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + SIGNAL RefSignal : IN std_logic_vector; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN VitalDelayArrayType; + CONSTANT SetupHigh : IN VitalDelayArrayType; + CONSTANT SetupLow : IN VitalDelayArrayType; + CONSTANT HoldHigh : IN VitalDelayArrayType; + CONSTANT HoldLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT ArcType : IN VitalMemoryArcType := CrossArc; + CONSTANT NumBitsPerSubWord : IN INTEGER := 1; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE +); + + +-- ---------------------------------------------------------------------------- +-- +-- Function Name: VitalPeriodPulseCheck +-- +-- Description: VitalPeriodPulseCheck checks for minimum and maximum +-- periodicity and pulse width for "1" and "0" values of +-- the input test signal. The timing constraint is +-- specified through parameters representing the minimal +-- period between successive rising and falling edges of +-- the input test signal and the minimum pulse widths +-- associated with high and low values. +-- +-- VitalPeriodCheck's accepts rising and falling edges +-- from 1 and 0 as well as transitions to and from 'X.' +-- +-- _______________ __________ +-- ____________| |_______| +-- +-- |<--- pw_hi --->| +-- |<-------- period ----->| +-- -->| pw_lo |<-- +-- +-- Arguments: +-- IN Type Description +-- TestSignal std_logic_vector Value of test signal +-- TestSignalName STRING Name of the test signal +-- TestDelay VitalDelayArrayType +-- Model's internal delay associated +-- with TestSignal +-- Period VitalDelayArrayType +-- Minimum period allowed between +-- consecutive rising ('P') or +-- falling ('F') transitions. +-- PulseWidthHigh VitalDelayArrayType +-- Minimum time allowed for a high +-- pulse ('1' or 'H') +-- PulseWidthLow VitalDelayArrayType +-- Minimum time allowed for a low +-- pulse ('0' or 'L') +-- CheckEnabled BOOLEAN Check performed if TRUE. +-- HeaderMsg STRING String that will accompany any +-- assertion messages produced. +-- XOn BOOLEAN If TRUE, Violation output parameter +-- is set to "X". Otherwise, Violation +-- is always set to "0." +-- MsgOn BOOLEAN If TRUE, period/pulse violation +-- message will be generated. +-- Otherwise, no messages are generated, +-- even though a violation is detected. +-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. +-- MsgFormat VitalMemoryMsgFormatType +-- Format of the Test/Reference signals +-- in violation messages. +-- +-- INOUT +-- PeriodData VitalPeriodDataArrayType +-- VitalPeriodPulseCheck information +-- storage area. This is used +-- internally to detect reference edges +-- and record the pulse and period +-- times. +-- OUT +-- Violation X01 This is the violation flag returned. +-- X01ArrayT Overloaded for array type. +-- +-- ---------------------------------------------------------------------------- +PROCEDURE VitalMemoryPeriodPulseCheck ( + VARIABLE Violation : OUT X01ArrayT; + VARIABLE PeriodData : INOUT VitalPeriodDataArrayType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + CONSTANT Period : IN VitalDelayArrayType; + CONSTANT PulseWidthHigh : IN VitalDelayArrayType; + CONSTANT PulseWidthLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType +); + +PROCEDURE VitalMemoryPeriodPulseCheck ( + VARIABLE Violation : OUT X01; + VARIABLE PeriodData : INOUT VitalPeriodDataArrayType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN VitalDelayArrayType; + CONSTANT Period : IN VitalDelayArrayType; + CONSTANT PulseWidthHigh : IN VitalDelayArrayType; + CONSTANT PulseWidthLow : IN VitalDelayArrayType; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT MsgFormat : IN VitalMemoryMsgFormatType +); + +-- ---------------------------------------------------------------------------- +-- Functionality Section +-- ---------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- All Memory Types and Record definitions. +-- ---------------------------------------------------------------------------- +TYPE MemoryWordType IS ARRAY (NATURAL RANGE <>) OF UX01; +TYPE MemoryWordPtr IS ACCESS MemoryWordType; + +TYPE MemoryArrayType IS ARRAY (NATURAL RANGE <>) OF MemoryWordPtr; +TYPE MemoryArrayPtrType IS ACCESS MemoryArrayType; + +TYPE VitalMemoryArrayRecType IS +RECORD +NoOfWords : POSITIVE; +NoOfBitsPerWord : POSITIVE; +NoOfBitsPerSubWord : POSITIVE; +NoOfBitsPerEnable : POSITIVE; +MemoryArrayPtr : MemoryArrayPtrType; +END RECORD; + +TYPE VitalMemoryDataType IS ACCESS VitalMemoryArrayRecType; + +TYPE VitalTimingDataVectorType IS +ARRAY (NATURAL RANGE <>) OF VitalTimingDataType; + +TYPE VitalMemoryViolFlagSizeType IS ARRAY (NATURAL RANGE <>) OF INTEGER; + +-- ---------------------------------------------------------------------------- +-- Symbol Literals used for Memory Table Modeling +-- ---------------------------------------------------------------------------- + +-- Symbol literals from '/' to 'S' are closely related to MemoryTableMatch +-- lookup matching and the order cannot be arbitrarily changed. +-- The remaining symbol literals are interpreted directly and matchting is +-- handled in the MemoryMatch procedure itself. + +TYPE VitalMemorySymbolType IS ( + '/', -- 0 -> 1 + '\', -- 1 -> 0 + 'P', -- Union of '/' and '^' (any edge to 1) + 'N', -- Union of '\' and 'v' (any edge to 0) + 'r', -- 0 -> X + 'f', -- 1 -> X + 'p', -- Union of '/' and 'r' (any edge from 0) + 'n', -- Union of '\' and 'f' (any edge from 1) + 'R', -- Union of '^' and 'p' (any possible rising edge) + 'F', -- Union of 'v' and 'n' (any possible falling edge) + '^', -- X -> 1 + 'v', -- X -> 0 + 'E', -- Union of 'v' and '^' (any edge from X) + 'A', -- Union of 'r' and '^' (rising edge to or from 'X') + + 'D', -- Union of 'f' and 'v' (falling edge to or from 'X') + + '*', -- Union of 'R' and 'F' (any edge) + 'X', -- Unknown level + '0', -- low level + '1', -- high level + '-', -- don't care + 'B', -- 0 or 1 + 'Z', -- High Impedance + 'S', -- steady value + + 'g', -- Good address (no transition) + 'u', -- Unknown address (no transition) + 'i', -- Invalid address (no transition) + 'G', -- Good address (with transition) + 'U', -- Unknown address (with transition) + 'I', -- Invalid address (with transition) + + 'w', -- Write data to memory + 's', -- Retain previous memory contents + + 'c', -- Corrupt entire memory with 'X' + 'l', -- Corrupt a word in memory with 'X' + 'd', -- Corrupt a single bit in memory with 'X' + 'e', -- Corrupt a word with 'X' based on data in + 'C', -- Corrupt a sub-word entire memory with 'X' + 'L', -- Corrupt a sub-word in memory with 'X' + + -- The following entries are commented since their + -- interpretation overlap with existing definitions. + + -- 'D', -- Corrupt a single bit of a sub-word with 'X' + -- 'E', -- Corrupt a sub-word with 'X' based on datain + + 'M', -- Implicit read data from memory + 'm', -- Read data from memory + 't' -- Immediate assign/transfer data in + +); + +TYPE VitalMemoryTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> ) + OF VitalMemorySymbolType; + +TYPE VitalMemoryViolationSymbolType IS ( + 'X', -- Unknown level + '0', -- low level + '-' -- don't care +); + +TYPE VitalMemoryViolationTableType IS + ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> ) + OF VitalMemoryViolationSymbolType; + +TYPE VitalPortType IS ( + UNDEF, + READ, + WRITE, + RDNWR +); + +TYPE VitalCrossPortModeType IS ( + CpRead, -- CpReadOnly, + WriteContention, -- WrContOnly, + ReadWriteContention, -- CpContention + CpReadAndWriteContention, -- WrContAndCpRead, + CpReadAndReadContention +); + +SUBTYPE VitalAddressValueType IS INTEGER; +TYPE VitalAddressValueVectorType IS + ARRAY (NATURAL RANGE <>) OF VitalAddressValueType; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalDeclareMemory +-- Parameters: NoOfWords - Number of words in the memory +-- NoOfBitsPerWord - Number of bits per word in memory +-- NoOfBitsPerSubWord - Number of bits per sub word +-- MemoryLoadFile - Name of data file to load +-- Description: This function is intended to be used to initialize +-- memory data declarations, i.e. to be executed duing +-- simulation elaboration time. Handles the allocation +-- and initialization of memory for the memory data. +-- Default NoOfBitsPerSubWord is NoOfBits. +-- ---------------------------------------------------------------------------- + +IMPURE FUNCTION VitalDeclareMemory ( + CONSTANT NoOfWords : IN POSITIVE; + CONSTANT NoOfBitsPerWord : IN POSITIVE; + CONSTANT NoOfBitsPerSubWord : IN POSITIVE; + CONSTANT MemoryLoadFile : IN string := ""; + CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE +) RETURN VitalMemoryDataType; + +IMPURE FUNCTION VitalDeclareMemory ( + CONSTANT NoOfWords : IN POSITIVE; + CONSTANT NoOfBitsPerWord : IN POSITIVE; + CONSTANT MemoryLoadFile : IN string := ""; + CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE +) RETURN VitalMemoryDataType; + + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryTable +-- Parameters: DataOutBus - Output candidate zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- PrevControls - Previous data in for edge detection +-- PrevEnableBus - Previous enables for edge detection +-- PrevDataInBus - Previous data bus for edge detection +-- PrevAddressBus - Previous address bus for edge detection +-- PortFlag - Indicates port operating mode +-- PortFlagArray - Vector form of PortFlag for sub-word +-- Controls - Agregate of scalar control lines +-- EnableBus - Concatenation of vector control lines +-- DataInBus - Input value of data bus in +-- AddressBus - Input value of address bus in +-- AddressValue - Decoded value of the AddressBus +-- MemoryTable - Input memory action table +-- PortType - The type of port (currently not used) +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- MsgSeverity - Control level of message generation +-- Description: This procedure implements the majority of the memory +-- modeling functionality via lookup of the memory action +-- tables and performing the specified actions if matches +-- are found, or the default actions otherwise. The +-- overloadings are provided for the word and sub-word +-- (using the EnableBus and PortFlagArray arguments) addressing +-- cases. +-- ---------------------------------------------------------------------------- + +PROCEDURE VitalMemoryTable ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PrevControls : INOUT std_logic_vector; + VARIABLE PrevDataInBus : INOUT std_logic_vector; + VARIABLE PrevAddressBus : INOUT std_logic_vector; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT Controls : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressBus : IN std_logic_vector; + VARIABLE AddressValue : INOUT VitalAddressValueType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType := UNDEF; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +); + +PROCEDURE VitalMemoryTable ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PrevControls : INOUT std_logic_vector; + VARIABLE PrevEnableBus : INOUT std_logic_vector; + VARIABLE PrevDataInBus : INOUT std_logic_vector; + VARIABLE PrevAddressBus : INOUT std_logic_vector; + VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType; + CONSTANT Controls : IN std_logic_vector; + CONSTANT EnableBus : IN std_logic_vector; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressBus : IN std_logic_vector; + VARIABLE AddressValue : INOUT VitalAddressValueType; + CONSTANT MemoryTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType := UNDEF; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +); + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryCrossPorts +-- Parameters: DataOutBus - Output candidate zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- SamePortFlag - Operating mode for same port +-- SamePortAddressValue - Decoded AddressBus for same port +-- CrossPortFlagArray - Operating modes for cross ports +-- CrossPortAddressArray - Decoded AddressBus for cross ports +-- CrossPortMode - Write contention and crossport read control +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- +-- Description: These procedures control the effect of memory operations +-- on a given port due to operations on other ports in a +-- multi-port memory. +-- This includes data write through when reading and writing +-- to the same address, as well as write contention when +-- there are multiple write to the same address. +-- If addresses do not match then data bus is unchanged. +-- The DataOutBus can be diabled with 'Z' value. +-- ---------------------------------------------------------------------------- + +PROCEDURE VitalMemoryCrossPorts ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType; + CONSTANT SamePortAddressValue : IN VitalAddressValueType; + CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType; + CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType; + CONSTANT CrossPortMode : IN VitalCrossPortModeType + := CpReadAndWriteContention; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) ; + +PROCEDURE VitalMemoryCrossPorts ( + VARIABLE MemoryData : INOUT VitalMemoryDataType; + CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType; + CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE +) ; + +-- ---------------------------------------------------------------------------- +-- Procedure: VitalMemoryViolation +-- Parameters: DataOutBus - Output zero delay data bus out +-- MemoryData - Pointer to memory data structure +-- PortFlag - Indicates port operating mode +-- DataInBus - Input value of data bus in +-- AddressValue - Decoded value of the AddressBus +-- ViolationFlags - Aggregate of scalar violation vars +-- ViolationFlagsArray - Concatenation of vector violation vars +-- ViolationTable - Input memory violation table +-- PortType - The type of port (currently not used) +-- PortName - Port name string for messages +-- HeaderMsg - Header string for messages +-- MsgOn - Control the generation of messages +-- MsgSeverity - Control level of message generation +-- Description: This procedure is intended to implement all actions on the +-- memory contents and data out bus as a result of timing viols. +-- It uses the memory action table to perform various corruption +-- policies specified by the user. +-- ---------------------------------------------------------------------------- + +PROCEDURE VitalMemoryViolation ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressValue : IN VitalAddressValueType; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationFlagsArray : IN X01ArrayT; + CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) ; + +PROCEDURE VitalMemoryViolation ( + VARIABLE DataOutBus : INOUT std_logic_vector; + VARIABLE MemoryData : INOUT VitalMemoryDataType; + VARIABLE PortFlag : INOUT VitalPortFlagVectorType; + CONSTANT DataInBus : IN std_logic_vector; + CONSTANT AddressValue : IN VitalAddressValueType; + CONSTANT ViolationFlags : IN std_logic_vector; + CONSTANT ViolationTable : IN VitalMemoryTableType; + CONSTANT PortType : IN VitalPortType; + CONSTANT PortName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := ""; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING +) ; + +END Vital_Memory; diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_b.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_b.vhdl new file mode 100644 index 0000000..dcfc92b --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_b.vhdl @@ -0,0 +1,5622 @@ +------------------------------------------------------------------------------- +-- Title : Standard VITAL_Primitives Package +-- : $Revision$ +-- : +-- Library : VITAL +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : +-- Purpose : This packages defines standard types, constants, functions +-- : and procedures for use in developing ASIC models. +-- : Specifically a set of logic primitives are defined. +-- : +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No:|Auth:| Mod.Date:| Changes Made: +-- v95.0 A | | 06/02/95 | Initial ballot draft 1995 +-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap +-- ---------------------------------------------------------------------------- +-- v95.2 | ddl | 09/14/96 | #223 - single input prmtvs use on-detect +-- | | | instead of glitch-on-event behavior +-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of +-- | | | of class SIGNAL +-- v95.4 | ddl | 01/16/97 | #243 - index constraint error in nbit xor/xnor +-- v99.1 | dbb | 03/31/99 | Updated for VHDL 93 +-- ---------------------------------------------------------------------------- + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +PACKAGE BODY VITAL_Primitives IS + -- ------------------------------------------------------------------------ + -- Default values for Primitives + -- ------------------------------------------------------------------------ + -- default values for delay parameters + CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01; + CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z; + + TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME; + + -- default primitive model operation parameters + -- Glitch detection/reporting + TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch); + CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly; + + -- ------------------------------------------------------------------------ + -- Local Type and Subtype Declarations + -- ------------------------------------------------------------------------ + --------------------------------------------------------------------------- + -- enumeration value representing the transition or level of the signal. + -- See function 'GetEdge' + --------------------------------------------------------------------------- + TYPE EdgeType IS ( 'U', -- Uninitialized level + 'X', -- Unknown level + '0', -- low level + '1', -- high level + '\', -- 1 to 0 falling edge + '/', -- 0 to 1 rising edge + 'F', -- * to 0 falling edge + 'R', -- * to 1 rising edge + 'f', -- rising to X edge + 'r', -- falling to X edge + 'x', -- Unknown edge (ie U->X) + 'V' -- Timing violation edge + ); + TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType; + + TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType; + TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType; + TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType; + TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType; + + TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType; + TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType; + + TYPE GlitchDataType IS + RECORD + SchedTime : TIME; + GlitchTime : TIME; + SchedValue : std_ulogic; + CurrentValue : std_ulogic; + END RECORD; + TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>) + OF GlitchDataType; + + -- Enumerated type used in selection of output path delays + TYPE SchedType IS + RECORD + inp0 : TIME; -- time (abs) of output change due to input change to 0 + inp1 : TIME; -- time (abs) of output change due to input change to 1 + InpX : TIME; -- time (abs) of output change due to input change to X + Glch0 : TIME; -- time (abs) of output glitch due to input change to 0 + Glch1 : TIME; -- time (abs) of output glitch due to input change to 0 + END RECORD; + + TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType; + CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns); + CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns); + + -- Constrained array declarations (common sizes used by primitives) + SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0); + SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0); + SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0); + SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0); + + SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0); + SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0); + SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0); + SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0); + + SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0); + SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0); + SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0); + SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0); + + SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0); + SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0); + SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0); + SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0); + + CONSTANT DefSchedArray2 : SchedArray2 := + (OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns)); + + TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; + + CONSTANT InitialEdge : LogicToLevelT := ( + '1'|'H' => 'R', + '0'|'L' => 'F', + OTHERS => 'x' + ); + + CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current + -- old \ new: U X 0 1 Z W L H - + 'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ), + 'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ), + '0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ), + '1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ), + 'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ), + 'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ), + 'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ), + 'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ), + '-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ) + ); + CONSTANT LogicToLevel : LogicToLevelT := ( + '1'|'H' => '1', + '0'|'L' => '0', + 'U' => 'U', + OTHERS => 'X' + ); + + -- ----------------------------------- + -- 3-state logic tables + -- ----------------------------------- + CONSTANT BufIf0_Table : stdlogic_table := + -- enable data value + ( '1'|'H' => ( OTHERS => 'Z' ), + '0'|'L' => ( '1'|'H' => '1', + '0'|'L' => '0', + 'U' => 'U', + OTHERS => 'X' ), + 'U' => ( OTHERS => 'U' ), + OTHERS => ( OTHERS => 'X' ) ); + CONSTANT BufIf1_Table : stdlogic_table := + -- enable data value + ( '0'|'L' => ( OTHERS => 'Z' ), + '1'|'H' => ( '1'|'H' => '1', + '0'|'L' => '0', + 'U' => 'U', + OTHERS => 'X' ), + 'U' => ( OTHERS => 'U' ), + OTHERS => ( OTHERS => 'X' ) ); + CONSTANT InvIf0_Table : stdlogic_table := + -- enable data value + ( '1'|'H' => ( OTHERS => 'Z' ), + '0'|'L' => ( '1'|'H' => '0', + '0'|'L' => '1', + 'U' => 'U', + OTHERS => 'X' ), + 'U' => ( OTHERS => 'U' ), + OTHERS => ( OTHERS => 'X' ) ); + CONSTANT InvIf1_Table : stdlogic_table := + -- enable data value + ( '0'|'L' => ( OTHERS => 'Z' ), + '1'|'H' => ( '1'|'H' => '0', + '0'|'L' => '1', + 'U' => 'U', + OTHERS => 'X' ), + 'U' => ( OTHERS => 'U' ), + OTHERS => ( OTHERS => 'X' ) ); + + + TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER; + CONSTANT To_StateChar : To_StateCharType := + ( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v', + 'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' ); + TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER; + CONSTANT To_TruthChar : To_TruthCharType := + ( 'X', '0', '1', '-', 'B', 'Z' ); + + TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic; + CONSTANT TruthTableOutMap : TruthTableOutMapType := + -- 'X', '0', '1', '-', 'B', 'Z' + ( 'X', '0', '1', 'X', '-', 'Z' ); + + TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic; + -- does conversion to X01Z or '-' if invalid + CONSTANT StateTableOutMap : StateTableOutMapType := + -- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v' + -- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S' + ( '-','-','-','-','-','-','-','-','-','-','-','-', + '-','-','-','-','X','0','1','X','-','Z','W'); + + -- ------------------------------------------------------------------------ + TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN; + -- checks if a symbol IS valid for the stimulus portion of a truth table + CONSTANT ValidTruthTableInput : ValidTruthTableInputType := + -- 'X' '0' '1' '-' 'B' 'Z' + ( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE ); + + TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN; + -- checks if an input matches th corresponding truth table symbol + -- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol) + CONSTANT TruthTableMatch : TruthTableMatchType := ( + -- X, 0, 1, - B Z + ( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X + ( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0 + ( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1 + ); + + -- ------------------------------------------------------------------------ + TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN; + CONSTANT ValidStateTableInput : ValidStateTableInputType := + -- '/', '\', 'P', 'N', 'r', 'f', + ( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, + -- 'p', 'n', 'R', 'F', '^', 'v', + TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, + -- 'E', 'A', 'D', '*', + TRUE, TRUE, TRUE, TRUE, + -- 'X', '0', '1', '-', 'B', 'Z', + TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, + -- 'S' + TRUE ); + + CONSTANT ValidStateTableState : ValidStateTableInputType := + -- '/', '\', 'P', 'N', 'r', 'f', + ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, + -- 'p', 'n', 'R', 'F', '^', 'v', + FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, + -- 'E', 'A', 'D', '*', + FALSE, FALSE, FALSE, FALSE, + -- 'X', '0', '1', '-', 'B', 'Z', + TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, + -- 'S' + FALSE ); + + TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN; + -- last value, present value, table symbol + CONSTANT StateTableMatch : StateTableMatchType := ( + ( -- X (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE), + (FALSE,FALSE,FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, FALSE,TRUE, + TRUE, FALSE,TRUE, TRUE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE), + (FALSE,FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,TRUE, FALSE,TRUE, FALSE, + TRUE, TRUE, FALSE,TRUE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE) + ), + + (-- 0 (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + (FALSE,FALSE,FALSE,FALSE,TRUE, FALSE, + TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE), + (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ), + (TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + TRUE, FALSE,TRUE, FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE) + ), + + (-- 1 (lastvalue) + -- / \ P N r f + -- p n R F ^ v + -- E A D * + -- X 0 1 - B Z S + (FALSE,FALSE,FALSE,FALSE,FALSE,TRUE , + FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,TRUE, TRUE, + TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE), + (FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,TRUE, FALSE,TRUE, FALSE,FALSE, + FALSE,FALSE,FALSE,TRUE, + FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE), + (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,FALSE,FALSE, + FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE ) + ) + ); + + TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z; + ---------------------------------------------------------- + -- table name : cvt_to_x01z + -- parameters : std_ulogic -- some logic value + -- returns : UX01Z -- state value of logic value + -- purpose : to convert state-strength to state only + ---------------------------------------------------------- + CONSTANT cvt_to_ux01z : Logic_UX01Z_Table := + ('U','X','0','1','Z','X','0','1','X' ); + + TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER; + CONSTANT LogicCvtTable : LogicCvtTableType + := ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); + + -------------------------------------------------------------------- + -- LOCAL Utilities + -------------------------------------------------------------------- + -- ------------------------------------------------------------------------ + -- FUNCTION NAME : MINIMUM + -- + -- PARAMETERS : in1, in2 - integer, time + -- + -- DESCRIPTION : return smaller of in1 and in2 + -- ------------------------------------------------------------------------ + FUNCTION Minimum ( + CONSTANT in1, in2 : INTEGER + ) RETURN INTEGER IS + BEGIN + IF (in1 < in2) THEN + RETURN in1; + END IF; + RETURN in2; + END; + -- ------------------------------------------------------------------------ + FUNCTION Minimum ( + CONSTANT t1,t2 : IN TIME + ) RETURN TIME IS + BEGIN + IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF; + END Minimum; + + -- ------------------------------------------------------------------------ + -- FUNCTION NAME : MAXIMUM + -- + -- PARAMETERS : in1, in2 - integer, time + -- + -- DESCRIPTION : return larger of in1 and in2 + -- ------------------------------------------------------------------------ + FUNCTION Maximum ( + CONSTANT in1, in2 : INTEGER + ) RETURN INTEGER IS + BEGIN + IF (in1 > in2) THEN + RETURN in1; + END IF; + RETURN in2; + END; + ----------------------------------------------------------------------- + FUNCTION Maximum ( + CONSTANT t1,t2 : IN TIME + ) RETURN TIME IS + BEGIN + IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF; + END Maximum; + + ----------------------------------------------------------------------- + FUNCTION GlitchMinTime ( + CONSTANT Time1, Time2 : IN TIME + ) RETURN TIME IS + BEGIN + IF ( Time1 >= NOW ) THEN + IF ( Time2 >= NOW ) THEN + RETURN Minimum ( Time1, Time2); + ELSE + RETURN Time1; + END IF; + ELSE + IF ( Time2 >= NOW ) THEN + RETURN Time2; + ELSE + RETURN 0 ns; + END IF; + END IF; + END; + + -------------------------------------------------------------------- + -- Error Message Types and Tables + -------------------------------------------------------------------- + TYPE VitalErrorType IS ( + ErrNegDel, + ErrInpSym, + ErrOutSym, + ErrStaSym, + ErrVctLng, + ErrTabWidSml, + ErrTabWidLrg, + ErrTabResSml, + ErrTabResLrg + ); + + TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL; + CONSTANT VitalErrorSeverity : VitalErrorSeverityType := ( + ErrNegDel => WARNING, + ErrInpSym => ERROR, + ErrOutSym => ERROR, + ErrStaSym => ERROR, + ErrVctLng => ERROR, + ErrTabWidSml => ERROR, + ErrTabWidLrg => WARNING, + ErrTabResSml => WARNING, + ErrTabResLrg => WARNING + ); + + CONSTANT MsgNegDel : STRING := + "Negative delay. New output value not scheduled. Output signal is: "; + CONSTANT MsgInpSym : STRING := + "Illegal symbol in the input portion of a Truth/State table."; + CONSTANT MsgOutSym : STRING := + "Illegal symbol in the output portion of a Truth/State table."; + CONSTANT MsgStaSym : STRING := + "Illegal symbol in the state portion of a State table."; + CONSTANT MsgVctLng : STRING := + "Vector (array) lengths not equal. "; + CONSTANT MsgTabWidSml : STRING := + "Width of the Truth/State table is too small."; + CONSTANT MsgTabWidLrg : STRING := + "Width of Truth/State table is too large. Extra elements are ignored."; + CONSTANT MsgTabResSml : STRING := + "Result of Truth/State table has too many elements."; + CONSTANT MsgTabResLrg : STRING := + "Result of Truth/State table has too few elements."; + + CONSTANT MsgUnknown : STRING := + "Unknown error message."; + + -------------------------------------------------------------------- + -- LOCAL Utilities + -------------------------------------------------------------------- + FUNCTION VitalMessage ( + CONSTANT ErrorId : IN VitalErrorType + ) RETURN STRING IS + BEGIN + CASE ErrorId IS + WHEN ErrNegDel => RETURN MsgNegDel; + WHEN ErrInpSym => RETURN MsgInpSym; + WHEN ErrOutSym => RETURN MsgOutSym; + WHEN ErrStaSym => RETURN MsgStaSym; + WHEN ErrVctLng => RETURN MsgVctLng; + WHEN ErrTabWidSml => RETURN MsgTabWidSml; + WHEN ErrTabWidLrg => RETURN MsgTabWidLrg; + WHEN ErrTabResSml => RETURN MsgTabResSml; + WHEN ErrTabResLrg => RETURN MsgTabResLrg; + WHEN OTHERS => RETURN MsgUnknown; + END CASE; + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) + SEVERITY VitalErrorSeverity(ErrorId); + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType; + CONSTANT Info : IN STRING + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) & Info + SEVERITY VitalErrorSeverity(ErrorId); + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType; + CONSTANT Info : IN CHARACTER + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) & Info + SEVERITY VitalErrorSeverity(ErrorId); + END; + + --------------------------------------------------------------------------- + PROCEDURE ReportGlitch ( + CONSTANT GlitchRoutine : IN STRING; + CONSTANT OutSignalName : IN STRING; + CONSTANT PreemptedTime : IN TIME; + CONSTANT PreemptedValue : IN std_ulogic; + CONSTANT NewTime : IN TIME; + CONSTANT NewValue : IN std_ulogic; + CONSTANT Index : IN INTEGER := 0; + CONSTANT IsArraySignal : IN BOOLEAN := FALSE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + + VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE; + BEGIN + + Write (StrPtr1, PreemptedTime ); + Write (StrPtr2, NewTime); + Write (StrPtr3, LogicCvtTable(PreemptedValue)); + Write (StrPtr4, LogicCvtTable(NewValue)); + IF IsArraySignal THEN + Write (StrPtr5, STRING'( "(" ) ); + Write (StrPtr5, Index); + Write (StrPtr5, STRING'( ")" ) ); + ELSE + Write (StrPtr5, STRING'( " " ) ); + END IF; + + -- Issue Report only if Preemted value has not been + -- removed from event queue + ASSERT PreemptedTime > NewTime + REPORT GlitchRoutine & ": GLITCH Detected on port " & + OutSignalName & StrPtr5.ALL & + "; Preempted Future Value := " & StrPtr3.ALL & + " @ " & StrPtr1.ALL & + "; Newly Scheduled Value := " & StrPtr4.ALL & + " @ " & StrPtr2.ALL & + ";" + SEVERITY MsgSeverity; + + DEALLOCATE(StrPtr1); + DEALLOCATE(StrPtr2); + DEALLOCATE(StrPtr3); + DEALLOCATE(StrPtr4); + DEALLOCATE(StrPtr5); + RETURN; + END ReportGlitch; + + --------------------------------------------------------------------------- + -- Procedure : VitalGlitchOnEvent + -- : + -- Parameters : OutSignal ........ signal being driven + -- : OutSignalName..... name of the driven signal + -- : GlitchData........ internal data required by the procedure + -- : NewValue.......... new value being assigned + -- : NewDelay.......... Delay accompanying the assignment + -- : (Note: for vectors, this is an array) + -- : GlitchMode........ Glitch generation mode + -- : MessagePlusX, MessageOnly, + -- : XOnly, NoGlitch ) + -- : GlitchDelay....... if <= 0 ns , then there will be no Glitch + -- : if > NewDelay, then there is no Glitch, + -- : otherwise, this is the time when a FORCED + -- : generation of a glitch will occur. + ---------------------------------------------------------------------------- + PROCEDURE VitalGlitchOnEvent ( + SIGNAL OutSignal : OUT std_logic; + CONSTANT OutSignalName : IN STRING; + VARIABLE GlitchData : INOUT GlitchDataType; + CONSTANT NewValue : IN std_logic; + CONSTANT NewDelay : IN TIME := 0 ns; + CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX; + CONSTANT GlitchDelay : IN TIME := -1 ns; -- IR#223 + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + -- ------------------------------------------------------------------------ + VARIABLE NoGlitchDet : BOOLEAN := FALSE; + VARIABLE OldGlitch : BOOLEAN := FALSE; + VARIABLE Dly : TIME := NewDelay; + + BEGIN + -- If nothing to schedule, just return + IF NewDelay < 0 ns THEN + IF (NewValue /= GlitchData.SchedValue) THEN + VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName ); + END IF; + + ELSE + -- If nothing currently scheduled + IF GlitchData.SchedTime <= NOW THEN + GlitchData.CurrentValue := GlitchData.SchedValue; + IF (GlitchDelay <= 0 ns) THEN + IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF; + NoGlitchDet := TRUE; + END IF; + + -- Transaction currently scheduled - if glitch already happened + ELSIF GlitchData.GlitchTime <= NOW THEN + GlitchData.CurrentValue := 'X'; + OldGlitch := TRUE; + IF (GlitchData.SchedValue = NewValue) THEN + dly := Minimum( GlitchData.SchedTime-NOW, NewDelay ); + END IF; + + -- Transaction currently scheduled (no glitch if same value) + ELSIF (GlitchData.SchedValue = NewValue) AND + (GlitchData.SchedTime = GlitchData.GlitchTime) AND + (GlitchDelay <= 0 ns) THEN + NoGlitchDet := TRUE; + Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay ); + + END IF; + + GlitchData.SchedTime := NOW+Dly; + IF OldGlitch THEN + OutSignal <= NewValue AFTER Dly; + + ELSIF NoGlitchDet THEN + GlitchData.GlitchTime := NOW+Dly; + OutSignal <= NewValue AFTER Dly; + + ELSE -- new glitch + GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime, + NOW+GlitchDelay ); + + IF (GlitchMode = MessagePlusX) OR + (GlitchMode = MessageOnly) THEN + ReportGlitch ( "VitalGlitchOnEvent", OutSignalName, + GlitchData.GlitchTime, GlitchData.SchedValue, + (Dly + NOW), NewValue, + MsgSeverity=>MsgSeverity ); + END IF; + + IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN + OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW; + OutSignal <= TRANSPORT NewValue AFTER Dly; + ELSE + OutSignal <= NewValue AFTER Dly; + END IF; + END IF; + + GlitchData.SchedValue := NewValue; + END IF; + + RETURN; + END; + + ---------------------------------------------------------------------------- + PROCEDURE VitalGlitchOnEvent ( + SIGNAL OutSignal : OUT std_logic_vector; + CONSTANT OutSignalName : IN STRING; + VARIABLE GlitchData : INOUT GlitchDataArrayType; + CONSTANT NewValue : IN std_logic_vector; + CONSTANT NewDelay : IN VitalTimeArray; + CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX; + CONSTANT GlitchDelay : IN VitalTimeArray; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + + ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH) + IS GlitchData; + ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue; + ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH) + IS GlitchDelay; + ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay; + + VARIABLE Index : INTEGER := OutSignal'LEFT; + VARIABLE Direction : INTEGER; + VARIABLE NoGlitchDet : BOOLEAN; + VARIABLE OldGlitch : BOOLEAN; + VARIABLE Dly, GlDly : TIME; + + BEGIN + IF (OutSignal'LEFT > OutSignal'RIGHT) THEN + Direction := -1; + ELSE + Direction := 1; + END IF; + + IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR + (OutSignal'LENGTH /= NewValue'LENGTH) OR + (OutSignal'LENGTH /= NewDelay'LENGTH) OR + (OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN + VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName ); + RETURN; + END IF; + + -- a call to the scalar function cannot be made since the actual + -- name associated with a signal parameter must be locally static + FOR n IN 1 TO OutSignal'LENGTH LOOP + + NoGlitchDet := FALSE; + OldGlitch := FALSE; + Dly := NewDelAlias(n); + + -- If nothing to schedule, just skip to next loop iteration + IF NewDelAlias(n) < 0 ns THEN + IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN + VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName ); + END IF; + ELSE + -- If nothing currently scheduled (i.e. last scheduled + -- transaction already occurred) + IF GlDataAlias(n).SchedTime <= NOW THEN + GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue; + IF (GlDelayAlias(n) <= 0 ns) THEN + -- Next iteration if no change in value + IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN + Index := Index + Direction; + NEXT; + END IF; + -- since last transaction already occurred there is no glitch + NoGlitchDet := TRUE; + END IF; + + -- Transaction currently scheduled - if glitch already happened + ELSIF GlDataAlias(n).GlitchTime <= NOW THEN + GlDataAlias(n).CurrentValue := 'X'; + OldGlitch := TRUE; + IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN + dly := Minimum( GlDataAlias(n).SchedTime-NOW, + NewDelAlias(n) ); + END IF; + + -- Transaction currently scheduled + ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND + (GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND + (GlDelayAlias(n) <= 0 ns) THEN + NoGlitchDet := TRUE; + Dly := Minimum( GlDataAlias(n).SchedTime-NOW, + NewDelAlias(n) ); + END IF; + + -- update last scheduled transaction + GlDataAlias(n).SchedTime := NOW+Dly; + + IF OldGlitch THEN + OutSignal(Index) <= NewValAlias(n) AFTER Dly; + ELSIF NoGlitchDet THEN + -- if no glitch then update last glitch time + -- and OutSignal(actual_index) + GlDataAlias(n).GlitchTime := NOW+Dly; + OutSignal(Index) <= NewValAlias(n) AFTER Dly; + ELSE -- new glitch + GlDataAlias(n).GlitchTime := GlitchMinTime ( + GlDataAlias(n).GlitchTime, + NOW+GlDelayAlias(n) ); + + IF (GlitchMode = MessagePlusX) OR + (GlitchMode = MessageOnly) THEN + ReportGlitch ( "VitalGlitchOnEvent", OutSignalName, + GlDataAlias(n).GlitchTime, + GlDataAlias(n).SchedValue, + (Dly + NOW), NewValAlias(n), + Index, TRUE, MsgSeverity ); + END IF; + + IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN + GlDly := GlDataAlias(n).GlitchTime - NOW; + OutSignal(Index) <= 'X' AFTER GlDly; + OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly; + ELSE + OutSignal(Index) <= NewValAlias(n) AFTER Dly; + END IF; + + END IF; -- glitch / no-glitch + GlDataAlias(n).SchedValue := NewValAlias(n); + + END IF; -- NewDelAlias(n) < 0 ns + Index := Index + Direction; + END LOOP; + + RETURN; + END; + + --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------ + -- PROCEDURE NAME : TruthOutputX01Z + -- + -- PARAMETERS : table_out - output of table + -- X01Zout - output converted to X01Z + -- err - true if illegal character is encountered + -- + -- + -- DESCRIPTION : converts the output of a truth table to a valid + -- std_ulogic + -- ------------------------------------------------------------------------ + PROCEDURE TruthOutputX01Z ( + CONSTANT TableOut : IN VitalTruthSymbolType; + VARIABLE X01Zout : OUT std_ulogic; + VARIABLE Err : OUT BOOLEAN + ) IS + VARIABLE TempOut : std_ulogic; + BEGIN + Err := FALSE; + TempOut := TruthTableOutMap(TableOut); + IF (TempOut = '-') THEN + Err := TRUE; + TempOut := 'X'; + VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut)); + END IF; + X01Zout := TempOut; + END; + + -- ------------------------------------------------------------------------ + -- PROCEDURE NAME : StateOutputX01Z + -- + -- PARAMETERS : table_out - output of table + -- prev_out - previous output value + -- X01Zout - output cojnverted to X01Z + -- err - true if illegal character is encountered + -- + -- DESCRIPTION : converts the output of a state table to a + -- valid std_ulogic + -- ------------------------------------------------------------------------ + PROCEDURE StateOutputX01Z ( + CONSTANT TableOut : IN VitalStateSymbolType; + CONSTANT PrevOut : IN std_ulogic; + VARIABLE X01Zout : OUT std_ulogic; + VARIABLE Err : OUT BOOLEAN + ) IS + VARIABLE TempOut : std_ulogic; + BEGIN + Err := FALSE; + TempOut := StateTableOutMap(TableOut); + IF (TempOut = '-') THEN + Err := TRUE; + TempOut := 'X'; + VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut)); + ELSIF (TempOut = 'W') THEN + TempOut := To_X01Z(PrevOut); + END IF; + X01Zout := TempOut; + END; + + -- ------------------------------------------------------------------------ + -- PROCEDURE NAME: StateMatch + -- + -- PARAMETERS : symbol - symbol from state table + -- in2 - input from VitalStateTble procedure + -- to state table + -- in2LastValue - previous value of input + -- state - false if the symbol is from the input + -- portion of the table, + -- true if the symbol is from the state + -- portion of the table + -- Err - true if symbol is not a valid input symbol + -- ReturnValue - true if match occurred + -- + -- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches + -- symbol (from the state table). If symbol is an edge + -- value edge is set to true and in2 and in2LastValue are + -- checked against symbol. Err is set to true if symbol + -- is an invalid value for the input portion of the state + -- table. + -- + -- ------------------------------------------------------------------------ + PROCEDURE StateMatch ( + CONSTANT Symbol : IN VitalStateSymbolType; + CONSTANT in2 : IN std_ulogic; + CONSTANT in2LastValue : IN std_ulogic; + CONSTANT State : IN BOOLEAN; + VARIABLE Err : OUT BOOLEAN; + VARIABLE ReturnValue : OUT BOOLEAN + ) IS + BEGIN + IF (State) THEN + IF (NOT ValidStateTableState(Symbol)) THEN + VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol)); + Err := TRUE; + ReturnValue := FALSE; + ELSE + Err := FALSE; + ReturnValue := StateTableMatch(in2LastValue, in2, Symbol); + END IF; + ELSE + IF (NOT ValidStateTableInput(Symbol) ) THEN + VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol)); + Err := TRUE; + ReturnValue := FALSE; + ELSE + ReturnValue := StateTableMatch(in2LastValue, in2, Symbol); + Err := FALSE; + END IF; + END IF; + END; + + -- ----------------------------------------------------------------------- + -- FUNCTION NAME: StateTableLookUp + -- + -- PARAMETERS : StateTable - state table + -- PresentDataIn - current inputs + -- PreviousDataIn - previous inputs and states + -- NumStates - number of state variables + -- PresentOutputs - current state and current outputs + -- + -- DESCRIPTION : This function is used to find the output of the + -- StateTable corresponding to a given set of inputs. + -- + -- ------------------------------------------------------------------------ + FUNCTION StateTableLookUp ( + CONSTANT StateTable : VitalStateTableType; + CONSTANT PresentDataIn : std_logic_vector; + CONSTANT PreviousDataIn : std_logic_vector; + CONSTANT NumStates : NATURAL; + CONSTANT PresentOutputs : std_logic_vector + ) RETURN std_logic_vector IS + + CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH; + CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1; + CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1); + CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2); + CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates; + VARIABLE Inputs : std_logic_vector(0 TO NumInputs); + VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs) + := (OTHERS => 'X'); + VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1)) + := (OTHERS => 'X'); + VARIABLE Temp : std_ulogic; + VARIABLE Match : BOOLEAN; + VARIABLE Err : BOOLEAN := FALSE; + + -- This needs to be done since the TableLookup arrays must be + -- ascending starting with 0 + VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1, + 0 TO TableWidth - 1) + := StateTable; + + BEGIN + Inputs(0 TO InputSize-1) := PresentDataIn; + Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1); + PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1); + + ColLoop: -- Compare each entry in the table + FOR i IN TableAlias'RANGE(1) LOOP + + RowLoop: -- Check each element of the entry + FOR j IN 0 TO InputSize + NumStates LOOP + + IF (j = InputSize + NumStates) THEN -- a match occurred + FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP + StateOutputX01Z ( + TableAlias(i, TableWidth - k - 1), + PresentOutputs(PresentOutputs'LENGTH - k - 1), + Temp, Err); + ReturnValue(OutSize - k - 1) := Temp; + IF (Err) THEN + ReturnValue := (OTHERS => 'X'); + RETURN ReturnValue; + END IF; + END LOOP; + RETURN ReturnValue; + END IF; + + StateMatch ( TableAlias(i,j), + Inputs(j), PrevInputs(j), + j >= InputSize, Err, Match); + EXIT RowLoop WHEN NOT(Match); + EXIT ColLoop WHEN Err; + END LOOP RowLoop; + END LOOP ColLoop; + + ReturnValue := (OTHERS => 'X'); + RETURN ReturnValue; + END; + + -------------------------------------------------------------------- + -- to_ux01z + ------------------------------------------------------------------- + FUNCTION To_UX01Z ( s : std_ulogic + ) RETURN UX01Z IS + BEGIN + RETURN cvt_to_ux01z (s); + END; + + --------------------------------------------------------------------------- + -- Function : GetEdge + -- Purpose : Converts transitions on a given input signal into a + -- enumeration value representing the transition or level + -- of the signal. + -- + -- previous "value" current "value" := "edge" + -- --------------------------------------------------------- + -- '1' | 'H' '1' | 'H' '1' level, no edge + -- '0' | 'L' '1' | 'H' '/' rising edge + -- others '1' | 'H' 'R' rising from X + -- + -- '1' | 'H' '0' | 'L' '\' falling egde + -- '0' | 'L' '0' | 'L' '0' level, no edge + -- others '0' | 'L' 'F' falling from X + -- + -- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level + -- 'Z' 'Z' 'X' unknown (X) level + -- 'U' 'U' 'U' 'U' level + -- + -- '1' | 'H' others 'f' falling to X + -- '0' | 'L' others 'r' rising to X + -- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge + -- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge + -- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge + -- + --------------------------------------------------------------------------- + FUNCTION GetEdge ( + SIGNAL s : IN std_logic + ) RETURN EdgeType IS + BEGIN + IF (s'EVENT) + THEN RETURN LogicToEdge ( s'LAST_VALUE, s ); + ELSE RETURN LogicToLevel ( s ); + END IF; + END; + + --------------------------------------------------------------------------- + PROCEDURE GetEdge ( + SIGNAL s : IN std_logic_vector; + VARIABLE LastS : INOUT std_logic_vector; + VARIABLE Edge : OUT EdgeArray ) IS + + ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s; + ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS; + ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge; + BEGIN + IF s'LENGTH /= LastS'LENGTH OR + s'LENGTH /= Edge'LENGTH THEN + VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" ); + END IF; + + FOR n IN 1 TO s'LENGTH LOOP + EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) ); + LastSAlias(n) := sAlias(n); + END LOOP; + END; + + --------------------------------------------------------------------------- + FUNCTION ToEdge ( Value : IN std_logic + ) RETURN EdgeType IS + BEGIN + RETURN LogicToLevel( Value ); + END; + + -- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92 + ---------------------------------------------------------------------------- + IMPURE FUNCTION CurValue ( + CONSTANT GlitchData : IN GlitchDataType + ) RETURN std_logic IS + BEGIN + IF NOW >= GlitchData.SchedTime THEN + RETURN GlitchData.SchedValue; + ELSIF NOW >= GlitchData.GlitchTime THEN + RETURN 'X'; + ELSE + RETURN GlitchData.CurrentValue; + END IF; + END; + --------------------------------------------------------------------------- + IMPURE FUNCTION CurValue ( + CONSTANT GlitchData : IN GlitchDataArrayType + ) RETURN std_logic_vector IS + VARIABLE Result : std_logic_vector(GlitchData'RANGE); + BEGIN + FOR n IN GlitchData'RANGE LOOP + IF NOW >= GlitchData(n).SchedTime THEN + Result(n) := GlitchData(n).SchedValue; + ELSIF NOW >= GlitchData(n).GlitchTime THEN + Result(n) := 'X'; + ELSE + Result(n) := GlitchData(n).CurrentValue; + END IF; + END LOOP; + RETURN Result; + END; + + --------------------------------------------------------------------------- + -- function calculation utilities + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- Function : VitalSame + -- Returns : VitalSame compares the state (UX01) of two logic value. A + -- value of 'X' is returned if the values are different. The + -- common value is returned if the values are equal. + -- Purpose : When the result of a logic model may be either of two + -- separate input values (eg. when the select on a MUX is 'X'), + -- VitalSame may be used to determine if the result needs to + -- be 'X'. + -- Arguments : See the declarations below... + --------------------------------------------------------------------------- + FUNCTION VitalSame ( + CONSTANT a, b : IN std_ulogic + ) RETURN std_ulogic IS + BEGIN + IF To_UX01(a) = To_UX01(b) + THEN RETURN To_UX01(a); + ELSE RETURN 'X'; + END IF; + END; + + --------------------------------------------------------------------------- + -- delay selection utilities + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- Procedure : BufPath, InvPath + -- + -- Purpose : BufPath and InvPath compute output change times, based on + -- a change on an input port. The computed output change times + -- returned in the composite parameter 'schd'. + -- + -- BufPath and InpPath are used together with the delay path + -- selection functions (GetSchedDelay, VitalAND, VitalOR... ) + -- The 'schd' value from each of the input ports of a model are + -- combined by the delay selection functions (VitalAND, + -- VitalOR, ...). The GetSchedDelay procedure converts the + -- combined output changes times to the single delay (delta + -- time) value for scheduling the output change (passed to + -- VitalGlitchOnEvent). + -- + -- The values in 'schd' are: (absolute times) + -- inp0 : time of output change due to input change to 0 + -- inp1 : time of output change due to input change to 1 + -- inpX : time of output change due to input change to X + -- glch0 : time of output glitch due to input change to 0 + -- glch1 : time of output glitch due to input change to 1 + -- + -- The output times are computed from the model INPUT value + -- and not the final value. For this reason, 'BufPath' should + -- be used to compute the output times for a non-inverting + -- delay paths and 'InvPath' should be used to compute the + -- ouput times for inverting delay paths. Delay paths which + -- include both non-inverting and paths require usage of both + -- 'BufPath' and 'InvPath'. (IE this is needed for the + -- select->output path of a MUX -- See the VitalMUX model). + -- + -- + -- Parameters : schd....... Computed output result times. (INOUT parameter + -- modified only on input edges) + -- Iedg....... Input port edge/level value. + -- tpd....... Propagation delays from this input + -- + --------------------------------------------------------------------------- + + PROCEDURE BufPath ( + VARIABLE Schd : INOUT SchedType; + CONSTANT Iedg : IN EdgeType; + CONSTANT tpd : IN VitalDelayType01 + ) IS + BEGIN + CASE Iedg IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd.inp0 := TIME'HIGH; + Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1; + Schd.InpX := Schd.inp1; + WHEN '\'|'F' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0; + Schd.InpX := Schd.inp0; + WHEN 'r' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := TIME'HIGH; + Schd.InpX := NOW + tpd(tr01); + WHEN 'f' => Schd.inp0 := TIME'HIGH; + Schd.inp1 := TIME'HIGH; + Schd.InpX := NOW + tpd(tr10); + WHEN 'x' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := TIME'HIGH; + -- update for X->X change + Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END; + + PROCEDURE BufPath ( + VARIABLE Schd : INOUT SchedArray; + CONSTANT Iedg : IN EdgeArray; + CONSTANT tpd : IN VitalDelayArrayType01 + ) IS + BEGIN + FOR n IN Schd'RANGE LOOP + CASE Iedg(n) IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH; + Schd(n).inp1 := NOW + tpd(n)(tr01); + Schd(n).Glch1 := Schd(n).inp1; + Schd(n).InpX := Schd(n).inp1; + WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := NOW + tpd(n)(tr10); + Schd(n).Glch0 := Schd(n).inp0; + Schd(n).InpX := Schd(n).inp0; + WHEN 'r' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := TIME'HIGH; + Schd(n).InpX := NOW + tpd(n)(tr01); + WHEN 'f' => Schd(n).inp0 := TIME'HIGH; + Schd(n).inp1 := TIME'HIGH; + Schd(n).InpX := NOW + tpd(n)(tr10); + WHEN 'x' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := TIME'HIGH; + -- update for X->X change + Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10), + tpd(n)(tr01) ); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END LOOP; + END; + + PROCEDURE InvPath ( + VARIABLE Schd : INOUT SchedType; + CONSTANT Iedg : IN EdgeType; + CONSTANT tpd : IN VitalDelayType01 + ) IS + BEGIN + CASE Iedg IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd.inp0 := TIME'HIGH; + Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1; + Schd.InpX := Schd.inp1; + WHEN '\'|'F' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0; + Schd.InpX := Schd.inp0; + WHEN 'r' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := TIME'HIGH; + Schd.InpX := NOW + tpd(tr10); + WHEN 'f' => Schd.inp0 := TIME'HIGH; + Schd.inp1 := TIME'HIGH; + Schd.InpX := NOW + tpd(tr01); + WHEN 'x' => Schd.inp1 := TIME'HIGH; + Schd.inp0 := TIME'HIGH; + -- update for X->X change + Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END; + + PROCEDURE InvPath ( + VARIABLE Schd : INOUT SchedArray; + CONSTANT Iedg : IN EdgeArray; + CONSTANT tpd : IN VitalDelayArrayType01 + ) IS + BEGIN + FOR n IN Schd'RANGE LOOP + CASE Iedg(n) IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH; + Schd(n).inp1 := NOW + tpd(n)(tr10); + Schd(n).Glch1 := Schd(n).inp1; + Schd(n).InpX := Schd(n).inp1; + WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := NOW + tpd(n)(tr01); + Schd(n).Glch0 := Schd(n).inp0; + Schd(n).InpX := Schd(n).inp0; + WHEN 'r' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := TIME'HIGH; + Schd(n).InpX := NOW + tpd(n)(tr10); + WHEN 'f' => Schd(n).inp0 := TIME'HIGH; + Schd(n).inp1 := TIME'HIGH; + Schd(n).InpX := NOW + tpd(n)(tr01); + WHEN 'x' => Schd(n).inp1 := TIME'HIGH; + Schd(n).inp0 := TIME'HIGH; + -- update for X->X change + Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10), + tpd(n)(tr01) ); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END LOOP; + END; + + --------------------------------------------------------------------------- + -- Procedure : BufEnab, InvEnab + -- + -- Purpose : BufEnab and InvEnab compute output change times, from a + -- change on an input enable port for a 3-state driver. The + -- computed output change times are returned in the composite + -- parameters 'schd1', 'schd0'. + -- + -- BufEnab and InpEnab are used together with the delay path + -- selection functions (GetSchedDelay, VitalAND, VitalOR... ) + -- The 'schd' value from each of the non-enable input ports of + -- a model (See BufPath, InvPath) are combined using the delay + -- selection functions (VitalAND, VitalOR, ...). The + -- GetSchedDelay procedure combines the output times on the + -- enable path with the output times from the data path(s) and + -- computes the single delay (delta time) value for scheduling + -- the output change (passed to VitalGlitchOnEvent) + -- + -- The values in 'schd*' are: (absolute times) + -- inp0 : time of output change due to input change to 0 + -- inp1 : time of output change due to input change to 1 + -- inpX : time of output change due to input change to X + -- glch0 : time of output glitch due to input change to 0 + -- glch1 : time of output glitch due to input change to 1 + -- + -- 'schd1' contains output times for 1->Z, Z->1 transitions. + -- 'schd0' contains output times for 0->Z, Z->0 transitions. + -- + -- 'BufEnab' is used for computing the output times for an + -- high asserted enable (output 'Z' for enable='0'). + -- 'InvEnab' is used for computing the output times for an + -- low asserted enable (output 'Z' for enable='1'). + -- + -- Note: separate 'schd1', 'schd0' parameters are generated + -- so that the combination of the delay paths from + -- multiple enable signals may be combined using the + -- same functions/operators used in combining separate + -- data paths. (See exampe 2 below) + -- + -- + -- Parameters : schd1...... Computed output result times for 1->Z, Z->1 + -- transitions. This parameter is modified only on + -- input edge values (events). + -- schd0...... Computed output result times for 0->Z, 0->1 + -- transitions. This parameter is modified only on + -- input edge values (events). + -- Iedg....... Input port edge/level value. + -- tpd....... Propagation delays for the enable -> output path. + -- + --------------------------------------------------------------------------- + PROCEDURE BufEnab ( + VARIABLE Schd1 : INOUT SchedType; + VARIABLE Schd0 : INOUT SchedType; + CONSTANT Iedg : IN EdgeType; + CONSTANT tpd : IN VitalDelayType01Z + ) IS + BEGIN + CASE Iedg IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := NOW + tpd(trz1); + Schd1.Glch1 := Schd1.inp1; + Schd1.InpX := Schd1.inp1; + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := NOW + tpd(trz0); + Schd0.Glch1 := Schd0.inp1; + Schd0.InpX := Schd0.inp1; + WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH; + Schd1.inp0 := NOW + tpd(tr1z); + Schd1.Glch0 := Schd1.inp0; + Schd1.InpX := Schd1.inp0; + Schd0.inp1 := TIME'HIGH; + Schd0.inp0 := NOW + tpd(tr0z); + Schd0.Glch0 := Schd0.inp0; + Schd0.InpX := Schd0.inp0; + WHEN 'r' => Schd1.inp1 := TIME'HIGH; + Schd1.inp0 := TIME'HIGH; + Schd1.InpX := NOW + tpd(trz1); + Schd0.inp1 := TIME'HIGH; + Schd0.inp0 := TIME'HIGH; + Schd0.InpX := NOW + tpd(trz0); + WHEN 'f' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := TIME'HIGH; + Schd1.InpX := NOW + tpd(tr1z); + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := TIME'HIGH; + Schd0.InpX := NOW + tpd(tr0z); + WHEN 'x' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := TIME'HIGH; + Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := TIME'HIGH; + Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END; + + PROCEDURE InvEnab ( + VARIABLE Schd1 : INOUT SchedType; + VARIABLE Schd0 : INOUT SchedType; + CONSTANT Iedg : IN EdgeType; + CONSTANT tpd : IN VitalDelayType01Z + ) IS + BEGIN + CASE Iedg IS + WHEN '0'|'1' => NULL; -- no edge: no timing update + WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := NOW + tpd(tr1z); + Schd1.Glch1 := Schd1.inp1; + Schd1.InpX := Schd1.inp1; + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := NOW + tpd(tr0z); + Schd0.Glch1 := Schd0.inp1; + Schd0.InpX := Schd0.inp1; + WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH; + Schd1.inp0 := NOW + tpd(trz1); + Schd1.Glch0 := Schd1.inp0; + Schd1.InpX := Schd1.inp0; + Schd0.inp1 := TIME'HIGH; + Schd0.inp0 := NOW + tpd(trz0); + Schd0.Glch0 := Schd0.inp0; + Schd0.InpX := Schd0.inp0; + WHEN 'r' => Schd1.inp1 := TIME'HIGH; + Schd1.inp0 := TIME'HIGH; + Schd1.InpX := NOW + tpd(tr1z); + Schd0.inp1 := TIME'HIGH; + Schd0.inp0 := TIME'HIGH; + Schd0.InpX := NOW + tpd(tr0z); + WHEN 'f' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := TIME'HIGH; + Schd1.InpX := NOW + tpd(trz1); + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := TIME'HIGH; + Schd0.InpX := NOW + tpd(trz0); + WHEN 'x' => Schd1.inp0 := TIME'HIGH; + Schd1.inp1 := TIME'HIGH; + Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + Schd0.inp0 := TIME'HIGH; + Schd0.inp1 := TIME'HIGH; + Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01)); + WHEN OTHERS => NULL; -- no timing change + END CASE; + END; + + --------------------------------------------------------------------------- + -- Procedure : GetSchedDelay + -- + -- Purpose : GetSchedDelay computes the final delay (incremental) for + -- for scheduling an output signal. The delay is computed + -- from the absolute output times in the 'NewSched' parameter. + -- (See BufPath, InvPath). + -- + -- Computation of the output delay for non-3_state outputs + -- consists of selection the appropriate output time based + -- on the new output value 'NewValue' and subtracting 'NOW' + -- to convert to an incremental delay value. + -- + -- The Computation of the output delay for 3_state output + -- also includes combination of the enable path delay with + -- the date path delay. + -- + -- Parameters : NewDelay... Returned output delay value. + -- GlchDelay.. Returned output delay for the start of a glitch. + -- NewValue... New output value. + -- CurValue... Current value of the output. + -- NewSched... Composite containing the combined absolute + -- output times from the data inputs. + -- EnSched1... Composite containing the combined absolute + -- output times from the enable input(s). + -- (for a 3_state output transitions 1->Z, Z->1) + -- EnSched0... Composite containing the combined absolute + -- output times from the enable input(s). + -- (for a 3_state output transitions 0->Z, Z->0) + -- + --------------------------------------------------------------------------- + PROCEDURE GetSchedDelay ( + VARIABLE NewDelay : OUT TIME; + VARIABLE GlchDelay : OUT TIME; + CONSTANT NewValue : IN std_ulogic; + CONSTANT CurValue : IN std_ulogic; + CONSTANT NewSched : IN SchedType + ) IS + VARIABLE Tim, Glch : TIME; + BEGIN + + CASE To_UX01(NewValue) IS + WHEN '0' => Tim := NewSched.inp0; + Glch := NewSched.Glch1; + WHEN '1' => Tim := NewSched.inp1; + Glch := NewSched.Glch0; + WHEN OTHERS => Tim := NewSched.InpX; + Glch := -1 ns; + END CASE; + IF (CurValue /= NewValue) + THEN Glch := -1 ns; + END IF; + + NewDelay := Tim - NOW; + IF Glch < 0 ns + THEN GlchDelay := Glch; + ELSE GlchDelay := Glch - NOW; + END IF; -- glch < 0 ns + END; + + PROCEDURE GetSchedDelay ( + VARIABLE NewDelay : OUT VitalTimeArray; + VARIABLE GlchDelay : OUT VitalTimeArray; + CONSTANT NewValue : IN std_logic_vector; + CONSTANT CurValue : IN std_logic_vector; + CONSTANT NewSched : IN SchedArray + ) IS + VARIABLE Tim, Glch : TIME; + ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1) + IS NewDelay; + ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1) + IS GlchDelay; + ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1) + IS NewSched; + ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 ) + IS NewValue; + ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 ) + IS CurValue; + BEGIN + FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP + CASE To_UX01(NewValueAlias(n)) IS + WHEN '0' => Tim := NewSchedAlias(n).inp0; + Glch := NewSchedAlias(n).Glch1; + WHEN '1' => Tim := NewSchedAlias(n).inp1; + Glch := NewSchedAlias(n).Glch0; + WHEN OTHERS => Tim := NewSchedAlias(n).InpX; + Glch := -1 ns; + END CASE; + IF (CurValueAlias(n) /= NewValueAlias(n)) + THEN Glch := -1 ns; + END IF; + + NewDelayAlias(n) := Tim - NOW; + IF Glch < 0 ns + THEN GlchDelayAlias(n) := Glch; + ELSE GlchDelayAlias(n) := Glch - NOW; + END IF; -- glch < 0 ns + END LOOP; + RETURN; + END; + + PROCEDURE GetSchedDelay ( + VARIABLE NewDelay : OUT TIME; + VARIABLE GlchDelay : OUT TIME; + CONSTANT NewValue : IN std_ulogic; + CONSTANT CurValue : IN std_ulogic; + CONSTANT NewSched : IN SchedType; + CONSTANT EnSched1 : IN SchedType; + CONSTANT EnSched0 : IN SchedType + ) IS + SUBTYPE v2 IS std_logic_vector(0 TO 1); + VARIABLE Tim, Glch : TIME; + BEGIN + + CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS + WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1); + Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0); + WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1); + Glch := EnSched1.Glch0; + WHEN "0Z" => Tim := EnSched0.inp0; + Glch := NewSched.Glch1; + WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX); + Glch := 0 ns; + WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1); + Glch := EnSched0.Glch0; + WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1); + Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0); + WHEN "1Z" => Tim := EnSched1.inp0; + Glch := NewSched.Glch0; + WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX); + Glch := 0 ns; + WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1); + IF NewSched.Glch0 > NOW + THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1); + ELSE Glch := 0 ns; + END IF; + WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1); + IF NewSched.Glch1 > NOW + THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1); + ELSE Glch := 0 ns; + END IF; + WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX); + Glch := 0 ns; + WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX); + Glch := 0 ns; + WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1); + Glch := 0 ns; + WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1); + Glch := 0 ns; + WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX); + Glch := 0 ns; + WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX); + Glch := 0 ns; + + END CASE; + NewDelay := Tim - NOW; + IF Glch < 0 ns + THEN GlchDelay := Glch; + ELSE GlchDelay := Glch - NOW; + END IF; -- glch < 0 ns + END; + + --------------------------------------------------------------------------- + -- Operators and Functions for combination (selection) of path delays + -- > These functions support selection of the "appripriate" path delay + -- dependent on the logic function. + -- > These functions only "select" from the possable output times. No + -- calculation (addition) of delays is performed. + -- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay' + -- > See primitive PROCEDURE models for examples. + --------------------------------------------------------------------------- + + FUNCTION "not" ( + CONSTANT a : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + z.inp1 := a.inp0 ; + z.inp0 := a.inp1 ; + z.InpX := a.InpX ; + z.Glch1 := a.Glch0; + z.Glch0 := a.Glch1; + RETURN (z); + END; + + FUNCTION "and" ( + CONSTANT a, b : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + z.inp1 := Maximum ( a.inp1 , b.inp1 ); + z.inp0 := Minimum ( a.inp0 , b.inp0 ); + z.InpX := GlitchMinTime ( a.InpX , b.InpX ); + z.Glch1 := Maximum ( a.Glch1, b.Glch1 ); + z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 ); + RETURN (z); + END; + + FUNCTION "or" ( + CONSTANT a, b : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + z.inp0 := Maximum ( a.inp0 , b.inp0 ); + z.inp1 := Minimum ( a.inp1 , b.inp1 ); + z.InpX := GlitchMinTime ( a.InpX , b.InpX ); + z.Glch0 := Maximum ( a.Glch0, b.Glch0 ); + z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 ); + RETURN (z); + END; + + IMPURE FUNCTION "nand" ( + CONSTANT a, b : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + z.inp0 := Maximum ( a.inp1 , b.inp1 ); + z.inp1 := Minimum ( a.inp0 , b.inp0 ); + z.InpX := GlitchMinTime ( a.InpX , b.InpX ); + z.Glch0 := Maximum ( a.Glch1, b.Glch1 ); + z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 ); + RETURN (z); + END; + + IMPURE FUNCTION "nor" ( + CONSTANT a, b : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + z.inp1 := Maximum ( a.inp0 , b.inp0 ); + z.inp0 := Minimum ( a.inp1 , b.inp1 ); + z.InpX := GlitchMinTime ( a.InpX , b.InpX ); + z.Glch1 := Maximum ( a.Glch0, b.Glch0 ); + z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 ); + RETURN (z); + END; + + -- ------------------------------------------------------------------------ + -- Delay Calculation for 2-bit Logical gates. + -- ------------------------------------------------------------------------ + IMPURE FUNCTION VitalXOR2 ( + CONSTANT ab,ai, bb,bi : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + -- z = (a AND b) NOR (a NOR b) + z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ), + Minimum (ab.inp1 , bb.inp1 ) ); + z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ), + Maximum (ab.inp0 , bb.inp0 ) ); + z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ), + Maximum (ab.InpX , bb.InpX ) ); + z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0), + GlitchMinTime (ab.Glch1, bb.Glch1) ); + z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1), + Maximum (ab.Glch0, bb.Glch0) ); + RETURN (z); + END; + + IMPURE FUNCTION VitalXNOR2 ( + CONSTANT ab,ai, bb,bi : IN SchedType + ) RETURN SchedType IS + VARIABLE z : SchedType; + BEGIN + -- z = (a AND b) OR (a NOR b) + z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ), + Minimum (ai.inp1 , bi.inp1 ) ); + z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ), + Maximum (ai.inp0 , bi.inp0 ) ); + z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ), + Maximum (ai.InpX , bi.InpX ) ); + z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0), + GlitchMinTime (ai.Glch1, bi.Glch1) ); + z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1), + Maximum (ai.Glch0, bi.Glch0) ); + RETURN (z); + END; + + -- ------------------------------------------------------------------------ + -- Delay Calculation for 3-bit Logical gates. + -- ------------------------------------------------------------------------ + IMPURE FUNCTION VitalXOR3 ( + CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType ) + RETURN SchedType IS + BEGIN + RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi), + VitalXOR2 (ai,ab, bi,bb), + cb, ci ); + END; + + IMPURE FUNCTION VitalXNOR3 ( + CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType ) + RETURN SchedType IS + BEGIN + RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ), + VitalXOR2 ( ai,ab, bi,bb ), + cb, ci ); + END; + + -- ------------------------------------------------------------------------ + -- Delay Calculation for 4-bit Logical gates. + -- ------------------------------------------------------------------------ + IMPURE FUNCTION VitalXOR4 ( + CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType ) + RETURN SchedType IS + BEGIN + RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ), + VitalXOR2 ( ai,ab, bi,bb ), + VitalXOR2 ( cb,ci, db,di ), + VitalXOR2 ( ci,cb, di,db ) ); + END; + + IMPURE FUNCTION VitalXNOR4 ( + CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType ) + RETURN SchedType IS + BEGIN + RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ), + VitalXOR2 ( ai,ab, bi,bb ), + VitalXOR2 ( cb,ci, db,di ), + VitalXOR2 ( ci,cb, di,db ) ); + END; + + -- ------------------------------------------------------------------------ + -- Delay Calculation for N-bit Logical gates. + -- ------------------------------------------------------------------------ + -- Note: index range on datab,datai assumed to be 1 TO length. + -- This is enforced by internal only usage of this Function + IMPURE FUNCTION VitalXOR ( + CONSTANT DataB, DataI : IN SchedArray + ) RETURN SchedType IS + CONSTANT Leng : INTEGER := DataB'LENGTH; + BEGIN + IF Leng = 2 THEN + RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) ); + ELSE + RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1), + DataI(1 TO Leng-1) ), + VitalXOR ( DataI(1 TO Leng-1), + DataB(1 TO Leng-1) ), + DataB(Leng),DataI(Leng) ); + END IF; + END; + + -- Note: index range on datab,datai assumed to be 1 TO length. + -- This is enforced by internal only usage of this Function + IMPURE FUNCTION VitalXNOR ( + CONSTANT DataB, DataI : IN SchedArray + ) RETURN SchedType IS + CONSTANT Leng : INTEGER := DataB'LENGTH; + BEGIN + IF Leng = 2 THEN + RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) ); + ELSE + RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1), + DataI(1 TO Leng-1) ), + VitalXOR ( DataI(1 TO Leng-1), + DataB(1 TO Leng-1) ), + DataB(Leng),DataI(Leng) ); + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Multiplexor + -- MUX .......... result := data(dselect) + -- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'), + -- data1 when (dselect = '1'), + -- 'X' when (dselect = 'X') and (data0 /= data1) + -- MUX4 .......... 4-input mux; result := data(dselect) + -- MUX8 .......... 8-input mux; result := data(dselect) + -- ------------------------------------------------------------------------ + FUNCTION VitalMUX2 ( + CONSTANT d1, d0 : IN SchedType; + CONSTANT sb, SI : IN SchedType + ) RETURN SchedType IS + BEGIN + RETURN (d1 AND sb) OR (d0 AND (NOT SI) ); + END; +-- + FUNCTION VitalMUX4 ( + CONSTANT Data : IN SchedArray4; + CONSTANT sb : IN SchedArray2; + CONSTANT SI : IN SchedArray2 + ) RETURN SchedType IS + BEGIN + RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) ) + OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) ); + END; + + FUNCTION VitalMUX8 ( + CONSTANT Data : IN SchedArray8; + CONSTANT sb : IN SchedArray3; + CONSTANT SI : IN SchedArray3 + ) RETURN SchedType IS + BEGIN + RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4), + sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) ) + OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0), + sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) ); + END; +-- + FUNCTION VInterMux ( + CONSTANT Data : IN SchedArray; + CONSTANT sb : IN SchedArray; + CONSTANT SI : IN SchedArray + ) RETURN SchedType IS + CONSTANT sMsb : INTEGER := sb'LENGTH; + CONSTANT dMsbHigh : INTEGER := Data'LENGTH; + CONSTANT dMsbLow : INTEGER := Data'LENGTH/2; + BEGIN + IF sb'LENGTH = 1 THEN + RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) ); + ELSIF sb'LENGTH = 2 THEN + RETURN VitalMUX4( Data, sb, SI ); + ELSIF sb'LENGTH = 3 THEN + RETURN VitalMUX8( Data, sb, SI ); + ELSIF sb'LENGTH > 3 THEN + RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1), + sb(sMsb-1 DOWNTO 1), + SI(sMsb-1 DOWNTO 1) )) + OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1), + sb(sMsb-1 DOWNTO 1), + SI(sMsb-1 DOWNTO 1) )); + ELSE + RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1 + END IF; + END; +-- + FUNCTION VitalMUX ( + CONSTANT Data : IN SchedArray; + CONSTANT sb : IN SchedArray; + CONSTANT SI : IN SchedArray + ) RETURN SchedType IS + CONSTANT msb : INTEGER := 2**sb'LENGTH; + VARIABLE lDat : SchedArray(msb DOWNTO 1); + ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data; + ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb; + ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI; + BEGIN + IF Data'LENGTH <= msb THEN + FOR i IN Data'LENGTH DOWNTO 1 LOOP + lDat(i) := DataAlias(i); + END LOOP; + FOR i IN msb DOWNTO Data'LENGTH+1 LOOP + lDat(i) := DefSchedAnd; + END LOOP; + ELSE + FOR i IN msb DOWNTO 1 LOOP + lDat(i) := DataAlias(i); + END LOOP; + END IF; + RETURN VInterMux( lDat, sbAlias, siAlias ); + END; + + -- ------------------------------------------------------------------------ + -- Decoder + -- General Algorithm : + -- (a) Result(...) := '0' when (enable = '0') + -- (b) Result(data) := '1'; all other subelements = '0' + -- ... Result array is decending (n-1 downto 0) + -- + -- DECODERn .......... n:2**n decoder + -- ------------------------------------------------------------------------ + FUNCTION VitalDECODER2 ( + CONSTANT DataB : IN SchedType; + CONSTANT DataI : IN SchedType; + CONSTANT Enable : IN SchedType + ) RETURN SchedArray IS + VARIABLE Result : SchedArray2; + BEGIN + Result(1) := Enable AND ( DataB); + Result(0) := Enable AND (NOT DataI); + RETURN Result; + END; + + FUNCTION VitalDECODER4 ( + CONSTANT DataB : IN SchedArray2; + CONSTANT DataI : IN SchedArray2; + CONSTANT Enable : IN SchedType + ) RETURN SchedArray IS + VARIABLE Result : SchedArray4; + BEGIN + Result(3) := Enable AND ( DataB(1)) AND ( DataB(0)); + Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0)); + Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0)); + Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0)); + RETURN Result; + END; + + FUNCTION VitalDECODER8 ( + CONSTANT DataB : IN SchedArray3; + CONSTANT DataI : IN SchedArray3; + CONSTANT Enable : IN SchedType + ) RETURN SchedArray IS + VARIABLE Result : SchedArray8; + BEGIN + Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0)); + Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0)); + Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0)); + Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0)); + Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0)); + Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0)); + Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0)); + Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0)); + RETURN Result; + END; + + + FUNCTION VitalDECODER ( + CONSTANT DataB : IN SchedArray; + CONSTANT DataI : IN SchedArray; + CONSTANT Enable : IN SchedType + ) RETURN SchedArray IS + CONSTANT DMsb : INTEGER := DataB'LENGTH - 1; + ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB; + ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI; + BEGIN + IF DataB'LENGTH = 1 THEN + RETURN VitalDECODER2 ( DataBAlias( 0 ), + DataIAlias( 0 ), Enable ); + ELSIF DataB'LENGTH = 2 THEN + RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0), + DataIAlias(1 DOWNTO 0), Enable ); + ELSIF DataB'LENGTH = 3 THEN + RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0), + DataIAlias(2 DOWNTO 0), Enable ); + ELSIF DataB'LENGTH > 3 THEN + RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0), + DataIAlias(DMsb-1 DOWNTO 0), + Enable AND ( DataBAlias(DMsb)) ) + & VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0), + DataIAlias(DMsb-1 DOWNTO 0), + Enable AND (NOT DataIAlias(DMsb)) ); + ELSE + RETURN DefSchedArray2; + END IF; + END; + + +------------------------------------------------------------------------------- +-- PRIMITIVES +------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------ + -- N-bit wide Logical gates. + -- ------------------------------------------------------------------------ + FUNCTION VitalAND ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '1'; + FOR i IN Data'RANGE LOOP + Result := Result AND Data(i); + END LOOP; + RETURN ResultMap(Result); + END; +-- + FUNCTION VitalOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '0'; + FOR i IN Data'RANGE LOOP + Result := Result OR Data(i); + END LOOP; + RETURN ResultMap(Result); + END; +-- + FUNCTION VitalXOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '0'; + FOR i IN Data'RANGE LOOP + Result := Result XOR Data(i); + END LOOP; + RETURN ResultMap(Result); + END; +-- + FUNCTION VitalNAND ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '1'; + FOR i IN Data'RANGE LOOP + Result := Result AND Data(i); + END LOOP; + RETURN ResultMap(NOT Result); + END; +-- + FUNCTION VitalNOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '0'; + FOR i IN Data'RANGE LOOP + Result := Result OR Data(i); + END LOOP; + RETURN ResultMap(NOT Result); + END; +-- + FUNCTION VitalXNOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + Result := '0'; + FOR i IN Data'RANGE LOOP + Result := Result XOR Data(i); + END LOOP; + RETURN ResultMap(NOT Result); + END; + + -- ------------------------------------------------------------------------ + -- Commonly used 2-bit Logical gates. + -- ------------------------------------------------------------------------ + FUNCTION VitalAND2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a AND b); + END; +-- + FUNCTION VitalOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a OR b); + END; +-- + FUNCTION VitalXOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a XOR b); + END; +-- + FUNCTION VitalNAND2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a NAND b); + END; +-- + FUNCTION VitalNOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a NOR b); + END; +-- + FUNCTION VitalXNOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a XOR b)); + END; +-- + -- ------------------------------------------------------------------------ + -- Commonly used 3-bit Logical gates. + -- ------------------------------------------------------------------------ + FUNCTION VitalAND3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a AND b AND c); + END; +-- + FUNCTION VitalOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a OR b OR c); + END; +-- + FUNCTION VitalXOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a XOR b XOR c); + END; +-- + FUNCTION VitalNAND3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a AND b AND c)); + END; +-- + FUNCTION VitalNOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a OR b OR c)); + END; +-- + FUNCTION VitalXNOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a XOR b XOR c)); + END; + + -- --------------------------------------------------------------------------- + -- Commonly used 4-bit Logical gates. + -- --------------------------------------------------------------------------- + FUNCTION VitalAND4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a AND b AND c AND d); + END; +-- + FUNCTION VitalOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a OR b OR c OR d); + END; +-- + FUNCTION VitalXOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(a XOR b XOR c XOR d); + END; +-- + FUNCTION VitalNAND4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a AND b AND c AND d)); + END; +-- + FUNCTION VitalNOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a OR b OR c OR d)); + END; +-- + FUNCTION VitalXNOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT (a XOR b XOR c XOR d)); + END; + + -- ------------------------------------------------------------------------ + -- Buffers + -- BUF ....... standard non-inverting buffer + -- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0') + -- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1') + -- ------------------------------------------------------------------------ + FUNCTION VitalBUF ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(To_UX01(Data)); + END; +-- + FUNCTION VitalBUFIF0 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(BufIf0_Table(Enable,Data)); + END; +-- + FUNCTION VitalBUFIF1 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(BufIf1_Table(Enable,Data)); + END; + FUNCTION VitalIDENT ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(To_UX01Z(Data)); + END; + + -- ------------------------------------------------------------------------ + -- Invertors + -- INV ......... standard inverting buffer + -- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0') + -- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1') + -- ------------------------------------------------------------------------ + FUNCTION VitalINV ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(NOT Data); + END; +-- + FUNCTION VitalINVIF0 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(InvIf0_Table(Enable,Data)); + END; +-- + FUNCTION VitalINVIF1 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic IS + BEGIN + RETURN ResultMap(InvIf1_Table(Enable,Data)); + END; + + -- ------------------------------------------------------------------------ + -- Multiplexor + -- MUX .......... result := data(dselect) + -- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'), + -- data1 when (dselect = '1'), + -- 'X' when (dselect = 'X') and (data0 /= data1) + -- MUX4 .......... 4-input mux; result := data(dselect) + -- MUX8 .......... 8-input mux; result := data(dselect) + -- ------------------------------------------------------------------------ + FUNCTION VitalMUX2 ( + CONSTANT Data1, Data0 : IN std_ulogic; + CONSTANT dSelect : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + CASE To_X01(dSelect) IS + WHEN '0' => Result := To_UX01(Data0); + WHEN '1' => Result := To_UX01(Data1); + WHEN OTHERS => Result := VitalSame( Data1, Data0 ); + END CASE; + RETURN ResultMap(Result); + END; +-- + FUNCTION VitalMUX4 ( + CONSTANT Data : IN std_logic_vector4; + CONSTANT dSelect : IN std_logic_vector2; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Slct : std_logic_vector2; + VARIABLE Result : UX01; + BEGIN + Slct := To_X01(dSelect); + CASE Slct IS + WHEN "00" => Result := To_UX01(Data(0)); + WHEN "01" => Result := To_UX01(Data(1)); + WHEN "10" => Result := To_UX01(Data(2)); + WHEN "11" => Result := To_UX01(Data(3)); + WHEN "0X" => Result := VitalSame( Data(1), Data(0) ); + WHEN "1X" => Result := VitalSame( Data(2), Data(3) ); + WHEN "X0" => Result := VitalSame( Data(2), Data(0) ); + WHEN "X1" => Result := VitalSame( Data(3), Data(1) ); + WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)), + VitalSame(Data(1),Data(0))); + END CASE; + RETURN ResultMap(Result); + END; +-- + FUNCTION VitalMUX8 ( + CONSTANT Data : IN std_logic_vector8; + CONSTANT dSelect : IN std_logic_vector3; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + VARIABLE Result : UX01; + BEGIN + CASE To_X01(dSelect(2)) IS + WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0), + dSelect(1 DOWNTO 0)); + WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4), + dSelect(1 DOWNTO 0)); + WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0), + dSelect(1 DOWNTO 0)), + VitalMUX4( Data(7 DOWNTO 4), + dSelect(1 DOWNTO 0))); + END CASE; + RETURN ResultMap(Result); + END; +-- + FUNCTION VInterMux ( + CONSTANT Data : IN std_logic_vector; + CONSTANT dSelect : IN std_logic_vector + ) RETURN std_ulogic IS + + CONSTANT sMsb : INTEGER := dSelect'LENGTH; + CONSTANT dMsbHigh : INTEGER := Data'LENGTH; + CONSTANT dMsbLow : INTEGER := Data'LENGTH/2; + ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data; + ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect; + + VARIABLE Result : UX01; + BEGIN + IF dSelect'LENGTH = 1 THEN + Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) ); + ELSIF dSelect'LENGTH = 2 THEN + Result := VitalMUX4( DataAlias, dSelAlias ); + ELSIF dSelect'LENGTH > 2 THEN + CASE To_X01(dSelect(sMsb)) IS + WHEN '0' => + Result := VInterMux( DataAlias(dMsbLow DOWNTO 1), + dSelAlias(sMsb-1 DOWNTO 1) ); + WHEN '1' => + Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1), + dSelAlias(sMsb-1 DOWNTO 1) ); + WHEN OTHERS => + Result := VitalSame( + VInterMux( DataAlias(dMsbLow DOWNTO 1), + dSelAlias(sMsb-1 DOWNTO 1) ), + VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1), + dSelAlias(sMsb-1 DOWNTO 1) ) + ); + END CASE; + ELSE + Result := 'X'; -- dselect'LENGTH < 1 + END IF; + RETURN Result; + END; +-- + FUNCTION VitalMUX ( + CONSTANT Data : IN std_logic_vector; + CONSTANT dSelect : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic IS + CONSTANT msb : INTEGER := 2**dSelect'LENGTH; + ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data; + ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect; + VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X'); + VARIABLE Result : UX01; + BEGIN + IF Data'LENGTH <= msb THEN + FOR i IN Data'LENGTH DOWNTO 1 LOOP + lDat(i) := DataAlias(i); + END LOOP; + ELSE + FOR i IN msb DOWNTO 1 LOOP + lDat(i) := DataAlias(i); + END LOOP; + END IF; + Result := VInterMux( lDat, dSelAlias ); + RETURN ResultMap(Result); + END; + + -- ------------------------------------------------------------------------ + -- Decoder + -- General Algorithm : + -- (a) Result(...) := '0' when (enable = '0') + -- (b) Result(data) := '1'; all other subelements = '0' + -- ... Result array is decending (n-1 downto 0) + -- + -- DECODERn .......... n:2**n decoder + -- ------------------------------------------------------------------------ + FUNCTION VitalDECODER2 ( + CONSTANT Data : IN std_ulogic; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector2 IS + VARIABLE Result : std_logic_vector2; + BEGIN + Result(1) := ResultMap(Enable AND ( Data)); + Result(0) := ResultMap(Enable AND (NOT Data)); + RETURN Result; + END; +-- + FUNCTION VitalDECODER4 ( + CONSTANT Data : IN std_logic_vector2; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector4 IS + VARIABLE Result : std_logic_vector4; + BEGIN + Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0))); + Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0))); + Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0))); + Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0))); + RETURN Result; + END; +-- + FUNCTION VitalDECODER8 ( + CONSTANT Data : IN std_logic_vector3; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector8 IS + VARIABLE Result : std_logic_vector8; + BEGIN + Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0)); + Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0)); + Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0)); + Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0)); + Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0)); + Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0)); + Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0)); + Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0)); + + Result(0) := ResultMap ( Enable AND Result(0) ); + Result(1) := ResultMap ( Enable AND Result(1) ); + Result(2) := ResultMap ( Enable AND Result(2) ); + Result(3) := ResultMap ( Enable AND Result(3) ); + Result(4) := ResultMap ( Enable AND Result(4) ); + Result(5) := ResultMap ( Enable AND Result(5) ); + Result(6) := ResultMap ( Enable AND Result(6) ); + Result(7) := ResultMap ( Enable AND Result(7) ); + + RETURN Result; + END; +-- + FUNCTION VitalDECODER ( + CONSTANT Data : IN std_logic_vector; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector IS + + CONSTANT DMsb : INTEGER := Data'LENGTH - 1; + ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data; + BEGIN + IF Data'LENGTH = 1 THEN + RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap ); + ELSIF Data'LENGTH = 2 THEN + RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap ); + ELSIF Data'LENGTH = 3 THEN + RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap ); + ELSIF Data'LENGTH > 3 THEN + RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0), + Enable AND ( DataAlias(DMsb)), ResultMap ) + & VitalDECODER (DataAlias(DMsb-1 DOWNTO 0), + Enable AND (NOT DataAlias(DMsb)), ResultMap ); + ELSE RETURN "X"; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- N-bit wide Logical gates. + -- ------------------------------------------------------------------------ + PROCEDURE VitalAND ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE Data_Schd : SchedArray(Data'RANGE); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalAND(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := '1'; + new_schd := Data_Schd(Data_Schd'LEFT); + FOR i IN Data'RANGE LOOP + NewValue := NewValue AND Data(i); + new_schd := new_schd AND Data_Schd(i); + END LOOP; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; --SN + END; +-- + PROCEDURE VitalOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE Data_Schd : SchedArray(Data'RANGE); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalOR(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := '0'; + new_schd := Data_Schd(Data_Schd'LEFT); + FOR i IN Data'RANGE LOOP + NewValue := NewValue OR Data(i); + new_schd := new_schd OR Data_Schd(i); + END LOOP; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; --SN + END; +-- + PROCEDURE VitalXOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH); + VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd; + ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalXOR(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q ); + InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalXOR ( Data ); + new_schd := VitalXOR ( DataB_Schd, DataI_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; --SN + END; +-- + PROCEDURE VitalNAND ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE Data_Schd : SchedArray(Data'RANGE); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalNAND(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + InvPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := '1'; + new_schd := Data_Schd(Data_Schd'LEFT); + FOR i IN Data'RANGE LOOP + NewValue := NewValue AND Data(i); + new_schd := new_schd AND Data_Schd(i); + END LOOP; + NewValue := NOT NewValue; + new_schd := NOT new_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE Data_Schd : SchedArray(Data'RANGE); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalNOR(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + InvPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := '0'; + new_schd := Data_Schd(Data_Schd'LEFT); + FOR i IN Data'RANGE LOOP + NewValue := NewValue OR Data(i); + new_schd := new_schd OR Data_Schd(i); + END LOOP; + NewValue := NOT NewValue; + new_schd := NOT new_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; --SN + END; +-- + PROCEDURE VitalXNOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH); + VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd; + ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN LOOP + q <= VitalXNOR(Data, ResultMap); + WAIT ON Data; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q ); + InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalXNOR ( Data ); + new_schd := VitalXNOR ( DataB_Schd, DataI_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data; + END LOOP; + END IF; --SN + END; +-- + + -- ------------------------------------------------------------------------ + -- Commonly used 2-bit Logical gates. + -- ------------------------------------------------------------------------ + PROCEDURE VitalAND2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalAND2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a AND b; + new_schd := a_schd AND b_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalOR2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a OR b; + new_schd := a_schd OR b_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNAND2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNAND2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a NAND b; + new_schd := a_schd NAND b_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNOR2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a NOR b; + new_schd := a_schd NOR b_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd : SchedType; + VARIABLE ai_schd, bi_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXOR2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a XOR b; + new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXNOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd : SchedType; + VARIABLE ai_schd, bi_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXNOR2 ( a, b, ResultMap ); + WAIT ON a, b; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := NOT (a XOR b); + new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Commonly used 3-bit Logical gates. + -- ------------------------------------------------------------------------ + PROCEDURE VitalAND3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN +-- + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalAND3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + BufPath ( c_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + BufPath ( c_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a AND b AND c; + new_schd := a_schd AND b_schd AND c_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalOR3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + BufPath ( c_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + BufPath ( c_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a OR b OR c; + new_schd := a_schd OR b_schd OR c_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNAND3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNAND3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + InvPath ( c_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + InvPath ( c_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := (a AND b) NAND c; + new_schd := (a_schd AND b_schd) NAND c_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNOR3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + InvPath ( c_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + InvPath ( c_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := (a OR b) NOR c; + new_schd := (a_schd OR b_schd) NOR c_schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd, cb_schd : SchedType; + VARIABLE ai_schd, bi_schd, ci_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXOR3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + BufPath ( cb_schd, InitialEdge(c), tpd_c_q ); + InvPath ( ci_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + BufPath ( cb_schd, GetEdge(c), tpd_c_q ); + InvPath ( ci_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a XOR b XOR c; + new_schd := VitalXOR3 ( ab_schd,ai_schd, + bb_schd,bi_schd, + cb_schd,ci_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXNOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd, cb_schd : SchedType; + VARIABLE ai_schd, bi_schd, ci_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXNOR3 ( a, b, c, ResultMap ); + WAIT ON a, b, c; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + BufPath ( cb_schd, InitialEdge(c), tpd_c_q ); + InvPath ( ci_schd, InitialEdge(c), tpd_c_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + BufPath ( cb_schd, GetEdge(c), tpd_c_q ); + InvPath ( ci_schd, GetEdge(c), tpd_c_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := NOT (a XOR b XOR c); + new_schd := VitalXNOR3 ( ab_schd, ai_schd, + bb_schd, bi_schd, + cb_schd, ci_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Commonly used 4-bit Logical gates. + -- ------------------------------------------------------------------------ + PROCEDURE VitalAND4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalAND4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + BufPath ( c_schd, InitialEdge(c), tpd_c_q ); + BufPath ( d_Schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + BufPath ( c_schd, GetEdge(c), tpd_c_q ); + BufPath ( d_Schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a AND b AND c AND d; + new_schd := a_schd AND b_schd AND c_schd AND d_Schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalOR4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( a_schd, InitialEdge(a), tpd_a_q ); + BufPath ( b_schd, InitialEdge(b), tpd_b_q ); + BufPath ( c_schd, InitialEdge(c), tpd_c_q ); + BufPath ( d_Schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( a_schd, GetEdge(a), tpd_a_q ); + BufPath ( b_schd, GetEdge(b), tpd_b_q ); + BufPath ( c_schd, GetEdge(c), tpd_c_q ); + BufPath ( d_Schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a OR b OR c OR d; + new_schd := a_schd OR b_schd OR c_schd OR d_Schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNAND4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNAND4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + InvPath ( c_schd, InitialEdge(c), tpd_c_q ); + InvPath ( d_Schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + InvPath ( c_schd, GetEdge(c), tpd_c_q ); + InvPath ( d_Schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := (a AND b) NAND (c AND d); + new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalNOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalNOR4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( a_schd, InitialEdge(a), tpd_a_q ); + InvPath ( b_schd, InitialEdge(b), tpd_b_q ); + InvPath ( c_schd, InitialEdge(c), tpd_c_q ); + InvPath ( d_Schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( a_schd, GetEdge(a), tpd_a_q ); + InvPath ( b_schd, GetEdge(b), tpd_b_q ); + InvPath ( c_schd, GetEdge(c), tpd_c_q ); + InvPath ( d_Schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := (a OR b) NOR (c OR d); + new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType; + VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXOR4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + + BufPath ( cb_schd, InitialEdge(c), tpd_c_q ); + InvPath ( ci_schd, InitialEdge(c), tpd_c_q ); + + BufPath ( DB_Schd, InitialEdge(d), tpd_d_q ); + InvPath ( di_schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + BufPath ( cb_schd, GetEdge(c), tpd_c_q ); + InvPath ( ci_schd, GetEdge(c), tpd_c_q ); + + BufPath ( DB_Schd, GetEdge(d), tpd_d_q ); + InvPath ( di_schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := a XOR b XOR c XOR d; + new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd, + cb_schd,ci_schd, DB_Schd,di_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalXNOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType; + VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType; + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_a_q = VitalZeroDelay01) + AND (tpd_b_q = VitalZeroDelay01) + AND (tpd_c_q = VitalZeroDelay01) + AND (tpd_d_q = VitalZeroDelay01)) THEN + LOOP + q <= VitalXNOR4 ( a, b, c, d, ResultMap ); + WAIT ON a, b, c, d; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( ab_schd, InitialEdge(a), tpd_a_q ); + InvPath ( ai_schd, InitialEdge(a), tpd_a_q ); + + BufPath ( bb_schd, InitialEdge(b), tpd_b_q ); + InvPath ( bi_schd, InitialEdge(b), tpd_b_q ); + + BufPath ( cb_schd, InitialEdge(c), tpd_c_q ); + InvPath ( ci_schd, InitialEdge(c), tpd_c_q ); + + BufPath ( DB_Schd, InitialEdge(d), tpd_d_q ); + InvPath ( di_schd, InitialEdge(d), tpd_d_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( ab_schd, GetEdge(a), tpd_a_q ); + InvPath ( ai_schd, GetEdge(a), tpd_a_q ); + + BufPath ( bb_schd, GetEdge(b), tpd_b_q ); + InvPath ( bi_schd, GetEdge(b), tpd_b_q ); + + BufPath ( cb_schd, GetEdge(c), tpd_c_q ); + InvPath ( ci_schd, GetEdge(c), tpd_c_q ); + + BufPath ( DB_Schd, GetEdge(d), tpd_d_q ); + InvPath ( di_schd, GetEdge(d), tpd_d_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := NOT (a XOR b XOR c XOR d); + new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd, + cb_schd,ci_schd, DB_Schd,di_schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON a, b, c, d; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Buffers + -- BUF ....... standard non-inverting buffer + -- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0') + -- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1') + -- ------------------------------------------------------------------------ + PROCEDURE VitalBUF ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_a_q = VitalZeroDelay01) THEN + LOOP + q <= ResultMap(To_UX01(a)); + WAIT ON a; + END LOOP; + + ELSE + LOOP + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := To_UX01(a); -- convert to forcing strengths + CASE EdgeType'(GetEdge(a)) IS + WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01); + WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10); + WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10)); + END CASE; + + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode ); + + WAIT ON a; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalBUFIF1 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) IS + VARIABLE NewValue : UX01Z; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_data_q = VitalZeroDelay01 ) + AND (tpd_enable_q = VitalZeroDelay01Z)) THEN + LOOP + q <= VitalBUFIF1( Data, Enable, ResultMap ); + WAIT ON Data, Enable; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( d_Schd, InitialEdge(Data), tpd_data_q ); + BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( d_Schd, GetEdge(Data), tpd_data_q ); + BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalBUFIF1( Data, Enable ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), + d_Schd, e1_Schd, e0_Schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalBUFIF0 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) IS + VARIABLE NewValue : UX01Z; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType; + VARIABLE ne1_schd, ne0_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_data_q = VitalZeroDelay01 ) + AND (tpd_enable_q = VitalZeroDelay01Z)) THEN + LOOP + q <= VitalBUFIF0( Data, Enable, ResultMap ); + WAIT ON Data, Enable; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( d_Schd, InitialEdge(Data), tpd_data_q ); + InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( d_Schd, GetEdge(Data), tpd_data_q ); + InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalBUFIF0( Data, Enable ); + ne1_schd := NOT e1_Schd; + ne0_schd := NOT e0_Schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), + d_Schd, ne1_schd, ne0_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; + + PROCEDURE VitalIDENT ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) IS + SUBTYPE v2 IS std_logic_vector(0 TO 1); + VARIABLE NewValue : UX01Z; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_a_q = VitalZeroDelay01Z) THEN + LOOP + q <= ResultMap(To_UX01Z(a)); + WAIT ON a; + END LOOP; + + ELSE + LOOP + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS + WHEN "00" => Dly := tpd_a_q(tr10); + WHEN "01" => Dly := tpd_a_q(tr01); + WHEN "0Z" => Dly := tpd_a_q(tr0z); + WHEN "0X" => Dly := tpd_a_q(tr01); + WHEN "10" => Dly := tpd_a_q(tr10); + WHEN "11" => Dly := tpd_a_q(tr01); + WHEN "1Z" => Dly := tpd_a_q(tr1z); + WHEN "1X" => Dly := tpd_a_q(tr10); + WHEN "Z0" => Dly := tpd_a_q(trz0); + WHEN "Z1" => Dly := tpd_a_q(trz1); + WHEN "ZZ" => Dly := 0 ns; + WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0)); + WHEN "X0" => Dly := tpd_a_q(tr10); + WHEN "X1" => Dly := tpd_a_q(tr01); + WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z)); + WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10)); + END CASE; + NewValue := To_UX01Z(a); + + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode ); + + WAIT ON a; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Invertors + -- INV ......... standard inverting buffer + -- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0') + -- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1') + -- ------------------------------------------------------------------------ + PROCEDURE VitalINV ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic ; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + IF (tpd_a_q = VitalZeroDelay01) THEN + LOOP + q <= ResultMap(NOT a); + WAIT ON a; + END LOOP; + + ELSE + LOOP + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := NOT a; + CASE EdgeType'(GetEdge(a)) IS + WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10); + WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01); + WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10)); + END CASE; + + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode ); + + WAIT ON a; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalINVIF1 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) IS + VARIABLE NewValue : UX01Z; + VARIABLE new_schd : SchedType; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_data_q = VitalZeroDelay01 ) + AND (tpd_enable_q = VitalZeroDelay01Z)) THEN + LOOP + q <= VitalINVIF1( Data, Enable, ResultMap ); + WAIT ON Data, Enable; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( d_Schd, InitialEdge(Data), tpd_data_q ); + BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( d_Schd, GetEdge(Data), tpd_data_q ); + BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalINVIF1( Data, Enable ); + new_schd := NOT d_Schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), + new_schd, e1_Schd, e0_Schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalINVIF0 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) IS + VARIABLE NewValue : UX01Z; + VARIABLE new_schd : SchedType; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType; + VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType; + VARIABLE Dly, Glch : TIME; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_data_q = VitalZeroDelay01 ) + AND (tpd_enable_q = VitalZeroDelay01Z)) THEN + LOOP + q <= VitalINVIF0( Data, Enable, ResultMap ); + WAIT ON Data, Enable; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + InvPath ( d_Schd, InitialEdge(Data), tpd_data_q ); + InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + InvPath ( d_Schd, GetEdge(Data), tpd_data_q ); + InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delay + -- ------------------------------------ + NewValue := VitalINVIF0( Data, Enable ); + ne1_schd := NOT e1_Schd; + ne0_schd := NOT e0_Schd; + new_schd := NOT d_Schd; + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), + new_schd, ne1_schd, ne0_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + -- Multiplexor + -- MUX .......... result := data(dselect) + -- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'), + -- data1 when (dselect = '1'), + -- 'X' when (dselect = 'X') and (data0 /= data1) + -- MUX4 .......... 4-input mux; result := data(dselect) + -- MUX8 .......... 8-input mux; result := data(dselect) + -- ------------------------------------------------------------------------ + PROCEDURE VitalMUX2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL d1, d0 : IN std_ulogic; + SIGNAL dSel : IN std_ulogic; + CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + VARIABLE d1_Schd, d0_Schd : SchedType; + VARIABLE dSel_bSchd, dSel_iSchd : SchedType; + VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType; + BEGIN + + -- ------------------------------------------------------------------------ + -- For ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF ( (tpd_d1_q = VitalZeroDelay01) + AND (tpd_d0_q = VitalZeroDelay01) + AND (tpd_dsel_q = VitalZeroDelay01) ) THEN + LOOP + q <= VitalMUX2 ( d1, d0, dSel, ResultMap ); + WAIT ON d1, d0, dSel; + END LOOP; + + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q ); + BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q ); + BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q ); + InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q ); + BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q ); + BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q ); + InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalMUX2 ( d1, d0, dSel ); + new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON d1, d0, dSel; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalMUX4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector4; + SIGNAL dSel : IN std_logic_vector2; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + VARIABLE Data_Schd : SchedArray4; + VARIABLE Data_Edge : EdgeArray4; + VARIABLE dSel_Edge : EdgeArray2; + VARIABLE dSel_bSchd : SchedArray2; + VARIABLE dSel_iSchd : SchedArray2; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN dSel'RANGE LOOP + IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + + IF (AllZeroDelay) THEN LOOP + q <= VitalMUX(Data, dSel, ResultMap); + WAIT ON Data, dSel; + END LOOP; + END IF; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + FOR n IN dSel'RANGE LOOP + BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + GetEdge ( dSel, LastdSel, dSel_Edge ); + BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q ); + InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalMUX4 ( Data, dSel ); + new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, dSel; + END LOOP; + END IF; --SN + END; + + PROCEDURE VitalMUX8 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector8; + SIGNAL dSel : IN std_logic_vector3; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + VARIABLE Data_Schd : SchedArray8; + VARIABLE Data_Edge : EdgeArray8; + VARIABLE dSel_Edge : EdgeArray3; + VARIABLE dSel_bSchd : SchedArray3; + VARIABLE dSel_iSchd : SchedArray3; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN dSel'RANGE LOOP + IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + + IF (AllZeroDelay) THEN LOOP + q <= VitalMUX(Data, dSel, ResultMap); + WAIT ON Data, dSel; + END LOOP; + END IF; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + FOR n IN dSel'RANGE LOOP + BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + GetEdge ( dSel, LastdSel, dSel_Edge ); + BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q ); + InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalMUX8 ( Data, dSel ); + new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, dSel; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalMUX ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + SIGNAL dSel : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : UX01; + VARIABLE Glitch_Data : GlitchDataType; + VARIABLE new_schd : SchedType; + VARIABLE Dly, Glch : TIME; + VARIABLE Data_Schd : SchedArray(Data'RANGE); + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE dSel_Edge : EdgeArray(dSel'RANGE); + VARIABLE dSel_bSchd : SchedArray(dSel'RANGE); + VARIABLE dSel_iSchd : SchedArray(dSel'RANGE); + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + FOR i IN dSel'RANGE LOOP + IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + IF (AllZeroDelay) THEN + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + + IF (AllZeroDelay) THEN LOOP + q <= VitalMUX(Data, dSel, ResultMap); + WAIT ON Data, dSel; + END LOOP; + END IF; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + FOR n IN dSel'RANGE LOOP + BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) ); + END LOOP; + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_Schd, Data_Edge, Atpd_data_q ); + + GetEdge ( dSel, LastdSel, dSel_Edge ); + BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q ); + InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalMUX ( Data, dSel ); + new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, dSel; + END LOOP; + END IF; --SN + END; + + -- ------------------------------------------------------------------------ + -- Decoder + -- General Algorithm : + -- (a) Result(...) := '0' when (enable = '0') + -- (b) Result(data) := '1'; all other subelements = '0' + -- ... Result array is decending (n-1 downto 0) + -- + -- DECODERn .......... n:2**n decoder + -- Caution: If 'ResultMap' defines other than strength mapping, the + -- delay selection is not defined. + -- ------------------------------------------------------------------------ + PROCEDURE VitalDECODER2 ( + SIGNAL q : OUT std_logic_vector2; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE NewValue : std_logic_vector2; + VARIABLE Glitch_Data : GlitchArray2; + VARIABLE new_schd : SchedArray2; + VARIABLE Dly, Glch : TimeArray2; + VARIABLE Enable_Schd : SchedType := DefSchedType; + VARIABLE Data_BSchd, Data_ISchd : SchedType; + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN + LOOP + q <= VitalDECODER2(Data, Enable, ResultMap); + WAIT ON Data, Enable; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q ); + InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q ); + BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q ); + InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q ); + + BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalDECODER2 ( Data, Enable, ResultMap ); + new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; -- SN + END; +-- + PROCEDURE VitalDECODER4 ( + SIGNAL q : OUT std_logic_vector4; + SIGNAL Data : IN std_logic_vector2; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : std_logic_vector4; + VARIABLE Glitch_Data : GlitchArray4; + VARIABLE new_schd : SchedArray4; + VARIABLE Dly, Glch : TimeArray4; + VARIABLE Enable_Schd : SchedType; + VARIABLE Enable_Edge : EdgeType; + VARIABLE Data_Edge : EdgeArray2; + VARIABLE Data_BSchd, Data_ISchd : SchedArray2; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_enable_q /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + ELSE + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + END IF; + IF (AllZeroDelay) THEN LOOP + q <= VitalDECODER4(Data, Enable, ResultMap); + WAIT ON Data, Enable; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_BSchd, Data_Edge, Atpd_data_q ); + InvPath ( Data_ISchd, Data_Edge, Atpd_data_q ); + + BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalDECODER4 ( Data, Enable, ResultMap ); + new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; +-- + PROCEDURE VitalDECODER8 ( + SIGNAL q : OUT std_logic_vector8; + SIGNAL Data : IN std_logic_vector3; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : std_logic_vector8; + VARIABLE Glitch_Data : GlitchArray8; + VARIABLE new_schd : SchedArray8; + VARIABLE Dly, Glch : TimeArray8; + VARIABLE Enable_Schd : SchedType; + VARIABLE Enable_Edge : EdgeType; + VARIABLE Data_Edge : EdgeArray3; + VARIABLE Data_BSchd, Data_ISchd : SchedArray3; + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_enable_q /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + ELSE + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + END IF; + IF (AllZeroDelay) THEN LOOP + q <= VitalDECODER(Data, Enable, ResultMap); + WAIT ON Data, Enable; + END LOOP; + ELSE + + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_BSchd, Data_Edge, Atpd_data_q ); + InvPath ( Data_ISchd, Data_Edge, Atpd_data_q ); + + BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalDECODER8 ( Data, Enable, ResultMap ); + new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; --SN + END; +-- + PROCEDURE VitalDECODER ( + SIGNAL q : OUT std_logic_vector; + SIGNAL Data : IN std_logic_vector; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) IS + VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U'); + VARIABLE NewValue : std_logic_vector(q'RANGE); + VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE); + VARIABLE new_schd : SchedArray(q'RANGE); + VARIABLE Dly, Glch : VitalTimeArray(q'RANGE); + VARIABLE Enable_Schd : SchedType; + VARIABLE Enable_Edge : EdgeType; + VARIABLE Data_Edge : EdgeArray(Data'RANGE); + VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE); + ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q; + VARIABLE AllZeroDelay : BOOLEAN := TRUE; + BEGIN + -- ------------------------------------------------------------------------ + -- Check if ALL zero delay paths, use simple model + -- ( No delay selection, glitch detection required ) + -- ------------------------------------------------------------------------ + IF (tpd_enable_q /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + ELSE + FOR i IN Data'RANGE LOOP + IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN + AllZeroDelay := FALSE; + EXIT; + END IF; + END LOOP; + END IF; + IF (AllZeroDelay) THEN LOOP + q <= VitalDECODER(Data, Enable, ResultMap); + WAIT ON Data, Enable; + END LOOP; + ELSE + -- -------------------------------------- + -- Initialize delay schedules + -- -------------------------------------- + FOR n IN Data'RANGE LOOP + BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) ); + END LOOP; + BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q ); + + LOOP + -- -------------------------------------- + -- Process input signals + -- get edge values + -- re-evaluate output schedules + -- -------------------------------------- + GetEdge ( Data, LastData, Data_Edge ); + BufPath ( Data_BSchd, Data_Edge, Atpd_data_q ); + InvPath ( Data_ISchd, Data_Edge, Atpd_data_q ); + + BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q ); + + -- ------------------------------------ + -- Compute function and propation delaq + -- ------------------------------------ + NewValue := VitalDECODER ( Data, Enable, ResultMap ); + new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd ); + + -- ------------------------------------------------------ + -- Assign Outputs + -- get delays to new value and possable glitch + -- schedule output change with On Event glitch detection + -- ------------------------------------------------------ + GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd ); + VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly, + PrimGlitchMode, GlitchDelay=>Glch ); + + WAIT ON Data, Enable; + END LOOP; + END IF; + END; + + -- ------------------------------------------------------------------------ + FUNCTION VitalTruthTable ( + CONSTANT TruthTable : IN VitalTruthTableType; + CONSTANT DataIn : IN std_logic_vector + ) RETURN std_logic_vector IS + + CONSTANT InputSize : INTEGER := DataIn'LENGTH; + CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize; + VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0) + := (OTHERS => 'X'); + VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1) + := To_X01(DataIn); + VARIABLE Index : INTEGER; + VARIABLE Err : BOOLEAN := FALSE; + + -- This needs to be done since the TableLookup arrays must be + -- ascending starting with 0 + VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1), + 0 TO (TruthTable'LENGTH(2)-1)) + := TruthTable; + + BEGIN + -- search through each row of the truth table + IF OutSize > 0 THEN + ColLoop: + FOR i IN TableAlias'RANGE(1) LOOP + + RowLoop: -- Check each input element of the entry + FOR j IN 0 TO InputSize LOOP + + IF (j = InputSize) THEN -- This entry matches + -- Return the Result + Index := 0; + FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP + TruthOutputX01Z ( TableAlias(i,k), + ReturnValue(Index), Err); + EXIT WHEN Err; + Index := Index + 1; + END LOOP; + + IF Err THEN + ReturnValue := (OTHERS => 'X'); + END IF; + RETURN ReturnValue; + END IF; + IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN + VitalError ( "VitalTruthTable", ErrInpSym, + To_TruthChar(TableAlias(i,j)) ); + EXIT ColLoop; + END IF; + EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j), + TableAlias(i, j))); + END LOOP RowLoop; + END LOOP ColLoop; + + ELSE + VitalError ( "VitalTruthTable", ErrTabWidSml ); + END IF; + RETURN ReturnValue; + END VitalTruthTable; + + FUNCTION VitalTruthTable ( + CONSTANT TruthTable : IN VitalTruthTableType; + CONSTANT DataIn : IN std_logic_vector + ) RETURN std_logic IS + + CONSTANT InputSize : INTEGER := DataIn'LENGTH; + CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize; + VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0) + := (OTHERS => 'X'); + BEGIN + IF (OutSize > 0) THEN + TempResult := VitalTruthTable(TruthTable, DataIn); + IF ( 1 > OutSize) THEN + VitalError ( "VitalTruthTable", ErrTabResSml ); + ELSIF ( 1 < OutSize) THEN + VitalError ( "VitalTruthTable", ErrTabResLrg ); + END IF; + RETURN (TempResult(0)); + ELSE + VitalError ( "VitalTruthTable", ErrTabWidSml ); + RETURN 'X'; + END IF; + END VitalTruthTable; + + PROCEDURE VitalTruthTable ( + SIGNAL Result : OUT std_logic_vector; + CONSTANT TruthTable : IN VitalTruthTableType; + SIGNAL DataIn : IN std_logic_vector -- IR#236 + ) IS + CONSTANT ResLeng : INTEGER := Result'LENGTH; + CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH; + CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng); + VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0) + := (OTHERS => 'X'); + + BEGIN + TempResult := VitalTruthTable(TruthTable, DataIn); + + IF (ResLeng > ActResLen) THEN + VitalError ( "VitalTruthTable", ErrTabResSml ); + ELSIF (ResLeng < ActResLen) THEN + VitalError ( "VitalTruthTable", ErrTabResLrg ); + END IF; + TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0); + Result <= TempResult; + + END VitalTruthTable; + + PROCEDURE VitalTruthTable ( + SIGNAL Result : OUT std_logic; + CONSTANT TruthTable : IN VitalTruthTableType; + SIGNAL DataIn : IN std_logic_vector -- IR#236 + ) IS + + CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH; + VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0) + := (OTHERS => 'X'); + + BEGIN + TempResult := VitalTruthTable(TruthTable, DataIn); + + IF ( 1 > ActResLen) THEN + VitalError ( "VitalTruthTable", ErrTabResSml ); + ELSIF ( 1 < ActResLen) THEN + VitalError ( "VitalTruthTable", ErrTabResLrg ); + END IF; + IF (ActResLen > 0) THEN + Result <= TempResult(0); + END IF; + + END VitalTruthTable; + + -- ------------------------------------------------------------------------ + PROCEDURE VitalStateTable ( + VARIABLE Result : INOUT std_logic_vector; + VARIABLE PreviousDataIn : INOUT std_logic_vector; + CONSTANT StateTable : IN VitalStateTableType; + CONSTANT DataIn : IN std_logic_vector; + CONSTANT NumStates : IN NATURAL + ) IS + + CONSTANT InputSize : INTEGER := DataIn'LENGTH; + CONSTANT OutSize : INTEGER + := StateTable'LENGTH(2) - InputSize - NumStates; + CONSTANT ResLeng : INTEGER := Result'LENGTH; + VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1) + := To_X01(DataIn); + VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1) + := To_X01(PreviousDataIn); + VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1) + := To_X01(Result); + VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1); + + BEGIN + IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN + VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn 'X'); + Result := ResultAlias; + + ELSIF (OutSize <= 0) THEN + VitalError ( "VitalStateTable", ErrTabWidSml ); + + ResultAlias := (OTHERS => 'X'); + Result := ResultAlias; + + ELSE + IF (ResLeng > OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResSml ); + ELSIF (ResLeng < OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResLrg ); + END IF; + + ExpResult := StateTableLookUp ( StateTable, DataInAlias, + PrevDataAlias, NumStates, + ResultAlias); + ResultAlias := (OTHERS => 'X'); + ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1) + := ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1); + + Result := ResultAlias; + PrevDataAlias(0 TO InputSize - 1) := DataInAlias; + PreviousDataIn := PrevDataAlias; + + END IF; + END VitalStateTable; + + + PROCEDURE VitalStateTable ( + VARIABLE Result : INOUT std_logic; -- states + VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states + CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data + CONSTANT DataIn : IN std_logic_vector -- Inputs + ) IS + + VARIABLE ResultAlias : std_logic_vector(0 TO 0); + BEGIN + ResultAlias(0) := Result; + VitalStateTable ( StateTable => StateTable, + DataIn => DataIn, + NumStates => 1, + Result => ResultAlias, + PreviousDataIn => PreviousDataIn + ); + Result := ResultAlias(0); + + END VitalStateTable; + + PROCEDURE VitalStateTable ( + SIGNAL Result : INOUT std_logic_vector; + CONSTANT StateTable : IN VitalStateTableType; + SIGNAL DataIn : IN std_logic_vector; + CONSTANT NumStates : IN NATURAL + ) IS + + CONSTANT InputSize : INTEGER := DataIn'LENGTH; + CONSTANT OutSize : INTEGER + := StateTable'LENGTH(2) - InputSize - NumStates; + CONSTANT ResLeng : INTEGER := Result'LENGTH; + + VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1) + := (OTHERS => 'X'); + VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1); + VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1); + VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1); + + BEGIN + IF (OutSize <= 0) THEN + VitalError ( "VitalStateTable", ErrTabWidSml ); + + ResultAlias := (OTHERS => 'X'); + Result <= ResultAlias; + + ELSE + IF (ResLeng > OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResSml ); + ELSIF (ResLeng < OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResLrg ); + END IF; + + LOOP + DataInAlias := To_X01(DataIn); + ResultAlias := To_X01(Result); + ExpResult := StateTableLookUp ( StateTable, DataInAlias, + PrevData, NumStates, + ResultAlias); + ResultAlias := (OTHERS => 'X'); + ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1) + := ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1); + + Result <= ResultAlias; + PrevData := DataInAlias; + + WAIT ON DataIn; + END LOOP; + + END IF; + + END VitalStateTable; + + PROCEDURE VitalStateTable ( + SIGNAL Result : INOUT std_logic; + CONSTANT StateTable : IN VitalStateTableType; + SIGNAL DataIn : IN std_logic_vector + ) IS + + CONSTANT InputSize : INTEGER := DataIn'LENGTH; + CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1; + + VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1) + := (OTHERS => 'X'); + VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1); + VARIABLE ResultAlias : std_logic_vector(0 TO 0); + VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1); + + BEGIN + IF (OutSize <= 0) THEN + VitalError ( "VitalStateTable", ErrTabWidSml ); + + Result <= 'X'; + + ELSE + IF ( 1 > OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResSml ); + ELSIF ( 1 < OutSize) THEN + VitalError ( "VitalStateTable", ErrTabResLrg ); + END IF; + + LOOP + ResultAlias(0) := To_X01(Result); + DataInAlias := To_X01(DataIn); + ExpResult := StateTableLookUp ( StateTable, DataInAlias, + PrevData, 1, ResultAlias); + + Result <= ExpResult(OutSize-1); + PrevData := DataInAlias; + + WAIT ON DataIn; + END LOOP; + END IF; + + END VitalStateTable; + + -- ------------------------------------------------------------------------ + -- std_logic resolution primitive + -- ------------------------------------------------------------------------ + PROCEDURE VitalResolve ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector --IR236 4/2/98 + ) IS + VARIABLE uData : std_ulogic_vector(Data'RANGE); + BEGIN + FOR i IN Data'RANGE LOOP + uData(i) := Data(i); + END LOOP; + q <= resolved(uData); + END; + +END VITAL_Primitives; + diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_p.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_p.vhdl new file mode 100644 index 0000000..857899e --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/prmtvs_p.vhdl @@ -0,0 +1,1413 @@ +-- ----------------------------------------------------------------------------- +-- Title : Standard VITAL_Primitives Package +-- : $Revision$ +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : +-- Purpose : This packages defines standard types, constants, functions +-- : and procedures for use in developing ASIC models. +-- : Specifically a set of logic primitives are defined. +-- : +-- Known Errors : +-- : +-- Note : No declarations or definitions shall be included in, +-- : or excluded from this package. The "package declaration" +-- : defines the objects (types, subtypes, constants, functions, +-- : procedures ... etc.) that can be used by a user. The package +-- : body shall be considered the formal definition of the +-- : semantics of this package. Tool developers may choose to +-- : implement the package body in the most efficient manner +-- : available to them. +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Acknowledgments: +-- This code was originally developed under the "VHDL Initiative Toward ASIC +-- Libraries" (VITAL), an industry sponsored initiative. Technical +-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator: +-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design +-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek, +-- Texas Instruments; Victor Martin, Hewlett-Packard Company. +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No:|Auth:| Mod.Date:| Changes Made: +-- v95.0 A | | 06/02/95 | Initial ballot draft 1995 +-- ---------------------------------------------------------------------------- +-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of +-- | | | of class SIGNAL (PROPOSED) +-- ---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.Std_Logic_1164.ALL; +USE IEEE.VITAL_Timing.ALL; + +PACKAGE VITAL_Primitives IS + -- ------------------------------------------------------------------------ + -- Type and Subtype Declarations + -- ------------------------------------------------------------------------ + + -- For Truth and State Tables + SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z'; + SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S'; + + TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> ) + OF VitalTruthSymbolType; + TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> ) + OF VitalStateSymbolType; + + -- --------------------------------- + -- Default values used by primitives + -- --------------------------------- + CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays + CONSTANT VitalDefDelay01Z : VitalDelayType01Z; + + -- ------------------------------------------------------------------------ + -- VITAL Primitives + -- + -- The primitives packages contains a collections of common gates, + -- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER + -- functions. In addition, for sequential devices, a STATE TABLE construct + -- is provided. For complex functions a modeler may wish to use either + -- a collection of connected VITAL primitives, or a TRUTH TABLE construct. + -- + -- For each primitive a Function and Procedure is provided. The primitive + -- functions are provided to support behavioral modeling styles. The + -- primitive procedures are provided to support structural modeling styles. + -- + -- The procedures wait internally for an event on an input signal, compute + -- the new result, perform glitch handling, schedule transaction on the + -- output signals, and wait for future input events. All of the functional + -- (logic) input or output parameters of the primitive procedures are + -- signals. All the other parameters are constants. + -- + -- The procedure primitives are parameterized for separate path delays + -- from each input signal. All path delays default to 0 ns. + -- + -- The sequential primitive functions compute the defined function and + -- return a value of type std_ulogic or std_logic_vector. All parameters + -- of the primitive functions are constants of mode IN. + -- + -- The primitives are based on 1164 operators. The user may also elect to + -- express functions using the 1164 operators as well. These styles are + -- all equally acceptable methods for device modeling. + -- + -- ------------------------------------------------------------------------ + -- + -- Sequential + -- Primitive + -- Function Name: N-input logic device function calls: + -- VitalAND VitalOR VitalXOR + -- VitalNAND VitalNOR VitalXNOR + -- + -- Description: The function calls return the evaluated logic function + -- corresponding to the function name. + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_logic_vector The input signals for the n-bit + -- wide logic functions. + -- ResultMap VitalResultMapType The output signal strength + -- result map to modify default + -- result mapping. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_ulogic The evaluated logic function of + -- the n-bit wide primitives. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalAND ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNAND ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXNOR ( + CONSTANT Data : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap + ) RETURN std_ulogic; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: N-input logic device concurrent procedure calls. + -- VitalAND VitalOR VitalXOR + -- VitalNAND VitalNOR VitalXNOR + -- + -- Description: The procedure calls return the evaluated logic function + -- corresponding to the function name as a parameter to the + -- procedure. Propagation delay form data to q is a + -- a parameter to the procedure. A vector of delay values + -- for inputs to output are provided. It is noted that + -- limitations in SDF make the back annotation of the delay + -- array difficult. + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_logic_vector The input signals for the n- + -- bit wide logic functions. + -- tpd_data_q VitalDelayArrayType01 The propagation delay from + -- the data inputs to the output + -- q. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic The output signal of the + -- evaluated logic function. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalAND ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNAND ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXNOR ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + -- ------------------------------------------------------------------------- + -- + -- Sequential + -- Primitive + -- Function Name: 2,3 and 4 input logic device function calls. + -- + -- VitalAND2 VitalOR2 VitalXOR2 + -- VitalAND3 VitalOR3 VitalXOR3 + -- VitalAND4 VitalOR4 VitalXOR4 + -- + -- VitalNAND2 VitalNOR2 VitalXNOR2 + -- VitalNAND3 VitalNOR3 VitalXNOR3 + -- VitalNAND4 VitalNOR4 VitalXNOR4 + -- + -- Description: The function calls return the evaluated 2, 3 or 4 input + -- logic function corresponding to the function name. + -- + -- Arguments: + -- + -- IN Type Description + -- a, b, c, d std_ulogic 2 input devices have a and b as + -- inputs. 3 input devices have a, b + -- and c as inputs. 4 input devices + -- have a, b, c and d as inputs. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_ulogic The result of the evaluated logic + -- function. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalAND2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNAND2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXNOR2 ( + CONSTANT a, b : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalAND3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNAND3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXNOR3 ( + CONSTANT a, b, c : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalAND4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNAND4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalNOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalXNOR4 ( + CONSTANT a, b, c, d : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: 2, 3 and 4 input logic device concurrent procedure + -- calls. + -- + -- VitalAND2 VitalOR2 VitalXOR2 + -- VitalAND3 VitalOR3 VitalXOR3 + -- VitalAND4 VitalOR4 VitalXOR4 + -- + -- VitalNAND2 VitalNOR2 VitalXNOR2 + -- VitalNAND3 VitalNOR3 VitalXNOR3 + -- VitalNAND4 VitalNOR4 VitalXNOR4 + -- + -- Description: The procedure calls return the evaluated logic function + -- corresponding to the function name as a parameter to the + -- procedure. Propagation delays from a and b to q are + -- a parameter to the procedure. The default propagation + -- delay is 0 ns. + -- + -- Arguments: + -- + -- IN Type Description + -- a, b, c, d std_ulogic 2 input devices have a and b as + -- inputs. 3 input devices have a, b + -- and c as inputs. 4 input devices + -- have a, b, c and d as inputs. + -- tpd_a_q VitalDelayType01 The propagation delay from the a + -- input to output q for 2, 3 and 4 + -- input devices. + -- tpd_b_q VitalDelayType01 The propagation delay from the b + -- input to output q for 2, 3 and 4 + -- input devices. + -- tpd_c_q VitalDelayType01 The propagation delay from the c + -- input to output q for 3 and 4 input + -- devices. + -- tpd_d_q VitalDelayType01 The propagation delay from the d + -- input to output q for 4 input + -- devices. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic The output signal of the evaluated + -- logic function. + -- + -- Returns + -- none + -- ------------------------------------------------------------------------- + PROCEDURE VitalAND2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNAND2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXNOR2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalAND3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNAND3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXNOR3 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalAND4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNAND4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalNOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalXNOR4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL a, b, c, d : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + -- ------------------------------------------------------------------------ + -- + -- Sequential + -- Primitive + -- Function Name: Buffer logic device concurrent procedure calls. + -- + -- Description: Four buffer sequential primitive function calls are + -- provided. One is a simple buffer and the others + -- offer high and low enables and the four permits + -- propagation of Z as shown below: + -- + -- VitalBUF Standard non-inverting buffer + -- VitalBUFIF0 Non-inverting buffer with Enable low + -- VitalBUFIF1 Non-inverting buffer with Enable high + -- VitalIDENT Pass buffer capable of propagating Z + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_ulogic Input to the buffers + -- Enable std_ulogic Enable for the enable high and low + -- buffers. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping for + -- simple buffer. + -- VitalResultZMapType The output signal strength result map + -- to modify default result mapping + -- which has high impedance capability + -- for the enable high, enable low and + -- identity buffers. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_ulogic The output signal of the evaluated + -- buffer function. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalBUF ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + FUNCTION VitalBUFIF0 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic; + FUNCTION VitalBUFIF1 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic; + FUNCTION VitalIDENT ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: Buffer device procedure calls. + -- + -- Description: Four buffer concurrent primitive procedure calls are + -- provided. One is a simple buffer and the others + -- offer high and low enables and the fourth permits + -- propagation of Z as shown below: + -- + -- VitalBUF Standard non-inverting buffer + -- VitalBUFIF0 Non-inverting buffer with Enable low + -- VitalBUFIF1 Non-inverting buffer with Enable high + -- VitalIDENT Pass buffer capable of propagating Z + -- + -- Arguments: + -- + -- IN Type Description + -- a std_ulogic Input signal to the buffers + -- Enable std_ulogic Enable signal for the enable high and + -- low buffers. + -- tpd_a_q VitalDelayType01 Propagation delay from input to + -- output for the simple buffer. + -- VitalDelayType01Z Propagation delay from input to + -- to output for the enable high and low + -- and identity buffers. + -- tpd_enable_q VitalDelayType01Z Propagation delay from enable to + -- output for the enable high and low + -- buffers. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping for + -- simple buffer. + -- VitalResultZMapType The output signal strength result map + -- to modify default result mapping + -- which has high impedance capability + -- for the enable high, enable low and + -- identity buffers. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic Output of the buffers. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalBUF ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalBUFIF0 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap); + + + PROCEDURE VitalBUFIF1 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap); + + PROCEDURE VitalIDENT ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap ); + + -- ------------------------------------------------------------------------ + -- + -- Sequential + -- Primitive + -- Function Name: VitalINV, VitalINVIF0, VitalINVIF1 + -- + -- Description: Inverter functions which return the inverted signal + -- value. Inverters with enable low and high are provided + -- which can drive high impedance when inactive. + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_ulogic Input to the inverter + -- Enable std_ulogic Enable to the enable high and low + -- inverters. + -- ResultMap VitalResultMap The output signal strength result map + -- to modify default result mapping for + -- simple inverter. + -- VitalResultZMapType The output signal strength result map + -- to modify default result mapping + -- which has high impedance capability + -- for the enable high, enable low + -- inverters. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_ulogic Output of the inverter + -- + -- ------------------------------------------------------------------------- + + FUNCTION VitalINV ( + CONSTANT Data : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalINVIF0 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic; + + FUNCTION VitalINVIF1 ( + CONSTANT Data, Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap + ) RETURN std_ulogic; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1 + -- + -- Description: The concurrent primitive procedure calls implement a + -- signal inversion function. The output is a parameter to + -- the procedure. The path delay information is passed as + -- a parameter to the call. + -- + -- Arguments: + -- + -- IN Type Description + -- a std_ulogic Input signal for the simple inverter + -- Data std_ulogic Input signal for the enable high and + -- low inverters. + -- Enable std_ulogic Enable signal for the enable high and + -- low inverters. + -- tpd_a_q VitalDelayType01 Propagation delay from input a to + -- output q for the simple inverter. + -- tpd_data_q VitalDelayType01 Propagation delay from input data to + -- output q for the enable high and low + -- inverters. + -- tpd_enable_q VitalDelayType01Z Propagation delay from input enable + -- to output q for the enable high and + -- low inverters. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping for + -- simple inverter. + -- VitalResultZMapType The output signal strength result map + -- to modify default result mapping + -- which has high impedance capability + -- for the enable high, enable low + -- inverters. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic Output signal of the inverter. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalINV ( + SIGNAL q : OUT std_ulogic; + SIGNAL a : IN std_ulogic; + CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + PROCEDURE VitalINVIF0 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap); + + PROCEDURE VitalINVIF1 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z; + CONSTANT ResultMap : IN VitalResultZMapType + := VitalDefaultResultZMap); + + -- ------------------------------------------------------------------------ + -- + -- Sequential + -- Primitive + -- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8 + -- + -- Description: The VitalMUX functions return the selected data bit + -- based on the value of dSelect. For MUX2, the function + -- returns data0 when dselect is 0 and returns data1 when + -- dselect is 1. When dselect is X, result is X for MUX2 + -- when data0 /= data1. X propagation is reduced when the + -- dselect signal is X and both data signals are identical. + -- When this is the case, the result returned is the value + -- of the data signals. + -- + -- For the N input device: + -- + -- N must equal 2**(bits of dSelect) + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_logic_vector Input signal for the N-bit, 4-bit and + -- 8-bit mux. + -- Data1,Data0 std_ulogic Input signals for the 2-bit mux. + -- dSelect std_ulogic Select signal for 2-bit mux + -- std_logic_vector2 Select signal for 4-bit mux + -- std_logic_vector3 Select signal for 8-bit mux + -- std_logic_vector Select signal for N-Bit mux + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping for + -- all muxes. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_ulogic The value of the selected bit is + -- returned. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalMUX ( + CONSTANT Data : IN std_logic_vector; + CONSTANT dSelect : IN std_logic_vector; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalMUX2 ( + CONSTANT Data1, Data0 : IN std_ulogic; + CONSTANT dSelect : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalMUX4 ( + CONSTANT Data : IN std_logic_vector4; + CONSTANT dSelect : IN std_logic_vector2; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + FUNCTION VitalMUX8 ( + CONSTANT Data : IN std_logic_vector8; + CONSTANT dSelect : IN std_logic_vector3; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_ulogic; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8 + -- + -- Description: The VitalMUX concurrent primitive procedures calls + -- return in the output q the value of the selected data + -- bit based on the value of dsel. For the two bit mux, + -- the data returned is either d0 or d1, the data input. + -- For 4, 8 and N-bit functions, data is the input and is + -- of type std_logic_vector. For the 2-bit mux, if d0 or + -- d1 are X, the output is X only when d0 do not equal d1. + -- When d0 and d1 are equal, the return value is this value + -- to reduce X propagation. + -- + -- Propagation delay information is passed as a parameter + -- to the procedure call for delays from data to output and + -- select to output. For 2-bit muxes, the propagation + -- delays from data are provided for d0 and d1 to output. + -- + -- + -- Arguments: + -- + -- IN Type Description + -- d1,d0 std_ulogic Input signals for the 2-bit mux. + -- Data std_logic_vector4 Input signals for the 4-bit mux. + -- std_logic_vector8 Input signals for the 8-bit mux. + -- std_logic_vector Input signals for the N-bit mux. + -- dsel std_ulogic Select signal for the 2-bit mux. + -- std_logic_vector2 Select signals for the 4-bit mux. + -- std_logic_vector3 Select signals for the 8-bit mux. + -- std_logic_vector Select signals for the N-bit mux. + -- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to + -- output q for 2-bit mux. + -- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to + -- output q for 2-bit mux. + -- tpd_data_q VitalDelayArrayType01 Propagation delay from input data + -- to output q for 4-bit, 8-bit and + -- N-bit muxes. + -- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel + -- to output q for 2-bit mux. + -- VitalDelayArrayType01 Propagation delay from input dsel + -- to output q for 4-bit, 8-bit and + -- N-bit muxes. + -- ResultMap VitalResultMapType The output signal strength result + -- map to modify default result + -- mapping for all muxes. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic The value of the selected signal. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalMUX ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector; + SIGNAL dSel : IN std_logic_vector; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalMUX2 ( + SIGNAL q : OUT std_ulogic; + SIGNAL d1, d0 : IN std_ulogic; + SIGNAL dSel : IN std_ulogic; + CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalMUX4 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector4; + SIGNAL dSel : IN std_logic_vector2; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalMUX8 ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector8; + SIGNAL dSel : IN std_logic_vector3; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_dsel_q : IN VitalDelayArrayType01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + -- ------------------------------------------------------------------------ + -- + -- Sequential + -- Primitive + -- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4, + -- VitalDECODER8 + -- + -- Description: The VitalDECODER functions are the sequential primitive + -- calls for decoder logic. The functions are provided + -- for N, 2, 4 and 8-bit outputs. + -- + -- The N-bit decoder is (2**(bits of data)) wide. + -- + -- The VitalDECODER returns 0 if enable is 0. + -- The VitalDECODER returns the result bit set to 1 if + -- enable is 1. All other bits of returned result are + -- set to 0. + -- + -- The returned array is in descending order: + -- (n-1 downto 0). + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_ulogic Input signal for 2-bit decoder. + -- std_logic_vector2 Input signals for 4-bit decoder. + -- std_logic_vector3 Input signals for 8-bit decoder. + -- std_logic_vector Input signals for N-bit decoder. + -- Enable std_ulogic Enable input signal. The result is + -- output when enable is high. + -- ResultMap VitalResultMapType The output signal strength result map + -- to modify default result mapping for + -- all output signals of the decoders. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- std_logic_vector2 The output of the 2-bit decoder. + -- std_logic_vector4 The output of the 4-bit decoder. + -- std_logic_vector8 The output of the 8-bit decoder. + -- std_logic_vector The output of the n-bit decoder. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalDECODER ( + CONSTANT Data : IN std_logic_vector; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector; + + FUNCTION VitalDECODER2 ( + CONSTANT Data : IN std_ulogic; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector2; + + FUNCTION VitalDECODER4 ( + CONSTANT Data : IN std_logic_vector2; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector4; + + FUNCTION VitalDECODER8 ( + CONSTANT Data : IN std_logic_vector3; + CONSTANT Enable : IN std_ulogic; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap + ) RETURN std_logic_vector8; + + -- ------------------------------------------------------------------------- + -- + -- Concurrent + -- Primitive + -- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4, + -- VitalDECODER8 + -- + -- Description: The VitalDECODER procedures are the concurrent primitive + -- procedure calls for decoder functions. The procedures + -- are provided for N, 2, 4 and 8 outputs. + -- + -- The N-bit decoder is (2**(bits of data)) wide. + -- + -- The procedural form of the decoder is used for + -- distributed delay modeling. The delay information for + -- each path is passed as an argument to the procedure. + -- + -- Result is set to 0 if enable is 0. + -- The result bit represented by data is set to 1 if + -- enable is 1. All other bits of result are set to 0. + -- + -- The result array is in descending order: (n-1 downto 0). + -- + -- For the N-bit decoder, the delay path is a vector of + -- delays from inputs to outputs. + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_ulogic Input signal for 2-bit decoder. + -- std_logic_vector2 Input signals for 4-bit decoder. + -- std_logic_vector3 Input signals for 8-bit decoder. + -- std_logic_vector Input signals for N-bit decoder. + -- enable std_ulogic Enable input signal. The result is + -- output when enable is high. + -- tpd_data_q VitalDelayType01 Propagation delay from input data + -- to output q for 2-bit decoder. + -- VitalDelayArrayType01 Propagation delay from input data + -- to output q for 4, 8 and n-bit + -- decoders. + -- tpd_enable_q VitalDelayType01 Propagation delay from input enable + -- to output q for 2, 4, 8 and n-bit + -- decoders. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_logic_vector2 Output signals for 2-bit decoder. + -- std_logic_vector4 Output signals for 4-bit decoder. + -- std_logic_vector8 Output signals for 8-bit decoder. + -- std_logic_vector Output signals for n-bit decoder. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalDECODER ( + SIGNAL q : OUT std_logic_vector; + SIGNAL Data : IN std_logic_vector; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + PROCEDURE VitalDECODER2 ( + SIGNAL q : OUT std_logic_vector2; + SIGNAL Data : IN std_ulogic; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + PROCEDURE VitalDECODER4 ( + SIGNAL q : OUT std_logic_vector4; + SIGNAL Data : IN std_logic_vector2; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + PROCEDURE VitalDECODER8 ( + SIGNAL q : OUT std_logic_vector8; + SIGNAL Data : IN std_logic_vector3; + SIGNAL Enable : IN std_ulogic; + CONSTANT tpd_data_q : IN VitalDelayArrayType01; + CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01; + CONSTANT ResultMap : IN VitalResultMapType + := VitalDefaultResultMap ); + + -- ------------------------------------------------------------------------- + -- Function Name: VitalTruthTable + -- + -- Description: VitalTruthTable implements a truth table. Given + -- a set of inputs, a sequential search is performed + -- to match the input. If a match is found, the output + -- is set based on the contents of the CONSTANT TruthTable. + -- If there is no match, all X's are returned. There is + -- no limit to the size of the table. + -- + -- There is a procedure and function for VitalTruthTable. + -- For each of these, a single value output (std_logic) and + -- a multi-value output (std_logic_vector) are provided. + -- + -- The first dimension of the table is for number of + -- entries in the truth table and second dimension is for + -- the number of elements in a row. The number of inputs + -- in the row should be Data'LENGTH plus result'LENGTH. + -- + -- Elements is a row will be interpreted as + -- Input(NumInputs - 1),.., Input(0), + -- Result(NumOutputs - 1),.., Result(0) + -- + -- All inputs will be mapped to the X01 subtype + -- + -- If the value of Result is not in the range 'X' to 'Z' + -- then an error will be reported. Also, the Result is + -- always given either as a 0, 1, X or Z value. + -- + -- Arguments: + -- + -- IN Type Description + -- TruthTable The input constant which defines the + -- behavior in truth table form. + -- DataIn The inputs to the truth table used to + -- perform input match to select + -- output(s) to value(s) to drive. + -- + -- INOUT + -- none + -- + -- OUT + -- Result std_logic Concurrent procedure version scalar + -- output. + -- std_logic_vector Concurrent procedure version vector + -- output. + -- + -- Returns + -- Result std_logic Function version scalar output. + -- std_logic_vector Function version vector output. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalTruthTable ( + CONSTANT TruthTable : IN VitalTruthTableType; + CONSTANT DataIn : IN std_logic_vector + ) RETURN std_logic_vector; + + FUNCTION VitalTruthTable ( + CONSTANT TruthTable : IN VitalTruthTableType; + CONSTANT DataIn : IN std_logic_vector + ) RETURN std_logic; + + PROCEDURE VitalTruthTable ( + SIGNAL Result : OUT std_logic_vector; + CONSTANT TruthTable : IN VitalTruthTableType; + SIGNAL DataIn : IN std_logic_vector -- IR#236 + ); + PROCEDURE VitalTruthTable ( + SIGNAL Result : OUT std_logic; + CONSTANT TruthTable : IN VitalTruthTableType; + SIGNAL DataIn : IN std_logic_vector -- IR#236 + ); + -- ------------------------------------------------------------------------- + -- + -- Function Name: VitalStateTable + -- + -- Description: VitalStateTable is a non-concurrent implementation of a + -- state machine (Moore Machine). It is used to model + -- sequential devices and devices with internal states. + -- + -- The procedure takes the value of the state table + -- data set and performs a sequential search of the + -- CONSTANT StateTable until a match is found. Once a + -- match is found, the result of that match is applied + -- to Result. If there is no match, all X's are returned. + -- The resultant output becomes the input for the next + -- state. + -- + -- The first dimension of the table is the number of + -- entries in the state table and second dimension is the + -- number of elements in a row of the table. The number of + -- inputs in the row should be DataIn'LENGTH. Result should + -- contain the current state (which will become the next + -- state) as well as the outputs + -- + -- Elements is a row of the table will be interpreted as + -- Input(NumInputs-1),.., Input(0), State(NumStates-1), + -- ..., State(0),Output(NumOutputs-1),.., Output(0) + -- + -- where State(numStates-1) DOWNTO State(0) represent the + -- present state and Output(NumOutputs - 1) DOWNTO + -- Outputs(NumOutputs - NumStates) represent the new + -- values of the state variables (i.e. the next state). + -- Also, Output(NumOutputs - NumStates - 1) + -- + -- This procedure returns the next state and the new + -- outputs when a match is made between the present state + -- and present inputs and the state table. A search is + -- made starting at the top of the state table and + -- terminates with the first match. If no match is found + -- then the next state and new outputs are set to all 'X's. + -- + -- (Asynchronous inputs (i.e. resets and clears) must be + -- handled by placing the corresponding entries at the top + -- of the table. ) + -- + -- All inputs will be mapped to the X01 subtype. + -- + -- NOTE: Edge transitions should not be used as values + -- for the state variables in the present state + -- portion of the state table. The only valid + -- values that can be used for the present state + -- portion of the state table are: + -- 'X', '0', '1', 'B', '-' + -- + -- Arguments: + -- + -- IN Type Description + -- StateTable VitalStateTableType The input constant which defines + -- the behavior in state table form. + -- DataIn std_logic_vector The current state inputs to the + -- state table used to perform input + -- matches and transition + -- calculations. + -- NumStates NATURAL Number of state variables + -- + -- INOUT + -- Result std_logic Output signal for scalar version of + -- the concurrent procedure call. + -- std_logic_vector Output signals for vector version + -- of the concurrent procedure call. + -- PreviousDataIn std_logic_vector The previous inputs and states used + -- in transition calculations and to + -- set outputs for steady state cases. + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalStateTable ( + VARIABLE Result : INOUT std_logic_vector; + VARIABLE PreviousDataIn : INOUT std_logic_vector; + CONSTANT StateTable : IN VitalStateTableType; + CONSTANT DataIn : IN std_logic_vector; + CONSTANT NumStates : IN NATURAL + ); + + PROCEDURE VitalStateTable ( + VARIABLE Result : INOUT std_logic; + VARIABLE PreviousDataIn : INOUT std_logic_vector; + CONSTANT StateTable : IN VitalStateTableType; + CONSTANT DataIn : IN std_logic_vector + ); + + PROCEDURE VitalStateTable ( + SIGNAL Result : INOUT std_logic_vector; + CONSTANT StateTable : IN VitalStateTableType; + SIGNAL DataIn : IN std_logic_vector; + CONSTANT NumStates : IN NATURAL + ); + + PROCEDURE VitalStateTable ( + SIGNAL Result : INOUT std_logic; + CONSTANT StateTable : IN VitalStateTableType; + SIGNAL DataIn : IN std_logic_vector + ); + + -- ------------------------------------------------------------------------- + -- + -- Function Name: VitalResolve + -- + -- Description: VitalResolve takes a vector of signals and resolves + -- them to a std_ulogic value. This procedure can be used + -- to resolve multiple drivers in a single model. + -- + -- Arguments: + -- + -- IN Type Description + -- Data std_logic_vector Set of input signals which drive a + -- common signal. + -- + -- INOUT + -- none + -- + -- OUT + -- q std_ulogic Output signal which is the resolved + -- value being driven by the collection of + -- input signals. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalResolve ( + SIGNAL q : OUT std_ulogic; + SIGNAL Data : IN std_logic_vector); --IR236 4/2/98 + +END VITAL_Primitives; diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_b.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_b.vhdl new file mode 100644 index 0000000..cf6f6f5 --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_b.vhdl @@ -0,0 +1,2187 @@ +------------------------------------------------------------------------------- +-- Title : Standard VITAL TIMING Package +-- : $Revision$ +-- Library : VITAL +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : +-- Purpose : This packages defines standard types, attributes, constants, +-- : functions and procedures for use in developing ASIC models. +-- : This file contains the Package Body. +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No:|Auth:| Mod.Date:| Changes Made: +-- v95.0 A | | 06/08/95 | Initial ballot draft 1995 +-- v95.1 | | 08/31/95 | #IR203 - Timing violations at time 0 +-- #IR204 - Output mapping prior to glitch detection +-- v98.0 |TAG | 03/27/98 | Initial ballot draft 1998 +-- | #IR225 - Negative Premptive Glitch +-- **Code_effected=ReportGlitch,VitalGlitch, +-- VitalPathDelay,VitalPathDelay01, +-- VitalPathDelay01z. +-- #IR105 - Skew timing check needed +-- **Code_effected=NONE, New code added!! +-- #IR245,IR246,IR251 ITC code to fix false boundry cases +-- **Code_effected=InternalTimingCheck. +-- #IR248 - Allows VPD to use a default timing delay +-- **Code_effected=VitalPathDelay, +-- VitalPathDelay01,VitalPathDelay01z, +-- VitalSelectPathDelay,VitalSelectPathDelay01, +-- VitalSelectPathDelay01z. +-- #IR250 - Corrects fastpath condition in VPD +-- **Code_effected=VitalPathDelay01, +-- VitalPathDelay01z, +-- #IR252 - Corrects cancelled timing check call if +-- condition expires. +-- **Code_effected=VitalSetupHoldCheck, +-- VitalRecoveryRemovalCheck. +-- v98.1 | jdc | 03/25/99 | Changed UseDefaultDelay to IgnoreDefaultDelay +-- and set default to FALSE in VitalPathDelay() +-- +-- ---------------------------------------------------------------------------- + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +PACKAGE BODY VITAL_Timing IS + + -- -------------------------------------------------------------------- + -- Package Local Declarations + -- -------------------------------------------------------------------- + + TYPE CheckType IS ( SetupCheck, HoldCheck, RecoveryCheck, RemovalCheck, + PulseWidCheck, PeriodCheck ); + + TYPE CheckInfoType IS RECORD + Violation : BOOLEAN; + CheckKind : CheckType; + ObsTime : TIME; + ExpTime : TIME; + DetTime : TIME; + State : X01; + END RECORD; + + TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER; + TYPE HiLoStrType IS ARRAY (std_ulogic RANGE 'X' TO '1') OF STRING(1 TO 4); + + CONSTANT LogicCvtTable : LogicCvtTableType + := ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); + CONSTANT HiLoStr : HiLoStrType := (" X ", " Low", "High" ); + + TYPE EdgeSymbolMatchType IS ARRAY (X01,X01,VitalEdgeSymbolType) OF BOOLEAN; + -- last value, present value, edge symbol + CONSTANT EdgeSymbolMatch : EdgeSymbolMatchType := ( + 'X'=>('X'=>( OTHERS => FALSE), + '0'=>('N'|'F'|'v'|'E'|'D'|'*' => TRUE, OTHERS => FALSE ), + '1'=>('P'|'R'|'^'|'E'|'A'|'*' => TRUE, OTHERS => FALSE ) ), + '0'=>('X'=>( 'r'|'p'|'R'|'A'|'*' => TRUE, OTHERS => FALSE ), + '0'=>( OTHERS => FALSE ), + '1'=>( '/'|'P'|'p'|'R'|'*' => TRUE, OTHERS => FALSE ) ), + '1'=>('X'=>( 'f'|'n'|'F'|'D'|'*' => TRUE, OTHERS => FALSE ), + '0'=>( '\'|'N'|'n'|'F'|'*' => TRUE, OTHERS => FALSE ), + '1'=>( OTHERS => FALSE ) ) ); + + + + + --------------------------------------------------------------------------- + -- Tables used to implement 'posedge' and 'negedge' in path delays + -- These are new tables for Skewcheck routines. IR105 + --------------------------------------------------------------------------- + + TYPE EdgeRable IS ARRAY(std_ulogic, std_ulogic) OF boolean; + + CONSTANT Posedge : EdgeRable := ( + -- ------------------------------------------------------------------------ + -- | U X 0 1 Z W L H - + -- ------------------------------------------------------------------------ + ( FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE ), -- U + ( FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE ), -- X + ( TRUE , TRUE , FALSE, TRUE , TRUE , TRUE , FALSE, TRUE , TRUE ), -- 0 + ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- 1 + ( FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE ), -- Z + ( FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE ), -- W + ( TRUE , TRUE , FALSE, TRUE , TRUE , TRUE , FALSE, TRUE , TRUE ), -- L + ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- H + ( FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE ) -- - + + ); --IR105 + + + CONSTANT Negedge : EdgeRable := ( + -- ----------------------------------------------------------------------- + -- | U X 0 1 Z W L H - + -- ----------------------------------------------------------------------- + ( FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, FALSE ), -- U + ( FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, FALSE ), -- X + ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- 0 + ( TRUE , TRUE , TRUE , FALSE, TRUE , TRUE , TRUE , FALSE, TRUE ), -- 1 + ( FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, FALSE ), -- Z + ( FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, FALSE ), -- W + ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- L + ( TRUE , TRUE , TRUE , FALSE, TRUE , TRUE , TRUE , FALSE, TRUE ), -- H + ( FALSE, FALSE, TRUE , FALSE, FALSE, FALSE, TRUE , FALSE, FALSE ) -- - + + ); --IR105 + + TYPE SkewType IS (Inphase, Outphase); --IR105 + + CONSTANT noTrigger : TIME := -1 ns; --IR105 + --------------------------------------------------------------------------- + -- End of Skew (IR105 additions) + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- Misc Utilities Local Utilities + --------------------------------------------------------------------------- + ----------------------------------------------------------------------- + FUNCTION Minimum ( CONSTANT t1,t2 : IN TIME ) RETURN TIME IS + BEGIN + IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF; + END Minimum; + ----------------------------------------------------------------------- + FUNCTION Maximum ( CONSTANT t1,t2 : IN TIME ) RETURN TIME IS + BEGIN + IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF; + END Maximum; + + -------------------------------------------------------------------- + -- Error Message Types and Tables + -------------------------------------------------------------------- + TYPE VitalErrorType IS ( + ErrVctLng , + ErrNoPath , + ErrNegPath , + ErrNegDel + ); + + TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL; + CONSTANT VitalErrorSeverity : VitalErrorSeverityType := ( + ErrVctLng => ERROR, + ErrNoPath => WARNING, + ErrNegPath => WARNING, + ErrNegDel => WARNING + ); + + CONSTANT MsgNoPath : STRING := + "No Delay Path Condition TRUE. 0-delay used. Output signal is: "; + CONSTANT MsgNegPath : STRING := + "Path Delay less than time since input. 0 delay used. Output signal is: "; + CONSTANT MsgNegDel : STRING := + "Negative delay. New output value not scheduled. Output signal is: "; + CONSTANT MsgVctLng : STRING := + "Vector (array) lengths not equal. "; + + CONSTANT MsgUnknown : STRING := + "Unknown error message."; + + FUNCTION VitalMessage ( + CONSTANT ErrorId : IN VitalErrorType + ) RETURN STRING IS + BEGIN + CASE ErrorId IS + WHEN ErrVctLng => RETURN MsgVctLng; + WHEN ErrNoPath => RETURN MsgNoPath; + WHEN ErrNegPath => RETURN MsgNegPath; + WHEN ErrNegDel => RETURN MsgNegDel; + WHEN OTHERS => RETURN MsgUnknown; + END CASE; + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) + SEVERITY VitalErrorSeverity(ErrorId); + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType; + CONSTANT Info : IN STRING + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) & Info + SEVERITY VitalErrorSeverity(ErrorId); + END; + + PROCEDURE VitalError ( + CONSTANT Routine : IN STRING; + CONSTANT ErrorId : IN VitalErrorType; + CONSTANT Info : IN CHARACTER + ) IS + BEGIN + ASSERT FALSE + REPORT Routine & ": " & VitalMessage(ErrorId) & Info + SEVERITY VitalErrorSeverity(ErrorId); + END; + + --------------------------------------------------------------------------- + -- Time Delay Assignment Subprograms + --------------------------------------------------------------------------- + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType + ) RETURN VitalDelayType01Z IS + BEGIN + RETURN (OTHERS => Delay); + END VitalExtendToFillDelay; + + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType01 + ) RETURN VitalDelayType01Z IS + VARIABLE Delay01Z : VitalDelayType01Z; + BEGIN + Delay01Z(tr01) := Delay(tr01); + Delay01Z(tr0z) := Delay(tr01); + Delay01Z(trz1) := Delay(tr01); + Delay01Z(tr10) := Delay(tr10); + Delay01Z(tr1z) := Delay(tr10); + Delay01Z(trz0) := Delay(tr10); + RETURN (Delay01Z); + END VitalExtendToFillDelay; + + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType01Z + ) RETURN VitalDelayType01Z IS + BEGIN + RETURN Delay; + END VitalExtendToFillDelay; + + --------------------------------------------------------------------------- + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType + ) RETURN TIME IS + BEGIN + RETURN delay; + END VitalCalcDelay; + + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType01 + ) RETURN TIME IS + VARIABLE Result : TIME; + BEGIN + CASE Newval IS + WHEN '0' | 'L' => Result := Delay(tr10); + WHEN '1' | 'H' => Result := Delay(tr01); + WHEN 'Z' => + CASE Oldval IS + WHEN '0' | 'L' => Result := Delay(tr01); + WHEN '1' | 'H' => Result := Delay(tr10); + WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01)); + END CASE; + WHEN OTHERS => + CASE Oldval IS + WHEN '0' | 'L' => Result := Delay(tr01); + WHEN '1' | 'H' => Result := Delay(tr10); + WHEN 'Z' => Result := MINIMUM(Delay(tr10), Delay(tr01)); + WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01)); + END CASE; + END CASE; + RETURN Result; + END VitalCalcDelay; + + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType01Z + ) RETURN TIME IS + VARIABLE Result : TIME; + BEGIN + CASE Oldval IS + WHEN '0' | 'L' => + CASE Newval IS + WHEN '0' | 'L' => Result := Delay(tr10); + WHEN '1' | 'H' => Result := Delay(tr01); + WHEN 'Z' => Result := Delay(tr0z); + WHEN OTHERS => Result := MINIMUM(Delay(tr01), Delay(tr0z)); + END CASE; + WHEN '1' | 'H' => + CASE Newval IS + WHEN '0' | 'L' => Result := Delay(tr10); + WHEN '1' | 'H' => Result := Delay(tr01); + WHEN 'Z' => Result := Delay(tr1z); + WHEN OTHERS => Result := MINIMUM(Delay(tr10), Delay(tr1z)); + END CASE; + WHEN 'Z' => + CASE Newval IS + WHEN '0' | 'L' => Result := Delay(trz0); + WHEN '1' | 'H' => Result := Delay(trz1); + WHEN 'Z' => Result := MAXIMUM (Delay(tr0z), Delay(tr1z)); + WHEN OTHERS => Result := MINIMUM (Delay(trz1), Delay(trz0)); + END CASE; + WHEN 'U' | 'X' | 'W' | '-' => + CASE Newval IS + WHEN '0' | 'L' => Result := MAXIMUM(Delay(tr10), Delay(trz0)); + WHEN '1' | 'H' => Result := MAXIMUM(Delay(tr01), Delay(trz1)); + WHEN 'Z' => Result := MAXIMUM(Delay(tr1z), Delay(tr0z)); + WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01)); + END CASE; + END CASE; + RETURN Result; + END VitalCalcDelay; + + --------------------------------------------------------------------------- + -- + -- VitalSelectPathDelay returns the path delay selected by the Paths array. + -- If no paths are selected, it returns either the appropriate default + -- delay or TIME'HIGH, depending upon the value of IgnoreDefaultDelay. + -- + + FUNCTION VitalSelectPathDelay ( + CONSTANT NewValue : IN std_logic; + CONSTANT OldValue : IN std_logic; + CONSTANT OutSignalName : IN string; + CONSTANT Paths : IN VitalPathArrayType; + CONSTANT DefaultDelay : IN VitalDelayType; + CONSTANT IgnoreDefaultDelay : IN BOOLEAN + ) RETURN TIME IS + + VARIABLE TmpDelay : TIME; + VARIABLE InputAge : TIME := TIME'HIGH; + VARIABLE PropDelay : TIME := TIME'HIGH; + BEGIN + -- for each delay path + FOR i IN Paths'RANGE LOOP + -- ignore the delay path if it is not enabled + NEXT WHEN NOT Paths(i).PathCondition; + -- ignore the delay path if a more recent input event has been seen + NEXT WHEN Paths(i).InputChangeTime > InputAge; + + -- This is the most recent input change (so far) + -- Get the transition dependent delay + TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay); + + -- If other inputs changed at the same time, + -- then use the minimum of their propagation delays, + -- else use the propagation delay from this input. + IF Paths(i).InputChangeTime < InputAge THEN + PropDelay := TmpDelay; + ELSE -- Simultaneous inputs change + IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF; + end if; + + InputAge := Paths(i).InputChangeTime; + END LOOP; + + -- If there were no paths (with an enabled condition), + -- use the default delay, if so indicated, otherwise return TIME'HIGH + IF (PropDelay = TIME'HIGH) THEN + IF (IgnoreDefaultDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + END IF; + + -- If the time since the most recent selected input event is + -- greater than the propagation delay from that input, + -- then use the default delay (won't happen if no paths are selected) + ELSIF (InputAge > PropDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + + -- Adjust the propagation delay by the time since the + -- the input event occurred (Usually 0 ns). + ELSE + PropDelay := PropDelay - InputAge; + END IF; + + RETURN PropDelay; + END; + + FUNCTION VitalSelectPathDelay ( + CONSTANT NewValue : IN std_logic; + CONSTANT OldValue : IN std_logic; + CONSTANT OutSignalName : IN string; + CONSTANT Paths : IN VitalPathArray01Type; + CONSTANT DefaultDelay : IN VitalDelayType01; + CONSTANT IgnoreDefaultDelay : IN BOOLEAN + ) RETURN TIME IS + + VARIABLE TmpDelay : TIME; + VARIABLE InputAge : TIME := TIME'HIGH; + VARIABLE PropDelay : TIME := TIME'HIGH; + BEGIN + -- for each delay path + FOR i IN Paths'RANGE LOOP + -- ignore the delay path if it is not enabled + NEXT WHEN NOT Paths(i).PathCondition; + -- ignore the delay path if a more recent input event has been seen + NEXT WHEN Paths(i).InputChangeTime > InputAge; + + -- This is the most recent input change (so far) + -- Get the transition dependent delay + TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay); + + -- If other inputs changed at the same time, + -- then use the minimum of their propagation delays, + -- else use the propagation delay from this input. + IF Paths(i).InputChangeTime < InputAge THEN + PropDelay := TmpDelay; + ELSE -- Simultaneous inputs change + IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF; + end if; + + InputAge := Paths(i).InputChangeTime; + END LOOP; + + -- If there were no paths (with an enabled condition), + -- use the default delay, if so indicated, otherwise return TIME'HIGH + IF (PropDelay = TIME'HIGH) THEN + IF (IgnoreDefaultDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + END IF; + + -- If the time since the most recent selected input event is + -- greater than the propagation delay from that input, + -- then use the default delay (won't happen if no paths are selected) + ELSIF (InputAge > PropDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + + -- Adjust the propagation delay by the time since the + -- the input event occurred (Usually 0 ns). + ELSE + PropDelay := PropDelay - InputAge; + END IF; + + RETURN PropDelay; + END; + + FUNCTION VitalSelectPathDelay ( + CONSTANT NewValue : IN std_logic; + CONSTANT OldValue : IN std_logic; + CONSTANT OutSignalName : IN string; + CONSTANT Paths : IN VitalPathArray01ZType; + CONSTANT DefaultDelay : IN VitalDelayType01Z; + CONSTANT IgnoreDefaultDelay : IN BOOLEAN + ) RETURN TIME IS + + VARIABLE TmpDelay : TIME; + VARIABLE InputAge : TIME := TIME'HIGH; + VARIABLE PropDelay : TIME := TIME'HIGH; + BEGIN + -- for each delay path + FOR i IN Paths'RANGE LOOP + -- ignore the delay path if it is not enabled + NEXT WHEN NOT Paths(i).PathCondition; + -- ignore the delay path if a more recent input event has been seen + NEXT WHEN Paths(i).InputChangeTime > InputAge; + + -- This is the most recent input change (so far) + -- Get the transition dependent delay + TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay); + + -- If other inputs changed at the same time, + -- then use the minimum of their propagation delays, + -- else use the propagation delay from this input. + IF Paths(i).InputChangeTime < InputAge THEN + PropDelay := TmpDelay; + ELSE -- Simultaneous inputs change + IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF; + end if; + + InputAge := Paths(i).InputChangeTime; + END LOOP; + + -- If there were no paths (with an enabled condition), + -- use the default delay, if so indicated, otherwise return TIME'HIGH + IF (PropDelay = TIME'HIGH) THEN + IF (IgnoreDefaultDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + END IF; + + -- If the time since the most recent selected input event is + -- greater than the propagation delay from that input, + -- then use the default delay (won't happen if no paths are selected) + ELSIF (InputAge > PropDelay) THEN + PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay); + + -- Adjust the propagation delay by the time since the + -- the input event occurred (Usually 0 ns). + ELSE + PropDelay := PropDelay - InputAge; + END IF; + + RETURN PropDelay; + END; + + + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- Glitch Handlers + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + PROCEDURE ReportGlitch ( + CONSTANT GlitchRoutine : IN STRING; + CONSTANT OutSignalName : IN STRING; + CONSTANT PreemptedTime : IN TIME; + CONSTANT PreemptedValue : IN std_ulogic; + CONSTANT NewTime : IN TIME; + CONSTANT NewValue : IN std_ulogic; + CONSTANT Index : IN INTEGER := 0; + CONSTANT IsArraySignal : IN BOOLEAN := FALSE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + + VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE; + BEGIN + + Write (StrPtr1, PreemptedTime ); + Write (StrPtr2, NewTime); + Write (StrPtr3, LogicCvtTable(PreemptedValue)); + Write (StrPtr4, LogicCvtTable(NewValue)); + IF IsArraySignal THEN + Write (StrPtr5, STRING'( "(" ) ); + Write (StrPtr5, Index); + Write (StrPtr5, STRING'( ")" ) ); + ELSE + Write (StrPtr5, STRING'( " " ) ); + END IF; + + -- Issue Report only if Preempted value has not been + -- removed from event queue + ASSERT PreemptedTime > NewTime + REPORT GlitchRoutine & ": GLITCH Detected on port " & + OutSignalName & StrPtr5.ALL & + "; Preempted Future Value := " & StrPtr3.ALL & + " @ " & StrPtr1.ALL & + "; Newly Scheduled Value := " & StrPtr4.ALL & + " @ " & StrPtr2.ALL & + ";" + SEVERITY MsgSeverity; + + + ASSERT PreemptedTime <= NewTime + REPORT GlitchRoutine & ": GLITCH Detected on port " & + OutSignalName & StrPtr5.ALL & + "; Negative Preempted Value := " & StrPtr3.ALL & + " @ " & StrPtr1.ALL & + "; Newly Scheduled Value := " & StrPtr4.ALL & + " @ " & StrPtr2.ALL & + ";" + SEVERITY MsgSeverity; + + + DEALLOCATE(StrPtr1); + DEALLOCATE(StrPtr2); + DEALLOCATE(StrPtr3); + DEALLOCATE(StrPtr4); + DEALLOCATE(StrPtr5); + RETURN; + END ReportGlitch; + + --------------------------------------------------------------------------- + PROCEDURE VitalGlitch ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT NewValue : IN std_logic; + CONSTANT NewDelay : IN TIME := 0 ns; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 + CONSTANT MsgOn : IN BOOLEAN := FALSE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + --------------------------------------------------------------------------- + VARIABLE NewGlitch : BOOLEAN := TRUE; + VARIABLE dly : TIME := NewDelay; + VARIABLE NOW_TIME : TIME := NOW; + VARIABLE NegPreemptGlitch : BOOLEAN := FALSE; + + BEGIN + NegPreemptGlitch:=FALSE;--reset Preempt-Glitch + + -- If nothing to schedule, just return + IF NewDelay < 0 ns THEN + IF (NewValue /= GlitchData.SchedValue) THEN + VitalError ( "VitalGlitch", ErrNegDel, OutSignalName ); + END IF; + RETURN; + END IF; + + -- If simple signal assignment + -- perform the signal assignment + IF ( Mode = VitalInertial) THEN + OutSignal <= NewValue AFTER dly; + ELSIF ( Mode = VitalTransport ) THEN + OutSignal <= TRANSPORT NewValue AFTER dly; + ELSE + -- Glitch Processing --- + -- If nothing currently scheduled + IF GlitchData.SchedTime <= NOW THEN -- NOW >= last event + -- Note: NewValue is always /= OldValue when called from VPPD + IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF; + NewGlitch := FALSE; + GlitchData.GlitchTime := NOW+dly; + + -- New value earlier than the earliest previous value scheduled + -- (negative preemptive) + ELSIF (NOW+dly <= GlitchData.GlitchTime) + AND (NOW+dly <= GlitchData.SchedTime) THEN + + -- Glitch is negative preemptive - check if same value and + -- NegPreempt is on IR225 + IF (GlitchData.SchedValue /= NewValue) AND (NegPreemptOn) AND + (NOW > 0 NS) THEN + NewGlitch := TRUE; + NegPreemptGlitch :=TRUE; -- Set preempt Glitch condition + ELSE + NewGlitch := FALSE; -- No new glitch, save time for + -- possible future glitch + END IF; + GlitchData.GlitchTime := NOW+dly; + + -- Transaction currently scheduled - if glitch already happened + ELSIF GlitchData.GlitchTime <= NOW THEN + IF (GlitchData.SchedValue = NewValue) THEN + dly := Minimum( GlitchData.SchedTime-NOW, NewDelay ); + END IF; + NewGlitch := FALSE; + + -- Transaction currently scheduled (no glitch if same value) + ELSIF (GlitchData.SchedValue = NewValue) + AND (GlitchData.SchedTime = GlitchData.GlitchTime) THEN + -- revise scheduled output time if new delay is sooner + dly := Minimum( GlitchData.SchedTime-NOW, NewDelay ); + -- No new glitch, save time for possable future glitch + NewGlitch := FALSE; + GlitchData.GlitchTime := NOW+dly; + + -- Transaction currently scheduled represents a glitch + ELSE + NewGlitch := TRUE; -- A new glitch has been detected + END IF; + + IF NewGlitch THEN + -- If messages requested, report the glitch + IF MsgOn THEN + IF NegPreemptGlitch THEN --IR225 + ReportGlitch ("VitalGlitch-Neg", OutSignalName, + GlitchData.GlitchTime, GlitchData.SchedValue, + (dly + NOW), NewValue, + MsgSeverity=>MsgSeverity ); + ELSE + ReportGlitch ("VitalGlitch", OutSignalName, + GlitchData.GlitchTime, GlitchData.SchedValue, + (dly + NOW), NewValue, + MsgSeverity=>MsgSeverity ); + END IF; + END IF; + + -- If 'X' generation is requested, schedule the new value + -- preceeded by a glitch pulse. + -- Otherwise just schedule the new value (inertial mode). + IF XOn THEN + IF (Mode = OnDetect) THEN + OutSignal <= 'X'; + ELSE + OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW; + END IF; + + IF NegPreemptGlitch THEN -- IR225 + OutSignal <= TRANSPORT NewValue AFTER GlitchData.SchedTime-NOW; + ELSE + OutSignal <= TRANSPORT NewValue AFTER dly; + END IF; + ELSE + OutSignal <= NewValue AFTER dly; -- no glitch regular prop delay + END IF; + + -- If there no new glitch was detected, just schedule the new value. + ELSE + OutSignal <= NewValue AFTER dly; + END IF; + END IF; + + -- Record the new value and time depending on glitch type just scheduled. + IF NOT NegPreemptGlitch THEN -- 5/2/96 for "x-pulse" IR225 + GlitchData.SchedValue := NewValue; + GlitchData.SchedTime := NOW+dly; -- pulse timing. + ELSE + GlitchData.SchedValue := 'X'; + -- leave GlitchData.SchedTime to old value since glitch is negative + END IF; + RETURN; + END; + + --------------------------------------------------------------------------- + PROCEDURE VitalPathDelay ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArrayType; + CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE --IR248 3/14/98 + ) IS + + VARIABLE PropDelay : TIME; + + BEGIN + -- Check if the new value to be scheduled is different than the + -- previously scheduled value + IF (GlitchData.SchedTime <= NOW) AND + (GlitchData.SchedValue = OutTemp) + THEN RETURN; + END IF; + + -- Evaluate propagation delay paths + PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue, + OutSignalName, Paths, DefaultDelay, + IgnoreDefaultDelay); + + GlitchData.LastValue := OutTemp; + + -- Schedule the output transactions - including glitch handling + VitalGlitch (OutSignal, GlitchData, OutSignalName, OutTemp, + PropDelay, Mode, XOn, NegPreemptOn, MsgOn, MsgSeverity ); + + END VitalPathDelay; + + --------------------------------------------------------------------------- + + PROCEDURE VitalPathDelay01 ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArray01Type; + CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98 + CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250 + + + ) IS + + VARIABLE PropDelay : TIME; + BEGIN + + -- Check if the new value to be scheduled is different than the + -- previously scheduled value + IF (GlitchData.SchedTime <= NOW) AND + (GlitchData.SchedValue = OutTemp) + THEN RETURN; + -- Check if the new value to be Scheduled is the same as the + -- previously scheduled output transactions. If this condition + -- exists and the new scheduled time is < the current GlitchData. + -- schedTime then a fast path condition exists (IR250). If the + -- modeler wants this condition rejected by setting the + -- RejectFastPath actual to true then exit out. + ELSIF (GlitchData.SchedValue=OutTemp) AND (RejectFastPath) + THEN RETURN; + END IF; + + -- Evaluate propagation delay paths + PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue, + OutSignalName, Paths, DefaultDelay, + IgnoreDefaultDelay); + + GlitchData.LastValue := OutTemp; + + + VitalGlitch (OutSignal, GlitchData, OutSignalName, OutTemp, + PropDelay, Mode, XOn, NegPreemptOn, MsgOn, MsgSeverity ); + END VitalPathDelay01; + + --------------------------------------------------------------------------- + PROCEDURE VitalPathDelay01Z ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArray01ZType; + CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98 + CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250 + ) IS + + VARIABLE PropDelay : TIME; + + BEGIN + -- Check if the new value to be scheduled is different than the + -- previously scheduled value + IF (GlitchData.SchedTime <= NOW) AND + (GlitchData.SchedValue = OutTemp) + THEN RETURN; + -- Check if the new value to be Scheduled is the same as the + -- previously scheduled output transactions. If this condition + -- exists and the new scheduled time is < the current GlitchData. + -- schedTime then a fast path condition exists (IR250). If the + -- modeler wants this condition rejected by setting the + -- RejectFastPath actual to true then exit out. + ELSIF (GlitchData.SchedValue=OutTemp) AND (RejectFastPath) + THEN RETURN; + END IF; + + -- Evaluate propagation delay paths + PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue, + OutSignalName, Paths, DefaultDelay, + IgnoreDefaultDelay); + + GlitchData.LastValue := OutTemp; + + + -- Schedule the output transactions - including glitch handling + VitalGlitch (OutSignal, GlitchData, OutSignalName, OutTemp, + PropDelay, Mode, XOn, NegPreemptOn, MsgOn, MsgSeverity ); + END VitalPathDelay01Z; + + + ---------------------------------------------------------------------------- + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType + ) IS + BEGIN + OutSig <= TRANSPORT InSig AFTER twire; + END VitalWireDelay; + + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType01 + ) IS + VARIABLE Delay : TIME; + BEGIN + Delay := VitalCalcDelay( InSig, InSig'LAST_VALUE, twire ); + OutSig <= TRANSPORT InSig AFTER Delay; + END VitalWireDelay; + + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType01Z + ) IS + VARIABLE Delay : TIME; + BEGIN + Delay := VitalCalcDelay( InSig, InSig'LAST_VALUE, twire ); + OutSig <= TRANSPORT InSig AFTER Delay; + END VitalWireDelay; + + ---------------------------------------------------------------------------- + PROCEDURE VitalSignalDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT dly : IN TIME + ) IS + BEGIN + OutSig <= TRANSPORT InSig AFTER dly; + END; + + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- Setup and Hold Time Check Routine + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + PROCEDURE ReportViolation ( + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT CheckInfo : IN CheckInfoType; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + VARIABLE Message : LINE; + BEGIN + IF NOT CheckInfo.Violation THEN RETURN; END IF; + + Write ( Message, HeaderMsg ); + Case CheckInfo.CheckKind IS + WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") ); + WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") ); + WHEN RecoveryCheck => Write ( Message, STRING'(" RECOVERY ") ); + WHEN RemovalCheck => Write ( Message, STRING'(" REMOVAL ") ); + WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH ")); + WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") ); + END CASE; + Write ( Message, HiLoStr(CheckInfo.State) ); + Write ( Message, STRING'(" VIOLATION ON ") ); + Write ( Message, TestSignalName ); + IF (RefSignalName'LENGTH > 0) THEN + Write ( Message, STRING'(" WITH RESPECT TO ") ); + Write ( Message, RefSignalName ); + END IF; + Write ( Message, ';' & LF ); + Write ( Message, STRING'(" Expected := ") ); + Write ( Message, CheckInfo.ExpTime); + Write ( Message, STRING'("; Observed := ") ); + Write ( Message, CheckInfo.ObsTime); + Write ( Message, STRING'("; At : ") ); + Write ( Message, CheckInfo.DetTime); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END ReportViolation; + + + --------------------------------------------------------------------------- + -- Procedure : InternalTimingCheck + --------------------------------------------------------------------------- + PROCEDURE InternalTimingCheck ( + CONSTANT TestSignal : IN std_ulogic; + CONSTANT RefSignal : IN std_ulogic; + CONSTANT TestDelay : IN TIME := 0 ns; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + VARIABLE RefTime : IN TIME; + VARIABLE RefEdge : IN BOOLEAN; + VARIABLE TestTime : IN TIME; + VARIABLE TestEvent : IN BOOLEAN; + VARIABLE SetupEn : INOUT BOOLEAN; + VARIABLE HoldEn : INOUT BOOLEAN; + VARIABLE CheckInfo : INOUT CheckInfoType; + CONSTANT MsgOn : IN BOOLEAN + ) IS + VARIABLE bias : TIME; + VARIABLE actualObsTime : TIME; + VARIABLE BC : TIME; + VARIABLE Message:LINE; + BEGIN + -- Check SETUP constraint + IF RefEdge THEN + IF SetupEn THEN + CheckInfo.ObsTime := RefTime - TestTime; + CheckInfo.State := To_X01(TestSignal); + CASE CheckInfo.State IS + WHEN '0' => CheckInfo.ExpTime := SetupLow; + -- start of new code IR245-246 + BC := HoldHigh; + -- end of new code IR245-246 + WHEN '1' => CheckInfo.ExpTime := SetupHigh; + -- start of new code IR245-246 + BC := HoldLow; + -- end of new code IR245-246 + WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow); + -- start of new code IR245-246 + BC := Maximum(HoldHigh,HoldLow); + -- end of new code IR245-246 + END CASE; + -- added the second condition for IR 245-246 + CheckInfo.Violation := ( (CheckInfo.ObsTime < CheckInfo.ExpTime) + AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))) ); + -- start of new code IR245-246 + IF(CheckInfo.ExpTime = 0 ns) THEN + CheckInfo.CheckKind := HoldCheck; + ELSE + CheckInfo.CheckKind := SetupCheck; + END IF; + -- end of new code IR245-246 + SetupEn := FALSE; + ELSE + CheckInfo.Violation := FALSE; + END IF; + + -- Check HOLD constraint + ELSIF TestEvent THEN + IF HoldEn THEN + CheckInfo.ObsTime := TestTime - RefTime; + CheckInfo.State := To_X01(TestSignal); + CASE CheckInfo.State IS + WHEN '0' => CheckInfo.ExpTime := HoldHigh; + + -- new code for unnamed IR + CheckInfo.State := '1'; + + -- start of new code IR245-246 + BC := SetupLow; + -- end of new code IR245-246 + WHEN '1' => CheckInfo.ExpTime := HoldLow; + + -- new code for unnamed IR + CheckInfo.State := '0'; + + -- start of new code IR245-246 + BC := SetupHigh; + -- end of new code IR245-246 + WHEN 'X' => CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow); + -- start of new code IR245-246 + BC := Maximum(SetupHigh,SetupLow); + -- end of new code IR245-246 + END CASE; + -- added the second condition for IR 245-246 + CheckInfo.Violation := ( (CheckInfo.ObsTime < CheckInfo.ExpTime) + AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))) ); + + -- start of new code IR245-246 + IF(CheckInfo.ExpTime = 0 ns) THEN + CheckInfo.CheckKind := SetupCheck; + ELSE + CheckInfo.CheckKind := HoldCheck; + END IF; + -- end of new code IR245-246 + HoldEn := NOT CheckInfo.Violation; + ELSE + CheckInfo.Violation := FALSE; + END IF; + ELSE + CheckInfo.Violation := FALSE; + END IF; + + -- Adjust report values to account for internal model delays + -- Note: TestDelay, RefDelay, TestTime, RefTime are non-negative + -- Note: bias may be negative or positive + IF MsgOn AND CheckInfo.Violation THEN + -- modified the code for correct reporting of violation in case of + -- order of signals being reversed because of internal delays + -- new variable + actualObsTime := (TestTime-TestDelay)-(RefTime-RefDelay); + bias := TestDelay - RefDelay; + IF (actualObsTime < 0 ns) THEN -- It should be a setup check + IF ( CheckInfo.CheckKind = HoldCheck) then + CheckInfo.CheckKind := SetupCheck; + CASE CheckInfo.State IS + WHEN '0' => CheckInfo.ExpTime := SetupLow; + WHEN '1' => CheckInfo.ExpTime := SetupHigh; + WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow); + END CASE; + END IF; + + CheckInfo.ObsTime := -actualObsTime; + CheckInfo.ExpTime := CheckInfo.ExpTime + bias; + CheckInfo.DetTime := RefTime - RefDelay; + ELSE -- It should be a hold check + IF ( CheckInfo.CheckKind = SetupCheck) then + CheckInfo.CheckKind := HoldCheck; + CASE CheckInfo.State IS + WHEN '0' => CheckInfo.ExpTime := HoldHigh; + CheckInfo.State := '1'; + WHEN '1' => CheckInfo.ExpTime := HoldLow; + CheckInfo.State := '0'; + WHEN 'X' => CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow); + END CASE; + END IF; + + CheckInfo.ObsTime := actualObsTime; + CheckInfo.ExpTime := CheckInfo.ExpTime - bias; + CheckInfo.DetTime := TestTime - TestDelay; + END IF; + + END IF; + END InternalTimingCheck; + + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + FUNCTION VitalTimingDataInit + RETURN VitalTimingDataType IS + BEGIN + RETURN (FALSE,'X', 0 ns, FALSE, 'X', 0 ns, FALSE, NULL, NULL, NULL, NULL); + END; + + --------------------------------------------------------------------------- + -- Procedure : VitalSetupHoldCheck + --------------------------------------------------------------------------- + PROCEDURE VitalSetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + ) IS + + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge, TestEvent : BOOLEAN; + VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay); + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; + BEGIN + + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLast := To_X01(TestSignal); + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF RefEdge THEN + TimingData.RefTime := NOW; + TimingData.SetupEn := TimingData.SetupEn AND EnableSetupOnRef; --IR252 3/23/98 + TimingData.HoldEn := EnableHoldOnRef; --IR252 3/23/98 + END IF; + + -- Detect test (data) changes and record the time of the last change + TestEvent := TimingData.TestLast /= To_X01Z(TestSignal); + TimingData.TestLast := To_X01Z(TestSignal); + IF TestEvent THEN + TimingData.TestTime := NOW; + TimingData.SetupEn := EnableSetupOnTest; --IR252 3/23/98 + TimingData.HoldEn := TimingData.HoldEn AND EnableHoldOnTest; --IR252 3/23/98 + END IF; + + -- Perform timing checks (if enabled) + Violation := '0'; + IF (CheckEnabled) THEN + InternalTimingCheck ( + TestSignal => TestSignal, + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh, + SetupLow => SetupLow, + HoldHigh => HoldHigh, + HoldLow => HoldLow, + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTime, + TestEvent => TestEvent, + SetupEn => TimingData.SetupEn, + HoldEn => TimingData.HoldEn, + CheckInfo => CheckInfo, + MsgOn => MsgOn ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + ReportViolation (TestSignalName, RefSignalName, + HeaderMsg, CheckInfo, MsgSeverity ); + END IF; + IF (XOn) THEN Violation := 'X'; END IF; + END IF; + END IF; + + END VitalSetupHoldCheck; + + --------------------------------------------------------------------------- + PROCEDURE VitalSetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + + ) IS + + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge : BOOLEAN; + VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE); + VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay); + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; + VARIABLE ChangedAllAtOnce : BOOLEAN := TRUE; + VARIABLE StrPtr1 : LINE; + + BEGIN + -- Initialization of working area. + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE); + TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE); + TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE); + FOR i IN TestSignal'RANGE LOOP + TimingData.TestLastA(i) := To_X01(TestSignal(i)); + END LOOP; + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF RefEdge THEN + TimingData.RefTime := NOW; + TimingData.SetupEn := TimingData.SetupEn AND EnableSetupOnRef; --IR252 3/23/98 + TimingData.HoldEnA.all := (TestSignal'RANGE => EnableHoldOnRef); --IR252 3/23/98 + END IF; + + -- Detect test (data) changes and record the time of the last change + FOR i IN TestSignal'RANGE LOOP + TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i)); + TimingData.TestLastA(i) := To_X01Z(TestSignal(i)); + IF TestEvent(i) THEN + TimingData.TestTimeA(i) := NOW; + TimingData.SetupEnA(i) := EnableSetupOnTest; --IR252 3/23/98 + TimingData.HoldEnA(i) := TimingData.HoldEn AND EnableHoldOnTest; --IR252 3/23/98 + TimingData.TestTime := NOW; --IR252 3/23/98 + END IF; + END LOOP; + + -- Check to see if the Bus subelements changed all at the same time. + -- If so, then we can reduce the volume of error messages since we no + -- longer have to report every subelement individually + FOR i IN TestSignal'RANGE LOOP + IF TimingData.TestTimeA(i) /= TimingData.TestTime THEN + ChangedAllAtOnce := FALSE; + EXIT; + END IF; + END LOOP; + + -- Perform timing checks (if enabled) + Violation := '0'; + IF (CheckEnabled) THEN + FOR i IN TestSignal'RANGE LOOP + InternalTimingCheck ( + TestSignal => TestSignal(i), + RefSignal => RefSignal, + TestDelay => TestDly, + RefDelay => RefDly, + SetupHigh => SetupHigh, + SetupLow => SetupLow, + HoldHigh => HoldHigh, + HoldLow => HoldLow, + RefTime => TimingData.RefTime, + RefEdge => RefEdge, + TestTime => TimingData.TestTimeA(i), + TestEvent => TestEvent(i), + SetupEn => TimingData.SetupEnA(i), + HoldEn => TimingData.HoldEnA(i), + CheckInfo => CheckInfo, + MsgOn => MsgOn ); + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF (MsgOn) THEN + IF ( ChangedAllAtOnce AND (i = TestSignal'LEFT) ) THEN + ReportViolation (TestSignalName&"(...)", RefSignalName, + HeaderMsg, CheckInfo, MsgSeverity ); + ELSIF (NOT ChangedAllAtOnce) THEN + Write (StrPtr1, i); + ReportViolation (TestSignalName & "(" & StrPtr1.ALL & ")", + RefSignalName, + HeaderMsg, CheckInfo, MsgSeverity ); + DEALLOCATE (StrPtr1); + END IF; + END IF; + IF (XOn) THEN + Violation := 'X'; + END IF; + END IF; + END LOOP; + END IF; + + DEALLOCATE (StrPtr1); + + END VitalSetupHoldCheck; + + --------------------------------------------------------------------------- + -- Function : VitalRecoveryRemovalCheck + --------------------------------------------------------------------------- + PROCEDURE VitalRecoveryRemovalCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT Recovery : IN TIME := 0 ns; + CONSTANT Removal : IN TIME := 0 ns; + CONSTANT ActiveLow : IN BOOLEAN := TRUE; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableRecOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRecOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRemOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRemOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + ) IS + VARIABLE CheckInfo : CheckInfoType; + VARIABLE RefEdge, TestEvent : BOOLEAN; + VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay); + VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay); + VARIABLE bias : TIME; + BEGIN + + IF (TimingData.NotFirstFlag = FALSE) THEN + TimingData.TestLast := To_X01(TestSignal); + TimingData.RefLast := To_X01(RefSignal); + TimingData.NotFirstFlag := TRUE; + END IF; + + -- Detect reference edges and record the time of the last edge + RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal), + RefTransition); + TimingData.RefLast := To_X01(RefSignal); + IF RefEdge THEN + TimingData.RefTime := NOW; + TimingData.SetupEn := TimingData.SetupEn AND EnableRecOnRef; --IR252 3/23/98 + TimingData.HoldEn := EnableRemOnRef; --IR252 3/23/98 + END IF; + + -- Detect test (data) changes and record the time of the last change + TestEvent := TimingData.TestLast /= To_X01Z(TestSignal); + TimingData.TestLast := To_X01Z(TestSignal); + IF TestEvent THEN + TimingData.TestTime := NOW; + TimingData.SetupEn := EnableRecOnTest; --IR252 3/23/98 + TimingData.HoldEn := TimingData.HoldEn AND EnableRemOnTest; --IR252 3/23/98 + END IF; + + -- Perform timing checks (if enabled) + Violation := '0'; + IF (CheckEnabled) THEN + + IF ActiveLow THEN + InternalTimingCheck ( + TestSignal, RefSignal, TestDly, RefDly, + Recovery, 0 ns, 0 ns, Removal, + TimingData.RefTime, RefEdge, + TimingData.TestTime, TestEvent, + TimingData.SetupEn, TimingData.HoldEn, + CheckInfo, MsgOn ); + ELSE + InternalTimingCheck ( + TestSignal, RefSignal, TestDly, RefDly, + 0 ns, Recovery, Removal, 0 ns, + TimingData.RefTime, RefEdge, + TimingData.TestTime, TestEvent, + TimingData.SetupEn, TimingData.HoldEn, + CheckInfo, MsgOn ); + END IF; + + + -- Report any detected violations and set return violation flag + IF CheckInfo.Violation THEN + IF CheckInfo.CheckKind = SetupCheck THEN + CheckInfo.CheckKind := RecoveryCheck; + ELSE + CheckInfo.CheckKind := RemovalCheck; + END IF; + IF (MsgOn) THEN + ReportViolation (TestSignalName, RefSignalName, + HeaderMsg, CheckInfo, MsgSeverity ); + END IF; + IF (XOn) THEN Violation := 'X'; END IF; + END IF; + END IF; + + END VitalRecoveryRemovalCheck; + + --------------------------------------------------------------------------- + PROCEDURE VitalPeriodPulseCheck ( + VARIABLE Violation : OUT X01; + VARIABLE PeriodData : INOUT VitalPeriodDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + CONSTANT Period : IN TIME := 0 ns; + CONSTANT PulseWidthHigh : IN TIME := 0 ns; + CONSTANT PulseWidthLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ) IS + + VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay); + VARIABLE CheckInfo : CheckInfoType; + VARIABLE PeriodObs : TIME; + VARIABLE PulseTest, PeriodTest : BOOLEAN; + VARIABLE TestValue : X01 := To_X01(TestSignal); + BEGIN + + IF (PeriodData.NotFirstFlag = FALSE) THEN + PeriodData.Rise := + -maximum(Period, maximum(PulseWidthHigh, PulseWidthLow)); + PeriodData.Fall := + -maximum(Period, maximum(PulseWidthHigh, PulseWidthLow)); + PeriodData.Last := To_X01(TestSignal); + PeriodData.NotFirstFlag := TRUE; + END IF; + + -- Initialize for no violation + -- No violation possible if no test signal change + Violation := '0'; + IF (PeriodData.Last = TestValue) THEN + RETURN; + END IF; + + -- record starting pulse times + IF EdgeSymbolMatch(PeriodData.Last, TestValue, 'P') THEN + -- Compute period times, then record the High Rise Time + PeriodObs := NOW - PeriodData.Rise; + PeriodData.Rise := NOW; + PeriodTest := TRUE; + ELSIF EdgeSymbolMatch(PeriodData.Last, TestValue, 'N') THEN + -- Compute period times, then record the Low Fall Time + PeriodObs := NOW - PeriodData.Fall; + PeriodData.Fall := NOW; + PeriodTest := TRUE; + ELSE + PeriodTest := FALSE; + END IF; + + -- do checks on pulse ends + IF EdgeSymbolMatch(PeriodData.Last, TestValue, 'p') THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData.Fall; + CheckInfo.ExpTime := PulseWidthLow; + PulseTest := TRUE; + ELSIF EdgeSymbolMatch(PeriodData.Last, TestValue, 'n') THEN + -- Compute pulse times + CheckInfo.ObsTime := NOW - PeriodData.Rise; + CheckInfo.ExpTime := PulseWidthHigh; + PulseTest := TRUE; + ELSE + PulseTest := FALSE; + END IF; + + IF PulseTest AND CheckEnabled THEN + -- Verify Pulse Width [ignore 1st edge] + IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN + IF (XOn) THEN Violation := 'X'; END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PulseWidCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := PeriodData.Last; + ReportViolation (TestSignalName, "", + HeaderMsg, CheckInfo, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + IF PeriodTest AND CheckEnabled THEN + -- Verify the Period [ignore 1st edge] + CheckInfo.ObsTime := PeriodObs; + CheckInfo.ExpTime := Period; + IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN + IF (XOn) THEN Violation := 'X'; END IF; + IF (MsgOn) THEN + CheckInfo.Violation := TRUE; + CheckInfo.CheckKind := PeriodCheck; + CheckInfo.DetTime := NOW - TestDly; + CheckInfo.State := TestValue; + ReportViolation (TestSignalName, "", + HeaderMsg, CheckInfo, MsgSeverity ); + END IF; -- MsgOn + END IF; + END IF; + + PeriodData.Last := TestValue; + + END VitalPeriodPulseCheck; + + + + PROCEDURE ReportSkewViolation ( + CONSTANT Signal1Name : IN STRING := ""; + CONSTANT Signal2Name : IN STRING := ""; + CONSTANT ExpectedTime : IN TIME; + CONSTANT OccuranceTime : IN TIME; + CONSTANT HeaderMsg : IN STRING; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT SkewPhase : IN SkewType; + CONSTANT ViolationFlag : IN BOOLEAN := TRUE + ) IS + VARIABLE Message : LINE; + BEGIN + Write ( Message, HeaderMsg ); + IF (ViolationFlag /= TRUE) THEN + Write ( Message, STRING'(" POSSIBLE") ); + END IF; + IF (SkewPhase = Inphase) THEN + Write ( Message, STRING'(" IN PHASE ") ); + ELSE + Write ( Message, STRING'(" OUT OF PHASE ") ); + END IF; + Write ( Message, STRING'("SKEW VIOLATION ON ") ); + Write ( Message, Signal2Name ); + IF (Signal1Name'LENGTH > 0) THEN + Write ( Message, STRING'(" WITH RESPECT TO ") ); + Write ( Message, Signal1Name ); + END IF; + Write ( Message, ';' & LF ); + Write ( Message, STRING'(" At : ") ); + Write ( Message, OccuranceTime); + Write ( Message, STRING'("; Skew Limit : ") ); + Write ( Message, ExpectedTime); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END ReportSkewViolation; + + + PROCEDURE VitalInPhaseSkewCheck ( + VARIABLE Violation : OUT X01; + VARIABLE SkewData : INOUT VitalSkewDataType; + SIGNAL Signal1 : IN std_ulogic; + CONSTANT Signal1Name : IN STRING := ""; + CONSTANT Signal1Delay : IN TIME := 0 ns; + SIGNAL Signal2 : IN std_ulogic; + CONSTANT Signal2Name : IN STRING := ""; + CONSTANT Signal2Delay : IN TIME := 0 ns; + CONSTANT SkewS1S2RiseRise : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1RiseRise : IN TIME := TIME'HIGH; + CONSTANT SkewS1S2FallFall : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1FallFall : IN TIME := TIME'HIGH; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT HeaderMsg : IN STRING := ""; + SIGNAL Trigger : INOUT std_ulogic + ) IS + VARIABLE ReportType : VitalSkewExpectedType := none; + VARIABLE ExpectedType : VitalSkewExpectedType := none; + VARIABLE ReportTime : TIME; + VARIABLE TriggerDelay : TIME; + VARIABLE ViolationCertain : Boolean := TRUE; + BEGIN + Violation := '0'; + ReportType := none; + TriggerDelay := noTrigger; + + IF (CheckEnabled) THEN + IF (SkewData.ExpectedType /= none) THEN + IF (trigger'Event) THEN + CASE SkewData.ExpectedType IS + WHEN s1r => ReportType := s1r; + ReportTime := NOW - Signal1Delay; + WHEN s1f => ReportType := s1f; + ReportTime := NOW - Signal1Delay; + WHEN s2r => ReportType := s2r; + ReportTime := NOW - Signal2Delay; + WHEN s2f => ReportType := s2f; + ReportTime := NOW - Signal2Delay; + WHEN OTHERS => + END CASE; + SkewData.ExpectedType := none; + ELSIF ( Signal1'Event OR Signal2'Event ) THEN + IF ( Signal1 /= 'X' AND Signal2 /= 'X' ) THEN + TriggerDelay := 0 ns; + ExpectedType := none; + END IF; + END IF; + END IF; + + IF (Signal1'EVENT and Signal2'EVENT) THEN + IF (Signal1 = Signal2) THEN + IF (Posedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - Signal2Delay) >= + SkewS1S2RiseRise) THEN + ReportType := s2r; + ReportTime := NOW - Signal1Delay + + SkewS1S2RiseRise; + ELSIF ((Signal2Delay -Signal1Delay) >= + SkewS2S1RiseRise) THEN + ReportType := s1r; + ReportTime := NOW - Signal2Delay + + SkewS2S1RiseRise; + END IF; + ELSIF (Negedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - Signal2Delay) >= + SkewS1S2FallFall) THEN + ReportType := s2f; + ReportTime := NOW - Signal1Delay + + SkewS1S2FallFall; + ELSIF ((Signal2Delay - Signal1Delay) >= + SkewS2S1FallFall) THEN + ReportType := s1f; + ReportTime := NOW - Signal2Delay + + SkewS2S1FallFall; + END IF; + END IF; + ELSIF (Posedge(Signal1'LAST_VALUE , Signal1)) THEN + IF ((Signal1Delay >= Signal2Delay) and (Signal2Delay > + SkewS2S1FallFall)) THEN + ReportType := s1f; + ReportTime := NOW - Signal2Delay + + SkewS2S1FallFall; + ELSIF ((Signal2Delay >= Signal1Delay) and (Signal1Delay > + SkewS1S2RiseRise)) THEN + ReportType := s2r; + ReportTime := NOW - Signal1Delay + + SkewS1S2RiseRise; + ELSIF (Signal2Delay > Signal1Delay) THEN + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2RiseRise + + Signal2Delay - Signal1Delay; + ELSIF (Signal1Delay > Signal2Delay) THEN + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1RiseRise + + Signal1Delay - Signal2Delay; + ELSIF (SkewS1S2RiseRise < SkewS2S1RiseRise) THEN + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2RiseRise; + ELSE + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1RiseRise; + END IF; + ELSIF (Negedge(Signal1'LAST_VALUE , Signal1)) THEN + IF ((Signal1Delay >= Signal2Delay) and (Signal2Delay > + SkewS2S1RiseRise)) THEN + ReportType := s1r; + ReportTime := NOW - Signal2Delay + + SkewS2S1RiseRise; + ELSIF ((Signal2Delay >= Signal1Delay) and (Signal1Delay > + SkewS1S2FallFall)) THEN + ReportType := s2f; + ReportTime := NOW - Signal1Delay + + SkewS1S2FallFall; + ELSIF (Signal2Delay > Signal1Delay) THEN + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2FallFall + + Signal2Delay - Signal1Delay; + ELSIF (Signal1Delay > Signal2Delay) THEN + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1FallFall + + Signal1Delay - Signal2Delay; + ELSIF (SkewS1S2FallFall < SkewS2S1FallFall) THEN + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2FallFall; + ELSE + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1FallFall; + END IF; + END IF; + ELSIF (Signal1'EVENT) THEN + IF ( Signal1 /= Signal2) THEN + IF ( Posedge( Signal1'LAST_VALUE, Signal1)) THEN + IF (SkewS1S2RiseRise > (Signal1Delay - + Signal2Delay)) THEN + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2RiseRise + + Signal2Delay - + Signal1Delay; + ELSE + ReportType := s2r; + ReportTime := NOW + SkewS1S2RiseRise - + Signal1Delay; + END IF; + ELSIF ( Negedge( Signal1'LAST_VALUE, Signal1)) THEN + IF (SkewS1S2FallFall > (Signal1Delay - + Signal2Delay)) THEN + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2FallFall + + Signal2Delay - + Signal1Delay; + ELSE + ReportType := s2f; + ReportTime := NOW + SkewS1S2FallFall - + Signal1Delay; + END IF; + END IF; + ELSE + IF ( Posedge( Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - SkewS1S2RiseRise) > + (Signal2'LAST_EVENT + Signal2Delay)) THEN + IF ((SkewData.Signal2Old2 - Signal2Delay) > + (NOW - Signal1Delay + + SkewS1S2RiseRise)) THEN + ViolationCertain := FALSE; + ReportType := s2r; + ReportTime := NOW + SkewS1S2RiseRise - + Signal1Delay; + END IF; + END IF; + ELSIF ( Negedge( Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - SkewS1S2FallFall) > + (Signal2'LAST_EVENT + Signal2Delay)) THEN + IF (( SkewData.Signal2Old2 - Signal2Delay) > + (NOW - Signal1Delay + + SkewS1S2FallFall )) THEN + ViolationCertain := FALSE; + ReportType := s2f; + ReportTime := NOW + SkewS1S2FallFall - + Signal1Delay; + END IF; + END IF; + END IF; + END IF; + ELSIF (Signal2'EVENT) THEN + IF (Signal1 /= Signal2) THEN + IF (Posedge(Signal2'LAST_VALUE,Signal2)) THEN + IF ( SkewS2S1RiseRise > (Signal2Delay - + Signal1Delay)) THEN + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1RiseRise + + Signal1Delay - + Signal2Delay; + ELSE + ReportType := s2r; + ReportTime := NOW + SkewS2S1RiseRise - + Signal2Delay; + END IF; + ELSIF (Negedge(Signal2'LAST_VALUE,Signal2)) THEN + IF ( SkewS2S1FallFall > (Signal2Delay - + Signal1Delay)) THEN + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1FallFall + + Signal1Delay - + Signal2Delay; + ELSE + ReportType := s1f; + ReportTime := NOW + SkewS2S1FallFall - + Signal2Delay; + END IF; + END IF; + ELSE + IF (Posedge(Signal2'LAST_VALUE, Signal2)) THEN + IF ((Signal2Delay - SkewS2S1RiseRise) > + (Signal1'LAST_EVENT + Signal1Delay)) THEN + IF (( SkewData.Signal1Old2 - Signal1Delay) > + (NOW - Signal2Delay + + SkewS2S1RiseRise )) THEN + ViolationCertain := FALSE; + ReportType := s1r; + ReportTime := NOW + SkewS2S1RiseRise - + Signal2Delay; + END IF; + END IF; + ELSIF (Negedge(Signal2'LAST_VALUE, Signal2)) THEN + IF ((Signal2Delay - SkewS2S1FallFall) > + (Signal1'LAST_EVENT + Signal1Delay)) THEN + IF (( SkewData.Signal1Old2 - Signal1Delay) > + (NOW - Signal2Delay + + SkewS2S1FallFall )) THEN + ViolationCertain := FALSE; + ReportType := s1f; + ReportTime := NOW + SkewS2S1FallFall - + Signal2Delay; + END IF; + END IF; + END IF; + END IF; + END IF; + + IF (ReportType /= none) THEN + IF (MsgOn) THEN + CASE ReportType IS + WHEN s1r => + ReportSkewViolation( + Signal2Name, + Signal1Name, + SkewS2S1RiseRise, + ReportTime, + HeaderMsg, + MsgSeverity, + Inphase, + ViolationCertain); + WHEN s1f => + ReportSkewViolation( + Signal2Name, + Signal1Name, + SkewS2S1FallFall, + ReportTime, + HeaderMsg, + MsgSeverity, + Inphase, + ViolationCertain); + WHEN s2r => + ReportSkewViolation( + Signal1Name, + Signal2Name, + SkewS1S2RiseRise, + ReportTime, + HeaderMsg, + MsgSeverity, + Inphase, + ViolationCertain); + WHEN s2f => + ReportSkewViolation( + Signal1Name, + Signal2Name, + SkewS1S2FallFall, + ReportTime, + HeaderMsg, + MsgSeverity, + Inphase, + ViolationCertain); + WHEN OTHERS => + END CASE; + END IF; + IF (XOn) THEN + Violation := 'X'; + END IF; + SkewData.ExpectedType := none; + END IF; + IF (TriggerDelay /= noTrigger) THEN + IF (TriggerDelay = 0 ns) THEN + trigger <= TRANSPORT trigger AFTER 0 ns; + ELSE + trigger <= TRANSPORT not (trigger) AFTER + TriggerDelay; + END IF; + END IF; + END IF; + IF (Signal1'EVENT and SkewData.Signal1Old1 /= NOW) THEN + SkewData.Signal1Old2 := SkewData.Signal1Old1; + SkewData.Signal1Old1 := NOW; + END IF; + IF (Signal2'EVENT and SkewData.Signal2Old1 /= NOW) THEN + SkewData.Signal2Old2 := SkewData.Signal2Old1; + SkewData.Signal2Old1 := NOW; + END IF; + END VitalInPhaseSkewCheck; + + PROCEDURE VitalOutPhaseSkewCheck ( + VARIABLE Violation : OUT X01; + VARIABLE SkewData : INOUT VitalSkewDataType; + SIGNAL Signal1 : IN std_ulogic; + CONSTANT Signal1Name : IN STRING := ""; + CONSTANT Signal1Delay : IN TIME := 0 ns; + SIGNAL Signal2 : IN std_ulogic; + CONSTANT Signal2Name : IN STRING := ""; + CONSTANT Signal2Delay : IN TIME := 0 ns; + CONSTANT SkewS1S2RiseFall : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1RiseFall : IN TIME := TIME'HIGH; + CONSTANT SkewS1S2FallRise : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1FallRise : IN TIME := TIME'HIGH; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT HeaderMsg : IN STRING := ""; + SIGNAL Trigger : INOUT std_ulogic + ) IS + VARIABLE ReportType : VitalSkewExpectedType := none; + VARIABLE ExpectedType : VitalSkewExpectedType := none; + VARIABLE ReportTime : TIME; + VARIABLE TriggerDelay : TIME; + VARIABLE ViolationCertain : Boolean := TRUE; + BEGIN + Violation := '0'; + TriggerDelay := noTrigger; + IF (CheckEnabled) THEN + IF (SkewData.ExpectedType /= none) THEN + IF (trigger'Event) THEN + CASE SkewData.ExpectedType IS + WHEN s1r => ReportType := s1r; + ReportTime := NOW - Signal1Delay; + WHEN s1f => ReportType := s1f; + ReportTime := NOW - Signal1Delay; + WHEN s2r => ReportType := s2r; + ReportTime := NOW - Signal2Delay; + WHEN s2f => ReportType := s2f; + ReportTime := NOW - Signal2Delay; + WHEN OTHERS => + END CASE; + SkewData.ExpectedType := none; + ELSIF (Signal1'Event OR Signal2'Event ) THEN + IF (Signal1 /= 'X' AND Signal2 /= 'X' ) THEN + TriggerDelay := 0 ns; + SkewData.ExpectedType := none; + END IF; + END IF; + END IF; + + IF (Signal1'EVENT and Signal2'EVENT) THEN + IF (Signal1 /= Signal2) THEN + IF (Posedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - Signal2Delay) >= + SkewS1S2RiseFall) THEN + ReportType := s2f; + ReportTime := NOW - Signal1Delay + + SkewS1S2RiseFall; + ELSIF ((Signal2Delay - Signal1Delay) >= + SkewS2S1FallRise) THEN + ReportType := s1r; + ReportTime := NOW - Signal2Delay + + SkewS2S1FallRise; + END IF; + ELSIF (Negedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - Signal2Delay) >= + SkewS1S2FallRise) THEN + ReportType := s2r; + ReportTime := NOW - Signal1Delay + + SkewS1S2FallRise; + ELSIF ((Signal2Delay - Signal1Delay) >= + SkewS2S1RiseFall) THEN + ReportType := s1f; + ReportTime := NOW - Signal2Delay + + SkewS2S1RiseFall; + END IF; + END IF; + ELSIF (Posedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay >= Signal2Delay) and (Signal2Delay > + SkewS2S1RiseFall)) THEN + ReportType := s1f; + ReportTime := NOW - Signal2Delay + + SkewS2S1RiseFall; + ELSIF ((Signal2Delay >= Signal1Delay) and (Signal1Delay > + SkewS1S2RiseFall)) THEN + ReportType := s2f; + ReportTime := NOW - Signal1Delay + + SkewS1S2RiseFall; + ELSIF (Signal1Delay > Signal2Delay) THEN + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1RiseFall + + Signal1Delay - Signal2Delay; + ELSIF (Signal2Delay > Signal1Delay) THEN + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2RiseFall + + Signal2Delay - Signal1Delay; + ELSIF (SkewS2S1RiseFall < SkewS1S2RiseFall) THEN + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1RiseFall; + ELSE + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2RiseFall; + END IF; + ELSIF (Negedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay >= Signal2Delay) and (Signal2Delay > + SkewS2S1FallRise)) THEN + ReportType := s1r; + ReportTime := NOW - Signal2Delay + + SkewS2S1FallRise; + ELSIF ((Signal2Delay >= Signal1Delay) and (Signal1Delay > + SkewS1S2FallRise)) THEN + ReportType := s2r; + ReportTime := NOW - Signal1Delay + + SkewS1S2FallRise; + ELSIF (Signal1Delay > Signal2Delay) THEN + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1FallRise + + Signal1Delay - Signal2Delay; + ELSIF (Signal2Delay > Signal1Delay) THEN + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2FallRise + + Signal2Delay - Signal1Delay; + ELSIF (SkewS2S1FallRise < SkewS1S2FallRise) THEN + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1FallRise; + ELSE + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2FallRise; + END IF; + END IF; + ELSIF (Signal1'EVENT) THEN + IF (Signal1 = Signal2) THEN + IF (Posedge(Signal1'LAST_VALUE,Signal1)) THEN + IF (SkewS1S2RiseFall > (Signal1Delay - + Signal2Delay)) THEN + SkewData.ExpectedType := s2f; + TriggerDelay := SkewS1S2RiseFall + + Signal2Delay - Signal1Delay; + ELSE + ReportType := s2f; + ReportTime := NOW - Signal1Delay + + SkewS1S2RiseFall; + END IF; + ELSIF ( Negedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ( SkewS1S2FallRise > (Signal1Delay - + Signal2Delay)) THEN + SkewData.ExpectedType := s2r; + TriggerDelay := SkewS1S2FallRise + + Signal2Delay - Signal1Delay; + ELSE + ReportType := s2r; + ReportTime := NOW - Signal1Delay + + SkewS1S2FallRise; + END IF; + END IF; + ELSE + IF (Posedge( Signal1'LAST_VALUE, Signal1 )) THEN + IF ((Signal1Delay - SkewS1S2RiseFall) > + (Signal2'LAST_EVENT + Signal2Delay)) THEN + IF (( SkewData.Signal2Old2 - Signal2Delay) > + (NOW - Signal1Delay + + SkewS1S2RiseFall )) THEN + ViolationCertain := FALSE; + ReportType := s2f; + ReportTime := NOW + SkewS1S2RiseFall - + Signal1Delay; + END IF; + END IF; + ELSIF (Negedge(Signal1'LAST_VALUE, Signal1)) THEN + IF ((Signal1Delay - SkewS1S2FallRise) > + (Signal2'LAST_EVENT + Signal2Delay)) THEN + IF (( SkewData.Signal2Old2 - Signal2Delay) > + (NOW - Signal1Delay + + SkewS1S2FallRise )) THEN + ViolationCertain := FALSE; + ReportType := s2r; + ReportTime := NOW + SkewS1S2FallRise - + Signal1Delay; + END IF; + END IF; + END IF; + END IF; + ELSIF (Signal2'EVENT) THEN + IF (Signal1 = Signal2) THEN + IF (Posedge(Signal2'LAST_VALUE,Signal2)) THEN + IF (SkewS2S1RiseFall > (Signal2Delay - + Signal1Delay)) THEN + SkewData.ExpectedType := s1f; + TriggerDelay := SkewS2S1RiseFall + Signal1Delay - + Signal2Delay ; + ELSE + ReportType := s1f; + ReportTime := NOW + SkewS2S1RiseFall - + Signal2Delay; + END IF; + ELSIF (Negedge(Signal2'LAST_VALUE,Signal2)) THEN + IF (SkewS2S1FallRise > (Signal2Delay - + Signal1Delay)) THEN + SkewData.ExpectedType := s1r; + TriggerDelay := SkewS2S1FallRise + Signal1Delay - + Signal2Delay; + ELSE + ReportType := s1r; + ReportTime := NOW + SkewS2S1FallRise - + Signal2Delay; + END IF; + END IF; + ELSE + IF (Posedge(Signal2'LAST_VALUE,Signal2)) THEN + IF ((Signal2Delay - SkewS2S1RiseFall) > + (Signal1'LAST_EVENT + Signal1Delay)) THEN + IF (( SkewData.Signal1Old2 - Signal1Delay) > + (NOW - Signal2Delay + + SkewS2S1RiseFall )) THEN + ViolationCertain := FALSE; + ReportType := s1f; + ReportTime := NOW + SkewS2S1RiseFall - + Signal2Delay; + END IF; + END IF; + ELSIF (Negedge(Signal2'LAST_VALUE,Signal2)) THEN + IF ((Signal2Delay - SkewS2S1FallRise) > + (Signal1'LAST_EVENT + Signal1Delay)) THEN + IF (( SkewData.Signal1Old2 - Signal1Delay) > + (NOW - Signal2Delay + + SkewS2S1FallRise )) THEN + ViolationCertain := FALSE; + ReportType := s1r; + ReportTime := NOW + SkewS2S1FallRise - + Signal2Delay; + END IF; + END IF; + END IF; + END IF; + END IF; + + IF (ReportType /= none) THEN + IF (MsgOn) THEN + CASE ReportType IS + WHEN s1r => + ReportSkewViolation( + Signal2Name, + Signal1Name, + SkewS2S1FallRise, + ReportTime, + HeaderMsg, + MsgSeverity, + Outphase, + ViolationCertain); + WHEN s1f => + ReportSkewViolation( + Signal2Name, + Signal1Name, + SkewS2S1RiseFall, + ReportTime, + HeaderMsg, + MsgSeverity, + Outphase, + ViolationCertain); + WHEN s2r => + ReportSkewViolation( + Signal1Name, + Signal2Name, + SkewS1S2FallRise, + ReportTime, + HeaderMsg, + MsgSeverity, + Outphase, + ViolationCertain); + WHEN s2f => + ReportSkewViolation( + Signal1Name, + Signal2Name, + SkewS1S2RiseFall, + ReportTime, + HeaderMsg, + MsgSeverity, + Outphase, + ViolationCertain); + WHEN OTHERS => + END CASE; + END IF; + IF (XOn) THEN + Violation := 'X'; + END IF; + ReportType := none; + END IF; + IF (TriggerDelay /= noTrigger) THEN + IF (TriggerDelay = 0 ns) THEN + trigger <= TRANSPORT trigger AFTER 0 ns; + ELSE + trigger <= TRANSPORT not (trigger) AFTER + TriggerDelay; + END IF; + END IF; + END IF; + IF (Signal1'EVENT and SkewData.Signal1Old1 /= NOW) THEN + SkewData.Signal1Old2 := SkewData.Signal1Old1; + SkewData.Signal1Old1 := NOW; + END IF; + IF (Signal2'EVENT and SkewData.Signal2Old1 /= NOW) THEN + SkewData.Signal2Old2 := SkewData.Signal2Old1; + SkewData.Signal2Old1 := NOW; + END IF; + END VitalOutPhaseSkewCheck; + +END VITAL_Timing; diff --git a/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_p.vhdl b/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_p.vhdl new file mode 100644 index 0000000..bbeb66f --- /dev/null +++ b/resources/dide-lsp/static/vhdl_std_lib/vital2000/timing_p.vhdl @@ -0,0 +1,1202 @@ +------------------------------------------------------------------------------- +-- Title : Standard VITAL TIMING Package +-- : $Revision$ +-- : +-- Library : This package shall be compiled into a library +-- : symbolically named IEEE. +-- : +-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4 +-- : +-- Purpose : This packages defines standard types, attributes, constants, +-- : functions and procedures for use in developing ASIC models. +-- : +-- Known Errors : +-- : +-- Note : No declarations or definitions shall be included in, +-- : or excluded from this package. The "package declaration" +-- : defines the objects (types, subtypes, constants, functions, +-- : procedures ... etc.) that can be used by a user. The package +-- : body shall be considered the formal definition of the +-- : semantics of this package. Tool developers may choose to +-- : implement the package body in the most efficient manner +-- : available to them. +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Acknowledgments: +-- This code was originally developed under the "VHDL Initiative Toward ASIC +-- Libraries" (VITAL), an industry sponsored initiative. Technical +-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator: +-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design +-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek, +-- Texas Instruments; Victor Martin, Hewlett-Packard Company. +-- ---------------------------------------------------------------------------- +-- +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No:|Auth:| Mod.Date:| Changes Made: +-- v95.0 A | | 06/02/95 | Initial ballot draft 1995 +-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0 +-- #204 - Output mapping prior to glitch detection +-- v98.0 |TAG | 03/27/98 | Initial ballot draft 1998 +-- | #IR225 - Negative Premptive Glitch +-- **Pkg_effected=VitalPathDelay, +-- VitalPathDelay01,VitalPathDelay01z. +-- #IR105 - Skew timing check needed +-- **Pkg_effected=NONE, New code added!! +-- #IR248 - Allows VPD to use a default timing +-- delay +-- **Pkg_effected=VitalPathDelay, +-- VitalPathDelay01,VitalPathDelay01z, +-- #IR250 - Corrects fastpath condition in VPD +-- **Pkg_effected=VitalPathDelay01, +-- VitalPathDelay01z, +-- #IR252 - Corrects cancelled timing check call if +-- condition expires. +-- **Pkg_effected=VitalSetupHoldCheck, +-- VitalRecoveryRemovalCheck. +-- #IR105 - Skew timing check +-- **Pkg_effected=NONE, New code added +-- v98.1 | jdc | 03/25/99 | Changed UseDefaultDelay to IgnoreDefaultDelay +-- and set default to FALSE in VitalPathDelay() +-- v00.7 | dbb | 07/18/00 | Removed "maximum" from VitalPeriodPulse() +-- comments + + +LIBRARY IEEE; +USE IEEE.Std_Logic_1164.ALL; + +PACKAGE VITAL_Timing IS + TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0, + tr0X, trx1, tr1x, trx0, trxz, trzx); + + SUBTYPE VitalDelayType IS TIME; + TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10) + OF TIME; + TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0) + OF TIME; + TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx) + OF TIME; + + TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType; + TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01; + TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z; + TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX; + -- ---------------------------------------------------------------------- + -- ********************************************************************** + -- ---------------------------------------------------------------------- + + CONSTANT VitalZeroDelay : VitalDelayType := 0 ns; + CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns ); + CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns ); + CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns ); + + --------------------------------------------------------------------------- + -- examples of usage: + --------------------------------------------------------------------------- + -- tpd_CLK_Q : VitalDelayType := 5 ns; + -- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns); + -- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ); + -- tpd_CLK_Q : VitalDelayArrayType(0 to 1) + -- := (0 => 5 ns, 1 => 6 ns); + -- tpd_CLK_Q : VitalDelayArrayType01(0 to 1) + -- := (0 => (tr01 => 2 ns, tr10 => 3 ns), + -- 1 => (tr01 => 2 ns, tr10 => 3 ns)); + -- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1) + -- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ), + -- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns )); + --------------------------------------------------------------------------- + + -- TRUE if the model is LEVEL0 | LEVEL1 compliant + ATTRIBUTE VITAL_Level0 : BOOLEAN; + ATTRIBUTE VITAL_Level1 : BOOLEAN; + + SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0); + SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0); + SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0); + SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0); + + -- Types for strength mapping of outputs + TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic; + TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic; + TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic; + CONSTANT VitalDefaultOutputMap : VitalOutputMapType + := "UX01ZWLH-"; + CONSTANT VitalDefaultResultMap : VitalResultMapType + := ( 'U', 'X', '0', '1' ); + CONSTANT VitalDefaultResultZMap : VitalResultZMapType + := ( 'U', 'X', '0', '1', 'Z' ); + + -- Types for fields of VitalTimingDataType + TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME; + TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT; + TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN; + TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT; + TYPE VitalLogicArrayPT IS ACCESS std_logic_vector; + + TYPE VitalTimingDataType IS RECORD + NotFirstFlag : BOOLEAN; + RefLast : X01; + RefTime : TIME; + HoldEn : BOOLEAN; + TestLast : std_ulogic; + TestTime : TIME; + SetupEn : BOOLEAN; + TestLastA : VitalLogicArrayPT; + TestTimeA : VitalTimeArrayPT; + HoldEnA : VitalBoolArrayPT; + SetupEnA : VitalBoolArrayPT; + END RECORD; + + FUNCTION VitalTimingDataInit RETURN VitalTimingDataType; + + -- type for internal data of VitalPeriodPulseCheck + TYPE VitalPeriodDataType IS RECORD + Last : X01; + Rise : TIME; + Fall : TIME; + NotFirstFlag : BOOLEAN; + END RECORD; + CONSTANT VitalPeriodDataInit : VitalPeriodDataType + := ('X', 0 ns, 0 ns, FALSE ); + + -- Type for specifying the kind of Glitch handling to use + TYPE VitalGlitchKindType IS (OnEvent, + OnDetect, + VitalInertial, + VitalTransport); + + TYPE VitalGlitchDataType IS + RECORD + SchedTime : TIME; + GlitchTime : TIME; + SchedValue : std_ulogic; + LastValue : std_ulogic; + END RECORD; + TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>) + OF VitalGlitchDataType; + + -- PathTypes: for handling simple PathDelay info + TYPE VitalPathType IS RECORD + InputChangeTime : TIME; -- timestamp for path input signal + PathDelay : VitalDelayType; -- delay for this path + PathCondition : BOOLEAN; -- path sensitize condition + END RECORD; + TYPE VitalPath01Type IS RECORD + InputChangeTime : TIME; -- timestamp for path input signal + PathDelay : VitalDelayType01; -- delay for this path + PathCondition : BOOLEAN; -- path sensitize condition + END RECORD; + TYPE VitalPath01ZType IS RECORD + InputChangeTime : TIME; -- timestamp for path input signal + PathDelay : VitalDelayType01Z;-- delay for this path + PathCondition : BOOLEAN; -- path sensitize condition + END RECORD; + + -- For representing multiple paths to an output + TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType; + TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type; + TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType; + + TYPE VitalTableSymbolType IS ( + '/', -- 0 -> 1 + '\', -- 1 -> 0 + 'P', -- Union of '/' and '^' (any edge to 1) + 'N', -- Union of '\' and 'v' (any edge to 0) + 'r', -- 0 -> X + 'f', -- 1 -> X + 'p', -- Union of '/' and 'r' (any edge from 0) + 'n', -- Union of '\' and 'f' (any edge from 1) + 'R', -- Union of '^' and 'p' (any possible rising edge) + 'F', -- Union of 'v' and 'n' (any possible falling edge) + '^', -- X -> 1 + 'v', -- X -> 0 + 'E', -- Union of 'v' and '^' (any edge from X) + 'A', -- Union of 'r' and '^' (rising edge to or from 'X') + 'D', -- Union of 'f' and 'v' (falling edge to or from 'X') + '*', -- Union of 'R' and 'F' (any edge) + 'X', -- Unknown level + '0', -- low level + '1', -- high level + '-', -- don't care + 'B', -- 0 or 1 + 'Z', -- High Impedance + 'S' -- steady value + ); + + SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*'; + + + + + -- Addition of Vital Skew Type Information + -- March 14, 1998 + + --------------------------------------------------------------------------- + -- Procedures and Type Definitions for Defining Skews + --------------------------------------------------------------------------- + + TYPE VitalSkewExpectedType IS (none, s1r, s1f, s2r, s2f); + + TYPE VitalSkewDataType IS RECORD + ExpectedType : VitalSkewExpectedType; + Signal1Old1 : TIME; + Signal2Old1 : TIME; + Signal1Old2 : TIME; + Signal2Old2 : TIME; + END RECORD; + + CONSTANT VitalSkewDataInit : VitalSkewDataType := ( none, 0 ns, 0 ns, 0 ns, 0 ns ); + + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalExtendToFillDelay + -- + -- Description: A six element array of delay values of type + -- VitalDelayType01Z is returned when a 1, 2 or 6 + -- element array is given. This function will convert + -- VitalDelayType and VitalDelayType01 delay values into + -- a VitalDelayType01Z type following these rules: + -- + -- When a VitalDelayType is passed, all six transition + -- values are assigned the input value. When a + -- VitalDelayType01 is passed, the 01 transitions are + -- assigned to the 01, 0Z and Z1 transitions and the 10 + -- transitions are assigned to 10, 1Z and Z0 transition + -- values. When a VitalDelayType01Z is passed, the values + -- are kept as is. + -- + -- The function is overloaded based on input type. + -- + -- There is no function to fill a 12 value delay + -- type. + -- + -- Arguments: + -- + -- IN Type Description + -- Delay A one, two or six delay value Vital- + -- DelayType is passed and a six delay, + -- VitalDelayType01Z, item is returned. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- VitalDelayType01Z + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType + ) RETURN VitalDelayType01Z; + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType01 + ) RETURN VitalDelayType01Z; + FUNCTION VitalExtendToFillDelay ( + CONSTANT Delay : IN VitalDelayType01Z + ) RETURN VitalDelayType01Z; + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalCalcDelay + -- + -- Description: This function accepts a 1, 2 or 6 value delay and + -- chooses the correct delay time to delay the NewVal + -- signal. This function is overloaded based on the + -- delay type passed. The function returns a single value + -- of time. + -- + -- This function is provided for Level 0 models in order + -- to calculate the delay which should be applied + -- for the passed signal. The delay selection is performed + -- using the OldVal and the NewVal to determine the + -- transition to select. The default value of OldVal is X. + -- + -- This function cannot be used in a Level 1 model since + -- the VitalPathDelay routines perform the delay path + -- selection and output driving function. + -- + -- Arguments: + -- + -- IN Type Description + -- NewVal New value of the signal to be + -- assigned + -- OldVal Previous value of the signal. + -- Default value is 'X' + -- Delay The delay structure from which to + -- select the appropriate delay. The + -- function overload is based on the + -- type of delay passed. In the case of + -- the single delay, VitalDelayType, no + -- selection is performed, since there + -- is only one value to choose from. + -- For the other cases, the transition + -- from the old value to the new value + -- decide the value returned. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- Time The time value selected from the + -- Delay INPUT is returned. + -- + -- ------------------------------------------------------------------------- + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType + ) RETURN TIME; + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType01 + ) RETURN TIME; + FUNCTION VitalCalcDelay ( + CONSTANT NewVal : IN std_ulogic := 'X'; + CONSTANT OldVal : IN std_ulogic := 'X'; + CONSTANT Delay : IN VitalDelayType01Z + ) RETURN TIME; + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalPathDelay + -- + -- Description: VitalPathDelay is the Level 1 routine used to select + -- the propagation delay path and schedule a new output + -- value. + -- + -- For single and dual delay values, VitalDelayType and + -- VitalDelayType01 are used. The output value is + -- scheduled with a calculated delay without strength + -- modification. + -- + -- For the six delay value, VitalDelayType01Z, the output + -- value is scheduled with a calculated delay. The drive + -- strength can be modified to handle weak signal strengths + -- to model tri-state devices, pull-ups and pull-downs as + -- an example. + -- + -- The correspondence between the delay type and the + -- path delay function is as follows: + -- + -- Delay Type Path Type + -- + -- VitalDelayType VitalPathDelay + -- VitalDelayType01 VitalPathDelay01 + -- VitalDelayType01Z VitalPathDelay01Z + -- + -- For each of these routines, the following capabilities + -- is provided: + -- + -- o Transition dependent path delay selection + -- o User controlled glitch detection with the ability + -- to generate "X" on output and report the violation + -- o Control of the severity level for message generation + -- o Scheduling of the computed values on the specified + -- signal. + -- + -- Selection of the appropriate path delay begins with the + -- candidate paths. The candidate paths are selected by + -- identifying the paths for which the PathCondition is + -- true. If there is a single candidate path, then that + -- delay is selected. If there is more than one candidate + -- path, then the shortest delay is selected using + -- transition dependent delay selection. If there is no + -- candidate paths, then the delay specified by the + -- DefaultDelay parameter to the path delay is used. + -- + -- Once the delay is known, the output signal is then + -- scheduled with that delay. In the case of + -- VitalPathDelay01Z, an additional result mapping of + -- the output value is performed before scheduling. The + -- result mapping is performed after transition dependent + -- delay selection but before scheduling the final output. + -- + -- In order to perform glitch detection, the user is + -- obligated to provide a variable of VitalGlitchDataType + -- for the propagation delay functions to use. The user + -- cannot modify or use this information. + -- + -- Arguments: + -- + -- IN Type Description + -- OutSignalName string The name of the output signal + -- OutTemp std_logic The new output value to be driven + -- Paths VitalPathArrayType A list of paths of VitalPathArray + -- VitalPathArrayType01 type. The VitalPathDelay routine + -- VitalPathArrayType01Z is overloaded based on the type + -- of constant passed in. With + -- VitalPathArrayType01Z, the + -- resulting output strengths can be + -- mapped. + -- DefaultDelay VitalDelayType The default delay can be changed + -- VitalDelayType01 from zero-delay to another set + -- VitalDelayType01Z of values. + -- + -- IgnoreDefaultDelay BOOLEAN If TRUE, the default delay will + -- be used when no paths are + -- selected. If false, no event + -- will be scheduled if no paths are + -- selected. + -- + -- Mode VitalGlitchKindType The value of this constant + -- selects the type of glitch + -- detection. + -- OnEvent Glitch on transition event + -- | OnDetect Glitch immediate on detection + -- | VitalInertial No glitch, use INERTIAL + -- assignment + -- | VitalTransport No glitch, use TRANSPORT + -- assignment + -- XOn BOOLEAN Control for generation of 'X' on + -- glitch. When TRUE, 'X's are + -- scheduled for glitches, otherwise + -- no are generated. + -- MsgOn BOOLEAN Control for message generation on + -- glitch detect. When TRUE, + -- glitches are reported, otherwise + -- they are not reported. + -- MsgSeverity SEVERITY_LEVEL The level at which the message, + -- or assertion, will be reported. + -- IgnoreDefaultDelay BOOLEAN Tells the VPD whether to use the + -- default delay value in the absense + -- of a valid delay for input conditions 3/14/98 MG + -- + -- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output + -- can be mapped to alternate + -- strengths to model tri-state + -- devices, pull-ups and pull-downs. + -- + -- INOUT + -- GlitchData VitalGlitchDataType The internal data storage + -- variable required to detect + -- glitches. + -- + -- OUT + -- OutSignal std_logic The output signal to be driven + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalPathDelay ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArrayType; + CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE --IR248 3/14/98 + ); + PROCEDURE VitalPathDelay01 ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArray01Type; + CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98 + CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250 + ); + PROCEDURE VitalPathDelay01Z ( + SIGNAL OutSignal : OUT std_logic; + VARIABLE GlitchData : INOUT VitalGlitchDataType; + CONSTANT OutSignalName : IN string; + CONSTANT OutTemp : IN std_logic; + CONSTANT Paths : IN VitalPathArray01ZType; + CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z; + CONSTANT Mode : IN VitalGlitchKindType := OnEvent; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap; + CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98 + CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98 + CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250 + ); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalWireDelay + -- + -- Description: VitalWireDelay is used to delay an input signal. + -- The delay is selected from the input parameter passed. + -- The function is useful for back annotation of actual + -- net delays. + -- + -- The function is overloaded to permit passing a delay + -- value for twire for VitalDelayType, VitalDelayType01 + -- and VitalDelayType01Z. twire is a generic which can + -- be back annotated and must be constructed to follow + -- the SDF to generic mapping rules. + -- + -- Arguments: + -- + -- IN Type Description + -- InSig std_ulogic The input signal (port) to be + -- delayed. + -- twire VitalDelayType The delay value for which the input + -- VitalDelayType01 signal should be delayed. For Vital- + -- VitalDelayType01Z DelayType, the value is single value + -- passed. For VitalDelayType01 and + -- VitalDelayType01Z, the appropriate + -- delay value is selected by VitalCalc- + -- Delay. + -- + -- INOUT + -- none + -- + -- OUT + -- OutSig std_ulogic The internal delayed signal + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType + ); + + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType01 + ); + + PROCEDURE VitalWireDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT twire : IN VitalDelayType01Z + ); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalSignalDelay + -- + -- Description: The VitalSignalDelay procedure is called in a signal + -- delay block in the architecture to delay the + -- appropriate test or reference signal in order to + -- accommodate negative constraint checks. + -- + -- The amount of delay is of type TIME and is a constant. + -- + -- Arguments: + -- + -- IN Type Description + -- InSig std_ulogic The signal to be delayed. + -- dly TIME The amount of time the signal is + -- delayed. + -- + -- INOUT + -- none + -- + -- OUT + -- OutSig std_ulogic The delayed signal + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalSignalDelay ( + SIGNAL OutSig : OUT std_ulogic; + SIGNAL InSig : IN std_ulogic; + CONSTANT dly : IN TIME + ); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalSetupHoldCheck + -- + -- Description: The VitalSetupHoldCheck procedure detects a setup or a + -- hold violation on the input test signal with respect + -- to the corresponding input reference signal. The timing + -- constraints are specified through parameters + -- representing the high and low values for the setup and + -- hold values for the setup and hold times. This + -- procedure assumes non-negative values for setup and hold + -- timing constraints. + -- + -- It is assumed that negative timing constraints + -- are handled by internally delaying the test or + -- reference signals. Negative setup times result in + -- a delayed reference signal. Negative hold times + -- result in a delayed test signal. Furthermore, the + -- delays and constraints associated with these and + -- other signals may need to be appropriately + -- adjusted so that all constraint intervals overlap + -- the delayed reference signals and all constraint + -- values (with respect to the delayed signals) are + -- non-negative. + -- + -- This function is overloaded based on the input + -- TestSignal. A vector and scalar form are provided. + -- + -- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX + -- : + -- : -->| error region |<-- + -- : + -- _______________________________ + -- RefSignal \______________________________ + -- : | | | + -- : | -->| |<-- thold + -- : -->| tsetup |<-- + -- + -- Arguments: + -- + -- IN Type Description + -- TestSignal std_ulogic Value of test signal + -- std_logic_vector + -- TestSignalName STRING Name of test signal + -- TestDelay TIME Model's internal delay associated + -- with TestSignal + -- RefSignal std_ulogic Value of reference signal + -- RefSignalName STRING Name of reference signal + -- RefDelay TIME Model's internal delay associated + -- with RefSignal + -- SetupHigh TIME Absolute minimum time duration before + -- the transition of RefSignal for which + -- transitions of TestSignal are allowed + -- to proceed to the "1" state without + -- causing a setup violation. + -- SetupLow TIME Absolute minimum time duration before + -- the transition of RefSignal for which + -- transitions of TestSignal are allowed + -- to proceed to the "0" state without + -- causing a setup violation. + -- HoldHigh TIME Absolute minimum time duration after + -- the transition of RefSignal for which + -- transitions of TestSignal are allowed + -- to proceed to the "1" state without + -- causing a hold violation. + -- HoldLow TIME Absolute minimum time duration after + -- the transition of RefSignal for which + -- transitions of TestSignal are allowed + -- to proceed to the "0" state without + -- causing a hold violation. + -- CheckEnabled BOOLEAN Check performed if TRUE. + -- RefTransition VitalEdgeSymbolType + -- Reference edge specified. Events on + -- the RefSignal which match the edge + -- spec. are used as reference edges. + -- HeaderMsg STRING String that will accompany any + -- assertion messages produced. + -- XOn BOOLEAN If TRUE, Violation output parameter + -- is set to "X". Otherwise, Violation + -- is always set to "0". + -- MsgOn BOOLEAN If TRUE, set and hold violation + -- message will be generated. + -- Otherwise, no messages are generated, + -- even upon violations. + -- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. + -- EnableSetupOnTest BOOLEAN If FALSE at the time that the + -- TestSignal signal changes, + -- no setup check will be performed. + -- EnableSetupOnRef BOOLEAN If FALSE at the time that the + -- RefSignal signal changes, + -- no setup check will be performed. + -- EnableHoldOnRef BOOLEAN If FALSE at the time that the + -- RefSignal signal changes, + -- no hold check will be performed. + -- EnableHoldOnTest BOOLEAN If FALSE at the time that the + -- TestSignal signal changes, + -- no hold check will be performed. + -- + -- INOUT + -- TimingData VitalTimingDataType + -- VitalSetupHoldCheck information + -- storage area. This is used + -- internally to detect reference edges + -- and record the time of the last edge. + -- + -- OUT + -- Violation X01 This is the violation flag returned. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalSetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + ); + + PROCEDURE VitalSetupHoldCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_logic_vector; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT SetupHigh : IN TIME := 0 ns; + CONSTANT SetupLow : IN TIME := 0 ns; + CONSTANT HoldHigh : IN TIME := 0 ns; + CONSTANT HoldLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + ); + + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalRecoveryRemovalCheck + -- + -- Description: The VitalRecoveryRemovalCheck detects the presence of + -- a recovery or removal violation on the input test + -- signal with respect to the corresponding input reference + -- signal. It assumes non-negative values of setup and + -- hold timing constraints. The timing constraint is + -- specified through parameters representing the recovery + -- and removal times associated with a reference edge of + -- the reference signal. A flag indicates whether a test + -- signal is asserted when it is high or when it is low. + -- + -- It is assumed that negative timing constraints + -- are handled by internally delaying the test or + -- reference signals. Negative recovery times result in + -- a delayed reference signal. Negative removal times + -- result in a delayed test signal. Furthermore, the + -- delays and constraints associated with these and + -- other signals may need to be appropriately + -- adjusted so that all constraint intervals overlap + -- the delayed reference signals and all constraint + -- values (with respect to the delayed signals) are + -- non-negative. + -- + -- Arguments: + -- + -- IN Type Description + -- TestSignal std_ulogic Value of TestSignal. The routine is + -- TestSignalName STRING Name of TestSignal + -- TestDelay TIME Model internal delay associated with + -- the TestSignal + -- RefSignal std_ulogic Value of RefSignal + -- RefSignalName STRING Name of RefSignal + -- RefDelay TIME Model internal delay associated with + -- the RefSignal + -- Recovery TIME A change to an unasserted value on + -- the asynchronous TestSignal must + -- precede reference edge (on RefSignal) + -- by at least this time. + -- Removal TIME An asserted condition must be present + -- on the asynchronous TestSignal for at + -- least the removal time following a + -- reference edge on RefSignal. + -- ActiveLow BOOLEAN A flag which indicates if TestSignal + -- is asserted when it is low - "0." + -- FALSE indicate that TestSignal is + -- asserted when it has a value "1." + -- CheckEnabled BOOLEAN The check in enabled when the value + -- is TRUE, otherwise the constraints + -- are not checked. + -- RefTransition VitalEdgeSymbolType + -- Reference edge specifier. Events on + -- RefSignal will match the edge + -- specified. + -- HeaderMsg STRING A header message that will accompany + -- any assertion message. + -- XOn BOOLEAN When TRUE, the output Violation is + -- set to "X." When FALSE, it is always + -- "0." + -- MsgOn BOOLEAN When TRUE, violation messages are + -- output. When FALSE, no messages are + -- generated. + -- MsgSeverity SEVERITY_LEVEL Severity level of the asserted + -- message. + -- EnableRecOnTest BOOLEAN If FALSE at the time that the + -- TestSignal signal changes, + -- no recovery check will be performed. + -- EnableRecOnRef BOOLEAN If FALSE at the time that the + -- RefSignal signal changes, + -- no recovery check will be performed. + -- EnableRemOnRef BOOLEAN If FALSE at the time that the + -- RefSignal signal changes, + -- no removal check will be performed. + -- EnableRemOnTest BOOLEAN If FALSE at the time that the + -- TestSignal signal changes, + -- no removal check will be performed. + -- + -- INOUT + -- TimingData VitalTimingDataType + -- VitalRecoveryRemovalCheck information + -- storage area. This is used + -- internally to detect reference edges + -- and record the time of the last edge. + -- OUT + -- Violation X01 This is the violation flag returned. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalRecoveryRemovalCheck ( + VARIABLE Violation : OUT X01; + VARIABLE TimingData : INOUT VitalTimingDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName: IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + SIGNAL RefSignal : IN std_ulogic; + CONSTANT RefSignalName : IN STRING := ""; + CONSTANT RefDelay : IN TIME := 0 ns; + CONSTANT Recovery : IN TIME := 0 ns; + CONSTANT Removal : IN TIME := 0 ns; + CONSTANT ActiveLow : IN BOOLEAN := TRUE; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT RefTransition : IN VitalEdgeSymbolType; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT EnableRecOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRecOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRemOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98 + CONSTANT EnableRemOnTest : IN BOOLEAN := TRUE --IR252 3/23/98 + ); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalPeriodPulseCheck + -- + -- Description: VitalPeriodPulseCheck checks for minimum + -- periodicity and pulse width for "1" and "0" values of + -- the input test signal. The timing constraint is + -- specified through parameters representing the minimal + -- period between successive rising and falling edges of + -- the input test signal and the minimum pulse widths + -- associated with high and low values. + -- + -- VitalPeriodCheck's accepts rising and falling edges + -- from 1 and 0 as well as transitions to and from 'X.' + -- + -- _______________ __________ + -- ____________| |_______| + -- + -- |<--- pw_hi --->| + -- |<-------- period ----->| + -- -->| pw_lo |<-- + -- + -- Arguments: + -- IN Type Description + -- TestSignal std_ulogic Value of test signal + -- TestSignalName STRING Name of the test signal + -- TestDelay TIME Model's internal delay associated + -- with TestSignal + -- Period TIME Minimum period allowed between + -- consecutive rising ('P') or + -- falling ('F') transitions. + -- PulseWidthHigh TIME Minimum time allowed for a high + -- pulse ('1' or 'H') + -- PulseWidthLow TIME Minimum time allowed for a low + -- pulse ('0' or 'L') + -- CheckEnabled BOOLEAN Check performed if TRUE. + -- HeaderMsg STRING String that will accompany any + -- assertion messages produced. + -- XOn BOOLEAN If TRUE, Violation output parameter + -- is set to "X". Otherwise, Violation + -- is always set to "0". + -- XOnChecks is a global that allows for + -- only timing checks to be turned on. + -- MsgOn BOOLEAN If TRUE, period/pulse violation + -- message will be generated. + -- Otherwise, no messages are generated, + -- even though a violation is detected. + -- MsgOnChecks allows for only timing + -- check messages to be turned on. + -- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. + -- + -- INOUT + -- PeriodData VitalPeriodDataType + -- VitalPeriodPulseCheck information + -- storage area. This is used + -- internally to detect reference edges + -- and record the pulse and period + -- times. + -- OUT + -- Violation X01 This is the violation flag returned. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------ + PROCEDURE VitalPeriodPulseCheck ( + VARIABLE Violation : OUT X01; + VARIABLE PeriodData : INOUT VitalPeriodDataType; + SIGNAL TestSignal : IN std_ulogic; + CONSTANT TestSignalName : IN STRING := ""; + CONSTANT TestDelay : IN TIME := 0 ns; + CONSTANT Period : IN TIME := 0 ns; + CONSTANT PulseWidthHigh : IN TIME := 0 ns; + CONSTANT PulseWidthLow : IN TIME := 0 ns; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT HeaderMsg : IN STRING := " "; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalInPhaseSkewCheck + -- + -- Description: The VitalInPhaseSkewCheck procedure detects an in-phase + -- skew violation between input signals Signal1 and Signal2. + -- This is a timer based skew check in which a + -- violation is detected if Signal1 and Signal2 are in + -- different logic states longer than the specified skew + -- interval. + -- + -- The timing constraints are specified through parameters + -- representing the skew values for the different states + -- of Signal1 and Signal2. + -- + -- + -- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX + -- : + -- : -->| |<-- + -- : Signal2 should go low in this region + -- : + -- + -- ____________ + -- Signal1 \_________________________________________________ + -- : | | + -- : |<-------- tskew -------->| + -- + -- Arguments: + -- + -- IN Type Description + -- Signal1 std_ulogic Value of first signal + -- Signal1Name STRING Name of first signal + -- Signal1Delay TIME Model's internal delay associated + -- with Signal1 + -- Signal2 std_ulogic Value of second signal + -- Signal2Name STRING Name of second signal + -- Signal2Delay TIME Model's internal delay associated + -- with Signal2 + -- SkewS1S2RiseRise TIME Absolute maximum time duration for + -- which Signal2 can remain at "0" + -- after Signal1 goes to the "1" state, + -- without causing a skew violation. + -- SkewS2S1RiseRise TIME Absolute maximum time duration for + -- which Signal1 can remain at "0" + -- after Signal2 goes to the "1" state, + -- without causing a skew violation. + -- SkewS1S2FallFall TIME Absolute maximum time duration for + -- which Signal2 can remain at "1" + -- after Signal1 goes to the "0" state, + -- without causing a skew violation. + -- SkewS2S1FallFall TIME Absolute maximum time duration for + -- which Signal1 can remain at "1" + -- after Signal2 goes to the "0" state, + -- without causing a skew violation. + -- CheckEnabled BOOLEAN Check performed if TRUE. + -- HeaderMsg STRING String that will accompany any + -- assertion messages produced. + -- XOn BOOLEAN If TRUE, Violation output parameter + -- is set to "X". Otherwise, Violation + -- is always set to "0." + -- MsgOn BOOLEAN If TRUE, skew timing violation + -- messages will be generated. + -- Otherwise, no messages are generated, + -- even upon violations. + -- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. + -- + -- INOUT + -- SkewData VitalSkewDataType + -- VitalInPhaseSkewCheck information + -- storage area. This is used + -- internally to detect signal edges + -- and record the time of the last edge. + -- + -- + -- Trigger std_ulogic This signal is used to trigger the + -- process in which the timing check + -- occurs upon expiry of the skew + -- interval. + -- + -- OUT + -- Violation X01 This is the violation flag returned. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + + PROCEDURE VitalInPhaseSkewCheck ( + VARIABLE Violation : OUT X01; + VARIABLE SkewData : INOUT VitalSkewDataType; + SIGNAL Signal1 : IN std_ulogic; + CONSTANT Signal1Name : IN STRING := ""; + CONSTANT Signal1Delay : IN TIME := 0 ns; + SIGNAL Signal2 : IN std_ulogic; + CONSTANT Signal2Name : IN STRING := ""; + CONSTANT Signal2Delay : IN TIME := 0 ns; + CONSTANT SkewS1S2RiseRise : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1RiseRise : IN TIME := TIME'HIGH; + CONSTANT SkewS1S2FallFall : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1FallFall : IN TIME := TIME'HIGH; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT HeaderMsg : IN STRING := ""; + SIGNAL Trigger : INOUT std_ulogic + ); + + + -- ------------------------------------------------------------------------ + -- + -- Function Name: VitalOutPhaseSkewCheck + -- + -- Description: The VitalOutPhaseSkewCheck procedure detects an + -- out-of-phase skew violation between input signals Signal1 + -- and Signal2. This is a timer based skew check in + -- which a violation is detected if Signal1 and Signal2 are + -- in the same logic state longer than the specified skew + -- interval. + -- + -- The timing constraints are specified through parameters + -- representing the skew values for the different states + -- of Signal1 and Signal2. + -- + -- + -- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX + -- : + -- : -->| |<-- + -- : Signal2 should go high in this region + -- : + -- + -- ____________ + -- Signal1 \_________________________________________________ + -- : | | + -- : |<-------- tskew -------->| + -- + -- Arguments: + -- + -- IN Type Description + -- Signal1 std_ulogic Value of first signal + -- Signal1Name STRING Name of first signal + -- Signal1Delay TIME Model's internal delay associated + -- with Signal1 + -- Signal2 std_ulogic Value of second signal + -- Signal2Name STRING Name of second signal + -- Signal2Delay TIME Model's internal delay associated + -- with Signal2 + -- SkewS1S2RiseFall TIME Absolute maximum time duration for + -- which Signal2 can remain at "1" + -- after Signal1 goes to the "1" state, + -- without causing a skew violation. + -- SkewS2S1RiseFall TIME Absolute maximum time duration for + -- which Signal1 can remain at "1" + -- after Signal2 goes to the "1" state, + -- without causing a skew violation. + -- SkewS1S2FallRise TIME Absolute maximum time duration for + -- which Signal2 can remain at "0" + -- after Signal1 goes to the "0" state, + -- without causing a skew violation. + -- SkewS2S1FallRise TIME Absolute maximum time duration for + -- which Signal1 can remain at "0" + -- after Signal2 goes to the "0" state, + -- without causing a skew violation. + -- CheckEnabled BOOLEAN Check performed if TRUE. + -- HeaderMsg STRING String that will accompany any + -- assertion messages produced. + -- XOn BOOLEAN If TRUE, Violation output parameter + -- is set to "X". Otherwise, Violation + -- is always set to "0." + -- MsgOn BOOLEAN If TRUE, skew timing violation + -- messages will be generated. + -- Otherwise, no messages are generated, + -- even upon violations. + -- MsgSeverity SEVERITY_LEVEL Severity level for the assertion. + -- + -- INOUT + -- SkewData VitalSkewDataType + -- VitalInPhaseSkewCheck information + -- storage area. This is used + -- internally to detect signal edges + -- and record the time of the last edge. + -- + -- Trigger std_ulogic This signal is used to trigger the + -- process in which the timing check + -- occurs upon expiry of the skew + -- interval. + -- + -- OUT + -- Violation X01 This is the violation flag returned. + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE VitalOutPhaseSkewCheck ( + VARIABLE Violation : OUT X01; + VARIABLE SkewData : INOUT VitalSkewDataType; + SIGNAL Signal1 : IN std_ulogic; + CONSTANT Signal1Name : IN STRING := ""; + CONSTANT Signal1Delay : IN TIME := 0 ns; + SIGNAL Signal2 : IN std_ulogic; + CONSTANT Signal2Name : IN STRING := ""; + CONSTANT Signal2Delay : IN TIME := 0 ns; + CONSTANT SkewS1S2RiseFall : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1RiseFall : IN TIME := TIME'HIGH; + CONSTANT SkewS1S2FallRise : IN TIME := TIME'HIGH; + CONSTANT SkewS2S1FallRise : IN TIME := TIME'HIGH; + CONSTANT CheckEnabled : IN BOOLEAN := TRUE; + CONSTANT XOn : IN BOOLEAN := TRUE; + CONSTANT MsgOn : IN BOOLEAN := TRUE; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING; + CONSTANT HeaderMsg : IN STRING := ""; + SIGNAL Trigger : INOUT std_ulogic + ); + + +END VITAL_Timing;