From 296d0aeae789a3189b3dbac0c0391364b3dd9117 Mon Sep 17 00:00:00 2001 From: Kirigaya <1193466151@qq.com> Date: Wed, 1 Nov 2023 22:22:25 +0800 Subject: [PATCH] async --- CHANGELOG.md | 10 +- package-lock.json | 74 +-- script/README.md | 9 +- src/function/hdlDoc/markdown.ts | 5 +- src/function/lsp/completion/vlog.ts | 2 +- src/function/lsp/util/feature.ts | 18 +- src/function/sim/simulate.ts | 7 + src/hdlParser/core.ts | 44 +- src/manager/prj.ts | 23 +- src/monitor/event.ts | 6 +- src/test/.vscode/property.json | 11 - src/test/manager/.vscode/property.json | 11 - src/test/manager/user/src/hello.v | 6 - src/test/monitor/.vscode/property.json | 17 - src/test/monitor/sim1/testbench.v | 50 -- src/test/monitor/src1/add.v | 11 - src/test/monitor/src2/add.v | 9 - src/test/runTest.ts | 23 - src/test/suite/extension.test.ts | 15 - src/test/suite/index.ts | 38 -- src/test/tcl/timing.xdc | 9 - src/test/user/Hardware/sim/testbench.v | 51 -- src/test/user/Hardware/src/Cordic.v | 265 ---------- src/test/user/Hardware/src/clkdiv.v | 29 -- src/test/user/Hardware/src/fsm_test.v | 58 --- src/test/user/Hardware/src/hello.v | 33 -- src/test/user/Hardware/src/hello.vhd | 14 - src/test/user/Hardware/src/mult_module.v | 80 --- src/test/user/Hardware/src/netlist_test.v | 34 -- src/test/vhdl/Scientific.vhd | 15 - src/test/vhdl/based.vhd | 16 - src/test/vhdl/bigfile.vhd | 467 ------------------ src/test/vhdl/clk.vhd | 36 -- src/test/vhdl/counters.vhd | 344 ------------- src/test/vhdl/dsp.vhd | 41 -- src/test/vhdl/expr.vhd | 46 -- src/test/vhdl/fifo.vhd | 202 -------- src/test/vhdl/forgen.vhd | 52 -- src/test/vhdl/forloop.vhd | 37 -- src/test/vhdl/formatter_vhdl.vhd | 0 src/test/vhdl/genericmap.vhd | 105 ---- src/test/vhdl/ifchain.vhd | 26 - src/test/vhdl/ifchain2.vhd | 36 -- src/test/vhdl/mem.vhd | 36 -- src/test/vhdl/operators.vhd | 85 ---- src/test/vhdl/partselect.vhd | 32 -- src/test/vhdl/signextend.vhd | 17 - src/test/vhdl/test.vhd | 191 ------- src/test/vhdl/todo.vhd | 74 --- src/test/vhdl/wbit1.vhd | 21 - src/test/vhdl/whileloop.vhd | 27 - src/test/vhdl/withselect.vhd | 34 -- .../dependence_test/.vscode/property.json | 17 - src/test/vlog/dependence_test/child_1.v | 17 - src/test/vlog/dependence_test/child_2.v | 8 - src/test/vlog/dependence_test/head_1.v | 23 - src/test/vlog/dependence_test/hello.v | 6 - src/test/vlog/dependence_test/parent.v | 69 --- src/test/vlog/dependence_test/pdf/parent.pdf | Bin 95015 -> 0 bytes src/test/vlog/dependence_test/readme_cn.md | 10 - .../dependence_test/simulation/icarus/out.vvp | 26 - src/test/vlog/formatter_test/formatter_test.v | 11 - src/test/vlog/fsm_test/fsm_test.v | 58 --- src/test/vlog/netlist_test/netlist_test.v | 33 -- src/test/vlog/parse_test/Cordic.v | 257 ---------- src/test/vlog/parse_test/instance_test.v | 11 - src/test/vlog/parse_test/mult_module.v | 80 --- src/test/vlog/wavedrom_test/sample.v | 35 -- 68 files changed, 96 insertions(+), 3467 deletions(-) delete mode 100644 src/test/.vscode/property.json delete mode 100644 src/test/manager/.vscode/property.json delete mode 100644 src/test/manager/user/src/hello.v delete mode 100644 src/test/monitor/.vscode/property.json delete mode 100644 src/test/monitor/sim1/testbench.v delete mode 100644 src/test/monitor/src1/add.v delete mode 100644 src/test/monitor/src2/add.v delete mode 100644 src/test/runTest.ts delete mode 100644 src/test/suite/extension.test.ts delete mode 100644 src/test/suite/index.ts delete mode 100644 src/test/tcl/timing.xdc delete mode 100644 src/test/user/Hardware/sim/testbench.v delete mode 100644 src/test/user/Hardware/src/Cordic.v delete mode 100644 src/test/user/Hardware/src/clkdiv.v delete mode 100644 src/test/user/Hardware/src/fsm_test.v delete mode 100644 src/test/user/Hardware/src/hello.v delete mode 100644 src/test/user/Hardware/src/hello.vhd delete mode 100644 src/test/user/Hardware/src/mult_module.v delete mode 100644 src/test/user/Hardware/src/netlist_test.v delete mode 100644 src/test/vhdl/Scientific.vhd delete mode 100644 src/test/vhdl/based.vhd delete mode 100644 src/test/vhdl/bigfile.vhd delete mode 100644 src/test/vhdl/clk.vhd delete mode 100644 src/test/vhdl/counters.vhd delete mode 100644 src/test/vhdl/dsp.vhd delete mode 100644 src/test/vhdl/expr.vhd delete mode 100644 src/test/vhdl/fifo.vhd delete mode 100644 src/test/vhdl/forgen.vhd delete mode 100644 src/test/vhdl/forloop.vhd delete mode 100644 src/test/vhdl/formatter_vhdl.vhd delete mode 100644 src/test/vhdl/genericmap.vhd delete mode 100644 src/test/vhdl/ifchain.vhd delete mode 100644 src/test/vhdl/ifchain2.vhd delete mode 100644 src/test/vhdl/mem.vhd delete mode 100644 src/test/vhdl/operators.vhd delete mode 100644 src/test/vhdl/partselect.vhd delete mode 100644 src/test/vhdl/signextend.vhd delete mode 100644 src/test/vhdl/test.vhd delete mode 100644 src/test/vhdl/todo.vhd delete mode 100644 src/test/vhdl/wbit1.vhd delete mode 100644 src/test/vhdl/whileloop.vhd delete mode 100644 src/test/vhdl/withselect.vhd delete mode 100644 src/test/vlog/dependence_test/.vscode/property.json delete mode 100644 src/test/vlog/dependence_test/child_1.v delete mode 100644 src/test/vlog/dependence_test/child_2.v delete mode 100644 src/test/vlog/dependence_test/head_1.v delete mode 100644 src/test/vlog/dependence_test/hello.v delete mode 100644 src/test/vlog/dependence_test/parent.v delete mode 100644 src/test/vlog/dependence_test/pdf/parent.pdf delete mode 100644 src/test/vlog/dependence_test/readme_cn.md delete mode 100644 src/test/vlog/dependence_test/simulation/icarus/out.vvp delete mode 100644 src/test/vlog/formatter_test/formatter_test.v delete mode 100644 src/test/vlog/fsm_test/fsm_test.v delete mode 100644 src/test/vlog/netlist_test/netlist_test.v delete mode 100644 src/test/vlog/parse_test/Cordic.v delete mode 100644 src/test/vlog/parse_test/instance_test.v delete mode 100644 src/test/vlog/parse_test/mult_module.v delete mode 100644 src/test/vlog/wavedrom_test/sample.v diff --git a/CHANGELOG.md b/CHANGELOG.md index 2d309e8..99254bb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,4 +6,12 @@ Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how ## [Unreleased] -- Initial release \ No newline at end of file +- Initial release + + +## [2023.11.1] + +Bug 修复 +- 修复文档化input, output处注释无法正常显示到文档的 bug +- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug +- 修复 iverilog 仿真功能中，将 `include 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性） diff --git a/package-lock.json b/package-lock.json index 3db6db8..887b58f 100644 --- a/package-lock.json +++ b/package-lock.json @@ -1,14 +1,13 @@ { - "name": "digital-ide", - "version": "0.3.0", + "name": "fpga-support", + "version": "0.3.1", "lockfileVersion": 2, "requires": true, "packages": { "": { - "name": "digital-ide", - "version": "0.3.0", + "name": "fpga-support", + "version": "0.3.1", "dependencies": { - "@vscode/wasm-wasi": "^0.8.2", "chokidar": "^3.5.3", "puppeteer-core": "^19.4.1", "showdown": "^2.1.0", @@ -344,26 +343,6 @@ "node": "^12.22.0 || ^14.17.0 || >=16.0.0" } }, - "node_modules/@vscode/sync-api-client": { - "version": "0.8.1", - "resolved": "https://registry.npmmirror.com/@vscode/sync-api-client/-/sync-api-client-0.8.1.tgz", - "integrity": "sha512-82NRZpZlvRtlFoqi/J8xGw964F8ZfJJeJu2D9QMAAzq8BMDCXqkhO2qHApnyEV4gG2mQSaHtfw0f30GOPExgUg==", - "dependencies": { - "@vscode/sync-api-common": "0.8.1", - "vscode-uri": "^3.0.6" - }, - "engines": { - "node": ">=16.14.2" - } - }, - "node_modules/@vscode/sync-api-common": { - "version": "0.8.1", - "resolved": "https://registry.npmmirror.com/@vscode/sync-api-common/-/sync-api-common-0.8.1.tgz", - "integrity": "sha512-XfanQNxkUlCpAsQ2+1SzNEdoY7jtcu48jYBR0n864ZWAWrH7m2QBK32YoNlrDN2V0eh8tdF0WH1NuHOm3Y021A==", - "engines": { - "node": ">=16.14.2" - } - }, "node_modules/@vscode/test-electron": { "version": "2.2.2", "resolved": "https://registry.npmmirror.com/@vscode/test-electron/-/test-electron-2.2.2.tgz", @@ -379,18 +358,6 @@ "node": ">=16" } }, - "node_modules/@vscode/wasm-wasi": { - "version": "0.8.2", - "resolved": "https://registry.npmmirror.com/@vscode/wasm-wasi/-/wasm-wasi-0.8.2.tgz", - "integrity": "sha512-TazXvphINUEoXVX2dEPdXhrwrQ9I6Z6t9LCDfALTmL43D/2Zmlc89KfNE/cO36n2uo+SDlPPP/6vWyF9TBbnnw==", - "dependencies": { - "@vscode/sync-api-client": "0.8.1", - "vscode-uri": "^3.0.6" - }, - "engines": { - "vscode": "^1.71.0" - } - }, "node_modules/acorn": { "version": "8.8.1", "resolved": "https://registry.npmmirror.com/acorn/-/acorn-8.8.1.tgz", @@ -2868,11 +2835,6 @@ "resolved": "https://registry.npmmirror.com/vscode-textmate/-/vscode-textmate-9.0.0.tgz", "integrity": "sha512-Cl65diFGxz7gpwbav10HqiY/eVYTO1sjQpmRmV991Bj7wAoOAjGQ97PpQcXorDE2Uc4hnGWLY17xme+5t6MlSg==" }, - "node_modules/vscode-uri": { - "version": "3.0.7", - "resolved": "https://registry.npmmirror.com/vscode-uri/-/vscode-uri-3.0.7.tgz", - "integrity": "sha512-eOpPHogvorZRobNqJGhapa0JdwaxpjVvyBp0QIUMRMSf8ZAlqOdEquKuRmw9Qwu0qXtJIWqFtMkmvJjUZmMjVA==" - }, "node_modules/wavedrom": { "version": "2.9.1", "resolved": "https://registry.npmmirror.com/wavedrom/-/wavedrom-2.9.1.tgz", @@ -3277,20 +3239,6 @@ "eslint-visitor-keys": "^3.3.0" } }, - "@vscode/sync-api-client": { - "version": "0.8.1", - "resolved": "https://registry.npmmirror.com/@vscode/sync-api-client/-/sync-api-client-0.8.1.tgz", - "integrity": "sha512-82NRZpZlvRtlFoqi/J8xGw964F8ZfJJeJu2D9QMAAzq8BMDCXqkhO2qHApnyEV4gG2mQSaHtfw0f30GOPExgUg==", - "requires": { - "@vscode/sync-api-common": "0.8.1", - "vscode-uri": "^3.0.6" - } - }, - "@vscode/sync-api-common": { - "version": "0.8.1", - "resolved": "https://registry.npmmirror.com/@vscode/sync-api-common/-/sync-api-common-0.8.1.tgz", - "integrity": "sha512-XfanQNxkUlCpAsQ2+1SzNEdoY7jtcu48jYBR0n864ZWAWrH7m2QBK32YoNlrDN2V0eh8tdF0WH1NuHOm3Y021A==" - }, "@vscode/test-electron": { "version": "2.2.2", "resolved": "https://registry.npmmirror.com/@vscode/test-electron/-/test-electron-2.2.2.tgz", @@ -3303,15 +3251,6 @@ "unzipper": "^0.10.11" } }, - "@vscode/wasm-wasi": { - "version": "0.8.2", - "resolved": "https://registry.npmmirror.com/@vscode/wasm-wasi/-/wasm-wasi-0.8.2.tgz", - "integrity": "sha512-TazXvphINUEoXVX2dEPdXhrwrQ9I6Z6t9LCDfALTmL43D/2Zmlc89KfNE/cO36n2uo+SDlPPP/6vWyF9TBbnnw==", - "requires": { - "@vscode/sync-api-client": "0.8.1", - "vscode-uri": "^3.0.6" - } - }, "acorn": { "version": "8.8.1", "resolved": "https://registry.npmmirror.com/acorn/-/acorn-8.8.1.tgz", @@ -5288,11 +5227,6 @@ "resolved": "https://registry.npmmirror.com/vscode-textmate/-/vscode-textmate-9.0.0.tgz", "integrity": "sha512-Cl65diFGxz7gpwbav10HqiY/eVYTO1sjQpmRmV991Bj7wAoOAjGQ97PpQcXorDE2Uc4hnGWLY17xme+5t6MlSg==" }, - "vscode-uri": { - "version": "3.0.7", - "resolved": "https://registry.npmmirror.com/vscode-uri/-/vscode-uri-3.0.7.tgz", - "integrity": "sha512-eOpPHogvorZRobNqJGhapa0JdwaxpjVvyBp0QIUMRMSf8ZAlqOdEquKuRmw9Qwu0qXtJIWqFtMkmvJjUZmMjVA==" - }, "wavedrom": { "version": "2.9.1", "resolved": "https://registry.npmmirror.com/wavedrom/-/wavedrom-2.9.1.tgz", diff --git a/script/README.md b/script/README.md index c4b2e2c..4ef84e8 100644 --- a/script/README.md +++ b/script/README.md @@ -2,4 +2,11 @@ Some scripts for config generation, batch processing etc. Please run the all the scripts in the `extensionPath`. -command: scripts for `commands` in package.json \ No newline at end of file +command: scripts for `commands` in package.json + + +## 一键打包 + +```bash +$ python script/command/make_package.py +``` \ No newline at end of file diff --git a/src/function/hdlDoc/markdown.ts b/src/function/hdlDoc/markdown.ts index 037a871..df5ac17 100644 --- a/src/function/hdlDoc/markdown.ts +++ b/src/function/hdlDoc/markdown.ts @@ -70,7 +70,10 @@ async function patchComment(path: AbsPath, ports: (HdlModulePort | HdlModulePara const ranges = ports.map(port => port.range); const comments = await getSymbolComments(path, ranges); for (let i = 0; i < ports.length; ++ i) { - const inlineComment = comments[i].replace(/\n/, ' '); + let inlineComment = comments[i].replace(/\n/, ' '); + if (inlineComment.startsWith('//')) { + inlineComment = inlineComment.substring(2); + } ports[i].desc = inlineComment; } } diff --git a/src/function/lsp/completion/vlog.ts b/src/function/lsp/completion/vlog.ts index 29bbe4f..af49735 100644 --- a/src/function/lsp/completion/vlog.ts +++ b/src/function/lsp/completion/vlog.ts @@ -108,7 +108,7 @@ class VlogMacroCompletionProvider implements vscode.CompletionItemProvider { class VlogPositionPortProvider implements vscode.CompletionItemProvider { public async provideCompletionItems(document: vscode.TextDocument, position: vscode.Position, token: vscode.CancellationToken, context: vscode.CompletionContext): Promise | null | undefined> { - console.log('enter VlogPositionPortProvider'); + // console.log('enter VlogPositionPortProvider'); try { const suggestPositionPorts: vscode.CompletionItem[] = []; diff --git a/src/function/lsp/util/feature.ts b/src/function/lsp/util/feature.ts index f828ee8..1332aba 100644 --- a/src/function/lsp/util/feature.ts +++ b/src/function/lsp/util/feature.ts @@ -126,16 +126,18 @@ function bin2float(bin: string, exp: number, fra: number): number | undefined { } } -async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, nonblank: RegExp, l_comment_symbol: string, l_comment_regExp: RegExp) { +async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, nonblank: RegExp, l_comment_symbol: string, l_comment_regExp: RegExp): Promise { const comments = []; let content = ''; let is_b_comment = false; - let line = range.start.line + 1; + let line = range.start.line; + const firstLine = range.start.line - 1; while (line) { - line--; + line --; content = document.lineAt(line).text; + // 首先判断该行是否是空白 let isblank = content.match(nonblank); if (!isblank) { @@ -159,12 +161,13 @@ async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, no // 判断该行是否存在行注释 let l_comment_index = content.indexOf(l_comment_symbol); + if (l_comment_index >= 0) { let before_l_comment = content.slice(0, l_comment_index); - // before_l_comment = del_comments(before_l_comment, b_comment_end_index); + // before_l_comment = del_comments(before_l_comment, b_comment_end_index); if (before_l_comment.match(nonblank)) { // 如果去除块注释之后还有字符则认为该注释不属于所要的 - if (line === range.start.line) { + if (line === firstLine) { // let b_comment_last_index = content.lastIndexOf('*/'); // b_comment_last_index = (b_comment_last_index == -1) ? 0 : (b_comment_last_index + 2); // comments.push(content.slice(b_comment_last_index, l_comment_index) + '\n'); @@ -187,7 +190,7 @@ async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, no behind_b_comment = del_comments(behind_b_comment, l_comment_regExp); if (behind_b_comment.match(nonblank)) { // 如果去除块注释之后还有字符则认为该注释不属于所要的 - if (line === range.start.line) { + if (line === firstLine) { comments.push(content.slice(0, b_comment_end_index) + '\n'); is_b_comment = true; continue; @@ -201,7 +204,7 @@ async function getFullSymbolInfo(document: vscode.TextDocument, range: Range, no } // 说明既不是块注释又不是行注释所以就是到了代码块 - if (line !== range.start.line) { + if (line !== firstLine) { break; } } @@ -271,6 +274,7 @@ async function getSymbolComments(path: string, ranges: Range[]): Promise; const args = []; for (const dep of dependences) { + if (visitedPath.has(dep)) { + continue; + } args.push('"' + dep + '"'); + visitedPath.add(dep); } return args.join(' ').trim(); } diff --git a/src/hdlParser/core.ts b/src/hdlParser/core.ts index 2137aa7..f72f6a2 100644 --- a/src/hdlParser/core.ts +++ b/src/hdlParser/core.ts @@ -305,7 +305,6 @@ class HdlParam { public async addHdlFile(path: AbsPath) { path = hdlPath.toSlash(path); await this.initHdlFiles([path]); - const moduleFile = this.getHdlFile(path); if (!moduleFile) { MainOutput.report('error happen when create moduleFile ' + path, ReportType.Warn); @@ -387,11 +386,18 @@ class HdlInstance { return false; } - public update(newInstance: common.RawHdlInstance) { + /** + * @description update Instance of each time + * @param newInstance + */ + public update(newInstance: common.RawHdlInstance) { this.type = newInstance.type; this.range = newInstance.range; this.instparams = newInstance.instparams; this.instports = newInstance.instports; + + this.instModPath = this.parentMod.path; + this.instModPathStatus = this.parentMod.solveInstModPathStatus(); } }; @@ -611,6 +617,26 @@ class HdlModule { } } + public solveInstModPathStatus(): common.InstModPathStatus { + const inst = hdlParam.getUnhandleInstanceByType(this.name); + if (!inst) { + return common.InstModPathStatus.Unknown; + } + const userModule = inst.parentMod; + if (userModule.path === this.path) { + return common.InstModPathStatus.Current; + } else { + const userIncludePaths = userModule.file.macro.includes.map( + include => hdlPath.rel2abs(userModule.path, include.path)); + + if (userIncludePaths.includes(this.path)) { + return common.InstModPathStatus.Include; + } else { + return common.InstModPathStatus.Others; + } + } + } + public solveUnhandleInstance() { const inst = hdlParam.getUnhandleInstanceByType(this.name); @@ -625,17 +651,7 @@ class HdlModule { inst.instModPath = this.path; // judge the type of instModPathStatus - if (userModule.path === this.path) { - inst.instModPathStatus = common.InstModPathStatus.Current; - } else { - const userIncludePaths = userModule.file.macro.includes.map( - include => hdlPath.rel2abs(userModule.path, include.path)); - if (userIncludePaths.includes(this.path)) { - inst.instModPathStatus = common.InstModPathStatus.Include; - } else { - inst.instModPathStatus = common.InstModPathStatus.Others; - } - } + inst.instModPathStatus = this.solveInstModPathStatus(); // assign module in the instance inst.locateHdlModule(); @@ -645,7 +661,7 @@ class HdlModule { public update(newModule: common.RawHdlModule) { this.ports = newModule.ports; this.params = newModule.params; - this.range = newModule.range; + this.range = newModule.range; // compare and make change to instance const uncheckedInstanceNames = new Set(); for (const inst of this.getAllInstances()) { diff --git a/src/manager/prj.ts b/src/manager/prj.ts index 5a5eae7..be09e71 100644 --- a/src/manager/prj.ts +++ b/src/manager/prj.ts @@ -14,6 +14,10 @@ import { hdlIgnore } from './ignore'; import { ppyAction } from '../monitor/event'; import { hdlMonitor } from '../monitor'; +interface RefreshPrjConfig { + mkdir: boolean +} + class PrjManage { pl?: PlManage; ps?: PsManage; @@ -55,7 +59,7 @@ class PrjManage { * init opeParam * @param context */ - public async initOpeParam(context: vscode.ExtensionContext) { + public async initOpeParam(context: vscode.ExtensionContext): Promise { const os = process.platform; const extensionPath = hdlPath.toSlash(context.extensionPath); const workspacePath = this.getWorkspacePath(); @@ -73,6 +77,8 @@ class PrjManage { // set path for merge in prjInfo opeParam.prjInfo.initContextPath(extensionPath, workspacePath); + const refreshPrjConfig: RefreshPrjConfig = {mkdir: true}; + // merge prjInfo from propertyJsonPath if exist if (fs.existsSync(propertyJsonPath)) { const rawPrjInfo = hdlFile.readJSON(propertyJsonPath) as RawPrjInfo; @@ -87,8 +93,12 @@ class PrjManage { await this.generatePropertyJson(); const rawPrjInfo = hdlFile.readJSON(propertyJsonPath) as RawPrjInfo; opeParam.mergePrjInfo(rawPrjInfo); + } else { + refreshPrjConfig.mkdir = false; } } + + return refreshPrjConfig; } /** @@ -130,9 +140,9 @@ class PrjManage { if (countTimeCost) { console.time('launch'); } - await this.initOpeParam(context); + const refreshPrjConfig = await this.initOpeParam(context); MainOutput.report('finish initialise opeParam', ReportType.Info); - prjManage.refreshPrjFolder(); + prjManage.refreshPrjFolder(refreshPrjConfig); const hdlFiles = await this.getPrjHardwareFiles(); MainOutput.report(`finish collect ${hdlFiles.length} hdl files`, ReportType.Info); @@ -153,7 +163,10 @@ class PrjManage { } } - public async refreshPrjFolder() { + public async refreshPrjFolder(config?: RefreshPrjConfig) { + if (config && config.mkdir === false) { + return; + } // read new prj from ppy const rawPrjInfo = opeParam.getRawUserPrjInfo(); @@ -161,7 +174,7 @@ class PrjManage { // configure user's info await this.createFolderByRawPrjInfo(rawPrjInfo); } else { - // configure by default + // configure by default await this.createFolderByDefault(rawPrjInfo); } diff --git a/src/monitor/event.ts b/src/monitor/event.ts index 6ffbf20..4f93d3f 100644 --- a/src/monitor/event.ts +++ b/src/monitor/event.ts @@ -158,12 +158,12 @@ class HdlAction extends BaseAction { } for (const rawHdlModule of fast.content) { - const moduleName = rawHdlModule.name; + const moduleName = rawHdlModule.name; if (uncheckedModuleNames.has(moduleName)) { // match the same module, check then const originalModule = moduleFile.getHdlModule(moduleName); uncheckedModuleNames.delete(moduleName); - originalModule?.update(rawHdlModule); + originalModule?.update(rawHdlModule); } else { // no matched, create it const newModule = moduleFile.createHdlModule(rawHdlModule); @@ -171,6 +171,8 @@ class HdlAction extends BaseAction { newModule.solveUnhandleInstance(); } } + + // 3. delete module not visited yet for (const moduleName of uncheckedModuleNames) { diff --git a/src/test/.vscode/property.json b/src/test/.vscode/property.json deleted file mode 100644 index 71cfab5..0000000 --- a/src/test/.vscode/property.json +++ /dev/null @@ -1,11 +0,0 @@ -{ - "toolChain": "xilinx", - "prjName": { - "PL": "template" - }, - "soc": { - "core": "cortexM3" - }, - "enableShowLog": false, - "device": "none" -} \ No newline at end of file diff --git a/src/test/manager/.vscode/property.json b/src/test/manager/.vscode/property.json deleted file mode 100644 index 7dc2beb..0000000 --- a/src/test/manager/.vscode/property.json +++ /dev/null @@ -1,11 +0,0 @@ -{ - "toolChain": "xilinx", - "prjName": { - "PL": "template" - }, - "soc": { - "core": "none" - }, - "enableShowLog": false, - "device": "none" -} \ No newline at end of file diff --git a/src/test/manager/user/src/hello.v b/src/test/manager/user/src/hello.v deleted file mode 100644 index 4165df3..0000000 --- a/src/test/manager/user/src/hello.v +++ /dev/null @@ -1,6 +0,0 @@ -module hello( - input clk, reset, - output value -); - -endmodule \ No newline at end of file diff --git a/src/test/monitor/.vscode/property.json b/src/test/monitor/.vscode/property.json deleted file mode 100644 index da1fccd..0000000 --- a/src/test/monitor/.vscode/property.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "toolChain": "xilinx", - "prjName": { - "PL": "template" - }, - "soc": { - "core": "none" - }, - "enableShowLog": false, - "device": "none", - "arch": { - "hardware": { - "src": "./src1", - "sim": "./sim1" - } - } -} \ No newline at end of file diff --git a/src/test/monitor/sim1/testbench.v b/src/test/monitor/sim1/testbench.v deleted file mode 100644 index ebc7f5f..0000000 --- a/src/test/monitor/sim1/testbench.v +++ /dev/null @@ -1,50 +0,0 @@ -module testbench(); - -parameter DATA_WIDTH = 32; -parameter ADDR_WIDTH = 32; -parameter MAIN_FRE = 100; //unit MHz -reg sys_clk = 0; -reg sys_rst = 1; -reg [DATA_WIDTH-1:0] data = 0; -reg [ADDR_WIDTH-1:0] addr = 0; - -always begin - #(500/MAIN_FRE) sys_clk = ~sys_clk; -end - -always begin - #50 sys_rst = 0; -end - -always @(posedge sys_clk) begin - if (sys_rst) - addr = 0; - else - addr = addr + 1; -end -always @(posedge sys_clk) begin - if (sys_rst) - data = 0; - else - data = data + 1; -end - -//Instance -// outports wire -wire [8:0] c; - -SimpleAdd_1 u_SimpleAdd_1( - .a ( a ), - .b ( b ), - .c ( c ) -); - - - -initial begin - $dumpfile("wave.vcd"); - $dumpvars(0, testbench); - #50000 $finish; -end - -endmodule //TOP diff --git a/src/test/monitor/src1/add.v b/src/test/monitor/src1/add.v deleted file mode 100644 index f544fb7..0000000 --- a/src/test/monitor/src1/add.v +++ /dev/null @@ -1,11 +0,0 @@ -module SimpleAdd_1( - input [8:0] a, b, - output [8:0] c -); - - assign c = a + b; - - -endmodule //SimpleAdd - - diff --git a/src/test/monitor/src2/add.v b/src/test/monitor/src2/add.v deleted file mode 100644 index 62647f8..0000000 --- a/src/test/monitor/src2/add.v +++ /dev/null @@ -1,9 +0,0 @@ -module SimpleAdd_2( - input [7:0] a, b, - output [7:0] c -); - - assign c = a + b; - - -endmodule //SimpleAdd diff --git a/src/test/runTest.ts b/src/test/runTest.ts deleted file mode 100644 index 27b3ceb..0000000 --- a/src/test/runTest.ts +++ /dev/null @@ -1,23 +0,0 @@ -import * as path from 'path'; - -import { runTests } from '@vscode/test-electron'; - -async function main() { - try { - // The folder containing the Extension Manifest package.json - // Passed to `--extensionDevelopmentPath` - const extensionDevelopmentPath = path.resolve(__dirname, '../../'); - - // The path to test runner - // Passed to --extensionTestsPath - const extensionTestsPath = path.resolve(__dirname, './suite/index'); - - // Download VS Code, unzip it and run the integration test - await runTests({ extensionDevelopmentPath, extensionTestsPath }); - } catch (err) { - console.error('Failed to run tests'); - process.exit(1); - } -} - -main(); diff --git a/src/test/suite/extension.test.ts b/src/test/suite/extension.test.ts deleted file mode 100644 index 4ca0ab4..0000000 --- a/src/test/suite/extension.test.ts +++ /dev/null @@ -1,15 +0,0 @@ -import * as assert from 'assert'; - -// You can import and use all API from the 'vscode' module -// as well as import your extension to test it -import * as vscode from 'vscode'; -// import * as myExtension from '../../extension'; - -suite('Extension Test Suite', () => { - vscode.window.showInformationMessage('Start all tests.'); - - test('Sample test', () => { - assert.strictEqual(-1, [1, 2, 3].indexOf(5)); - assert.strictEqual(-1, [1, 2, 3].indexOf(0)); - }); -}); diff --git a/src/test/suite/index.ts b/src/test/suite/index.ts deleted file mode 100644 index 7029e38..0000000 --- a/src/test/suite/index.ts +++ /dev/null @@ -1,38 +0,0 @@ -import * as path from 'path'; -import * as Mocha from 'mocha'; -import * as glob from 'glob'; - -export function run(): Promise { - // Create the mocha test - const mocha = new Mocha({ - ui: 'tdd', - color: true - }); - - const testsRoot = path.resolve(__dirname, '..'); - - return new Promise((c, e) => { - glob('**/**.test.js', { cwd: testsRoot }, (err, files) => { - if (err) { - return e(err); - } - - // Add files to the test suite - files.forEach(f => mocha.addFile(path.resolve(testsRoot, f))); - - try { - // Run the mocha test - mocha.run(failures => { - if (failures > 0) { - e(new Error(`${failures} tests failed.`)); - } else { - c(); - } - }); - } catch (err) { - console.error(err); - e(err); - } - }); - }); -} diff --git a/src/test/tcl/timing.xdc b/src/test/tcl/timing.xdc deleted file mode 100644 index 3128e9f..0000000 --- a/src/test/tcl/timing.xdc +++ /dev/null @@ -1,9 +0,0 @@ -create_debug_core u_ila_0 ila -set_property ALL_PROBE_SAME_MU true -set_property C_ADV_TRIGGER true -set_property C_EN_STRG_QUAL true -set_property C_INPUT_PIPE_STAGES true -set_property C_TRIGIN_EN false -set_property C_TRIGOUT_EN false -set_property port_width -connect_debug_port u_ila_0/clk \ No newline at end of file diff --git a/src/test/user/Hardware/sim/testbench.v b/src/test/user/Hardware/sim/testbench.v deleted file mode 100644 index 7ad4f51..0000000 --- a/src/test/user/Hardware/sim/testbench.v +++ /dev/null @@ -1,51 +0,0 @@ -module testbench(); - -parameter DATA_WIDTH = 32; -parameter ADDR_WIDTH = 32; -parameter MAIN_FRE = 100; //unit MHz -reg sys_clk = 0; -reg sys_rst = 1; -reg [DATA_WIDTH-1:0] data = 0; -reg [ADDR_WIDTH-1:0] addr = 0; - -always begin - #(500/MAIN_FRE) sys_clk = ~sys_clk; -end - -always begin - #50 sys_rst = 0; -end - -always @(posedge sys_clk) begin - if (sys_rst) - addr = 0; - else - addr = addr + 1; -end -always @(posedge sys_clk) begin - if (sys_rst) - data = 0; - else - data = data + 1; -end - -//Instance -// outports wire -wire outp; - -mux2to1 u_mux2to1( - .a ( a ), - .b ( b ), - .sel ( sel ), - .outp ( outp ) -); - - - -initial begin - $dumpfile("wave.vcd"); - $dumpvars(0, testbench); - #50000 $finish; -end - -endmodule //TOP diff --git a/src/test/user/Hardware/src/Cordic.v b/src/test/user/Hardware/src/Cordic.v deleted file mode 100644 index 20b354c..0000000 --- a/src/test/user/Hardware/src/Cordic.v +++ /dev/null @@ -1,265 +0,0 @@ -`timescale 1ns / 1ps - - -`include "mult_module.v" - -module Cordic #( - parameter XY_BITS = 12, - parameter PH_BITS = 32, - parameter ITERATIONS = 32, - parameter CORDIC_STYLE = "ROTATE", - parameter PHASE_ACC = "ON" -)( - input clk, - input RST, - input signed [XY_BITS-1:0] x_i, - input signed [XY_BITS-1:0] y_i, - input signed [PH_BITS-1:0] phase_in, - - output signed [XY_BITS-1:0] x_o, - output signed [XY_BITS-1:0] y_o, - output signed [PH_BITS-1:0] phase_out, - input valid_in, - output valid_out -); - -localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2; - -/* -//360°--2^16,phase_in = 16bits (input [15:0] phase_in) -//1°--2^16/360 -*/ -function [PH_BITS-1:0] tanangle; -input [4:0] i; -begin - case (i) - 5'b00000: tanangle = (32'h20000000 >> (32 - PH_BITS)); //tan = 1/2^1 = 1/2 - 5'b00001: tanangle = (32'h12e4051e >> (32 - PH_BITS)); //tan = 1/2^2 = 1/4 - 5'b00010: tanangle = (32'h09fb385b >> (32 - PH_BITS)); //tan = 1/2^3 = 1/8 - 5'b00011: tanangle = (32'h051111d4 >> (32 - PH_BITS)); //tan = 1/2^4 = 1/16 - 5'b00100: tanangle = (32'h028b0d43 >> (32 - PH_BITS)); //tan = 1/2^5 = 1/32 - 5'b00101: tanangle = (32'h0145d7e1 >> (32 - PH_BITS)); //tan = 1/2^6 = 1/64 - 5'b00110: tanangle = (32'h00a2f61e >> (32 - PH_BITS)); //tan = 1/2^7 = 1/128 - 5'b00111: tanangle = (32'h00517c55 >> (32 - PH_BITS)); //tan = 1/2^8 = 1/256 - 5'b01000: tanangle = (32'h0028be53 >> (32 - PH_BITS)); //tan = 1/2^9 = 1/512 - 5'b01001: tanangle = (32'h00145f2f >> (32 - PH_BITS)); //tan = 1/2^10 = 1/1024 - 5'b01010: tanangle = (32'h000a2f98 >> (32 - PH_BITS)); //tan = 1/2^11 = 1/2048 - 5'b01011: tanangle = (32'h000517cc >> (32 - PH_BITS)); //tan = 1/2^12 = 1/4096 - 5'b01100: tanangle = (32'h00028be6 >> (32 - PH_BITS)); //tan = 1/2^13 = 1/8192 - 5'b01101: tanangle = (32'h000145f3 >> (32 - PH_BITS)); //tan = 1/2^14 = 1/16384 - 5'b01110: tanangle = (32'h0000a2fa >> (32 - PH_BITS)); //tan = 1/2^15 = 1/32768 - 5'b01111: tanangle = (32'h0000517d >> (32 - PH_BITS)); //tan = 1/2^16 = 1/65536 - 5'b10000: tanangle = (32'h000028be >> (32 - PH_BITS)); //tan = 1/2^17 = 1/131072 - 5'b10001: tanangle = (32'h0000145f >> (32 - PH_BITS)); //tan = 1/2^18 = 1/262144 - 5'b10010: tanangle = (32'h00000a30 >> (32 - PH_BITS)); //tan = 1/2^19 = 1/524288 - 5'b10011: tanangle = (32'h00000518 >> (32 - PH_BITS)); //tan = 1/2^20 = 1/1048576 - 5'b10100: tanangle = (32'h0000028c >> (32 - PH_BITS)); //tan = 1/2^21 = 1/2097152 - 5'b10101: tanangle = (32'h00000146 >> (32 - PH_BITS)); //tan = 1/2^22 = 1/4194304 - 5'b10110: tanangle = (32'h000000a3 >> (32 - PH_BITS)); //tan = 1/2^23 = 1/8388608 - 5'b10111: tanangle = (32'h00000051 >> (32 - PH_BITS)); //tan = 1/2^24 = 1/16777216 - 5'b11000: tanangle = (32'h00000029 >> (32 - PH_BITS)); //tan = 1/2^25 = 1/33554432 - 5'b11001: tanangle = (32'h00000014 >> (32 - PH_BITS)); //tan = 1/2^26 = 1/67108864 - 5'b11010: tanangle = (32'h0000000a >> (32 - PH_BITS)); //tan = 1/2^27 = 1/134217728 - 5'b11011: tanangle = (32'h00000005 >> (32 - PH_BITS)); //tan = 1/2^28 = 1/268435456 - 5'b11100: tanangle = (32'h00000003 >> (32 - PH_BITS)); //tan = 1/2^29 = 1/536870912 - 5'b11101: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^30 = 1/1073741824 - 5'b11110: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^31 = 1/2147483648 - 5'b11111: tanangle = (32'h00000000 >> (32 - PH_BITS)); //tan = 1/2^32 = 1/4294967296 - endcase -end -endfunction - -reg [1:0] data_in_buff [ITERATIONS:0]; -reg signed [XY_BITS-1:0] x [ITERATIONS:0]; -reg signed [XY_BITS-1:0] y [ITERATIONS:0]; -reg signed [PH_BITS-1:0] z [ITERATIONS:0]; - -integer m; -initial begin - for (m = 0; m<=ITERATIONS; m=m+1) begin - x[m] = 0; - end -end - - - -integer n; -initial begin - for (n = 0; n<=ITERATIONS; n=n+1) begin - y[n] = 0; - end -end - -integer s; -initial begin - for (s = 0; s<=ITERATIONS; s=s+1) begin - z[s] = 0; - end -end - -integer k; -initial begin - for (k = 0; k<=ITERATIONS; k=k+1) begin - data_in_buff[k] = 0; - end -end - - - - -genvar i; -generate for(i=0;i>>i); - y[i+1] <= y[i] - (x[i]>>>i); - z[i+1] <= z[i] + tanangle(i); - end - else begin - x[i+1] <= x[i] - (y[i]>>>i); - y[i+1] <= y[i] + (x[i]>>>i); - z[i+1] <= z[i] - tanangle(i); - end - end - else if(CORDIC_STYLE == "VECTOR") begin - if (y[i] > 0) begin - x[i+1] <= x[i] + (y[i]>>>i); - y[i+1] <= y[i] - (x[i]>>>i); - z[i+1] <= z[i] + tanangle(i); - end else begin - x[i+1] <= x[i] - (y[i]>>>i); - y[i+1] <= y[i] + (x[i]>>>i); - z[i+1] <= z[i] - tanangle(i); - end - end - end -end -always @ (posedge clk) begin - data_in_buff[i+1] <= data_in_buff[i]; -end -end -endgenerate - -generate if (CORDIC_STYLE == "ROTATE") begin : IQ_Gen -reg [PH_BITS - 1 : 0] Phase_input = 0; -if (PHASE_ACC == "ON") begin - reg [PH_BITS - 1 : 0] addr_r0 = 0; - always @(posedge clk) begin - addr_r0 <= addr_r0 + phase_in; - end - always @(posedge clk) begin - Phase_input <= addr_r0; - end -end -else if (PHASE_ACC == "OFF") begin - always @(posedge clk) begin - Phase_input <= phase_in; - end -end -always @(posedge clk) begin - if(valid_in & (~RST)) begin - x[0] <= K_COS; - y[0] <= 0; - z[0] <= Phase_input[PH_BITS - 3 : 0]; - data_in_buff[0] <= Phase_input[PH_BITS - 1 : PH_BITS - 2]; - end - else begin - x[0] <= 0; - y[0] <= 0; - z[0] <= 0; - data_in_buff[0] <= 0; - end -end -reg signed [XY_BITS-1:0] cos = 0; -reg signed [XY_BITS-1:0] sin = 0; -always @ (posedge clk) begin - case(data_in_buff[ITERATIONS]) - 2'b00:begin //if the phase is in first quadrant,the sin(X)=sin(A),cos(X)=cos(A) - cos <= x[ITERATIONS]; - sin <= y[ITERATIONS]; - end - 2'b01:begin //if the phase is in second quadrant,the sin(X)=sin(A+90)=cosA,cos(X)=cos(A+90)=-sinA - cos <= ~(y[ITERATIONS]) + 1'b1;//-sin - sin <= x[ITERATIONS];//cos - end - 2'b10:begin //if the phase is in third quadrant,the sin(X)=sin(A+180)=-sinA,cos(X)=cos(A+180)=-cosA - cos <= ~(x[ITERATIONS]) + 1'b1;//-cos - sin <= ~(y[ITERATIONS]) + 1'b1;//-sin - end - 2'b11:begin //if the phase is in forth quadrant,the sin(X)=sin(A+270)=-cosA,cos(X)=cos(A+270)=sinA - cos <= y[ITERATIONS];//sin - sin <= ~(x[ITERATIONS]) + 1'b1;//-cos - end - endcase -end -assign x_o = cos; -assign y_o = sin; -assign phase_out = z[ITERATIONS]; -end -endgenerate - -generate if (CORDIC_STYLE == "VECTOR") begin : Demodule_Gen -localparam signed [PH_BITS-1:0] PHASE_COE = (2**(PH_BITS-2)) - 1; -//localparam MODUIUS_COE = ; -always @(posedge clk) begin - if(valid_in & (~RST)) begin - case ({x_i[XY_BITS-1],y_i[XY_BITS-1]}) - 2'b00 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - 2'b01 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - 2'b10 : begin x[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; - y[0] <= -{x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end - 2'b11 : begin x[0] <= -{y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; - y[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end - default : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - endcase - z[0] <= phase_in; - data_in_buff[0] <= {x_i[XY_BITS-1],y_i[XY_BITS-1]}; - end - else begin - x[0] <= 0; - y[0] <= 0; - z[0] <= 0; - data_in_buff[0] <= 0; - end -end -reg [XY_BITS*2-1:0] Modulus = 0; -wire [XY_BITS*2-1:0] Modulus_buf; -reg signed [PH_BITS - 1:0] phase_r = 0; -always @ (posedge clk) begin - case(data_in_buff[ITERATIONS]) - 2'b00:begin phase_r <= $signed(z[ITERATIONS]); end - 2'b01:begin phase_r <= $signed(z[ITERATIONS]); end - 2'b10:begin phase_r <= $signed(z[ITERATIONS]) + $signed(PHASE_COE); end - 2'b11:begin phase_r <= $signed(z[ITERATIONS]) - $signed(PHASE_COE); end - endcase - Modulus[XY_BITS:0] <= x[ITERATIONS]; -end -assign Modulus_buf = (Modulus * 32'd39797)>>15; -assign x_o = Modulus_buf[XY_BITS-1:0]; -assign y_o = y[ITERATIONS]; -assign phase_out = phase_r; -end -endgenerate - -reg [ITERATIONS+1:0] v = 0; -always @ (posedge clk) begin - if (RST) - v <= 0; - else begin - v <= v << 1; - v[0] <= valid_in; - end -end -assign valid_out = v[ITERATIONS+1]; - -endmodule diff --git a/src/test/user/Hardware/src/clkdiv.v b/src/test/user/Hardware/src/clkdiv.v deleted file mode 100644 index 05a47c1..0000000 --- a/src/test/user/Hardware/src/clkdiv.v +++ /dev/null @@ -1,29 +0,0 @@ -module clkdiv( - input clk50, - input rst_n, - output reg clkout -); - reg [15:0] cnt; - always @(posedge clk50 or negedge rst_n) - begin - if(!rst_n) - begin - cnt <= 16'b0; - clkout <= 1'b0; - end - else if(cnt == 16'd162) - begin - clkout <= 1'b1; - cnt <= cnt + 16'd1; - end - else if(cnt == 16'd325) - begin - clkout <= 1'b0; - cnt <= 16'd0; - end - else - begin - cnt <= cnt + 16'd1; - end - end -endmodule \ No newline at end of file diff --git a/src/test/user/Hardware/src/fsm_test.v b/src/test/user/Hardware/src/fsm_test.v deleted file mode 100644 index 95b2134..0000000 --- a/src/test/user/Hardware/src/fsm_test.v +++ /dev/null @@ -1,58 +0,0 @@ -module fsm_test( - input clock, - input reset, - input [2 : 0] req_0, - input [2 : 0] req_1, - output reg [2 : 0] gnt_0, - output reg [2 : 0] gnt_1 - ); - - reg [2:0] state; - - parameter IDLE = 3'h1; - parameter GNT0 = 3'd2; - parameter GNT1 = 3'b100; - - always @ (posedge clock) begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end - else - case(state) - IDLE : - if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end - else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT1; - end - else begin - state <= #1 IDLE; //example comment - end - GNT0 : - if (req_0 == 1'b1) begin - state <= #1 GNT0; - end - else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : - if (req_1 == 1'b1) begin - state <= #1 GNT1; - end - else begin - gnt_1 <= 0; - state <= #1 IDLE; - end - default : - state <= #1 IDLE; - endcase - end - - -endmodule //module_name diff --git a/src/test/user/Hardware/src/hello.v b/src/test/user/Hardware/src/hello.v deleted file mode 100644 index 015ee6b..0000000 --- a/src/test/user/Hardware/src/hello.v +++ /dev/null @@ -1,33 +0,0 @@ -// VHDL code for a 2-to-1 multiplexer - -module mux2to1( - input wire a, - input wire b, - input wire sel, - output wire outp - ); - - // outports wire -wire [XY_BITS-1:0] x_o; -wire [XY_BITS-1:0] y_o; -wire [PH_BITS-1:0] phase_out; -wire valid_out; - -Cordic u_Cordic( - .clk ( clk ), - .RST ( RST ), - .x_i ( x_i ), - .y_i ( y_i ), - .phase_in ( phase_in ), - .x_o ( x_o ), - .y_o ( y_o ), - .phase_out ( phase_out ), - .valid_in ( valid_in ), - .valid_out ( valid_out ) -); - - - - assign outp = sel == 1'b0 ? a : b; - -endmodule diff --git a/src/test/user/Hardware/src/hello.vhd b/src/test/user/Hardware/src/hello.vhd deleted file mode 100644 index f40f549..0000000 --- a/src/test/user/Hardware/src/hello.vhd +++ /dev/null @@ -1,14 +0,0 @@ --- VHDL code for a 2-to-1 multiplexer -library IEEE; -use IEEE.std_logic_1164.all; - -entity mux2to1 is - port(a, b : in std_logic; - sel : in std_logic; - outp : out std_logic); -end mux2to1; - -architecture behavioral of mux2to1 is -begin - outp <= a when sel = '0' else b; -end behavioral; \ No newline at end of file diff --git a/src/test/user/Hardware/src/mult_module.v b/src/test/user/Hardware/src/mult_module.v deleted file mode 100644 index d202dd5..0000000 --- a/src/test/user/Hardware/src/mult_module.v +++ /dev/null @@ -1,80 +0,0 @@ -// template -module template #( - parameter INPUT_WIDTH = 12, - parameter OUTPUT_WIDTH = 12 - )( - input [INPUT_WIDTH - - 1 : 0]data_in, - output reg clk_in = (INPUT_WIDTH - - OUTPUT_WIDTH) , - clk=9'hd0, - input rst_n, RST, - output [OUTPUT_WIDTH - 1 : 0] data_out - ); - -endmodule //template - - -module test # ( - parameter INPUT_WIDTH = 12, - parameter OUTPUT_WIDTH = 12 - )( - input clk_in, - input rst_n, - input [INPUT_WIDTH - 1 : 0] data_in , - input [3:2] dasta_ff, - - output reg signed [OUTPUT_WIDTH - 1 : 0] data_out, - output reg signed [OUTPUT_WIDTH - 1 : 0] data_ff - ); - - wire valid_out; - - Cordic #( - .XY_BITS ( 12 ), - .PH_BITS ( 32 ), - .ITERATIONS ( 32 ), - .CORDIC_STYLE ( "ROTATE" ), - .PHASE_ACC ( "ON" )) - u_Cordic( - //input - .clk_in ( clk_in ), - .RST ( RST ), - .x_i ( x_i ), - .y_i ( y_i ), - .phase_in ( phase_in ), - .valid_in ( valid_in ), - - //output - .x_o ( x_o ), - .y_o ( y_o ), - .phase_out ( phase_out ), - .valid_out ( valid_out ) - - //inout - ); - - wire [3 : 0] count_high; - wire [3 : 0] count_low; - wire over; - - template u_template( - //input - .clk ( clk ), - .data ( data ), - .en ( en ), - .load ( load ), - .rst ( rst ), - .switch ( switch ), - - //output - .count_high ( count_high ), - .count_low ( count_low ), - .over ( over ) - - //inout - ); - - - -endmodule //test diff --git a/src/test/user/Hardware/src/netlist_test.v b/src/test/user/Hardware/src/netlist_test.v deleted file mode 100644 index ea8dc7d..0000000 --- a/src/test/user/Hardware/src/netlist_test.v +++ /dev/null @@ -1,34 +0,0 @@ -// borrowed with some modifications from -// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html -module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out); - -input [8:0] data_in; -input clock, up, down; - -output reg [8:0] count_out; -output reg carry_out, borrow_out, parity_out; - -reg [9:0] cnt_up, cnt_dn; -reg [8:0] count_nxt; - - -always @(posedge clock) -begin - cnt_dn = count_out - 3'b 101; - cnt_up = count_out + 2'b 11; - - case ({up,down}) - 2'b 00 : count_nxt = data_in; - 2'b 01 : count_nxt = cnt_dn; - 2'b 10 : count_nxt = cnt_up; - 2'b 11 : count_nxt = count_out; - default : count_nxt = 9'bX; - endcase - - parity_out <= ^count_nxt; - carry_out <= up & cnt_up[9]; - borrow_out <= down & cnt_dn[9]; - count_out <= count_nxt; -end - -endmodule \ No newline at end of file diff --git a/src/test/vhdl/Scientific.vhd b/src/test/vhdl/Scientific.vhd deleted file mode 100644 index 3d6655a..0000000 --- a/src/test/vhdl/Scientific.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -entity Scientific is - generic ( - exp1: integer := 25e6; - exp2: integer := 25E6; - exp3: real := 25.0e6; - exp4: real := 50.0e+3; - exp5: real := 50.0e-3 - ); - port( - clk : in std_logic - ); -end Scientific; diff --git a/src/test/vhdl/based.vhd b/src/test/vhdl/based.vhd deleted file mode 100644 index 7c7c1e2..0000000 --- a/src/test/vhdl/based.vhd +++ /dev/null @@ -1,16 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -entity based is port (sysclk : in std_logic); -end based; -architecture rtl of based is - signal foo, foo1, foo2, foo8, foo10, foo11, foo16 : integer; -begin - foo <= 123; - foo1 <= 123_456; - foo2 <= 2#00101101110111#; - foo8 <= 8#0177362#; - foo10 <= 10#01234#; - --foo11<= 11#01234#; - foo16 <= 16#12af#; -end rtl; \ No newline at end of file diff --git a/src/test/vhdl/bigfile.vhd b/src/test/vhdl/bigfile.vhd deleted file mode 100644 index 5897f16..0000000 --- a/src/test/vhdl/bigfile.vhd +++ /dev/null @@ -1,467 +0,0 @@ -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- CONNECTIVITY DEFINITION -entity bigfile is - port ( - -- from external pins - sysclk : in std_logic; - g_zaq_in : in std_logic_vector(31 downto 0); - g_aux : in std_logic_vector(31 downto 0); - scanb : in std_logic; - g_wrb : in std_logic; - g_rdb : in std_logic; - g_noop_clr : in std_logic_vector(31 downto 0); - swe_ed : in std_logic; - swe_lv : in std_logic; - din : in std_logic_vector(63 downto 0); - g_dout_w0x0f : in std_logic_vector(4 downto 0); - n9_bit_write : in std_logic; - -- from reset_gen block - reset : in std_logic; - alu_u : in std_logic_vector(31 downto 0); - debct_ping : in std_logic; - g_sys_in : out std_logic_vector(31 downto 0); - g_zaq_in_rst_hold : out std_logic_vector(31 downto 0); - g_zaq_hhh_enb : out std_logic_vector(31 downto 0); - g_zaq_out : out std_logic_vector(31 downto 0); - g_dout : out std_logic_vector(31 downto 0); - g_zaq_ctl : out std_logic_vector(31 downto 0); - g_zaq_qaz_hb : out std_logic_vector(31 downto 0); - g_zaq_qaz_lb : out std_logic_vector(31 downto 0); - gwerth : out std_logic_vector(31 downto 0); - g_noop : out std_logic_vector(31 downto 0); - g_vector : out std_logic_vector(8*32-1 downto 0); - swe_qaz1 : out std_logic_vector(31 downto 0) - ); -end bigfile; - - --- IMPLEMENTATION -architecture rtl of bigfile is - - -- constants - constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000"; - constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001"; - constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010"; - constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011"; - constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100"; - constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101"; - constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110"; - constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111"; - constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000"; - constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001"; - constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010"; - constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011"; - constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100"; - constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101"; - constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110"; - constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111"; - constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000"; - constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001"; - constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010"; - constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011"; - constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100"; - constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101"; - constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110"; - constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111"; - - -- comment - signal g_t_klim_dout : std_logic_vector(31 downto 0); - signal g_t_u_dout : std_logic_vector(31 downto 0); - signal g_t_l_dout : std_logic_vector(31 downto 0); - signal g_t_hhh_l_dout : std_logic_vector(31 downto 0); - signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0); - signal g_secondary_t_l_dout : std_logic_vector(31 downto 0); - signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used - signal g_e_z_dout : std_logic_vector(31 downto 0); - signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0); - signal g_style_vfr_dout : std_logic_vector(31 downto 0); - signal g_style_klim_dout : std_logic_vector(31 downto 0); - signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0); - signal g_style_t_y_dout : std_logic_vector(31 downto 0); - signal g_n_l_dout : std_logic_vector(31 downto 0); - signal g_n_vfr_dout : std_logic_vector(31 downto 0); - signal g_e_n_r_dout : std_logic_vector(31 downto 0); - signal g_n_r_bne_dout : std_logic; - signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0); - signal g_alu_l_dout : std_logic_vector(31 downto 0); - signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0); - signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0); - signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0); - signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0); - signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0); - - -- other - signal q_g_zaq_in : std_logic_vector(31 downto 0); - signal q2_g_zaq_in : std_logic_vector(31 downto 0); - signal q3_g_zaq_in : std_logic_vector(31 downto 0); - signal q_g_zaq_in_cd : std_logic_vector(3 downto 0); - signal q_g_style_vfr_dout : std_logic_vector(31 downto 0); - signal q_g_unzq : std_logic_vector(3 downto 0); - signal g_n_active : std_logic_vector(31 downto 0); - - -- inter - signal g_zaq_in_y : std_logic_vector(31 downto 0); - signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0); - signal g_zaq_out_i : std_logic_vector(31 downto 0); - signal g_zaq_ctl_i : std_logic_vector(31 downto 0); - signal g_sys_in_i : std_logic_vector(31 downto 0); - signal g_sys_in_ii : std_logic_vector(31 downto 0); - signal g_dout_i : std_logic_vector(31 downto 0); - -begin - - -- qaz out - g_zaq_out_i <= - -- if secondary - (g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or - -- if alu - (g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or - -- otherwise - (not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout); - -- Changed - g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout; - - -- qaz - -- JLB - g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or - (g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i)); - -- mux - --vnavigatoroff - g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000"; - --vnavigatoron - - g_zaq_hhh_enb <= not(g_t_hhh_l_dout); - - g_zaq_qaz_hb <= g_t_qaz_mult_high_dout; - g_zaq_qaz_lb <= g_t_qaz_mult_low_dout; - - - -- Dout - g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else - g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else - g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else - g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else - g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else - g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else - ("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else - g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else - g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else - g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else - g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else - g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else - g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else - g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else - g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else - g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else - ("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else - g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else - g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else - g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else - g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else - gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else - g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else - gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else - "00000000000000000000000000000000"; - g_dout <= g_dout_i when g_rdb = '0' else (others => '1'); - - - -- this can be used to use zzz1 - g_style_main_reset_hold_dout_proc : - process(sysclk) - begin - if( sysclk'event and sysclk = '1' ) then - if( scanb = '1' ) then - if( reset = '1' ) then - g_style_main_reset_hold_dout <= g_zaq_in; - end if; - --vnavigatoroff - else - g_style_main_reset_hold_dout <= q2_g_zaq_in; - end if; - --vnavigatoron - end if; - end process; - -- qaz - g_zaq_in_rst_hold <= g_style_main_reset_hold_dout; - - -- Din - g_doutister_proc : - process(reset, sysclk) - variable g_dout_w0x0f_v : std_logic_vector(4 downto 0); - variable i : integer; - variable j : integer; - begin - if( reset /= '0' ) then - g_t_klim_dout <= (others => '0'); - g_t_u_dout <= (others => '0'); - g_t_l_dout <= (others => '0'); - g_t_hhh_l_dout <= (others => '0'); - g_t_jkl_sink_l_dout <= (others => '0'); - g_secondary_t_l_dout <= (others => '0'); - g_style_c_l_dout <= (others => '0'); - g_e_z_dout <= (others => '0'); - g_n_both_qbars_l_dout <= (others => '0'); - g_style_klim_dout <= (others => '0'); - g_style_t_y_dout <= (others => '0'); - g_n_l_dout <= (others => '0'); - g_e_n_r_dout <= (others => '0'); - g_n_r_bne_dout <= '0'; - g_n_div_rebeq_dout <= (others => '1'); - g_alu_l_dout <= (others => '0'); - g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low - g_t_qaz_mult_high_dout <= (others => '0'); - gwerthernal_style_u_dout <= (others => '0'); - gwerthernal_style_l_dout <= (others => '0'); - elsif( sysclk'event and sysclk = '1' ) then - -- clear - g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr; - if( g_wrb = '0' ) then - -- because we now... - for i in 0 to 1 loop - if( i = 0 ) then - g_dout_w0x0f_v := g_dout_w0x0f; - elsif( i = 1 ) then - if( n9_bit_write = '1' ) then - -- set - g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1'; - end if; - --vnavigatoroff - else - -- not possible but added for code coverage's sake - end if; - --vnavigatoron - case g_dout_w0x0f_v is - when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32); - when g_t_u_w0x0f => - -- output klim - for j in 0 to 31 loop - if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then - g_t_u_dout(j) <= din(32*i+j); - end if; - end loop; - when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32); - when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32); - when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32); - when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32); - when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32); - when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32); - when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32); - when g_style_vfr_w0x0f => null; -- read-only register - when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32); - when g_unklimed_style_vfr_w0x0f => null; -- read-only register - when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32); - when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32); - when g_n_vfr_w0x0f => null; -- writes - when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32); - when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32); - when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or - g_n_div_rebeq_dout; -- a '1' writes - when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32); - when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32); - when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32); - when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32); - when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32); - --vnavigatoroff - when others => null; - --vnavigatoron - end case; - end loop; - - end if; - end if; - end process; - - -- sample - g_zaq_in_sample_proc : - process(reset, sysclk) - begin - if( reset /= '0' ) then - q_g_zaq_in <= (others => '0'); - q2_g_zaq_in <= (others => '0'); - q3_g_zaq_in <= (others => '0'); - elsif( sysclk'event and sysclk = '1' ) then - q_g_zaq_in <= g_zaq_in; - q2_g_zaq_in <= q_g_zaq_in; - q3_g_zaq_in <= g_zaq_in_y; - end if; - end process; - - -- vfr register - g_unklimed_style_vfr_dout <= q2_g_zaq_in; - - -- switch - g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in; - - -- qaz - g_style_vfr_dout <= -- top 2 - (g_zaq_in_y(31 downto 4) & - -- FSM - (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or - -- otherwise just use - (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0)))); - - -- in scan mode - g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1' - --vnavigatoroff - else g_style_t_y_dout; - --vnavigatoron - - g_sys_in_i <= (-- top 28 - (g_zaq_in_y_no_dout(31 downto 4) & - -- is enabled - (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or - -- otherwise just use - (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0))))); - - g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout ); - - g_sys_in <= g_sys_in_ii; - - lpq_proc : - process(reset, sysclk) - variable i : integer; - begin - if( reset /= '0' ) then - q_g_zaq_in_cd <= (others => '0'); - q_g_unzq <= (others => '1'); - elsif( sysclk'event and sysclk = '1' ) then - -- sample - if( debct_ping = '1') then - -- taken - for i in 0 to 3 loop - if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then - q_g_unzq(i) <= '1'; - else - if( q_g_unzq(i) = '0' ) then - q_g_zaq_in_cd(i) <= g_zaq_in_y(i); - else - q_g_unzq(i) <= '0'; - end if; - end if; - end loop; - else - for i in 0 to 3 loop - if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then - q_g_unzq(i) <= '1'; - end if; - end loop; - end if; - end if; - end process; - - -- generate lqqs - sample_forwerth_proc : - process(reset, sysclk) - begin - if( reset /= '0' ) then - q_g_style_vfr_dout <= (others => '0'); - elsif( sysclk'event and sysclk = '1' ) then - if( scanb = '1' ) then - q_g_style_vfr_dout <= g_style_vfr_dout; - --vnavigatoroff - else - -- in scan - q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii; - end if; - --vnavigatoron - end if; - end process; - - -- generate - g_n_active <= -- 1 to 0 - (((q_g_style_vfr_dout and not g_style_vfr_dout) or - -- get this - (not q_g_style_vfr_dout and g_style_vfr_dout and - g_n_both_qbars_l_dout))) and - -- must be - g_n_l_dout; - - -- check for lqq active and set lqq vfr register - -- also clear - n_proc : - process(reset, sysclk) - variable i : integer; - begin - if( reset /= '0' ) then - g_n_vfr_dout <= (others => '0'); - gwerth <= (others => '0'); - elsif( sysclk'event and sysclk = '1' ) then - for i in 0 to 31 loop - -- lqq - -- vfr matches - if( g_n_active(i) = '1' ) then - gwerth(i) <= '1'; - if( g_e_z_dout(i) = '1' ) then - -- lqq - g_n_vfr_dout(i) <= '1'; - else - g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); - end if; - else - -- clear - if( g_e_z_dout(i) = '0' ) then - g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign - -- in both - if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then - gwerth(i) <= '0'; - end if; - else - -- write - if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then - gwerth(i) <= '0'; - g_n_vfr_dout(i) <= '0'; - end if; - end if; - end if; - end loop; - end if; - end process; - - ---- - -- Create the Lqq - createwerth_vec_proc : - process( g_n_r_bne_dout, g_e_n_r_dout) - variable imod8, idiv8 : integer; - variable i : integer; - begin - for i in 0 to 31 loop - imod8 := i mod 8; - idiv8 := i / 8; - - if( g_n_r_bne_dout = '0' ) then - -- non-unique - g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); - else - -- unique - if( imod8 = 0 ) then - g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); - else - g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) + - to_unsigned(imod8, 8)); - end if; - end if; - end loop; - end process; - - ---- - -- Qaz - g_noop <= g_n_div_rebeq_dout; - - - create_g_ack_bne_proc : - process( swe_ed,swe_lv,g_e_z_dout) - variable i : integer; - begin - for i in 0 to 31 loop - if( g_e_z_dout(i) = '1') then - swe_qaz1(i) <= swe_ed; - else - swe_qaz1(i) <= swe_lv; - end if; - end loop; - end process; - -end rtl; diff --git a/src/test/vhdl/clk.vhd b/src/test/vhdl/clk.vhd deleted file mode 100644 index 541c7cd..0000000 --- a/src/test/vhdl/clk.vhd +++ /dev/null @@ -1,36 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic; - ival : in std_logic_vector(31 downto 0) - ); -end clk; -architecture rtl of clk is - signal foo : std_logic_vector(10+3 downto 0); - signal baz : std_logic_vector(2 downto 0); - signal egg : std_logic_vector(4 to 7-1); -begin - pfoo: process(reset, sysclk) - begin - if( reset /= '0' ) then - foo <= (others => '1'); - elsif( sysclk'event and sysclk = '1' ) then - foo <= ival(31 downto 31-(10+3)); - end if; - end process; - pbaz: process(preset, dsysclk) - begin - if( preset /= '1' ) then - baz <= (others => '0'); - elsif( dsysclk'event and dsysclk = '0' ) then - baz <= ival(2 downto 0); - end if; - end process; - pegg: process(qreset, esysclk) - begin - if( qreset /= '1' ) then - egg <= (others => '0'); - elsif( esysclk'event and esysclk = '0' ) then - egg <= ival(6 downto 4); - end if; - end process; -end rtl; diff --git a/src/test/vhdl/counters.vhd b/src/test/vhdl/counters.vhd deleted file mode 100644 index 77f7bbb..0000000 --- a/src/test/vhdl/counters.vhd +++ /dev/null @@ -1,344 +0,0 @@ -library IEEE; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity counters is - port( - sysclk : in std_logic; - foo_card : in std_logic; - wfoo0_baz : in std_logic; - wfoo0_blrb : in std_logic; - wfoo0_zz1pb : in std_logic; - wfoo0_turn : in std_logic_vector(31 downto 0); - debct_baz : in std_logic; - debct_blrb : in std_logic; - debct_zz1pb : in std_logic; - debct_bar : in std_logic; - debct_turn : in std_logic_vector(31 downto 0); - Z0_bar : in std_logic; - Z0_baz : in std_logic; - Z0_blrb : in std_logic; - Z0_zz1pb : in std_logic; - Z0_turn : in std_logic_vector(31 downto 0); - Y1_bar : in std_logic; - Y1_baz : in std_logic; - Y1_blrb : in std_logic; - Y1_zz1pb : in std_logic; - Y1_turn : in std_logic_vector(31 downto 0); - X2_bar : in std_logic; - X2_baz : in std_logic; - X2_blrb : in std_logic; - X2_zz1pb : in std_logic; - X2_turn : in std_logic_vector(31 downto 0); - W3_bar : in std_logic; - W3_baz : in std_logic; - W3_blrb : in std_logic; - W3_zz1pb : in std_logic; - W3_turn : in std_logic_vector(31 downto 0); - -- to engine block - Z0_cwm : out std_logic; - Z0 : out std_logic_vector(31 downto 0); - Y1_cwm : out std_logic; - Y1 : out std_logic_vector(31 downto 0); - X2_cwm : out std_logic; - X2 : out std_logic_vector(31 downto 0); - W3_cwm : out std_logic; - W3 : out std_logic_vector(31 downto 0); - wfoo0_cwm : out std_logic; - wfoo0_llwln : out std_logic_vector(31 downto 0); - debct_cwm : out std_logic; - debct_pull : out std_logic; - debct : out std_logic_vector(31 downto 0); - wdfilecardA2P : out std_logic - ); -end counters; - -architecture rtl of counters is - - signal wfoo0_llwln_var : unsigned(31 downto 0); - signal debct_var : unsigned(31 downto 0); - signal Z0_var : unsigned(31 downto 0); - signal Y1_var : unsigned(31 downto 0); - signal X2_var : unsigned(31 downto 0); - signal W3_var : unsigned(31 downto 0); - signal main_wfoo0_cwm : std_logic; - signal do_q3p_Z0 : std_logic; - signal do_q3p_Y1 : std_logic; - signal do_q3p_X2 : std_logic; - signal do_q3p_W3 : std_logic; - signal do_q3p_wfoo0 : std_logic; - signal do_q3p_debct : std_logic; - - signal Z0_cwm_i : std_logic; - signal Y1_cwm_i : std_logic; - signal X2_cwm_i : std_logic; - signal W3_cwm_i : std_logic; - signal debct_cwm_i : std_logic; - - signal file_card_i : std_logic; - signal do_file_card_i : std_logic; - signal prev_do_file_card : std_logic; - -begin - - ----- - -- form the outputs - wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var); - debct <= std_logic_vector(debct_var); - Z0 <= std_logic_vector(Z0_var); - Y1 <= std_logic_vector(Y1_var); - X2 <= std_logic_vector(X2_var); - W3 <= std_logic_vector(W3_var); - Z0_cwm <= Z0_cwm_i; - Y1_cwm <= Y1_cwm_i; - X2_cwm <= X2_cwm_i; - W3_cwm <= W3_cwm_i; - debct_cwm <= debct_cwm_i; - - wdfilecardA2P <= do_file_card_i; - - LLWLNS : - process(foo_card, sysclk) - begin - if foo_card = '1' then - wfoo0_llwln_var <= (others => '0'); - debct_var <= (others => '0'); - Z0_var <= (others => '0'); - Y1_var <= (others => '0'); - X2_var <= (others => '0'); - W3_var <= (others => '0'); - - wfoo0_cwm <= '0'; - debct_cwm_i <= '0'; - debct_pull <= '0'; - Z0_cwm_i <= '0'; - Y1_cwm_i <= '0'; - X2_cwm_i <= '0'; - W3_cwm_i <= '0'; - main_wfoo0_cwm <= '0'; - file_card_i <= '0'; - - do_q3p_wfoo0 <= '0'; - do_file_card_i <= '0'; - prev_do_file_card <= '0'; - - do_q3p_Z0 <= '0'; - do_q3p_Y1 <= '0'; - do_q3p_X2 <= '0'; - do_q3p_W3 <= '0'; - do_q3p_debct <= '0'; - - else - if sysclk'event and sysclk = '1' then - - -- pull - debct_pull <= '0'; - do_file_card_i <= '0'; - - ---- - -- wfoo0 - - if wfoo0_baz = '1' then - wfoo0_llwln_var <= unsigned(wfoo0_turn); - main_wfoo0_cwm <= '0'; - if wfoo0_llwln_var = "00000000000000000000000000000000" then - do_q3p_wfoo0 <= '0'; - else - do_q3p_wfoo0 <= '1'; - end if; - else - if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then - wfoo0_llwln_var <= wfoo0_llwln_var - 1; - if (wfoo0_llwln_var = "00000000000000000000000000000000") then - wfoo0_llwln_var <= unsigned(wfoo0_turn); - if main_wfoo0_cwm = '0' then - wfoo0_cwm <= '1'; - main_wfoo0_cwm <= '1'; - else - do_file_card_i <= '1'; - do_q3p_wfoo0 <= '0'; - end if; - end if; - end if; - end if; - - if wfoo0_zz1pb = '0' then - wfoo0_cwm <= '0'; - end if; - - if Z0_baz = '1' then -- counter Baz - Z0_var <= unsigned(Z0_turn); - if Z0_turn = "00000000000000000000000000000000" then - do_q3p_Z0 <= '0'; - else - do_q3p_Z0 <= '1'; - end if; - else - if do_q3p_Z0 = '1' and Z0_blrb = '1' then - if Z0_bar = '0' then - if Z0_cwm_i = '0' then - if do_q3p_Z0 = '1' then - Z0_var <= Z0_var - 1; - if (Z0_var = "00000000000000000000000000000001") then - Z0_cwm_i <= '1'; - do_q3p_Z0 <= '0'; - end if; - end if; - end if; - else - Z0_var <= Z0_var - 1; - if (Z0_var = "00000000000000000000000000000000") then - Z0_cwm_i <= '1'; - Z0_var <= unsigned(Z0_turn); - end if; - end if; -- Z0_bar - end if; - end if; -- Z0_blrb - - if Z0_zz1pb = '0' then - Z0_cwm_i <= '0'; - end if; - - if Y1_baz = '1' then -- counter Baz - Y1_var <= unsigned(Y1_turn); - if Y1_turn = "00000000000000000000000000000000" then - do_q3p_Y1 <= '0'; - else - do_q3p_Y1 <= '1'; - end if; - elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then - if Y1_bar = '0' then - if Y1_cwm_i = '0' then - if do_q3p_Y1 = '1' then - Y1_var <= Y1_var - 1; - if (Y1_var = "00000000000000000000000000000001") then - Y1_cwm_i <= '1'; - do_q3p_Y1 <= '0'; - end if; - end if; - end if; - else - Y1_var <= Y1_var - 1; - - if (Y1_var = "00000000000000000000000000000000") then - Y1_cwm_i <= '1'; - Y1_var <= unsigned(Y1_turn); - end if; - end if; -- Y1_bar - - end if; -- Y1_blrb - - if Y1_zz1pb = '0' then - Y1_cwm_i <= '0'; - end if; - - if X2_baz = '1' then -- counter Baz - X2_var <= unsigned(X2_turn); - if X2_turn = "00000000000000000000000000000000" then - do_q3p_X2 <= '0'; - else - do_q3p_X2 <= '1'; - end if; - elsif do_q3p_X2 = '1' and X2_blrb = '1' then - if X2_bar = '0' then - if X2_cwm_i = '0' then - if do_q3p_X2 = '1' then - X2_var <= X2_var - 1; - if (X2_var = "00000000000000000000000000000001") then - X2_cwm_i <= '1'; - do_q3p_X2 <= '0'; - end if; - end if; - end if; - else - X2_var <= X2_var - 1; - - if (X2_var = "00000000000000000000000000000000") then --{ - X2_cwm_i <= '1'; - X2_var <= unsigned(X2_turn); - end if; - end if; --X2_bar - end if; -- X2_blrb - - if X2_zz1pb = '0' then - X2_cwm_i <= '0'; - end if; - - if W3_baz = '1' then -- counter Baz - W3_var <= unsigned(W3_turn); - if W3_turn = "00000000000000000000000000000000" then - do_q3p_W3 <= '0'; - else - do_q3p_W3 <= '1'; - end if; - elsif do_q3p_W3 = '1' and W3_blrb = '1' then - if W3_bar = '0' then - if W3_cwm_i = '0'then - if do_q3p_W3 = '1' then - W3_var <= W3_var - 1; - if (W3_var = "00000000000000000000000000000001") then - W3_cwm_i <= '1'; - do_q3p_W3 <= '0'; - end if; - end if; - end if; - else - W3_var <= W3_var - 1; - - if (W3_var = "00000000000000000000000000000000") then --{ - W3_cwm_i <= '1'; - W3_var <= unsigned(W3_turn); - end if; - end if; -- W3_bar - - end if; -- W3_blrb - - if W3_zz1pb = '0' then - W3_cwm_i <= '0'; - end if; - - if debct_baz = '1' then -- counter Baz - debct_var <= unsigned(debct_turn); - if debct_turn = "00000000000000000000000000000000" then - do_q3p_debct <= '0'; - else - do_q3p_debct <= '1'; - end if; - elsif do_q3p_debct = '1' and debct_blrb = '1' then - if debct_bar = '0' then - if debct_cwm_i = '0'then - if do_q3p_debct = '1' then - debct_var <= debct_var - 1; - if (debct_var = "00000000000000000000000000000001") then - debct_cwm_i <= '1'; - debct_pull <= '1'; - do_q3p_debct <= '0'; - end if; - end if; - end if; - else - ---- T - -- Continue - debct_var <= debct_var - 1; - - -- ending - if (debct_var = "00000000000000000000000000000000") then --{ - debct_cwm_i <= '1'; - debct_pull <= '1'; - debct_var <= unsigned(debct_turn); - end if; - end if; -- debct_bar - - end if; -- debct_blrb - - -- comment - if debct_zz1pb = '0' then - debct_cwm_i <= '0'; - end if; - - end if; - end if; - end process; - -end rtl; diff --git a/src/test/vhdl/dsp.vhd b/src/test/vhdl/dsp.vhd deleted file mode 100644 index a762a4e..0000000 --- a/src/test/vhdl/dsp.vhd +++ /dev/null @@ -1,41 +0,0 @@ --- Nearly useless stub, it's here to support genericmap.vhd -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity dsp is generic( - rst_val : std_logic := '0'; - thing_size: integer := 51; - bus_width : integer := 24); - port( - -- Inputs - clk, rstn : in std_logic; - en, start : in std_logic; - param : in std_logic_vector(7 downto 0); - addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(bus_width-1 downto 0); - we : in std_logic; - memdin : out std_logic_vector(13 downto 0); - -- Outputs - dout : out std_logic_vector(bus_width-1 downto 0); - memaddr : out std_logic_vector(5 downto 0); - memdout : out std_logic_vector(13 downto 0) - ); -end; - -architecture rtl of dsp is - signal foo : std_logic; - signal sr : std_logic_vector(63 downto 0); - signal iparam : integer; -begin - iparam <= to_integer(unsigned(param)); - process(clk) begin - -- dout <= std_logic_vector(to_unsigned(1,bus_width)); - if rising_edge(clk) then - if we = '1' then - sr <= sr(thing_size-bus_width-1 downto 0) & din; - end if; - dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width); - end if; - end process; -end rtl; diff --git a/src/test/vhdl/expr.vhd b/src/test/vhdl/expr.vhd deleted file mode 100644 index 103e762..0000000 --- a/src/test/vhdl/expr.vhd +++ /dev/null @@ -1,46 +0,0 @@ -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity expr is -generic(SIZE: positive:=2**8-1); -port(reset, sysclk, ival : in std_logic); -end expr; - -architecture rtl of expr is - constant SIZE_OF : positive:=2**8-1; - signal foo : std_logic_vector(13 downto 0); - signal baz : std_logic_vector(2 downto 0); - signal bam : std_logic_vector(22 downto 0); - signal out_i : std_logic_vector(5 downto 3); - signal input_status : std_logic_vector(8 downto 0); - signal enable, debug, aux, outy, dv, value : std_logic; - signal expo : std_logic_vector(2**3-1 downto 0); -begin - -- drive input status - input_status <= -- top bits - (foo(9 downto 4) & - (( (baz(2 downto 0) and foo(3 downto 0)) or - (not baz(2 downto 0) and bam(3 downto 0))))); - -- drive based on foo - out_i(4) <= - -- if secondary enabl is set then drive aux out - (enable and (aux xor outy)) or - -- if debug is enabled - (debug and dv and not enable) or - -- otherwise we drive reg - (not debug and not enable and value); - -- not drive - - pfoo: process(reset, sysclk) - begin - if( reset /= '0' ) then - foo <= (others => '0'); - elsif( sysclk'event and sysclk = '0' ) then - foo(3*(2-1)) <= baz(1*(1+2)-2); - bam(foo'range) <= foo; - end if; - end process; - - expo <= std_logic_vector(to_unsigned(2**4, 2**8)); -end rtl; diff --git a/src/test/vhdl/fifo.vhd b/src/test/vhdl/fifo.vhd deleted file mode 100644 index 112068f..0000000 --- a/src/test/vhdl/fifo.vhd +++ /dev/null @@ -1,202 +0,0 @@ ---------------------------------------------------------------------- --- Filename: gh_fifo_async16_sr.vhd --- --- Description: --- an Asynchronous FIFO --- --- Copyright (c) 2006 by George Huber --- an OpenCores.org Project --- free to use, but see documentation for conditions --- --- Revision History: --- Revision Date Author Comment --- -------- ---------- --------- ----------- --- 1.0 12/17/06 h lefevre Initial revision --- --------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -USE ieee.numeric_std.all; - -entity fifo is - GENERIC (data_width: INTEGER :=8 ); -- size of data bus - port ( - clk_WR : in STD_LOGIC; -- write clock - clk_RD : in STD_LOGIC; -- read clock - rst : in STD_LOGIC; -- resets counters - srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR) - WR : in STD_LOGIC; -- write control - RD : in STD_LOGIC; -- read control - D : in STD_LOGIC_VECTOR (data_width-1 downto 0); - Q : out STD_LOGIC_VECTOR (data_width-1 downto 0); - empty : out STD_LOGIC; - full : out STD_LOGIC); -end entity; - -architecture rtl of fifo is - - type ram_mem_type is array (15 downto 0) - of STD_LOGIC_VECTOR (data_width-1 downto 0); - signal ram_mem : ram_mem_type; - signal iempty : STD_LOGIC; - signal ifull : STD_LOGIC; - signal add_WR_CE : std_logic; - signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM - signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare - signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags - signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk - signal add_RD_CE : std_logic; - signal add_RD : std_logic_vector(4 downto 0); - signal add_RD_GC : std_logic_vector(4 downto 0); - signal add_RD_GCwc : std_logic_vector(4 downto 0); - signal n_add_RD : std_logic_vector(4 downto 0); - signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk - signal srst_w : STD_LOGIC; - signal isrst_w : STD_LOGIC; - signal srst_r : STD_LOGIC; - signal isrst_r : STD_LOGIC; - -begin - --------------------------------------------- -------- memory ----------------------------- --------------------------------------------- - -process (clk_WR) -begin - if (rising_edge(clk_WR)) then - if ((WR = '1') and (ifull = '0')) then - --ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D; - end if; - end if; -end process; - - --Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0)))); - ------------------------------------------ ------ Write address counter ------------- ------------------------------------------ - - add_WR_CE <= '0' when (ifull = '1') else - '0' when (WR = '0') else - '1'; - - n_add_WR <= std_logic_vector(unsigned(add_WR) + x"1"); - -process (clk_WR,rst) -begin - if (rst = '1') then - add_WR <= (others => '0'); - add_RD_WS <= "11000"; - add_WR_GC <= (others => '0'); - elsif (rising_edge(clk_WR)) then - add_RD_WS <= add_RD_GCwc; - if (srst_w = '1') then - add_WR <= (others => '0'); - add_WR_GC <= (others => '0'); - elsif (add_WR_CE = '1') then - add_WR <= n_add_WR; - add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1); - add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2); - add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3); - add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4); - add_WR_GC(4) <= n_add_WR(4); - else - add_WR <= add_WR; - add_WR_GC <= add_WR_GC; - end if; - end if; -end process; - - full <= ifull; - - ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000" - '0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000" - '1'; - ------------------------------------------ ------ Read address counter -------------- ------------------------------------------ - - add_RD_CE <= '0' when (iempty = '1') else - '0' when (RD = '0') else - '1'; - - n_add_RD <= std_logic_vector(unsigned(add_RD) + x"1"); - -process (clk_RD,rst) -begin - if (rst = '1') then - add_RD <= (others => '0'); - add_WR_RS <= (others => '0'); - add_RD_GC <= (others => '0'); - add_RD_GCwc <= "11000"; - elsif (rising_edge(clk_RD)) then - add_WR_RS <= add_WR_GC; - if (srst_r = '1') then - add_RD <= (others => '0'); - add_RD_GC <= (others => '0'); - add_RD_GCwc <= "11000"; - elsif (add_RD_CE = '1') then - add_RD <= n_add_RD; - add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1); - add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2); - add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3); - add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4); - add_RD_GC(4) <= n_add_RD(4); - add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1); - add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2); - add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3); - add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4)); - add_RD_GCwc(4) <= (not n_add_RD(4)); - else - add_RD <= add_RD; - add_RD_GC <= add_RD_GC; - add_RD_GCwc <= add_RD_GCwc; - end if; - end if; -end process; - - empty <= iempty; - - iempty <= '1' when (add_WR_RS = add_RD_GC) else - '0'; - ----------------------------------- ---- sync rest stuff -------------- ---- srst is sync with clk_WR ----- ---- srst_r is sync with clk_RD --- ----------------------------------- - -process (clk_WR,rst) -begin - if (rst = '1') then - srst_w <= '0'; - isrst_r <= '0'; - elsif (rising_edge(clk_WR)) then - isrst_r <= srst_r; - if (srst = '1') then - srst_w <= '1'; - elsif (isrst_r = '1') then - srst_w <= '0'; - end if; - end if; -end process; - -process (clk_RD,rst) -begin - if (rst = '1') then - srst_r <= '0'; - isrst_w <= '0'; - elsif (rising_edge(clk_RD)) then - isrst_w <= srst_w; - if (isrst_w = '1') then - srst_r <= '1'; - else - srst_r <= '0'; - end if; - end if; -end process; - -end architecture; diff --git a/src/test/vhdl/forgen.vhd b/src/test/vhdl/forgen.vhd deleted file mode 100644 index 61f11fe..0000000 --- a/src/test/vhdl/forgen.vhd +++ /dev/null @@ -1,52 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; - -entity forgen is - generic( - bus_width : integer := 15; - TOP_GP2 : integer:= 0 - ); - port( - sysclk, reset, wrb : in std_logic; - din : in std_logic_vector(bus_width downto 0); - rdout: out std_logic_vector(bus_width downto 0) - ); -end forgen; - -architecture rtl of forgen is - component wbit1 -- register bit default 1 - port( - clk : in std_logic; - wrb : in std_logic; - reset : in std_logic; - enb : in std_logic; - din : in std_logic; - dout : out std_logic); - end component; - - signal regSelect : std_logic_vector(bus_width * 2 downto 0); -begin - ----------------------------------------------------- - -- Reg : GP 2 - -- Active : 32 - -- Type : RW - ----------------------------------------------------- - reg_gp2 : for bitnum in 0 to bus_width generate - wbit1_inst : wbit1 - PORT MAP( - clk => sysclk, - wrb => wrb, - reset => reset, - enb => regSelect(TOP_GP2), - din => din(bitnum), - dout => rdout(bitnum) - ); - end generate; - - process(sysclk) begin - if sysclk'event and sysclk = '1' then - regSelect(1) <= '1'; - end if; - end process; - -end rtl; diff --git a/src/test/vhdl/forloop.vhd b/src/test/vhdl/forloop.vhd deleted file mode 100644 index 492ec27..0000000 --- a/src/test/vhdl/forloop.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity forloop is port( - reset, sysclk : in std_logic -); -end forloop; - -architecture rtl of forloop is - signal selection : std_logic; - signal egg_timer : std_logic_vector(6 downto 0); -begin - TIMERS : - process(reset, sysclk) - variable timer_var : integer; - variable a, i, j, k : integer; - variable zz5 : std_logic_vector(31 downto 0); - variable zz : std_logic_vector(511 downto 0); - begin - if reset = '1' then - selection <= '1'; - timer_var := 2; - egg_timer <= (others => '0'); - elsif sysclk'event and sysclk = '1' then - -- pulse only lasts for once cycle - selection <= '0'; - egg_timer <= (others => '1'); - for i in 0 to j*k loop - a := a + i; - for k in a-9 downto -14 loop - zz5 := zz(31+k downto k); - end loop; -- k - end loop; -- i - end if; - end process; -end rtl; diff --git a/src/test/vhdl/formatter_vhdl.vhd b/src/test/vhdl/formatter_vhdl.vhd deleted file mode 100644 index e69de29..0000000 diff --git a/src/test/vhdl/genericmap.vhd b/src/test/vhdl/genericmap.vhd deleted file mode 100644 index 3038f88..0000000 --- a/src/test/vhdl/genericmap.vhd +++ /dev/null @@ -1,105 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -entity genericmap is -generic( - rst_val : std_logic := '0'; - thing_size: integer := 201 rem 2; - bus_width : integer := 201 mod 32); -port( - clk, rstn : in std_logic; - en, start_dec : in std_logic; - addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(25 downto 0); - we : in std_logic; - pixel_in : in std_logic_vector(7 downto 0); - pix_req : in std_logic; - bip : in std_logic; - a, b : in std_logic_vector(7 downto 0); - c, load : in std_logic_vector(7 downto 0); - pack : in std_logic_vector(6 downto 0); - base : in std_logic_vector(2 downto 0); - qtd : in std_logic_vector(21 downto 0); - -- Outputs - dout : out std_logic_vector(25 downto 0); - pixel_out : out std_logic_vector(7 downto 0); - pixel_valid : out std_logic; - code : out std_logic_vector(9 downto 0); - complex : out std_logic_vector(23 downto 0); - eno : out std_logic -); -end genericmap; -architecture rtl of genericmap is - - component dsp - generic( - rst_val : std_logic := '0'; - thing_size: integer := 201; - bus_width : integer := 24); - port( - -- Inputs - clk, rstn : in std_logic; - en, start : in std_logic; - param : in std_logic_vector(7 downto 0); - addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(bus_width-1 downto 0); - we : in std_logic; - memdin : out std_logic_vector(13 downto 0); - -- Outputs - dout : out std_logic_vector(bus_width-1 downto 0); - memaddr : out std_logic_vector(5 downto 0); - memdout : out std_logic_vector(13 downto 0) - ); - end component; - signal param : std_logic_vector(7 downto 0); - signal selection : std_logic; - signal start, enf : std_logic; -- Start and enable signals - signal memdin : std_logic_vector(13 downto 0); - signal memaddr : std_logic_vector(5 downto 0); - signal memdout : std_logic_vector(13 downto 0); - signal colour : std_logic_vector(1 downto 0); -begin - dsp_inst0 : dsp - -- default bus_width is 24 - port map( - -- Inputs - clk => clk, - rstn => rstn, - en => '1', - start => '0', - param => X"42", - addr => "101", - din => "000100010001000100010001", - we => '0', - -- Outputs - dout => dout(23 downto 0), - memaddr => memaddr, - memdout => memdout - ); - - dsp_inst1 : dsp - generic map( - rst_val => '1', - bus_width => 16) - port map( - -- Inputs - clk => clk, - rstn => rstn, - en => '1', - start => '0', - param => X"42", - addr => "101", - din => "0001000100010001", - we => '0', - -- Outputs - dout => dout(15 downto 0), - memaddr => memaddr, - memdout => memdout - ); - - signextend_inst2 : entity work.signextend - port map ( - i => "0000000000000000", - o => open - ); - -end rtl; diff --git a/src/test/vhdl/ifchain.vhd b/src/test/vhdl/ifchain.vhd deleted file mode 100644 index a830272..0000000 --- a/src/test/vhdl/ifchain.vhd +++ /dev/null @@ -1,26 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; - -entity ifchain is port( - clk, rstn : in std_logic -); -end ifchain; - -architecture rtl of ifchain is - type t is array (3 downto 0) of std_logic_vector(31 downto 0); - signal a : std_logic_vector(3 downto 0); - signal b : std_logic_vector(3 downto 0); - signal status : std_logic; - signal c : t; -begin - - process(clk) begin - if clk'event and clk = '1' then - if b(1) & a(3 downto 2) = "001" then - status <= '1'; - c(0) <= x"FFFFFFFF"; - end if; - end if; - end process; - -end rtl; diff --git a/src/test/vhdl/ifchain2.vhd b/src/test/vhdl/ifchain2.vhd deleted file mode 100644 index b002568..0000000 --- a/src/test/vhdl/ifchain2.vhd +++ /dev/null @@ -1,36 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity ifchain2 is port( - clk, rstn : in std_logic; - enable: in std_logic; - result: out std_logic -); -end ifchain2; - -architecture rtl of ifchain2 is - signal counter : unsigned(3 downto 0); - constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4); -begin - -clk_src : process(clk, rstn) is -begin - if (rstn = '0') then - counter <= (others => '0'); - result <= '0'; - elsif (rising_edge(clk)) then -- Divide by 2 by default - if (enable = '1') then - if (counter = 0) then - counter <= CLK_DIV_VAL; - result <= '1'; - else - counter <= counter - 1; - result <= '0'; - end if; -- counter - end if; -- enable - end if; -- clk, rst_n -end process clk_src; -assert (counter < CLK_DIV_VAL) report "test case" severity error; - -end rtl; diff --git a/src/test/vhdl/mem.vhd b/src/test/vhdl/mem.vhd deleted file mode 100644 index ca0afef..0000000 --- a/src/test/vhdl/mem.vhd +++ /dev/null @@ -1,36 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity mem is -generic( - addr_width : integer := 6; - bus_width : integer := 14 -); - port ( - clk : in std_logic; - rstn : in std_logic; -- not implemented - en : in std_logic; - cs : in std_logic; -- not implemented - addr : in unsigned(addr_width-1 downto 0); - din : in unsigned(bus_width-1 downto 0); - dout : out unsigned(bus_width-1 downto 0) - ); -end entity; - -architecture rtl of mem is - signal al : unsigned(addr_width-1 downto 0) := X"00"; - type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0); - signal mem : mem_Type; -begin - dout <= mem(to_integer(al)); - process (clk) is - begin - if rising_edge(clk) then - al <= addr; - if en = '1' then - mem(to_integer(addr)) <= din; - end if; - end if; - end process; -end architecture; diff --git a/src/test/vhdl/operators.vhd b/src/test/vhdl/operators.vhd deleted file mode 100644 index 8922cc1..0000000 --- a/src/test/vhdl/operators.vhd +++ /dev/null @@ -1,85 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity operators is - generic ( - g_and : std_logic_vector(1 downto 0) := "11" and "10"; - g_or : std_logic_vector(1 downto 0) := "11" or "10"; - g_nand : std_logic_vector(1 downto 0) := "11" nand "10"; - g_nor : std_logic_vector(1 downto 0) := "11" nor "10"; - g_xor : std_logic_vector(1 downto 0) := "11" xor "10"; - g_xnor : std_logic_vector(1 downto 0) := "11" xnor "10"; - g_not : std_logic_vector(1 downto 0) := not "10" - ); - port ( - clk_i : in std_logic - ); -end entity operators; - -architecture rtl of operators is - constant c_and : std_logic_vector(1 downto 0) := "11" and "10"; - constant c_or : std_logic_vector(1 downto 0) := "11" or "10"; - constant c_nand : std_logic_vector(1 downto 0) := "11" nand "10"; - constant c_nor : std_logic_vector(1 downto 0) := "11" nor "10"; - constant c_xor : std_logic_vector(1 downto 0) := "11" xor "10"; - constant c_xnor : std_logic_vector(1 downto 0) := "11" xnor "10"; - constant c_not : std_logic_vector(1 downto 0) := not "10"; - signal s_op1 : std_logic_vector(1 downto 0); - signal s_op2 : std_logic_vector(1 downto 0); - signal s_res : std_logic_vector(1 downto 0); - signal s_int : integer; - signal s_sig : signed(7 downto 0); - signal s_uns : unsigned(7 downto 0); -begin - - test_i: process(clk_i) - variable v_op1 : std_logic_vector(1 downto 0); - variable v_op2 : std_logic_vector(1 downto 0); - variable v_res : std_logic_vector(1 downto 0); - begin - if rising_edge(clk_i) then - if - (s_op1="11" and s_op2="00") or - (s_op1="11" or s_op2="00") or - (s_op1="11" nand s_op2="00") or - (s_op1="11" nor s_op2="00") or - (not (s_op1="11")) - then - s_res <= s_op1 and s_op2; - s_res <= s_op1 or s_op2; - v_res := v_op1 nand v_op2; - v_res := v_op1 nor v_op2; - s_res <= s_op1 xor s_op2; - v_res := v_op1 xnor v_op2; - s_res <= not s_op1; - s_int <= abs(s_int); - s_sig <= abs(s_sig); - s_sig <= s_sig sll 2; - s_sig <= s_sig srl to_integer(s_sig); - s_uns <= s_uns sll to_integer(s_uns); - s_uns <= s_uns srl 9; - s_sig <= shift_left(s_sig,2); - s_sig <= shift_right(s_sig,to_integer(s_sig)); - -- s_uns <= s_uns ror 3; -- Not yet implemented - -- s_uns <= s_uns rol to_integer(s_uns); -- Not yet implemented - -- s_uns <= rotate_right(s_uns,3); -- Not yet implemented - -- s_uns <= rotate_left(s_uns,to_integer(s_uns)); -- Not yet implemented - s_sig <= s_sig rem s_int; - s_sig <= s_sig mod s_int; - end if; - if - s_sig = signed(s_uns) or unsigned(s_sig) /= s_uns or s_sig < "101010101" or - s_sig <= signed(s_uns) or unsigned(s_sig) > s_uns or s_sig >= "00000101" - then - s_sig <= s_sig + s_sig; - s_sig <= s_sig - s_sig; - s_sig <= s_sig * s_sig; - s_sig <= s_sig / s_sig; - s_sig <= s_sig(7 downto 4) & "10" & signed(s_uns(1 downto 0)); - s_int <= 2 ** 3; - end if; - end if; - end process test_i; - -end architecture rtl; diff --git a/src/test/vhdl/partselect.vhd b/src/test/vhdl/partselect.vhd deleted file mode 100644 index 90c67b2..0000000 --- a/src/test/vhdl/partselect.vhd +++ /dev/null @@ -1,32 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -entity partselect is - port( - clk_i : in std_logic - ); -end entity partselect; - -architecture rtl of partselect is - signal big_sig : std_logic_vector(31 downto 0); - signal lit_sig : std_logic_vector(0 to 31); - signal i : integer:=8; -begin - - test_i: process(clk_i) - variable big_var : std_logic_vector(31 downto 0); - variable lit_var : std_logic_vector(0 to 31); - variable j : integer; - begin - if rising_edge(clk_i) then - big_sig(31 downto 24) <= big_sig(7 downto 0); - big_var(31 downto 24) := big_var(7 downto 0); - lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7); - lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0); - -- - big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0); - big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0); - end if; - end process test_i; - -end architecture rtl; diff --git a/src/test/vhdl/signextend.vhd b/src/test/vhdl/signextend.vhd deleted file mode 100644 index 48b7130..0000000 --- a/src/test/vhdl/signextend.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity signextend is - port( - i : in std_logic_vector(15 downto 0); - o : out std_logic_vector(31 downto 0) - ); -end entity signextend; - -architecture behavior of signextend is -begin - o(31 downto 24) <= (others => '0'); - o(23 downto 16) <= (others => i(15)); - o(15 downto 0) <= i; -end architecture behavior; diff --git a/src/test/vhdl/test.vhd b/src/test/vhdl/test.vhd deleted file mode 100644 index 236fcae..0000000 --- a/src/test/vhdl/test.vhd +++ /dev/null @@ -1,191 +0,0 @@ --- Project: VHDL to Verilog RTL translation --- Revision: 1.0 --- Date of last Revision: February 27 2001 --- Designer: Vincenzo Liguori --- vhd2vl test file --- This VHDL file exercises vhd2vl - -LIBRARY IEEE; - -USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; - -entity test is port( - -- Inputs - clk, rstn : in std_logic; - en, start_dec : in std_logic; - addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(25 downto 0); - we : in std_logic; - pixel_in : in std_logic_vector(7 downto 0); - pix_req : in std_logic; - config1, bip : in std_logic; - a, b : in std_logic_vector(7 downto 0); - c, load : in std_logic_vector(7 downto 0); - pack : in std_logic_vector(6 downto 0); - base : in std_logic_vector(2 downto 0); - qtd : in std_logic_vector(21 downto 0); - -- Outputs - dout : out std_logic_vector(23 downto 0); - pixel_out : out std_logic_vector(7 downto 0); - pixel_valid : out std_logic; - code : out std_logic_vector(9 downto 0); - code1 : out std_logic_vector(9 downto 0); - complex : out std_logic_vector(23 downto 0); - eno : out std_logic -); -end test; - -architecture rtl of test is - --- Components declarations are ignored by vhd2vl --- but they are still parsed - -component dsp port( - -- Inputs - clk, rstn : in std_logic; - en, start : in std_logic; - param : in std_logic_vector(7 downto 0); - addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(23 downto 0); - we : in std_logic; - memdin : out std_logic_vector(13 downto 0); - -- Outputs - dout : out std_logic_vector(23 downto 0); - memaddr : out std_logic_vector(5 downto 0); - memdout : out std_logic_vector(13 downto 0) -); -end component; - -component mem port( - -- Inputs - clk, rstn : in std_logic; - en : in std_logic; - cs : in std_logic; - addr : in std_logic_vector(5 downto 0); - din : in std_logic_vector(13 downto 0); - -- Outputs - dout : out std_logic_vector(13 downto 0) -); -end component; - - type state is (red, green, blue, yellow); - signal status : state; - constant PARAM1 : std_logic_vector(7 downto 0):="01101101"; - constant PARAM2 : std_logic_vector(7 downto 0):="11001101"; - constant PARAM3 : std_logic_vector(7 downto 0):="00010111"; - signal param : std_logic_vector(7 downto 0); - signal selection : std_logic := '0'; - signal start, enf : std_logic; -- Start and enable signals - signal memdin : std_logic_vector(13 downto 0); - signal memaddr : std_logic_vector(5 downto 0); - signal memdout : std_logic_vector(13 downto 0); - signal colour : std_logic_vector(1 downto 0); -begin - - param <= PARAM1 when config1 = '1' else PARAM2 when status = green else PARAM3; - - -- Synchronously process - process(clk) begin - if clk'event and clk = '1' then - pixel_out <= pixel_in xor "11001100"; - end if; - end process; - - -- Synchronous process - process(clk) begin - if rising_edge(clk) then - case status is - when red => colour <= "00"; - when green => colour <= B"01"; - when blue => colour <= "10"; - when others => colour <= "11"; - end case; - end if; - end process; - - -- Synchronous process with asynch reset - process(clk,rstn) begin - if rstn = '0' then - status <= red; - elsif rising_edge(clk) then - case status is - when red => - if pix_req = '1' then - status <= green; - end if; - when green => - if a(3) = '1' then - start <= start_dec; - status <= blue; - elsif (b(5) & a(3 downto 2)) = "001" then - status <= yellow; - end if; - when blue => - status <= yellow; - when others => - start <= '0'; - status <= red; - end case; - end if; - end process; - - -- Example of with statement - with memaddr(2 downto 0) select - code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110", - "11100010" when "101", - (others => '1') when "010", - (others => '0') when "011", - std_logic_vector(unsigned(a) + unsigned(b)) when others; - code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); - - -- Asynch process - decode : process(we, addr, config1, bip) begin - if we = '1' then - if addr(2 downto 0) = "100" then - selection <= '1'; - elsif (b & a) = a & b and bip = '0' then - selection <= config1; - else - selection <= '1'; - end if; - else - selection <= '0'; - end if; - end process decode; - - -- Components instantiation - dsp_inst : dsp port map( - -- Inputs - clk => clk, - rstn => rstn, - en => en, - start => start, - param => param, - addr => addr, - din => din(23 downto 0), - we => we, - memdin => memdin, - -- Outputs - dout => dout, - memaddr => memaddr, - memdout => memdout - ); - - dsp_mem : mem port map( - -- Inputs - clk => clk, - rstn => rstn, - en => en, - cs => selection, - addr => memaddr, - din => memdout, - -- Outputs - dout => memdin - ); - - complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; - - enf <= '1' when c < "1000111" else '0'; - eno <= enf; - -end rtl; diff --git a/src/test/vhdl/todo.vhd b/src/test/vhdl/todo.vhd deleted file mode 100644 index 7b05d2a..0000000 --- a/src/test/vhdl/todo.vhd +++ /dev/null @@ -1,74 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity todo is - generic( - INBYLEVEL : boolean:=FALSE - ); - port ( - clk_i : in std_logic; - data_i : in std_logic_vector(7 downto 0); - data_o : out std_logic_vector(7 downto 0) - ); -end todo; - -architecture rtl of todo is - type mem_type is array (0 to 255) of integer; - signal mem : mem_type; - - signal int : integer; - signal uns : unsigned(7 downto 0); - - constant BYTES : positive:=4; - constant WIDTH : positive:=BYTES*8; - signal index : natural range 0 to BYTES-1; - signal comma : std_logic_vector(BYTES*3-1 downto 0); - - -- (others => (others => '0')) must be replaced by an initial block with a for - -- or something similar. - --type ff_array is array (0 to 255) of std_logic_vector(7 downto 0); - --signal data_r : ff_array :=(others => (others => '0')); -begin - --************************************************************************** - -- Wrong translations - --************************************************************************** - -- - test_i: process(clk_i) - -- iverilog: variable declaration assignments are only allowed at the module level. - variable i : integer:=8; - begin - for i in 0 to 7 loop - if i=4 then - exit; -- iverilog: error: malformed statement - end if; - end loop; - end process test_i; - -- indexed part-select not applied - do_boundary: process (clk_i) - begin - if rising_edge(clk_i) then - for i in 0 to BYTES-1 loop - if comma(BYTES*2+i-1 downto BYTES+i)=comma(3 downto 0) then - index <= i; - end if; - end loop; - end if; - end process; - comma <= comma(BYTES+index-1 downto index); - --************************************************************************** - -- Translations which abort with syntax error (uncomment to test) - --************************************************************************** - -- Concatenation in port assignament fail --- uns <= "0000" & X"1"; -- It is supported --- dut1_i: entity work.signextend --- port map ( --- i => "00000000" & X"11", -- But here fail --- o => open --- ); - -- Unsupported generate with boolean? --- in_by_level: --- if INBYLEVEL generate --- int <= 9; --- end generate in_by_level; -end rtl; diff --git a/src/test/vhdl/wbit1.vhd b/src/test/vhdl/wbit1.vhd deleted file mode 100644 index 12b1e38..0000000 --- a/src/test/vhdl/wbit1.vhd +++ /dev/null @@ -1,21 +0,0 @@ --- Nearly useless stub, it's here to support generate.vhd -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; - -entity wbit1 is - port( - clk : in std_logic; - wrb : in std_logic; - reset : in std_logic; - enb : in std_logic; - din : in std_logic; - dout : out std_logic); -end; - -architecture rtl of wbit1 is - signal foo : std_logic; -begin - process(clk) begin - dout <= '1'; - end process; -end rtl; diff --git a/src/test/vhdl/whileloop.vhd b/src/test/vhdl/whileloop.vhd deleted file mode 100644 index 44793e3..0000000 --- a/src/test/vhdl/whileloop.vhd +++ /dev/null @@ -1,27 +0,0 @@ -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity whileloop is port( - A : in integer; - Z : out std_logic_vector(3 downto 0) -); -end whileloop; - -architecture rtl of whileloop is -begin - -process (A) - variable I : integer range 0 to 4; -begin - Z <= "0000"; - I := 0; - while (I <= 3) loop - if (A = I) then - Z(I) <= '1'; - end if; - I := I + 1; - end loop; -end process; - -end rtl; diff --git a/src/test/vhdl/withselect.vhd b/src/test/vhdl/withselect.vhd deleted file mode 100644 index 48f6f0a..0000000 --- a/src/test/vhdl/withselect.vhd +++ /dev/null @@ -1,34 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; - -entity withselect is - generic( - dog_width : std_logic_vector(7 downto 0) := "10101100"; - bus_width : integer := 32 - ); - port( reset, sysclk : in std_logic; - a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) - ); -end withselect; - -architecture rtl of withselect is - signal foo : std_logic_vector(1+1 downto 0); - signal code,code1: std_logic_vector(9 downto 0); - signal egg : std_logic_vector(324 to 401); - signal baz : std_logic_vector(bus_width*3-1 to bus_width*4); - signal complex : std_logic_vector(31 downto 0); -begin - -- Example of with statement - with foo(2 downto 0) select - code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110", - "11100010" when "101", - (others => '1') when "010", - (others => '0') when "011", - std_logic_vector(unsigned(a) + unsigned(b)) when others; - code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); - - foo <= (others => '0'); - egg <= (others => '0'); - baz <= (others => '1'); - complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; -end rtl; diff --git a/src/test/vlog/dependence_test/.vscode/property.json b/src/test/vlog/dependence_test/.vscode/property.json deleted file mode 100644 index 276c76f..0000000 --- a/src/test/vlog/dependence_test/.vscode/property.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "toolChain": "xilinx", - "prjName": { - "PL": "template" - }, - "soc": { - "core": "none" - }, - "arch": { - "hardware": { - "sim": "./", - "src": "./" - } - }, - "enableShowLog": false, - "device": "none" -} \ No newline at end of file diff --git a/src/test/vlog/dependence_test/child_1.v b/src/test/vlog/dependence_test/child_1.v deleted file mode 100644 index 962b445..0000000 --- a/src/test/vlog/dependence_test/child_1.v +++ /dev/null @@ -1,17 +0,0 @@ -module dependence_1 ( - // this is a test - input a, b, c, - // a test - output Result // balabalabala for result -); - - // a & b | ((b & c) & (b | c)) - // &=*, |=+ AB + BC(B+C) - // Distribute AB + BBC + BCC - // Simplify AA = A AB + BC + BC - // Simplify A + A = A AB + BC - // Factor B(A+C) - - assign Result = a & (b | c); - -endmodule \ No newline at end of file diff --git a/src/test/vlog/dependence_test/child_2.v b/src/test/vlog/dependence_test/child_2.v deleted file mode 100644 index 72b0112..0000000 --- a/src/test/vlog/dependence_test/child_2.v +++ /dev/null @@ -1,8 +0,0 @@ -module dependence_2 ( - input a, b, c, - output Q -); - - assign Q = a & b | ((b & c) & (b | c)); - -endmodule \ No newline at end of file diff --git a/src/test/vlog/dependence_test/head_1.v b/src/test/vlog/dependence_test/head_1.v deleted file mode 100644 index 8543ebd..0000000 --- a/src/test/vlog/dependence_test/head_1.v +++ /dev/null @@ -1,23 +0,0 @@ -`define cow 34 - -module dependence_1 ( - input port_a, port_b, port_c, - output out_q -); - // a & b | ((b & c) & (b | c)) - // &=*, |=+ AB + BC(B+C) - // Distribute AB + BBC + BCC - // Simplify AA = A AB + BC + BC - // Simplify A + A = A AB + BC - // Factor B(A+C) - - assign out_q = port_b & (port_a | port_c); -endmodule - - -module test_1 ( - input port_a, port_b, - output Q -); - assign Q = port_b & port_a; -endmodule \ No newline at end of file diff --git a/src/test/vlog/dependence_test/hello.v b/src/test/vlog/dependence_test/hello.v deleted file mode 100644 index 92f23ac..0000000 --- a/src/test/vlog/dependence_test/hello.v +++ /dev/null @@ -1,6 +0,0 @@ -module hello; - initial begin - $display("hello world"); - $finish; - end -endmodule \ No newline at end of file diff --git a/src/test/vlog/dependence_test/parent.v b/src/test/vlog/dependence_test/parent.v deleted file mode 100644 index 7170374..0000000 --- a/src/test/vlog/dependence_test/parent.v +++ /dev/null @@ -1,69 +0,0 @@ -/* - * EN: A simple demo to test search order of dependence - * current file -> macro include -> whole project - * expect dependence_1 from child_1.v (macro include) - * expect dependence_2 from child_2.v (whole project) - * cannot find dependence_3 `main - */ - -`include "child_1.v" -`include "child_2.v" -`define main out - -module Main ( - // Main input - input a, b, c, - // Main output - output Qus, Qs, `main -); - -dependence_1 u_dependence_1( - .a(a), - .b(b), - .c(c), - .Result(Qus) -); - -dependence_2 u_dependence_2( - .a(a), - .b(b), - .c(c), - .Q(Qs) -); - -dependence_3 u_dependence_3( - .a(a), - .b(b), - .c(c), - .Q(Qs) -); - -endmodule - - -/* @wavedrom this is wavedrom demo1 -{ - signal : [ - { name: "clk", wave: "p......" }, - { name: "bus", wave: "x.34.5x", data: "head body tail" }, - { name: "wire", wave: "0.1..0." } - ] -} -*/ - - -/* @wavedrom this is wavedrom demo2 -{ - signal: [ - { name: "pclk", wave: "p......." }, - { name: "Pclk", wave: "P......." }, - { name: "nclk", wave: "n......." }, - { name: "Nclk", wave: "N......." }, - {}, - { name: "clk0", wave: "phnlPHNL" }, - { name: "clk1", wave: "xhlhLHl." }, - { name: "clk2", wave: "hpHplnLn" }, - { name: "clk3", wave: "nhNhplPl" }, - { name: "clk4", wave: "xlh.L.Hx" }, -]} -*/ \ No newline at end of file diff --git a/src/test/vlog/dependence_test/pdf/parent.pdf b/src/test/vlog/dependence_test/pdf/parent.pdf deleted file mode 100644 index 356b431d084d3030bd8d956873172a1cf4e90f5c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 95015 zcmdSAWmH{TvnGrO5AL#Ych}(V?(Xgu+#x`4m*5cGg1dWg2n5#v!QFcAoO8eTzPC^J z===TZ9wTe7S@o=%QuRz_hC)e9f`NsR9iC$D_-G5B1;7k&G_ir_=VuaiF*kN|bOBI{ zTDdsdTf5uSz%wbiIGVYengf-pw${c>KwE%43kwGj`SZ24ql1{Sn>m15jF**}m5rI3 zg^Pugm4}6cj+vPX_z(D%l502yk@+w#pvfD|^uI=hQB@ z%ihZ!hIeP6E4d1(xDj(;`zgz9U(fFX@DD;CPs5bWdv2c~gFf7{*dJ+^A9n`du->h=71v-3glb|>RP(feF|j6&efT>5kN z>LtCk;^(*LZsND=4@7Scn!5*?C!cRMVB2sd|I2;NMf8WBs}s; zx1-Y?%^G(Zw+*T+?teWq<{TI=-1-&zp|q)Wp2;VDB7C$p04-!Sa>X(7Goj$8=ud1G zsm~!1(|5|8^hS#Mq3RiScPYOY%rGkqU$%d8xSTMCWzH62XzKCl!MJBuwngi{5n!BE zR6E2tbI6%p39ea{z$FRDT)jO%CZrA;`t?>=u8gn0CCWv4(@3U}0BoOF%?>8fCT71C zjx;8&Fj1t3%|)C@?WHefY$EYw87h&%`8PCXmT^bk{&eHA=FT9i9@pVyfi^RzX^I}5 zHK8jzR-xPxX*=+9fgJg<7)Sd%5i2Y7!8L~fVOAxp-P^Nw@`Lr#@2zqa4uq1zMJMa- zMT^B$^Y_z=uf5wWPB2m)D|J0^?8yN86?R79v_u(IZF}L4&x4%3$;;32mB{&c6Ii( zSL>&2b{4D+uGS_$?N?tGczp|>z>8We{Jt9k`j;vAkD0YEwA~0jvDfsXkG6l!sgpE# z+f(@d*fg)`di8g|d+je?1()G2EE=~H%k%zR${6zdW!oJGN`x(u?io=&ZRLYfCazmQ zX7R%(CSpWq{}`p7Em%Ak!vX{qbT++Y+H%HKXa0)D0r^YPt13&>iv+mN6~r@`P6W}2AftCLmfo1hD)-1 zGU~%@yi|fI3j}oF+yNv*KQ*Mwx|b%>4<}!U3x&F=?Fo| z=nzV4z2$ekxj^e6&7@x6ioV*>weM_3H7oie2|vYt^NfKV-v-B$xI1E~XnT78P;a$l z=$f~;ph*&;LeHscdKWXh?sGko2{&6r6e3e>>)KA3V>ico$bEMF#q=YzB=zXVfk3aM z9@zm-eA9~y+oz-;wrq{{<{-&zL9_FnjJT_=_vs}vmj=9Y5!-;HtwOx1k2gZLCI};e zeKu?%fcHP`Ss9BoIl~c+z7OcLlAa6=#X}fz8k>%QiOC;w>zZvG;`GrGih2|SHL2dw zlu|Wr**~+UM^4W4#J%?1_ziO4u!mvky`3Nm8H+?%6{*f&eVYw zYmoueE3v-IKG90ep~D_r3>CGLff|GRh*SgM>(;tfe@RHYnmvWQLt!Ts1+D|?xDj`wV+rplB%D)1pJ>R_^tukTD0s88sF zTV#PTyA!x{;OwlwbXe@JXEpQG;52NhyNuJH9vF*X(_Sgr{z%jWZPv4`Z)b5A0IZgQ zHf}u~-C1NEKAotKx%mh$K|+e>r!!=|zA+S!P%=8v#f11u#0=4WH3wGXVGSBN;e8x> zX!>afeMPUmdHOt4#;J?+%Hdd!iUY)uJadZP>3Xv*OJ#-g2I`Al%b9P0(q#%}jT3Aw zIaxZJIjYFBYr@%{Bl9a5#*Tyukx~lCna-3799T0B7{ry&`4sG1)usR#-TdXxH?+=-2e@6xZ~jSl9Fe*w^$JJbPWjC5aT%-q*C( zzTwwPpV=l#H#Jadon7hBwa6!oTKl4z{Ov_%-tk_N*9Hhl9$-U#&(c^S^z09pgm?x?yj7H76w+2Wk3E{-zW6ev+ zCIJ-Mc*mOp&S`MNsnPV7-WMrFca1SPSzdERWVWRJCF)u}iq^Gm)~iO=ANP=zCCWc` z*Rh*pS-YSwg`FGq2#`Ax4chpL&%`2A#HHhzt6W#PmVSYkE3{v^q7dZeS2 zViHJZGv_oLhb0m*LWEg5Sy7Lle41(;H6JZufe-LYq?OoWl7VlYDLt+kFAdUx8cqwd zH;qWCsng>3<6ht>9d&@H31%%F4K#WNS*%p7Jt)~vXo{&=_6Yvb`Vdxw{@^2xjUrrr z!2rdLgzcmA`qr@@IdxXbSqgOSt4?R-efU9urcGF!a$HF(YiAx4rLW&ni&d(^1#*h- zl3`@o*25+tu|sblh1msQ%M$oW0n(ST=2YD`(s^Y(js@?!6v*WXQt9bX zK8_7T{K#kt0>Ay8pRnm(E!B{Oq_NUi!f?`G!09bB{=p`C%uCK;w8^~FOXl_dZsS_%r(mw#iaQVe*u-}%q6nJJ3K>~Ww%_{`h9a3H z9JQ-P^=54oy0rIJeZk5fg4`D|^JE7n?8`oj1mj+ooztQ3z|9y#cmZTU)fN3e-?;)?&p zbOwVC>$40Q-@s%YVJ|Cs{X*Tfszts}i^HS+qAE%80~y{Gw+!lw#g)KOEEsDAiGQ55 z{Zr3GW8BlzF49<@eVCzZ)WSE^a{6kn8Hqu*k--8v4o#L=%v#T1%d8n~q~_vP2aOTv zADc4L$MIMY$8qm|SaKO2e&rMlQ(psLieT3}7>__y;?jI?f$7QG=yY>f6vM8^CulLT zp>{atJtA`a`&aqbq_!RNgCHe?pHCd`m7N*Ik`A?Z5rK6!pG4bAy?ExCNp@<8u`G6)wu_~?WLYnv(kUCw z2C=%1tL*NK%5$N6c|}V`W6wU55!ZpCr<6`!m(?qvXNs<>A6F*13n+Q^QA%J~sf=5H zR^b|yPjVO``o<1fI;vc^Lb=JFuiM4fYyDfbO>u-qMOcB5Bv|e@W^dUQ+R3~)l-DmG zNO(0KD5M3`o=?B{z|>;NV85pF*U8Hh;ZU!W;LzrhhJa>IK}+Z`boGlxYao(Iemgw{AAA5;x#5JA3c-m8#EVOx_N5l-Z#gp zXZ`Id-rzi0Wl$A2$cvVX?2C&@bZI^8c6nu*7ws4-Kc)bhqWH$ZoN@M=1wW=NOm6gO zROvNxuj&PPuc|vQGT;^06U`7yPQB*6lDQkKGjn{hDUO?nWXyD+I+8`NI+8ENK-z>i zWX80p22L3W73!&?)_@o8I9g$U+JzJ8-o3u0$D^VWocRfWmv$f{h zCA?NwExL1hF!sw$YS|qookM|xw){HF*4B4vu1Jl=yV%yi-@T|SZDnPfZ=Wt`zf#pa z?jWp60;28cEqx{JYC~Fi80psRHsnU)fcT; z<@?+I?S(ck`g6^;=~rJFa&ciXQbrjnRXd3U@dEB>mKYBWdkk!?4U*tmWVda^WASK7 zWli|a#7kAMY>cl^fZ{R=u=1N46x)3I-$mja8A({1L%U5%*tYYTxn-iq0r@;t7~#=P zU#S=4AWNP+mN@*Rfk7@7GJrnA9wb>= zfJ1?W$c(Ovetn1upLq>{mVd;nd7l=u`rX}K#LamsCm&FWBFuIn8Hyc6S)g=Jz3pyM z%~qeXW8l0+C@k1K|G?L?PxqE5lLL{p0bfDwWd$bTY!9%`jwY}^x)_WWnh6<@!m=(Slg-Oe-jah5KSqE}E6%ST zh4EY_NQ0y@Q%U+&zGzeGY4qEt)ctR=;Os@{fi7U+O6xKx>=qp0)Yt&9v0^l#@)S6s za$#^K8y&FZrb##5lFyCOr&zm+RJPJ-cMqQHr3$d=R!9Mht0 zDEp%VjPflYkg(jLjI>_i04DiX!IjiBaBbp8(njYkB>QUf7z8P^*q)D-@pYsy1yny#D4UxphYd<$8P3uj7OCYYEscl&?ub2k zDoE!!MJY_D(H(UST646f$wd+(@G`@UOKClV)vW*3o)Bn#DTOd2&8`;}MJyPz$t$jdc&n!$os?bTsW z&R5;DHTRdBq1}>d&hJ?BD_3J>*xtP6Bc;;zf=Nfgxuf-T^o|5f9IwJtwZ?So`h{-} z(?}?p})pk^CYP-SgO!2 z)U|w`pBakTccCn0Olj3Bm_HZ8RXIUul2&G(r`r={3B|zcH>rn17$2jg_cfxm3h$PK zmiMjUZ*Ki^Wa#=~KbW#BR_)eS7=5Gf>y`3UsAHggS~O*siUyM;k81T%>!T+?qCZ~BIs%961< zfKkaLG&78Y8(*#mX0>{q!UXO+)rG08ttjEYiQMJjJ< zTap&1peUQBu;!Mc^(s{>JPXhmuETB{$#HBJFY~p;Xk(4}ep-elnCDSg0q1;KLIA1k zZw%D3q(q|yXfds06|z@#1~K@BO*opbzXFLkK7A?4WHwTbC2XPcCuyM(ByXWv$6A`B zQC!A2z+A)N`aCMj4aLIj5GsUYWQGSriW^13=d20UT)Rfc*%2~wkjftLZr6A3RcBUh z_gOiXN!eO7U`(4Pd<-Hozh2FxtW2C)jU5Mv_A6z$jJhg|nw%6OrYXAU5q5C? zwrFtvF9!l4f~!#F8{=N(8&BgPHbyBdL_jg-P$n}o}q{m)Qnwd9b>U5RO zE0NVBDN5s4p8O-O9ou9Pax`tujDlPGS}89{TnVQ@%q%!It)HmA#)MMwksM^usv2of zn+5O`QeJC9s>hk|#VXJ{sdLPO|qO z@kGPd;k4U`vyx)g;eJ#Rs$45r%~lcCuk!`PrjZRTCLITGg6jvlJjYXLs} z0vu0LtBt}86mC#efoq>3$W&-o^F11s`H`FwvK_+3-%R0M;}qu2goyef%&vb4Gl120 z+!b-0w366=`7lsHBIcM*KJ{MvLNf++q~l@)SI%8;t$p^o_R2vb-dhwgoGO=u)W%u- zLg@99B+nJ>HdlgR+80qn(Pc+v?eL&-7;$n?!j!CfK+leyb31XIg}2)+3~3K%^Yf5| zS^=u0qn((2R+%T~uWxuB<;N>4k+*CshjwDJ_;c6(Tt5}V71QUdg(YPk<3@en5nj~8 zlm2LH>nF4&YQSuU9)I{c(0k0;_6*=B#gOCWtz6ss?v!z2w=zb}Zrq$OKx4LE zH&VE)TLq{+7Ho1j7>2?&;TA?&*Ze|BNga=YfO?K6>v2vxfwX64{ZoOW-u>zOZLvGw zDXA2}E&2qOEJ9m^A}oU2Mutvvp26++sndS^CRe^3PA!@2EHf-+KsNRa=?V9?&F?jT zm@l3VmZ8W*MDiw*%mFXlkiPJ?NN?b4W|kv9uB_&kQXgGe#dBFRlW0UzX0q*q>wn?N zpznJ(vsv1km=eZ@SzriAAdn8O7JAaEXbHmDO@pmVxUz;la%LvMQB;mwDR3sd^D*^7 z=grS>CzM6u711pCMNiTZCLu`(AF_3s8F4uh+RC+}`z?x%Vuu^j;)X?k{QU~#b$4#07jp}Lwo4iDN+Pvg?y6>^9GX!x$NvrWH=@l3%>3t%M8;&+DLf&DtreFp|5SmLK~TcLx|O(k*3zx3+VzMfGU1) zaczCiS2J1g?nHHHCB=uOsKdlE=<|0p2;%X{VY0!=VXovUh%T9lQ(su56+?cL$0C_v zm|(#pnfT`jW0M@R6?FS&D+`+F7QRVL#@}Ey%?uHX~nowo>4{h^xLOfnXO$*f$!$fljh^&;U}7pZ--xa z)Zq%2O6Jk0VCqynB9ZI9ntD7GaV#SxYnW~*H8JtU%%U$xB_sFe7XQ+*bC97jLs#Ra zTP=>(Y^b6AnfIcJOF2`fo{>SQKRR*pJO(RnxI8ueI`*I~h@HT+11)RZbDKFgf3dXCjuANn3(p zd}E*<@F8K#d5$iEHlpx^2c!}lV@jj1QrNdAHO50r>u6C(=`2g4jcbxKgi?;$pyZJ^ z2`99DRPapfDw&m;&hrUhW=**;vgZ|D+dW?AS6i-~y-A-!;UdVrmSl34soOd+qe){M z@JK4{^_yWEu;0j=+Zy?HaL{&Upu0^YGq-znp6~r*wqy8&n{eEY(`jKt5wMPMIzBxG!o4?IRi)#BSlLoO$FWYKmxAK5e9q=zJBW?UAu*%c40l|-kG{}LLPwiZ(+c^^<7iG^7+1#TW ziu6ve+!x(d<~r1gRQ$zxYQY%xH;^8p?jyf5?{rK21#|}<0!J|x0$8@wE5o1NYsJ$& zM{aSMM0tD7^_Z+y&gL-ahC>;(cuE9?_p}UEiU^{$sJ;;3RSb;gFVS1M>KJ7?MSUX; zoGF3g)iDfG(GyQlS(B0Y0y$Q7SUFdDxLgkw4)y>DHYbf^D@isXy^l;sD~rxRn}?co ztOIS~E_PQ{cpbL6@IIh&8Q#Aweb%fiP`+P1BiFF{PNbIGAFiS|VC<)VQLBK_VW z@zgsGm*AX%a`h*NIBNFe`fcv}T&s|Vz4kmlb-k~n9@ze~Ij|b&$b^K_3DqU|lnMtw zGyVNIrX*NI_i$+~>iO-9d6=fnS$Os@7$|3)CuAE=xsf?tT!=hOx2O6YGPj3m*d3s~ zv|@E(h-}fbi`1MGmt=39*TcC-`yHZ__)jFVV-}=++-!vB%D!uu>E^4Bj*2{~-eP$q zvNN5~92sf(i;SKp!jbpqL6P;JL6P>0QiUQKVg(}Rz4wh-R`QC0Mf2i^l<#37b?F<5 z)DIe3n(*w8RGgqveK&;J{dmlSgqYhHk5z{6ag z|6_aJhu3qtWNH&xT$8&(16!?3x3br2#`+aIe?*dmDnUuRzoL zCqu#9;T>xP;)uf`+jjgP@pDe8k}!+A%opm*7$>D4`W1_ zA1sn>e!6$q@XaOKi*j$Q4q&aBXO@WH1rsaLwte}bxMY_$xU=jqKG;2m?(-Gj=ocQu+)V4D^Gp9W|1>w+Pt_EF2Fm4rR6 zVe;?-C}B+VS0zHfzWo})9p9O(?bcVqeBYIQ*8XDNsJDhh&$>4SgVm4pJas_s>drMH zc;(6ihI$op^S$_B=NgiDQw^PT{kbPt2qXGC=LaqIyGXkh;o}l~3s#zrFIoQSuDWY* z=i`Wt&)>3{UM}ZkQC2(_a*4MUVeRnO@8x_Qb*IZ)&T{UKnJQ z#!c~HIs$!WDN9nXL2ZP3XKyIsh0slkCdv_+7qrj?jNm2qEC3%8J^hy{K#cG(szZJR z646)#6TErYDtz-yw{!>|d|x^ue!d1w`uAFxLS{}#%`yQ}Uxjy%Y>}3tw^eVqZog<7 z%^-Nj^JbQZC(Pd}RdcsL{g5a~^uOF4_yTW;ze@ilb(rbxxwgCVqoS_AcLLrd&kQY3 z0!hpIc;b?eR{-C-^I3UM(q zQ6?L?^f!5_hPVr(+L*jO?y9;j=FB%dXvX*tw;VgQ(!>L+C3hUdryZh?S`8bFl$=;E z-=Sl~6=hGEp4c>h6&W^uQ1kRV7fs=}m|?(J#JTb-TTtQJul3i$GkFxzqc$LGMtO^F zjl>_y9yB(0-~N&R4ld~Xl2bOPZK^URWf_y4J0c%Mu7#2mIDDDE!WX5qh^?EzkfxjS zjjO;gbfQ#b)bYHhjirg{)A9g^n)?Z8+C=XH5%E67hG`{m)a(X$wawK|=009w=pxOs zz>{UM)6v^a&+NeKV009HX9!j~;~Xc5SvrLx=kN(<`zN02b@i3yi-#ur5s64Gov=aSYfB%Jn(tgQb6Yfq5`~vB6|G53v zTA}DqMO_f6LsJtc%DRK(CEM_!=~c-ZDgldTH72Uy%7*P&8UXpO(p^D{hfHQj2WveG z8zxnCXcew_4E1Nv5>xarPaU=1k2GI58JcYf;@WvToloAlMSr8WqB+pGPp7Ho4xS3V7xVo&0d0Y6#}W9+0($se+Evwxx4jB~5aRy&bu~A#MRSfUReWaa z$C*Ptm@eq0=L4fwBVTa8)kV{hz}=f;xxnco~BqCvhE z`!gMhmu=$CMZY6KQ;iqCQO$=^NoJ)zCTF}PyGHB%t&O&IYcNjUA>l+CjwO~L4SPG_ z23=^P4#lS3^~Hc%riTSX1_g5x;YWBZRC0eR#0GoYrmt7Td9PE!P+KJ5D(8aOVUmdG zR{JiUvkS>L*mqmqu=vI@aLiltu;N?muq#nj0d6eh8M<#RCL_0mgDC6H)6T;`;Nx7g zJv+|A*sC(mS_AlE`&3hJ)@<`Tf*X%c{ps=)s|-?1){9gRJ4ud`p*tk^c#Bozb?k^L zid5rCI0q$J+v?WpX{2fttLuYaDRP2gsbW@>6@-1HOY4LBIC6p!kLI5z;Ad@lQ+iFX zRMfXo>p${BTbG(iaGT-ieE~q4S3h8czFLW+(T>#8daFUt2;>K2_$2zm7uX8!)$0mE zmur_v^M>^=L+N(Rxxt@NM6;cX8_^r=krfmw-#@2!a5zK-P5o4bNPh}#I^tQG) zYMH>%=iY~PaP!rrtCLc7<>_W(R82xONS76wrZR^-LxhjGR&ow{2OsR!4_dyY<3h3j zy-zgE46ndxyWm?0;_XzXoG|Q1DoRz{NuKElmC{)G@HFqS62Q$cdZN7W{xr*cr_!?Q zWcMjWT;y!7yk?$&aJV_)uOHMWTS4Q=^1|@y>K3Xftr8q1fOd1$c!PQxZ2kIjy{lyT ztxgNo4hbb7E%<@7xCGMTi;21zt9F+VkQQHnw15TDVi8D-r2f?4brbjAhx7MaAx?!- zrSm^SP5M~EqWXfQwYQJ@>`~GCf>8PTQqjysDo{U*bfY$-8^0aKz`q9z(34Q_A}ib` z)F!^YU{h1ooE!Gu`8ea{w;8}0^t#O%goiGqZJQZ5w?lihkRf9~+&tH`v$|7kX3$Rh zKG~RMD^GIh)?)eg)Of2Oi*2qffRCtq!9U`()bVo%;|9@>?zrx>B2!bj*4>F&4rc`)!@tcUciQCNyyzmllR- zi-sF9FD19qu7lr?+pQfoh-4=E>r~zXiXN|oo9Z~E4z9ahX&i5f2fL5`epv>vNj(th zk85>{FWvCDP3CX>db|h8A9R*ZJFAbqA)G%p7|M-%9%Y)o!04B91xe};e?N1}Sr5%S z1geaHDw1eN6kQ!og^v!VwVu2I=tc89!_SjRewt9+H&a_1zh302O@6vBxp(VcWwj)6 z410BZPdWxC*v4&bR6qFXEw~XGt_{`rO<_H^qJHs2}i}tF?1}^|+DjLcg-4 zqEPi9PV;W|IEiJ1u{c}jsSBW3OdwSQO!^ttvhNR~h_iJ|eIb!I2r)0vx81-tE8kOl z`|5qH4@>45G0zFpD#cKm+QssHZa98xk9WZZ(Dcc}j}s;X$>A9fKS9SA%RDQZCw}o^ zjYUi=HM^yvnCXLj6M+;{6G3Ek6G7Tf8=m++G4*I3$|Mto(~sB72-}?)uIH&wqbz#k z^;ZO3xu5Y}!`DWKL|XP1FkM~c7M#!t@pc__)hGRU?E7B$?1yu@ba-SS+#;w6zT0XU zE4`U81m})qLJOoWAl=w63gbXkrZH=2Y0uP}AW?2l=S7+e;+w*L%Zv^Q1Nvbp2>oxs8xKnuo5uLfPL?CqK@E zVvrlV;L*~l$-&x{)KFq7sDN0mpA?vxjE0U__|9diSKi)Sf=Oy~=l5e~b8e_jCUPBFWug z%ZFIr)x2SW7oyv@WyNN$JD+Y6>!;Tx>N|N7i;oS~sCz>%0n2_Hb{1l-9cRtS?Qd@> z?VaWH$?K4ZH8a1n7%pzBPq2Taz&-DA4Pjfp;hU1Ql!7jD|9#>5?TNsEh-GU z)BV@YZaGmiHci=Vdf4ch3@}DoO|F1J+T&TcT;kc~3b&4^(UVMe@=M+U(%mW7Cn5;Fkzgn*>G zcm679?Oh8yA&s5Zd{en0ceLfwx3pio7-w~7M~5Gtr=7K4{X9gpsQ4y1r*H1Bj{Cdc zm*)=MPN2qM~X7@0sDEQ

XN2Iz0s9C+mm1jR?Il>#`lK zIKk}q2S--pPzvLScDTByjZ+pK#%&x2N%G~@?U{=13KTh|S*e{w4+p$w8v-~msgR6M zetxgk!*6{2=q&UmFFg8^MW<1eCC8CIge;DV?8-G{SRqUOF{j-5zW6E4%EbcMw1$!o zoaTcQ~KwCUI@DURoyo?OeluSbVT=$or9#eXQ6R!?OADC#G> z8bM#wte)8ZQM65Ved7^rT6*Su!ehEsIz9>Dk?Yqm#%?0A%~lMv5%{&YQXVUNx}v0t zuesXNDuDm>oAW_t`xr|c;t>ny@G=@Cz!m@4c%=WGxz{E0-c}f^uQ$%sxhU@X&^c!~ z$r$jbnFUcfyqTs$-Z&ENfUZNHTQPpi9^O$ErvTBBrlXiy40m0{OV&7&wPWu*wI9XY zYkZ3#0%)1quZt|2yj2z2j22GauM6i$0m=t&-3DaH(XqfR7NvvWh{*xtU4H$8w)2|| zQ`M|&#s4CSmts&jE34)cB~zn(#6jCBR-9IL{r|2KTcgdJ?xsTTz5QbJ3+RQvHa&wSXU?-Wxq1t&?&X0AW%g%_`^j@^ zJb$)l3y=Y>KO4v#q8pk>yx%cs1LAYRR&$?Y7|=`?m?*SbWPH|0rN2ob<)KatA*G>C z4F1OyF2?8=DF|^i>O|oL#AtFQ@*vXxXH*HKg6z?Hd)~;dN@flit;p#ncG2MRsxeh8 z9&zCD97DM@_5T;e!8vPoN3eJ}R^~Hb3Q;qyz;AV*waV)j-6QAr*&YAlVI26x+NO{PG$R7)~7K|5-flP=y=K}`#o^Z=E6c}#4-ZQAr z1>Oc*p4&%7;Tv%NR3Lu9`J;pQ0o4r$;z#%fB9I?kzyyd^zy#2o;anF)D=c6FNGrN$ z4Uie8KOKLx#c7|T`KXE^4O+91!0#ZRHK>~wgkR41^E-lN!?8-A`SOXHMFf6_`K%${ zwBWZ9F0(}a-$M5=(homxb>HVIj7GS;Rz+;JoOpVdXUkN3zr?=t1Ng6QWobqn1PJ=y zEL;&AJ|C@`&o3DUT%CUEzdAc8lrPO*++Zmm*6b!Yx%@=s;k&=b-oDWEJa@5h+^^Zs zyjSzN=GB|JbS7TF8U_ipD?zh@0{zxTm`cJ*7X zrDZ>F=T=|JmQRz%>&0abTt;W^Wft1yt*Bm{Q>Rkfv+p#E#Yfj!;^}ZC>$RT|8J&9z zSCJBxCjlZ8r8hCVg!VE0K7zlw`(7xATp7-+O?a_~t0_yo&)5=Xe_N8Su3M6(bxw;_ zA{I_kF%f@bT}GnoZ^=y~;nNIv+xHdF#;byPQ}r9)d8l?LVRe>P8h>G(V%(X%bmDag zIq}VNiS+XOvF)AK*~n*i@cOjZwsjk*FQJ84=QjLfJ|~fB!a|p*+bT<|pxZ8Qh9Xi? z_lpy)Xr^WjDwMEA+p64j8u0^b+QakOhg8bDPHp_=Q|S6M#5lVHvH;=^ClLX&Cm`1dhxh?W7W6+CaL@Fv3#nuvU#D) z`$~NFI`vbjwa@rY7`8fZ&Be=AJ$rVzH+{3-;sc-M`O^i{x?sc63)@w(#hweBejHm) zI4d&edVD6fW4rK!fThRku}S>}yYD99vfH@3hv0&CO~V}V^jyKX-h9lo6Y)<9@;+Hoy~Mp0=IDpo%$ZcOPY75uiyx-dSz?AWlv1>9?Lh2iDz}k zw#Oa))y-I*pY^BTkKE|$#ANBT>Ki=h&NWR>jpwYq{hSJT#5pVNstX#iH|BopY^M(y zx6PkuWvu#H-`7~|WDn4It?^V(gNyk(N4%u&{J>K)V3>C3F0GYzzW27p+ohMQyL025 z<)+Nv9r97Tc=myCt!aNQIQ3=;b}?@28RmDfJ$JG0dWV2rXjK!V<#_IT+spOhse(YK z`_o*P`;#8*>d678C2*~E#rf0fa zO{-UTPGC7bsd`PRXi923j36*ZHy4g0JF0 zae#qV7bLC~w1LEV23kFk__JUPBVw4ff*&C9nt|2;ByJS^0*Vw^?<-@-O5M;unGFiww zWHC<3KPI?2vaam;ra{1RK{)}-H9PMK0+yT53;7OMt^~|`g2?|4c*vYp7(IpdUoz5^ zR3s)$$`$0@KPohReFuE&#BSMxR($rzj;^3JUfOY-dIO>y|L}DSo0%0L1vHX^K`aLvjRuk~oa?q| zxil4p8}^I_k^{34!mTX=W>|Yanf@5uL)Q?*s33L!F`Fev+Q!}GCTYGCaQcyNmU-RSn=Tz6$%_207a zYZdwUIMQAE`5E+LdLw(QUcg!32Q9+)&pAQMZjV-xRdyUwpPqZT9rPh3MI1vG{~;V3 zr!XTD1+fr@P=o|hpc8N)HGp*km8Fj3+P8OVVOjgex^Xvo*1Cc4Y3U5+t1)! zK;NFT03?CF6@obd1!N?U2v}bf+;dPs$RLA(83mg4!~>0z5vhT02>V2#DGQXc5v70< zSTeXQFpGHBFVes))L{65P3{>Bq+U3A{~ds6hfp>{76@{LL>?H(1-#F^e?0d0;$MLj_TNJGZ$=h*@4Hh@1^zueX>^UH zpKbgf%l7|%y?-d%uj<+I1g(Ym`p-ZsqdOPeWe69Ukf2q$HA?4nDD>v?HH&>_xDm#n zG!$9LOIa|=`Po1oz(CCIFNpm>0NZQ@LONvMgj6k~5wZk$3yL04tHhRA3DgEpN;Lqr zuv}y_Z9tRF7`0;{7|)hi1p=p}nn55R*%k;qk4XlB-`NtYLEyAhI}nVf->=V@i?*0MD;Q{IV82pZ!yEALt38{Wz7Zh#P2Kc@*)An^P&o%2td!lIRTb0=Vnq1 zEdP&9{A(&tdQnBnKchy-e+u~TfV(;oJY_CnWWbjEspABA#^HbwwqA`zUKi``5uIr6 zUoXK;I?-so8Xp3 zIv{UmC)j~NH;Fb7xQq)2a&?epksb)lO>hH&z7juxppqF&+5#xfVC*V2KyQhBm+AtA zQiSXU6iUQcD3B|K*i~u~ib{=D*`%n*z@PB`_|(YpukefnB}FM9dIY&V%{BaQTJF^1x5McT7e{8OsCwj^CtDyc7{V%@#chi3c z0ZY6S!YOnFKyv(5$G;-G>B8}Jz2L5BsDJnOi^NdB8I${Y3baeGywBMJ?imcKEp&wx zteKs%qE^X~lZ>`GQ&uMkD8W}K&e2S)h5X@qLUr(f{!35L1NqNP!UyEsbX+)~=X-!uo-kU;}2?q$Nv%B2uoKJ5c=3@c@?p$7Xhe^<9!% z6Od>Bg#Pz~6{L5}{7${viTvMtS}?FD>@gG`5a?~3cKtqngt?2iyjz-fiK?T45fbzZ zyPVUc{s4TvO=(g)LL>jxdvN_NL3_HTiWLSxDLYQff4O!&{LeTQ4+;Da^}u24fHPwi1K13n z_#uTh9?+onyQmN}#=$7IfyTK1%xYlye{7B%GeV@>bp8wH{{#K^f$-l00BqNP9wq+< zg{s}tLufU*|4aCLZ)|QaZ-2NVSLY$tBDeYD2#qv69UrU@EMq_dN^x{ePY56ZwlSSO zj!!K}6Tv@N1WkQ=aefi(5K;6@*4@b|G1!ZQ|#3()=upko2} zZcNazK-dQS=K}5ab6xHF`Tv*-J;VPRfp2U)5JqT_U>w+-vj&XO`eTsc#^Vm+U79Jc$Vffjw+0Ao7SzOSOSOL9$aINL`;kZo>%V2N+&CXnZEI zA_q-{Q27b|Ao7GuKzIN_03OXU^z2-1Ic`x>LZIJYeY>`qkz!JQ~_S1x=)XA2a?r6`H()??zXo;`p0H|8cNL2}}S9_U{Lah~1!h_&*L7 zdmMv+i>1E~7VoQo31xO$Y=1i0)cxh;0_M zp6Z*FY6MY%n`{AOvKwOt0>7}$f=JXiCDj4~`N{S`;B`z92;5|w1(GO)^iyl)KCo*- zeM#^E@g!K{5;Vx5;2nWTWNbxl1R_yELa;tS04Xa|m=_mrdFjt=3;q%R&+s9Hoc*WQ zXRn$$sB+6e>@yGVERY6`;Y#;ubwSks`t-3d+l?{SEK%UCC$W} z^>4?k+>9SK{6bfbvlIq)w9_qDSNdEo&WEt)cD!qgPd8RWQ+(Dh46ss*E$f`FUeCCg z4Lm#2f-dwB`0&zwH`tgb`SOC2Zw3AbZ(kk{_4oZ>C<$q?l#+=gS!c{(LQ>YUWZy!_ zR`z|DBt=NFlp=&|QTFVq?E5Zjvai{9zt=2%dQE(y@1x)6{r+R7{h>LF%)-ExQ!c?NtN@$W)p}SQAu{fm%-$jB^ujRb0A0!tvFr!&JqQOJm|N z`!QvzjnR^`Y^T)*GuG{0h6alTf;4($f-VkNg)>Zbit>a<`}I*L3`o7rzU9J|kzG5{ zpTn9K?l+pjHQAq?R2A+wnDGMm#ySXmYu-K9pKZMh^$kAOk92jJyKeJ#aEQ|=EC2P$ zE`v(4T&E1+fXvA?Qg!ClLx)_T^21Zj&&<`e-oY(T;uTeE)t;dFP9vkMD=ud;0v))C zzh21;_b~45tooQSHKDJiCTg3Sk`%R~(i-%+ljVEo?TE4K#LE4NQnAZ|!3`CsO_T>l zm{iIw_?=Y-jCi6yu&5c*r@_n7MK#rYb$1ZMcW~;>Oy>cVT0J9s*!%)-{7bT-=|{Jm~NeK6M?SD z1m;ZLOqbt1oz#m=s#;Lanwg(pnO|d?Fr5sp%YeIzy!|?|I^@wD)PKCwC0Exz`FSOG z^Y;?XAlia^@93mkJ}%v%XcJiT;_FPO6MgdGiSm~=-Rr6+rAmw+Cq)_k+}wOk8Ea_- zEo7r-xv%^omick&oNl&|j)h-^C*lnE$zDO9GMW_^Go9&_mLg;RGO0Gdpzn17-PBJO z#+LfJ8C!e#(l2}$Nu^CEv!9jwy8O5^J|02I`yyfW@$(Ov{C2C(QT$?t>$L^@j|w-@d{xU%jx045liOW_f#_6 z3)xw;Hg%`DsEyXnRok1Uu-|o{{KQQN_&)ls-L#BF!*0o#tK*emtWR_}krgZ*^ zpbh`8Uo0~6S%Qc5n^-NKDyW-J5$bBE?MPk7q14G)2%Ng(-7VT}sWwFGTw@&JS`#L) zzV?kqLot60WZPJc;H#eB`Tu+WKt6vN^}3Lz6A3f(dEUQn5gr*ploU-RktW zv`Ttk9m~t>k2|NXZfMupKP!53e$D)0Z2w^HYGTDk#bR0|d}(^aj7F2KCh5m=R@W`f zBeNTvKA!?N=MaF->E-RsbRq25wDf@t0a;y3Q)>$yT}udXcO7s~osOKY6+{hvMIF1m zuALQxUECOGcnSM?8T%=&zMoy#&Pr6y3UzTE@KaGv2TE}b`et(D-=xx4uPX+ z00jX-V83xexG?QdEhTkt8fslKwS%akG8_;{I2#gyL~=oR;7~Rs6p7>k9&;J!P1nTA z5`wz34(Lk`NNv!ux~64;CIXocn6D7%&*x*4CU}76*gN_De=@wET@*;qKxb$GgA)a^ zE6@oRxPth_J`#fbKe7)+&EO{fft-*3!arIbn*?Bq5~wvWKd}AmR}F7kLe$XRLQv9@ zRsVHCAQUxBoL^()E^MT049o%QMnMw{1sDJXivBs!BSa0DcZ|3tF9Uzh>=gCxIOITUQ=oZA@&E;DGv++KwdTQP$p!|gEb+HdoN9_MCrgo2HnbGu2$;e`{0 zL_5G1t}S?hK|%U}?&wdtwrOI}1KrFF3~Y{^e`SuGJ2Xe`t(XCuBf6tMF(WUAni)>4 zHvyPGdY~v~1ko#wG=yDVOWO$WXXJEDQO?a}QzL6*6CmLbQ2$?llr^=LGt)AG0LYE| z2cY@SKWs8X7#uA2zcNG49hxD}RssT>A-bc#6VOjH{2vGiY})X@GHuQsnl^GP0f9{$ z-O*nO2tCmMkp_YB0{&Nc0pB5BK)3R&IKhB{?&Rxj8Z``qT6iF;1wIbogaV$-tb@e^T$;cx|L_h35F4LPk)>YAry=7Uo4_W zx|O<$>1y57wE+BhkV_3f7U0U`Lfroe`#5ogwVf}3D=f6bwEe0L-OBUi#DSFU7A5&j z!b0Qj7Mi=Iu(Foobf;zrpxQq&L-10E28BNk`geH5;1&dqwnzvZt!ogB z6gR;mCphLqY=^`+N{sl0R)2=atsHeY7-`Tw{gFkq#Us!Q6xwRgBi-q|{4;oj;|Oaz zn8Fp-4t;0nR*?W4j5LVt)-a64gN21wgq>Razk)|NcmYIg2UEDh+Myo}-73<6;~>p; zYuILCq0MEd!unV62nR2KTz}>JF}MXm+mS2;fz~x(FB%o7Z-PfS*rnz|0p6b;g`>n=ztHN>@VHg5g8(B9x~D%q z7o)^nzhVdUNOw9f{|p`xIKtWvrf`L|LsuKNRosIBBMsMfYuILCp`m%F7XPo{5dmHR zxweBTTw$T{e0%Q^wpCn$z(Jbr*09aOLYvD@h4ruC5dmHRx&F%4=0fB74urK;T!H{2 z4Z5elGsB;t^82RDR&mKcgGU5-0Yrns9|!$AJYsMQg0>@B2p3w{AQ&lbf=2|{yXO9@ zoeu6_X!S>Ugl!c9aeX$b}=U?O+PW;<X8AZVsHdqN1Xr^x+R5X`+(2;M68;lg?Dc3}i|LePs88uQU3 z{ok89c-`RntKANsUoiD&T-+-5;RfR(x~D%X0tOd<2@5^a9SiGUnL0NZ7kU25$L86g zj}6-@_TdKOBD$x)6BZhi|JSC@jf0EZxs984&M~G4!6+F7Bfd?mIv3c1;Q1@;<=H9r zZWZ)!<2-j~*vs=Pa6pfA$J+a^w#>P~{xr{a_=K}i@%*y9Kbkt{RzVLp7#Gn!ZLhsx zVWBa3r`r3^OdX7i$iLd=;6eM++xzjHTLnElIJmgo;)Pj6K*B}x6ShBU5$4PtCxr=fNRK_bf?#$XA(*WQ2*xpjaHI7c zNb=iqiv#QXN#sspa;xA6iDQb}!sPEtgc<7pMvIVOL`P54A7>LC@*saj z(HL8UU=#|15!z;(0x#`Qj=%Cup}?g9JIegx+$!inf?*lc)gReIJMvJDUvP*S?N(E< z)z%YWlKpWUIYA|E6eRWM!st;Epq3n;-(HtTqh|4L%G zI<}od|C_|nyA3<=iM9%Vkhmzb-BN{dig0xd4aYl_7+|pfNXNh{9cDa#oax_9A8VOF z3O`!kfKRj(H(5Utyplt~S2Avy82j7I>=cH#h=YIuf-(@H9NXeB*80&46j~WDqy1l7 zKQI^Iaii-O{xmbV62nwcY_H4kErKCnDsi5?-G<9gT?R`G4c9x=<$q=U07~PG8>Ntc zA+cY}*&p!|zC}a?C_T=Tw_Dq`k{H^2b||rbW&OaK0vVTiUG4P_&)_I*bOg%{mPB ziO@FiCl$sf)Z+yAnD_@+BC*DTwl|dV{PdN63x08o6I~kgrzher0GL{+trq|+Q2)1@ zGCgd^FQgvmMr~rk8qVAr)mSbZNU*POPG4B?PqDL0GSg<>$WXH z+lr;FtA(IAwH459Q}2Ic=?`0e;91(Lcnc68c$&7Y8rzbmtwR}{5(wzul|VuNR0D;> z(^ftVP6{}ttG`vf|I|U@svb`H02IF6y8GKap`D2BRd1_OB`8j&Ht?_igE^sxi`t#} zjVB!J`MZK5D5lC|2Rv=%#o#1VW4ik5dDVd{Zru&j_z&c#^9tTV!HZU zp8iw(^V>Y(pwG6oE4aD`D$DreVhi2MkHN_bhi;qsz7>sxwV^xQP|85SE%@(9jV{C#gW2xN+)EhV{Hsv z0tCGKNXtYYa#q)b2_40wRSG@5nEjC7h0TGxpN{xBeC$;+5UlTwxxNGfLkk&#jv-|s zm`DbKxk~|p)o!eEV|5#=+L(n3g28qO8ohzy63o5{Mye3>lK~>eHZZj_5KO5CgbOnP z=t2M>>l)+kWAcfhK<19P?seu}J^(T~+7;8WgmuVfRn~ z?ZW;9D@#m34m<)YO(<5JSnnU8V;_yJ5h?0q0b|x1K9nCV7Kr<#oU0cVedP_X^Q};7{vj% z(?MnSLSzn92iCG5QFmA^|F9ra@F-XA*)9MZr{nS?tt;sQ?$)a1~4i#*3YP zFclat7Nx*c)Oa`X25eJ7uuukW3yc@5Mj$G%{{z9|9heFQsGE2L@{N9iBDgKU1vZrl zOaj8pA z9&lTLH>}ZssQ_=-g%?Z(c*7bNm_172pkPpkOM%8^)gl za{+`VKQR*276^rYCX#`v0B=}B2U7vwu<#0|0=!}C`@mFyH>|CLsQ_=-B0w+|;0+7Z zU@E{Hrcw}x3xGE)nuFQ`4(QK3I4~994O?LYrUJZS7XmO9;0;@b1EvDJVOI+<72pk9 zs{^J2ykVCVFcshpQ_utE0;qNRx$c150=!|<_&`*klm&vV8URxP-mps+mlR;E@3-nnh%02f$y5ljWRz@7?$sQ?$)lqxV4-~#J> zfT;i%*t{zc70Ax}>7jtBC@wb58<3{5VJy8s#EB!OF_xWsyeATr8# zz@A8g9|;`N0_06x0z23LiAKPkpa!_fTS1-k0p#D8bkvC!K*sp9;7(8j+~lwTu@8!j zaVbHqfzv5~yopPcyYO=x9^4u=4V#=6)DZ_j-ozzvrt%-}7u*So%T0a@>bL?RZ{iZz z6bHzgxCFM~0rIA~1VUzjyopO-8yX;Q;u6^R2FMsU95g^+hZi7k(pX?i86a=s64*Qi zeDzHl3+&bc`XxzZY3P9e(C9snNkT=aGP!tZ3H*pDs z6#yB{B{((#-xGnk+ZBqv#sCz+pgO||fiPF0qCy~9Q&S+Az6x{=v_YlGq3_s5{Y476 z3HYk6J?hffUqqlCT1KdSOH?Buc0o%4^svp<#+S9Mw2VykQT^xxK@kRufQx{&EN+XN z=$WGKtiq(z{iI<2rh60pMq{9B?ESw##|z8|YOvsEqJ;Z1Len+Tw=w_%IT(TqxGDHg zFDT|lpmIqdmR1(JTE_eBUPL<(ImtK8ZDdd8wJnrY-u!s;S=qsi-S=b)}2HvF>Vs6KKwy@E~ z9gy;Qebv=vvfrgUZ}5fVMD}1<4(UO9I^K(P&pDW0aL*4r3enBO-yr0!lqe)8YFIul z&3GrEdX?5TSNy4EQ0e!?WHqaCg$AkdGZvbHualC))zxBMGX&c84E*+* z->tY+Dx6K-KQZSWr0Ljie4mo;(6rIgM~2i}qJA{IbW!#j~V20(X-Pq-7uY?{f6&$TFw&x-UfG?(|hTv{qV~=>&O0Vx<}_R%VKp$G}N_9c`0 z*$C0|=T8Z(-==l_L9Z^!xgkB*9Zk93w2JsKZU+~ABOD?zy#((ZBi3C{_G|PjUs7^< zc;>1py|Cf?DLT@j9^yEwzCGiP2060?^$GE-HVOlx?QCpOaUZG3KL{1Lr#&|(B%+|I#6_oyFdgAw4%#nQXOGZC6Ate; z2u)g2o`EXXc%&UqC=8g*nYme@@PqJmXo`!;D`P4H)zDQFahHvlZ z?G-}-WE!tMJe}F<$$9&@NH z_oCuCv4PJsL-qFdq;%ckmA4;G;svCHS4A@vmMNF4#PthLbxYJzMtaI!(};JlB4SyP zyD%3kSa>D9Ykz6uT~{e@&8EHrp_;xCUyfZ&WZC9Dm6!4uYI6yAODt-yJXZ6fxu?T= z_95kpJ0}S>3d`~pLB=ZsH?yuC74&6nP#-Bb`9H>aO)*hxY^zU!@A zU3l7?%gxF4!ErjFJfv2iBt->yT#<<(p3f_K_IOG0S+xc{U$4%&Gpgk1)RHXaIBNV| zNdsTGahGxyLCTGHC7CyVkY3GU)$Fy1t$9fn!b!%F)72lU?%L4QSs!HomRX!Q@lt#7 zxz>B?^NAm{PICDN(G$s+pSeaMOH*GVc9yZr|QF(7{{wU44j^fC%X?5+h z?d5FUo%Hf{X|lAp6y`-PD_qd*&2K?O40-0QkW0mrUkVhx_gItb+5Q62f#?FFh#}%L zS9^&a5%IYTV$YMO^4y=-w$uT{;uVjBhvJKb&WNla+ShPA5s;QFo0;f(2i0oMG2jI;<1bDt0A; z<%>+!s0?Qzhm6_RW%qVF*iayB1S~V zfRlQ$iIgQxFNs{$+eu9)()F^QL&JW3uJ^SfuSvzYxvxZoPO1A%{`j&1-#IDJ`$4}!It^&soy`ua>L`Mu6yf^ z#5-qRjIdumC))0L+6}hvsUVz2{1dDGz7a#)hgX_Yc5%XvjEp|pJ(n)wxlEig3Tv#3 z@;#|KJIhkvBBuX1t>fH^Wf{M)W(|I0=S$7`r_^j}+xZPDD&H@s8qM-m z2)k#07yU*Rzq?MPxpvTu*3By<&oRyM^1{nbhR{weuA`EANm8bi3_j07ZcIc-*3^4- zv4kqKoILz_W#}MLMq^^5S-gRzZuUnuXv@)ei^}&uCyeTuf0bjED$^xeQSOesAe`sr zKyJ-m&NfY@OS$BgD?CA`@1In9?KSIR?>BGgWIx~3M+Pd92Fo4I54d09f6YE&DEaBk zrT+I3+78ylI+$KZ3jSFtG>h`-f@q zrs)rlLSB?`X6k=>bGdy*-4=j47Q@jFoKv87qd+1MhSzl&)(ldTI@N zy}20tg#B>u^)_azVt*=2HIj}fiooIuU1tW_&sN!L2R&M@9lduK$@8MSYHHfEa@I8O zu1=KT!@e+m0%`@gKas(i)Oz2}s{LtCB$3`LaWn>ugtdZF{Up`ED~`Op*skpPP?qrG zi(!b)x#-<_jiezW!{x4K0TsKJ&mIYpQYj>vX5NUA*uN|F?D3)4iE`;ICG*Od6E_|^ z?8=dozHwkq*5%WMmgB7f%ex$9_6-hoHBz;DF5_P&S9B@VK<;Ywvv6BuB0H*RzKirz z8B_4In>~Er(TJi#H~CjiegPt<%np+7J`h89!_CXXDtnrSG$Nv~;>}TIq2i|jR!CC9 z1JSZKpne;Uvb)tyqHtQ6%Dq$|=;xQ>^ZoFi<9}c$&-o}L9xjm%U&mq-%{0?`mh)1|CHpl7_$&;0NPsTp%8er~|To-W}9CR!QJaRQU56}PX$yL*y{1^X{|Se(S0 zc;)F<5FvVJp*E_Va8}KM#EzZ+K(1fdt_gyC>4gT`J7l%AZe;ZVg`RJO?a4A}eEn+K zdZK2@r=UGKJe(7I*L~MXobIZ+6%gjTA1^)GLpyw|Ctx1@oXEe778?U-$^RWG*ffjvq+M+*C|MYaNVQp+JRb4L)s}MMR@F5VP0WD z1M#eFkGIvX#V20u4Qk~ZJ&M)`7x(AkI|X*_$rqVqS{b%>pk3VSysJZ$7O(rY-&1aL z(3_rIr#Co2@Df9yV$=CFSwnLWvq#YsoyYfXf@w#K93dx4T%SUHV z(crrXY3>$?Np=h0r5WXV?f8`3`Q3c4ziFM1%e@j_XIn@=%id4X@tVg)P+(WVYq`Rx zS^BB)S<@b9Pxlbd%e^kb`gb%F7D>~Y+51jb{vco~G(CnNMvyPm4L!7&=e41Ic#1Ga zM&q@d1mUXxu$urBf2zCkP42}FtusA_dV9mPD0@`&=J9Lu2xI zqiOxitvS5^`k~P@>y458T&O*RTJZ9mh&xwA=`9ZG?3}|^o-`DQ zf{OyS-X6s5Ikl!d(gjs^QUz|ZF9zPuYVtie)5NN%QP$?+LVv9B;&-nTX96BtIjG;A zkb0*cr*L|E*UuCN<^BlkZfDKZ~>bpPJ7e7Gnu=#xS@w=%qs2R3`SFsqCyUcThtVv-q9XCzU}>BJN) z(iiPM^ywjSjJcpD)w1zT>#2+1S4|Fhx=T>%+?}Yg(xhe$KA`QjT#*}0tY;I^Eto;> z$rK^L&%oeOsc8AJ@?tZ4{iLkx@i~jA_kaj&k&;Bh$C%iZJY5L;Z#w3vzVDz4X-_4MR^# zYsy!D%BGGnk6N~kC^&A<>Fj$i!kH6DT>jiAVa2Pe!0oJ>7;o`$(OjpZApNhg@21#>jH`~;9}ECCHv`_8ZWnUTMB} z^9ob2Iz{m1!djxD&r3z3DiDczkM2^40v~18TNG_UL3(K z=<|zEb3A!?8pq7F7(D{Zw#Srivy@piWmT+whWRHtue(d6kh|bB_MeDVXv^t$qKr@# zWn=Kadi2!ot2fm@?%Uu)sxmj|xnAwglT=e3ho_#o`Ifl3NkfL!JN=-+DQIkB{uL?q zz6T3V+P(Mc(kso2$qC`=#l`oU2(A`!K9x7!H#S!$ zz1PjVL?672C9medtY+pDWP<2iGR$o4=e zwNKP&W6?vCw{sPvdezdOG{%E`7s=plx-)*eA07BYh-mT>S88sm96VE#+~3I(I%(R@ zr#3!9nST3$l55+lY?z&}kbtDfxM7p-T+w?=(#XEj2S}oIHj4Lz8hcGm3-bE|n{=Zuq%XX`ChKe;+R}30$zGW8nf<8-a+4VbC;1CZ$`_!A z_RP^-lM4(fyfj#P8P1e^t8;R0T+~I#Oh{6$;lV3cAvsAo&(nq-T3>Geq%CuTgnSXtSJ_kIbIrSe z8InVOS%Wi)W$UCyoI1kOOQKW#(G&@Hr8B6e4EJ9>qoi}PQdUQCPo4S9V@98x$~JJ5W#N=Q(H``vk&`38w@Hn01akLFNUw|y-#mmYXw zP4l991R?k+FnHtOf~L;$s-1}i!OQiJDI>1d*+~HliV=PrY>(&ml=Vt6#Zfw6f-x=% zg>l|baiS=TJC#niK%`i9#l9SI4Wb&ruLQ5a*|DocpFne*z`b&$H zMVqeTX-=}(Bh9kb;#6|Pg<~WqT~*{HVIQg|6)o`JBusuVef*BFj$iXqS1-x*$^1Ar z!?M8h`UK%u^Dkb~mXOGpo>R_niNYJ33zT1Zw|pZ*N}h8a=E_fN)TSvH&xQ}}Uiz-s zZzjp4Ie!C2^@E|9I>c<;MYPzmw zgRVg0rI#9GkFy(d`W2|2RyR~|-`mx?=cQ#qyz0qABi91Y`jISEv-^H{!2iKra_U|; z^f@oZinQA#9`zUQ=MXI#mA)L`Nk%+UQ=<1iN7N#X`d%A0IhuW$HcgE0V&I5)t!I}Q z&1(mcK6%BR5IHDxWinn#lj^^6PLQ?cmhS8NSsJ)Vs;UP;RhYpW z&-QCi3Cvy-Ft(p!b&HX%ZH|M_8J_A|cq4P9Nt9G3^~ND5)<*$0Zqp>iTF>j`^z^jy zDI4SE%aV-Ly-$r?6-#s%f@}4DDI0tq#+S6r#2NA2%fNugwP(cI%x2HPq4tn!X@&O% zUq|!L@M=c)D?doSsX5(ms$nSLVnx2VA?;6%U^ZuJk;!}`ULy2R$ma`0#;zchBbPS( z+gdh0o$nob#-4qAbS@4ynJGEWkM#P7V{%^qFsqm781lPiBO`F`!MA(4W$m_djm3PG z?cDtQx}q%VjPttAlfF=P3eOYdKk#1453zijSh2{=Fk7j}#>aD8b-Ns0boukD+nUFX z48>pp`A6S%_nQPO)T#()@tLvnF%C$%L{{n2P+AFZ`w{tshyoOYf;ihmD#Vixp`Ss~&zR zH6!Gfb|tI~XjW!9fS>6d8ki=AD4r~=^5ed`WCM3h4xyx_D6k&1)K|W>BK@3ZT=z$8 zpZ9Bg{q^GO`fbuj#k;PssY2`S7;xv==}RQH+zOHFgL|pgUA%oPbtpRh`D;Qt`9~#g zEYFLf+&%lw+l2_hv%52Dc+4-^O{r;_uPDN2Q#feab?N3g(!6hWS6L(X9HLgvl1!q} zA`3si=j|QoF!(ZTgy_<*4&L0Z7odXT>*M665ePdVFA%Ct%g6}xfuQfr< z%&sNq2sTIQ*Y@2<>>d#JA)&6sYZq|V3FPy&Yr6bHTq^kW#y!a!3704(rOv69T>13! zDsBGzg=hG($!1kggR83>$9U8->}s3bKMNGk^p`__n3s9ym{Usn3_R;t_)>b4o9I|% z*=uuHX2@IdZpsEbBO7=7r&Zt5jJ%QKTym5M7-dRyXQF46ys7ZVhl^zP0S$K?C*qm) z-&9wS-Ewc^pB_gd@!i`#tO_0~xE$MXtCNk4jQYoqn%7G!nF2*$Qg;)sI}PGbrhF-$ zY^e%^x~vbpOd>PB(T0DCHn~&jNWqUHiHg$J6!9vh8CR9(Bo#`97Tg26d!L0In>i~i zX6Q?FGN3Fn6J9c_EG9WWceK{b)4I!S8o$DV@O$C8a#}I}TzOlv%BxLbMc<}JX;;dw2gPlt*Q*BO>U3`?PLy^ERx z0yE9s$xnTq?MJ^I4>eV@u2Oe(@`z6RtkOmQ(OTcPGk2(keSJMlfd5&F7$2!0kGbw! zA64-RiAcqY*YFJfpyqg|gX6tsT|CV}L4jv@KBd9kt02bS$N0EvGD51}HqFeHm~!L)xubjam&NlucBgpCe8*8K~bXL_Rr+4&DRwh zExq_qWi$UViC6D}nh()3>nPR6`pu>1RccDwEQC`VdGQp7Jo@W2M7Xawq<+zca+k1h z#nzs%goWsH-7fjz%G9V#>LWt0cW0!YPe_A@d^jzzM~Kmg<-SMCmvP@L_YmfyRk8I# z!KrssGFd}Eju@AOIZeM@iTQ5$F@KPI@(N$@G3pm^LSj z@$T7MH=Bp0`pkl(>W2F|OGbjP$IM)!*(*f%`ST$=2qN;pK}~3*@}-6GGSg2qy+P5_ z$KG^07%hJs=04%tSFXTeRK`0qS)uH3PhtPsWP$Sn>G&j3vGTwqcX|P19ezz>*2v36 z1)|&0VYlwh`NY67i;UBrF@!cgTI}_ofQ=p}EgKqcCH3}JxXK1AWS!&7Fm-A8(O3VT zj5e@NzS%jU{oRj^iO*yUjDyXxX*wUfJ}=${TzmSBxwQ4l4izP|U;2xq)C2-4bB9m3R0Xp;&-Uf8b9ZDcD%qN-zH?Zy8Dp3fSkqhmBtYR+z$9d9 zkTp0Ln<;RLF-nMs4XLFt`9^fG`Rjv6SMMD+BTv)zv7}D-Ip6y2>?f910eW`!>n|Ry zO9dzRyXMy1%a$}it^~z>-VHr!r>EaRUsvRjAZvGA?w!M|Xw8b8HC(BoB8Vw_S>{~o zgE+&tX#*h@QkB&N0i~Z@v@H|E84>A90}i1+4oNKrd#@e!NudA6A|WBn8&3N2nCAyi z(rV8mi^tyRyCzy*_W1tc_GiJfa$;5FOZI0&_~*WK=Xb76i~E0TV`!sSG)c%x*Xj+* zr=O{BAoQy^e!)~CS*B&(W<+OwK|krhzBFV+S;g zN{`k3s3;kDrFp79YwGElN9nqD@E!}~9>#9EMwlrl;9cKugs25aFm zVq24=t5ROKNsp&jTM2EI5r+QhHzQSOib5M-@ppUedAz*A`zUxYe>a`lWapBK@)u=T?p!M z85q_j^t)_X5!^5~ZUiTgS;Y#6aRFbsf$VJHb+$-04j7P`0VIU*uyJxCdEh{DFzRQ( zxwI|}I6gY`fwK@xJ-+E(b-{{pXLMKwho zwgad7z`x{8Ma6|AwakDw{N4oQVQ6KKCd=7d0@C<-HZQBIZwMTb+e6L@-Za(L1rqM1 zEr8cg8KUyWk0(TDz93N3yxqzaG+#?$`gQb18@69$wM8L zhOCA_AlRTNNvWfs)XR-WP>BQfYdAmlA8_6#SNsb{pySZ7&o9B zP;Q_l9OxLx@&M+V6X=Z-#slS4N2S!MAvl1U=Ky4&4otm}5?VSxv(wQ@oLEi&Q>FqZ z2T)A^D^Wq+zvfmk2g#R7m;E$3m&L!GHpV}dl1^gLN*gq{TUKqD#9QaY!sE>6NdE1udgm=eI1a#dGEb9zC!yU z1$mCxyNw@C5As@Ed(!emVq&TNQMo7bo^z)si%IkH(wFEjMfd&B`7GpxmJujq39zY$ zu5QMc|6*bPF%y)10LHxo%Mv!xF};a0g#XwND{vtm23>Ay0Y(m38&CxRXeXdlsA@lX zQw0-4;5Vqm8Fa=C*z!@iO1~wsz&Kzq9>DkwjjVJnASg_;(iPH0bpTYrpc7pHT!V1~ zHNU@cNYdvebc$yZUY@s@gH%V)@q{%wh_d=5;br3v(D)fRdKg}Ay61?)6#%fQE zS%Cv$Ik%n9cKvQEf$F1qSXURHsl&{8_(Hq*O`^kw?w`cYunw0AK39Ik^2vJUwjrba zkXHR;A;tZ*bG7$WT$yG+J9?8JuPNaZ{kYcdc|P*!M(Cv8ONX+<6!bRI1(f7XF~^!h zY1=tJ%g){CC(4EcJO3~55Ip^y=C8fi&Hrs@~;()uTk{KOxQ6M z2yvdyQDitK|KzUU>5`>aHwNiT)W84eDGvyYIe+wJp#*TST6US`%U5z)Q!J-@x{l$?7F-3K3yhy#?`uKl#btF&|WZ0r7(EJ!`pa|Tq$7=j z96$S>YqBDOu@6Gn$HzREJ7~G53&P>M+dJ1(lcFou1I)iumxfCsyk4F;_th{UH*h47 zrgV3F@Y|?MU831;TCfm(+v9PTelEzH;)Y!+F4(D>F7>xY$am`v~?U5mrk(Q335R;E&oO>YjV z3pET|*!5d|2oY&uI6GM9^eG|RYR{Lms+H0LMzy4OWHuN4# z>IQ=V=e-Mj@DnX^bsytMFCFLCedNc_P% zW?5cHD{RqlvZJGa+4v>JWJFsgvCrX^#w$0Hi}c5IXj0xDGdOc~3_ee*_$tuo;_)_} zZvU50?i_Fve~M@IgxSXH$)1>N=W2xw3+1o)tp(Jd#UF~%D6}dk(0j~i^TffQDnwl6 zBH5hp8vbpj5|;A4%V!B&Lzj1@#+i<(wPw?%kj)X!Gq{dTHu~+|wIat>EA7_GJr&5; zbCH^$GTQ0J#TzF{eVrxU-y95)7B0j)xA#EIlUAh=+vq|%YCM)0*o}vUvgZZn8Biy~ zGjC2Pixg`!4mnXDIB|vkPQN@630^_r32LGfQdGN`4am(1e0-gy0^xgkp2Xjws#Wee zOHIXlKsxIn&;58e1^8|rN;{GZviK*Y(+i1*wIR*O9)e|+G0sYl^F6}kc+K^nT4O_2 z0`3IYMi++H=@y=MJN5kV3c-)W-8|ww(QwvzsALSs6byBE%&AQ)!>@keUdgW5{Vzl~ z-L#%ltUPu+ZMIi^w@~hGE?LVl{Kb~Q!e?+Y9`6Bs{f3XNGK-URJrsC@_1X|U-l;1+ zD^tKzmhh-*5rrOB#$)^FDq%g^s=Ke_IgzE#4HhQsVT-2hL8R@sV^yc+m8cln+hd_h zdR_3g_GGisstRMU*@VbO-@l9h$3)SwJ)+bq!O>upovg7R}%ypme%M%<0PK001LZ;Xp_AL@S z@Yp<nnhjh%^o0ed^d@$#2c5(>iLvRKypvozX~;Mw)4r$Ul3&RI*?VCG8AKgd zT!FJ_{=)HD`7zyPe16gn!J1vPQTlGoUIB;5`&a2{ zc1`SF4-AVezzdI|a;w?5dL)m0g_!>;p_}6{MNjy!X`%D%t+8F>u`PFM>P8C(hYwEe zaiE{aqj{Bi$Mw*nlEd*uy1XNfVH%Oeg~7x8J%Z=)oIJYx_(ff#q6(FU@q2F1o|>{= zKARDKpsu8ldq}P)boSU3YtIFTP+$D+h#I%a{d^LP+O9DRLsxqaEuYT_?xM1Ln!nrS zqAQ_`ST~+PWI&;x8{oWI?O$YaCR~;1fsQ;_d+1BN`a-*q{V0Cet_znnVaFB&3zMJW zt=^B*mTu^Nws(=W0dJ$osxUx;*3oOdjHFPma^I@&vpccR7%~V4Ntij#aeOg)$Io-( zeZ*I5Hm)xX)#c}z-FcapUIt#&XUI&2y-L*{OFa9MB0Kft-R_5~5;x>~4Ba$|S7m#M z+%)&`u}#UjnG!i&?is}++s_A?+T&J3)WL2RUYLisaeB(o&5_{3DUNED&_Y(c7NYCS zDGEK*ZVY(ddouQ2XEMt!)Wu7t;8D1dUMPcCbpl`dT**5-jW;Lo_XgJ7B|R@UoZ}fF zSFgEr{Khb%Y$Celb^a`D#G4X-0FJL$v#0U{T^s+XSN}{sC5wbbjOK+S98p9ZdC)Tc zJoBbN!?>A%OiP}S;J37a$6Aw|#C8WtJh{>}@Id#Zi|i6%n6vULQRKU- zo6Mvc%;6@8(}5F@#%1zb2ddAp((1|P3$9d^w-n|QxSX7DhZN74Y;f1b5jaRE`Svar=I+*BPbQNP7J22uZ{BxM6|SiVnG;mi#${#a7LG z%=M7vAQ{Wz`H(@9(eeNouB$m+m*V*<O_w5bYZOQE2*I>`^A@cihUwz;(XhnCvnlad_F^_M?rT(ae$f!G8OpH?PsT*P-nnR}=hAFKT$?z8C)CT0dPw85idinfQQ0 z$I{>igVjk3is_ls{bz+=k=LER`7F_B--MiLpw6@6T!|WzEX@k5EX^u-mMdk0wiW&q z-}iIhOZ){cuOCqHq2w2-Z&1DYEY4l!=-F7mY*X5+TK?IuO6$8#PxfTqT&m1-4$^q0 zCmrLlUb?sUo%=x&!XLIGEbLi#5eotxnvpQQahkEtjup2qug|wQM`rg%sYW5ny~@QT zU;}R&IGf%xH_!!FOqNftDN~%jdPVOFL^$KL?wLJLZgN*}WWx>5#3DZ5RC*$@oBQ~+ z=7L016)Ba;_lYoRm1LOhvxG_&J@(Y6!{v>-7RLe=s2blt$n%Q7iQ$GtdYnMrCyJ&oeozrDcdKbaN70Kr}5(x0=!jJcN*8>AjF8(SO|He3g=gsbbGfkwH?<2_dbW7d+XZ-O?vrF+G`;_i~|ETgV)qR~_gGH;w z(W&6xBfab&ONztqckeGaJv_&!szOpnZaEgmiR z)rxO_WbF;??eEp?yzk$cH$)0Q;9 zC>mNc5O|UEDW`qtt)2An#j&grL6~@yc6iyT7xYB>PfeI?t}_)bnbX@O+04YEjT>MNm+-e&zvHo3$S3U z?oQ{Ss392CK}gmKwi??yrpBLugf8!%;FS4zOrNkiDA!1IY0*#rv`C#HjpcdD&n_p` z;+BQx@~2;0NE~2}L(hDlj5vslzhEr)6psKE#R0Zb+NV^dG(3gf1)AL#kZpO+ zDjL#y$&ajTRpXf%+Maz+`I<{+q-FZVd<)0AH`A7(>-kz`9golV%mi9N(u$5 z_v~juj;~(NkNV&p3Yt~8hoq}S9$;B;A}AO)D??gcI~F#aK*B8;)w|4jp8rtGo0f(V z!=$)WidW}CzAWiqQV$i>>`e%HOXx=6);_!U8p(@0r=EWeF+Y2RqD&e2T9Ph_Xe8Cr zhS@&s7}47#(a+p?4wt?AB(6Fd)qI$cy!Z9|ZC^XqY9S%@Lv^2?O~Hllk{(hWH9VdY zYptFW7}LDsqotYETmRuf$DISlr}dS%nni%(2gbYiL{GJFJ7i^x?(6w7BhTfaYF@R{ zjPFdJRp(e+?9(us9h&0My)SL}+=$84gn8dC4cp7Qp9cIwYOAc~WHLKchi^?!RWvsr z=kq5lG|5zC7v*syPRvwXo`RDoA}x8i#a~qzeLODe>0y5NHqeMdPXCK@vX*-6hND{2 zp}tHFWy1NQm*2kJJ6Al%iLBr}o)r?v$)9vPmRP2RsIDhDto#|h-2nH;m0|4;{&#QR z*D2W#xE(w}fm|7L%55jy+b=PQjm{qwQo^4S-pnQ3JLXvC-0@?0-{4Rgbfzcq4BG|OZ5 zP+a81Y9HHzd1FF+PHCmbg(SDWi7elEwrK^)2abX|jEyZ{7*iT`?X4tdsiIDrWs|+S zP|y87Ki&Fu4d?sx{PYO^4DI+Dow@XkV?Ie$fpaIJGslKa88~$TBQ`v`7mKHFU0JHw~mZ zUctY#LDzAg-tpF{zOp9|GEQrmhzh?P3p$J_W1V^4k0qbjN)Y^M1S+QYcP^GEZe@WmZ(wUVH66EWvDfZyrl{VcolPQ!ZzPc;>z_LaMZR zh+3sUC-%Z`QQA|xrB;=)uBtAzh){ej*T3s>V-~@#e_wyFw8uz3`GcE>iDhxePZKw@ zZWv0D85~@*8Ss#Nd26FQ;R@wRtwa(UR6I7{8;W*45e=n-cW@zX9)?|x+0uujx}~`Y z)CArwJ3qGk>OAb zNo+|-&p{!&awz?wn#7eymm3)0H3&3N_~Do5S1};cn-Yf1G}@7i)py~>5a1x=15t@L z0I|JF-=e5_74USiok3%5xoSv@fVLcY2Js7)A#qLqmBCP_$R>=mu+}v@)hPVtdKBxn z9L^0x5chAp*i~ImfQ+A?YR!{kEzEzn7Mo#B=ru0N1WH5PVMMEXy4}std=9t1O5KojBV5 zxJUM}btNe^Y7{Ayr!45@tCPu}jm=YFqF9%0=><(OVlwL#JjSfKL&Kyh;VAk zZI2JzY2!{<2v;edHCHYe%spZ8NuQZZzE{PHQkvs#-z-CGWOY$fPI{GrTe2p3+I zpo(+2IAI$MeA+PN2zP~dYf;bVuFRSz5PksW)+nddyzZ)ee5cVVBkVp^E?m7FpxXFB zx}UT*qR;4^t;+55TU}-)$@PiuF~>~VJzy$FH30~?v;s81Z>tA1>-jhEn`qehxl^jg zlq*VU1Lz0a3);m2U(-X*(E@1xhS^MP+^q#GW>mqfd8GTe>)DBfCsEe*cgyE5Jn# z7_ws4nAE7d5=$|t)c_#D>Qdr|xLdpuTAUc>(LZOyZY_j4)@HQHqy8*aq(;P~QT@@# zn45Its#O8&Nu|jlU>J{FvcdI-k;}0|W`g0ed5#6pdG#N}W^?K|s3Fp_&bUeQ=dfTH z6QJ$H`=onG~2aAYzYaYM$GKz7um6@G%lamF4M+hq8yfxh_l^v z`mon{3r?~u0gQ`r=~jejF=L(DrKLu-8QS8V-U2$Uzgyqk?;~a0=hhVCrdXU*PeRU4 z`R&maf6FwFOPO;~JW4yZkER<*OFn!Ab~v=&g1NiX2!b-O{T8$Tv!|9=i@^rXB__p2 z#p)F}ppEW|O^sqF%_Uv#KOo#t93{wq*Q8XmGp@a+4N{(u=(V@ z_2hK?CN0MwRy#8GTx2d|ot+}(sW}$iLl|%mlX+$nDk7r|0>|`3N+%@3#QELI1#t7- zvG19`sEF}vo{*JtKOD2nxV8ctk>?mB0DE`yp8IafF4@jsVY9e7G@Uut)PbSWaA8Ut z3_m?CWf*4HS-9h-OTn#*;iL({t|v>e<4Zd91QJwv#*DoO+$hvJK!Ty6?2&RNEL4 zS#*(%DPwta40C68auPoydTy|w+-Zq;0m*6@GLdwwf;gd$h9QU$Nvb0#kN^SOqj+Rg z#Xo1ebH)xJ7Pn}mr6d)lz_y~Lptu@QsU8ld%EoPSTI*QpR+m%pzQ;qYGsO+-!r|@# zt@EDiJ)f2RWV0TFEn4fyaQm6Iq@U1-)9lOzi-R3ht0RBzZ)*Hangphip;Dw@3iBZE z#(}HG7bN4rlbQ&u1#{5PI0r{m0YQ72^Hl#O$qI2`<*G0XHrJW(z=_lTQ*dR zRBD%lR?*$><3=x9ZC(#g#hFSYm~4)Tgk-EUq|%lgy%XvLTAR)`w~-Qz+?m)l+7_qv zI%BltiPYI|T`7H-oV_l*>1f!=9VC;pnoB0e=H}8f2G^E~^Qpv97<&y&s==0mC9F%t zufehXxzjVq<{0Lc8ZjzMqZ*Yug|fe-Ls|CgMiW|bg91&(pcMo(unMHfQAC&pS9yX) zL7oK*1?N3&b3tnLCJ!kb!b=(DpN2`rK8 z+|B5spdXq}&7+nz_hf@^3lFWp3k!=6)z2QjOUBy`bl60beXsF*o@}a+ZkA zup4_rHid2eSEsj2)wjjBKI5vwQ$-+Fb(cyX|?9$zJ5*_B4vSiz`!)3fWJARSQ zycd@Vg&C5)$+ooVW2IJ|a-$dEEdF4D*Q3J^!B3TrJI)-6|VNAIHUS3&mF8KZB5C$ z`B`boe(~XZS?;HcW>TEnJdN9dlU(C=gQfRz9>I;g+IyW^D+iW}Y~F?vvXrA5O2+Jw zv@*8JoJCf1uwC9{3$xL%N|mSW?_XEyJk(HML6$ln6x7uBj}r{*QPJGE$wyhrL80C2 z7afvCtm}(5k<>5d`&M0O5SwT-7S}_Yy56FKc@DB{JFiczT7#M-#PP(}Eh0o}Z!*UfZ9F9-!D z*oo6|?6~aior{v~$(q;^mJdjvs33lzKy&<+hBwG;z{?X!vIZ%ZDy zBD-dN9mx}kN(81#|5M*&bKr#c4_QdpiYusMGBR+f3uvMbS9Ket$$*=Y>3s0Mz!+MP zprtdba@lWCG1B?+?0;-#ze6NDb z^%K6?rODh1c<;|R>PrwQs?sYR3Ki?MF-aPW^c9jAPPQ|$?k39PG6xN8%OO;wn9Wn2 zJO%X>MtgObtra3P<@SY8ihk|w5$&DwiI-sWGkXrkWyGA9Hizry9qpaM2aLm@c~pL6 zjPUz>CZ6X9kR#K)`Os3aEucH#lmb92JfsIfQN!r%^Woq`q~Gu&xAIMPlcKPa%6Z%# z))hm3X1|y3pZYj%!m#qX595>>;@r~;#rPmc31_E>Y<6^q>nZvZ5G?(Uhjv&HfiUKtX3-V zm4A@4%oD$a!?^D*BnkM#W?av}3q8?g#fXI+tEsTBH!-xxz8rP@J_6UB@r8N(VUBDm5akjgS#6=lpv}%~w9>&5&P1ku z{!0dC1!`T|6s!le6w2f81c+&Fgfm($*7-pYCwm}mExu(5>TDdgV&Im>#`UOQ>)Gv* zWa0d7-Zle)NRsya`qJz+T`lA&ry|B1hq7J+N48+6`qNS47jNs;OI0gxM>+>=xW>;J z1?AlypH-ILk4y8`U=Kru$(zA2=f8Swp96$}a~I#n&w*hMX9@Vm`?yCrc1=4@}!cX=4yE}I##b%9nQ z#Paqzg}KD$7^QlB?7jzY*B|u{!9Hu8Y(KD09aG@w(gV&f=B4O3?vh@TVT%sKDFJ%_X&G*zhijN_~>eOV{Q;7Oooqtc-yFUy)%+%y0jDF_SS1AooNT`7-4qh>iS7&+||9;eN=`O`g+Qx@*0796SV?*!R_cxy*fdb*=ySEkCTiib=T zs6iQUrUREC>q7V^2c4t=oq>-Wks2GC;~ti7w$>5RA!gbhRAcQo@!5nwnuMrsRyU(j*|dJu6cHPGNQKu_Ew@Y2>)@P>+0in7F&kfjC*^SZTKffd z19%i18lT*0z9F8bYr zJnUu$hPK5;R(2Pg_Xc-kHf>Qf8B_(zJdbXL1o*7HAjig`^sW*CUsu@=8~J#8Bq!9k zrJN7yu(Ahn`nEY6&NE9l+rAk+aJcqnrlem?rn&?!iW&O6MsP2?G)Uf4J;F6RH&EWq zR0S#OgvsQ}@S?>}6n;?7|%DXuPnKi+#ZrE4$lCMgTXwRpdX z&%F*8a(P)@&f__j%5~Pfr?e5@lvXQ$5xAI7>XHG-ADn?tj(~69~pGb=k1--;h1~mz*H-C_8@E4h7kE;0|8RM z7q-!v!P%vJv~^ZK;d#Miu-M##+Ipu)r<~BgXGC%uDOGHU+DCPx$sXZ+p&ZmvM7v#b zVtHKn9Y#uAT0$F7qArigk{b1-U18AYJsCQfyNoNTKw%%@ zkz)q|Vi=y+bmJ4ZqNo0f=~U;4Tc`Hg5l09S>tR%pM3&|tg?2Hd9gd za6C|z_pgH=?$!pPl-jID5_hL!MnwIi_IrW3!1uT;d~H_i zrF}<|ryL)yZrZ3RTd2RDLi;`wuJmfm8q&9ASs?l~j7*ev^-Pp7o|~2|W;K323hX;T z)$1i~P2_V;rX3c7Q=vu(PQRYI`EXxW+s+=f0#f2d5UWnuJY+f5MzIGu%Dn%AkWU9#*9p521F=e04Jw2k#t z#jWTKBalttyD9do$&lehGflc7Zuo{HeT9Fu9N5?K6G_Uf7;IIFo6*I}L4T4%Ulxz_ zX$AId4;us%iFWCBY*35Xc{bvp&dvOdLr)|jqfzr+qm2%vX-zF{- zMYz?cp5a~VW@nyiL*4$btm-3WjnNxI)xCuAcQD%s`zsF8?njZ z!2O9Wlb%63Ly2Ltg{mUiFVyo4U|7{0&J^M=p5nt)D4&NtpFpI1wHp5lMFP;)|HKdf zrsMiUFa9TT{5J&oZ_u^Ce}S$6|M}mr*367F3=Dq|TmW|IP-tQTK}bs`)4Bbzc0W)*wOzVAl8gD>d zfIC`~k&T^(1wcdt2y6he3;>}4R5T483*Z7Eztdy`FwX2u?0?x6|Dvt|uMq&6W?%-e z)hzg$O!Uk&0P-3@Q8NHQc{&yVbPW*tveB@z{Y6%@vC{mxUOfR*?&ITj}N z|6tSq4W|9a0Qf(`v;p-4{*%N7VA?hTe=u#gaO`$L5OJur?|}nH6!yRHqAq~&>9q?G z@?vpaUqRYW3xxfT4xj3ISH#z`F)hE!ZoC(0fP2!Zc%&9bsP=fUVT}jwt(Mpkzm?ZI zQibg}rvXPs;gF~xXOiMw|A6)0&XADh{$0B_X?ZpD^ZB6OhNv0suuK0Nmh0G9yd}Cp zVaimeGtt#I<28|C7o=qCg*W3&R4^?UQQDCS(mw9(gz&=nt#KNHIE z7E}-EJ<#gsm5PYx;z~piW5n9A%~J@^;ehn9%-9Yxv&??Z3Q_|MY(GmjwC0 z5!!%l&HzX<`M(j`tN`=nKW~fkbT?OI<+jgFMdePH;_~K#geiqA7ON;HG4Sv3(g{(- zUkSdEPMUm$2$atAZHW-fllu19vc;hjf>Etg*%OImXEK1mDgp@eG0^0&osjV>301{c zy>c&R!OQzhzx7`7Ji1jWFBDI`{Cw;<}SAx}kZKhz>z3RoC&q%3CE zTCf`|7h*{ovD2F!D`L?vSCjhw6t~%Nl*c@Vf|N`{BEczRgwxn!Jvv7I! zn`F95v%IfBtm$DTmAd`t&MRK&PrgJ>=;x%$NlMy}Q+r#UxKj~ALrY6Z#oO!iX{Ee3 z_e8vLqz>|AsewZRZ;{h6X0+*4^N!Te)1IXYwZ;_t z0kL_~b6a2Gh@T;jk3skdQ_Ovk1MXp`@Ln=w%J`!v=;Z+HWk+Z#f0O3(K-g3(h3zT5 zx){BQhKDBG^`6W0SQVM>6eGq<`32pl8>@r*<@^R|nR9nZn9LF*7GHw94{wCeq#sp~ zARY4i#?E+ynq3Br|0I=I3kZGg@Tlb~l`wxy`VnG(`E}ZazBeB{vH|9F!bnY!X7C)J zU$g%(6vI2UJT;!^Z?4WT4Kwn_S&h37MCo}&RC&tE94I96)!yF6$Cs(O_oe4NQtP{;@EuyZH*kSGRTx2NXly;YK59kgsL}sUO(a)c=lIb$UZ`57<35EHt zC+0VN8{-QEO7mqOY<)OI?kBMuJ-0w(xcRW1Hh~-iuoP(ZW^6Z0H%x{|9nvY)Sv})I zjxDSbs9rD{snCpxrINuQ6I-RDHDVZv+0c>!eV{kHGJ#P8%XR8k`@}OfK_>Ia90_9x zI{cGPGzv5Yi&wYGPCN&~2vK>pTcbDOI)WG_v!6VT1A?w-d;wp7LrMn>2*-9n)~U`K zXaqDs2GR_8?pO&(`ZVSxU`i)(o?vuDKrOWYfyhYPm8#tTI!lPM8?nd$E zA(z+G*m{Z;MPXZGY6rCA_w(i(j)hJ+S@j5o$+mmsg60$Rc{-WE-4N3CMBo+dYg0f_h3X zOdM-FWGg=S%+$Ay%YNfDvM^fCZZG52_@1*Idd65a1}HUeZwoy)x7BTQhLalAw2q?; zde;g$g^O5b=I1T=L|#8m3Q>-GC9i}?Rtw?C4PxneVa0UwOTVEUk2r^ve_ti?s+&BZ zUdcU==UKxYp(f8b>Y*}m3b-Rq&E7L@3&*o<9wj#RG1?DhUlD4{mX72I+|`BJu8zj+ z6YWm!<6f;g*9{RMb``DfdMHTte2YW>I1(hlexKQ;#JEMyxJM(<3Msycu|iqgMfgS0 zWRQ_u|0eFtL*Eon9g?Tt#azUv;9-1AmC_)5AtbX&8{ll_L!IF9aEhrm-bh4Ju#hTc;%<;y;-kYd|S za8l;lpw5wjE-vHo3$7$o;?X6t=_qVdVxx#?=(a3p;T36?!4pS^ LOOs}ws_tOl zX?0?s>UQgngyPefvwRA>elBmPkv=Ds?SLcoPs>%9?PzC1SHX62Z1lt1nEU5&&kK4U z)7)vDt@_9Zj9V{*0nvO%8AW=wri9v9pXs(m@zv77!0 zXV<>%^nO|FkB6FGXQPX_(`Zi*A&&1B?1I5X&{!wf26rJYHG@{-3%l3|G8h=n2f+$c z;OzB|3W?Z#MMNIdPI_$QY?nP~u zB}H9Y_c@fz^<#^DcG58=3#B02n2QRW&AA!1r-ow6K~db1C(7oAF}^A722;O-ag(R& zIlpq!?G!9AIa@^s^{ZPrPF8^a@KTYY-txn$H&Dt)olpYKy}2q~w!kTu6+g#iDUiUC zUo42Ou&7vos*s0ME)^|HW+@dFNIKarD-2~S3lR+aeT5Hn=3#vmp;FDhvXL{SN;;G6 zdt{-Vv1rM+Se@KUvZ?C+qd91;xT&f`gn47#aG(19Cbb4x?ZU{Xhjx~UhFXt6b`{xOj3#|tubIhrf*yU!TxSc zQk=os`fO~8BEJ1(6<)&q=HJ=;Mf~)`%|vVK_X14k%8K>A+id+WOk3O?7k-X6*9?l3Yf~XyRsJdxN!YZOjgOrzoW(pnpCYYx$MR*y4vL#vcVx~j<1jg-)RsfSJcDDna z1hqWYvLktydPU|m1!jvd(Bqz*<>?jIr*Wm31ojbu0z~}jIb>f+r+B2dw6bo^;vVR` z@X~uh7QX%zjcAN1iA(nVrP~w4fi}xfla_3Wck>RVC3P6UmgQTyQ1lMmJ`1wN&<3w1 zQ{Icxpz`{qeO-9#nL~A!1Kt$)>gyH$L;ZNqBFFN~{+33YfCt`T9A)p12HXyGPdJa) z>0ZenIwI#=`wKui{L5xwM-pwQ9pNngr^jfk-fig|z1j05cEHx4Ysc>A+L=hzqEDD@ zK--qbB6dXU&>#Lbvm3cGZ73blZ9URX84oPhMQgpM$1+!-t6w+3yM$S1wYMgnSY4sk zp*AEQ&3%e#+VDD}ydgGZ;Cx+Xy3JpYWZdC@3v_?I%&Xj5zq34-ZVT}S-jIazdz|gx zdf&pjlYD`@0&+)wV|9o2jBRV|o~?GWDYV|IHs^f8y84k>gA4YVP9*;Ha{Rx*8<`ahD7Q&VJ zOJ>*>8b`MgqH7{X1Mj@*#5Y_+lPgOTpcuyT2jq9OdcRFN&L?U|U(!^?HDNC)&|MDZ zgRc;ljPm)D7923T#v%-bCYV2VVFcEAH?PEcMA~g{Z zv7Z$Sc7;WnjIc^ReQC&;G+{u8c>}{lVppsv=I=_ALOn9yzEPw?MISP1&^u*HIOD>( zp*CvTQCzeDlnnxi-BPA`XQ=k#t&2swDs{W88dt#$^#+}731Y^*G50h_4MK3Nw7SM^ zLi8s{IAIZ0Zrl`P0z9$QacTm9c`WYOuwfZACt#(%U_C4D&*N|MI~NC#1-+V;%|i@Y zqmsgM!9o_a13HkhYsnB|@EFOYXv_V!NwD{HP*CY{#M~QC+zH0f((>*(cTQN>cihz@ zNr>O)gt^h)yX%9+eTpR>-@T6~8ocPGpBC;tn?+_}zBG9z4(7!k|q>aWrQ1#)R$k+w&~@5Jg{dsbkv5(5auIoYFOdn{N6XGmzqi ziF$`*JsWeoX)?UhWcK0qxNX(pq1Xjh>M4I}Xa>-#OjG^Ksv^os|AVWS8E4h8Y}tT zv%bYHd?hU5 z04d;f2yM7nGDuA%K4ocq%4A-RWbC}(+>y0~{X^K(aC5BdwGn0&B)C7gxeyJ8d`BA) zjl%jlXlCPExmiq9@cw!9B)j~dKc6FwejmQ;H!78a9*HMrEwhp_3e3vGSkO^Uz*A^A zOfe^=>7x_;r|PiIi8BitNh)pQluZtUo>k4o3UsJ5wbTi zVrMV!>%J&vShrG^cqO9LN-M*krdGvn@MIM6J=N-VS{QWhdd8Z2`-(}3tEKCA78Ou zgt{3OQzvmCCr^JH@}G*doQT^%Y~bl`uAvh!)<;8mA=(ZuAsxoBPi8k|n|7>n(An?k zb<3V-;Dsmh$rDQ(*LK+Of7btca2R6(buj;?S3_n5y$?$se|s|&=pZd@IE+d`BN#V& zbX$aq8j12asGE{}cI=+YT)Qyr^I3l5L!}opy!orOkOb4ReLpUQr5+*w#=HK;?jqH7 z@`9qDGV4X9v2ic4Wl zH{R&-(Hqy1urLD%)SQ-}Kr2MhP*_IFB|EYY*09R%r3p=&)2^3`la>?z#tPM|mx-R~ z!ElUBr|tYud(lm80PGw^=CkqGjz%buU=EataTjv-f0+Zea zyBc5*X7Bf4F~e~6`nI@FfHa#XN0pV8rT0d>%zmz6CKf{P zvw-@IE(ajIao7nzx0?J25mDfYoq9=`Qp$tGN}=;ex3dH1!FXE)D!CBKMNU0|bx)d& zBDhif!TRksJPgcsLC9dHEh{a3om4#(PwgneA7f)QgW@WQG>V8opB2t)$ zA`VY-86xU*%kL3p2SXFc=OlVxd~<*aSdN)#+FEAy%;Vr zR+MZAtlOjNH8Da>nLeKgq-NNMu3opj41YFW!YxFuA6K|YTHDr9nN8BSiP3OCmVB*w zqq_xUSVS?<;P^rv*(Ru^V0Wxq%~zZ ze#ctxbkaRv4X|pXbNghT^pb^|f2`!~zGM%(sMfsMOSnGxu-7W_&@sTSocf4+tF@P! z3RE1LO+gA&s{>qqveilJ)S78JgaZu`<$72J*6~iK2c-jG)PtF z6|gh?2<7e5G)vt;Y0yO$+OZ4rzM84^?aeNvL(XTKKFWw7k&*<}mk>ime_E^!W2x)m zcUPCHGnHjVyTLl8bV}vvnu)97_`{QFw!kxYUuv82^4p6{vV)`p)j-Z(aENGL8cFtw zIWbK+m%&KoUrb!tT zl0Nc38EpbTBd-$#j3bJnvud}u-QYmbg+-#mjo`)~IOoI54wJGxo+G)kAI->&Zb7`# z`s?P-N)5}W{Q#eR+UfuZZ_gSu=_eIS`7G`ez( zbPme7S!q;1Un(nmDjqW9LP0@^eKj>e5~LE)(O4^7m7|2_GgRa3@@B)b9k&v(64>rD zjEj_fZ@t!RQ%k4(xkk^hB=I&}w`#Wi3z}tNc*uPP9*eT6&K{LT#fbPTmP`d(6h@YL zo^;L2SKJK7NVnZlO_+Cc_R5MH0kXI21UykOmv!lQTr>Y z(#hu=1t+DTA>0aTBa6dIE+|vkmpl3DGrXY~9@<F;T2_AhKvB@f4NqOP@X(_^ zP|$nBa-x$ZX5gT}Ww9YXim^dHiW!L}%2mSdbg^P-c?#CRKJE>V5piOJz36JoIVO*y zhP8MK4q$Ojr^w93^)jt%KXv3w8p zF_k`SkUCcVcJONWm2d0hly4Q(8d|Rlq+`BQVJdMXO|^ll68N{xF`wKrVzpT>h06&? zpghBn!l@MatX_3AKpY2w!dA2>SxD1WM#iqcsQotD2JLW}vo$Uds@il)lAOs)Yb)6Q3xz zs8nUNv^d0vklr@8Qhu^iJ=qE%rEEI%HBAGUy#>$uF@OYhR+HC~$HJ zE8<$jN)Bj`Yd)QbWBvi7oCMVQSSB}Xr&7&36JaNP&c|?@FJ)T58e1bjSs^z$5s23C zkYCF~?-%43Cpv57rhTI0qet7fn0qobHFXlJu)gwZWg)*(7hPdb&a`=bV?|}LRWxI02fEdZyQt@&<2B)T^_@nhPgZSoQkmns8Y<|& z`eAFrfFj_}&l6I08a5{&v~bUeg=imy3fd&kggEqz`6g5QoxN*?%hbzfitm01erRm^ zGyU@Ocs}60bsoimk{DtA3 z#M)oEP7#)zHb{xR0+RyM8AQS`{H*V0NY2C|bsDoGk2Xk0&-46ybw!;*QsIqLpGFz& zv4I9X16ZbL>4}w;`|_3zF{|&v65a*Y*a(3WZ7kWPLx?M!?m|k#ot7Dj7X< zQPI`CnlyU>@CzsfCUONJ_lWV{SD~=srdK6tNWu#v6ap!Wf0i0yNkaP_Ax?YfHVj=AU{EN^ygf*bWPw+dS6uddokNp7E`1xQ(WMW zz3`qwPhJEyHJPww_`o4VEz zVZKXLh=!R7^hedpvT%FI^gDCrrpquXP0^-$a6{`vv<9*ql&yHe+jl4=MWTJpV$iKx zR7<5b2cSb+3N7L;xNB;hEwZ;tw$kgrea8$;KUgEdp7Z`Sk_m8x{kvG^zvn9i{|jG1 zE%3h=+5z-s0OuSaTK@kEvS6g60R;O2@%;a1q21pK#r|{9^pD~0-^6hLD_sI075=IY z_|K5Vzg>lYgns|OBrX0!H3#4e=-8P5Duw!oD`02)V~}H^2WSQXYsCntNlZ`k$2a)L z)JON1HID9&3J>sw6%#;v$NpD=cL3|~k4NkPQsZy!|CsRpez*T{$pI<`|J^hPpdJ3f zX)pos4R)qKr4|2>9e`?l0At>N_6B(K04*6=0Duf&1k8UQ@4pez{Z*a!e?T|@NSl8S zWoyfi14MN29jBBJskr{x_6l^t3&dN3cngzYY;zna3w5#k0iRv*OFwd<5GO9CDwwbq zCmr((f{xZBJA|P+mHM`rrhVER#5*=5Zr?GbP@-x^JO8T0iPc z{MOYYSv~b;GZ4%Q+WIdvnqiykmp0jQ>fr0kzWQ}4x*y+Jvf>N*HQ5H1OSYfk99Hi- z&VrlwKy(Jjd?j7CXUb|LqBKN9Nkl_K5hVUtWHeZJ|5(J>%sQ;%jE*R{IkJO2a{aD^ z5ZvGdL;ooll|0&Jzw+hVvm1g)` z{pEi?nE&L#`Hph?sCV(Fg3(rT$Iq)qkkoasQI**KBn2uwNjWL=dy2UnsPTjYL%}7L4G|>+O z9Cl(IoLKe{Q$+g5H4VEcNk1>ye4eH8mCl$ z9$TEG#IyL^yZqvo{UtTR&-V+cTraEw7c7gOdcr8${`c*vKho=wp1O2;2yzm$eLf7)?9YntW6E?7Z zz@7UvvO-xT{<%E9y{7?u|C~1qV{BM#oemuv0wQii4Y(oNRKOR8#9pCP=*b%N)7I`&%z(iYTK)K=xo%nF1q3*8@6N$jeiALO5CaQB;? z1I%>5{q5)!^b7hUFT6`nKKA0Y{qI~=0bn25O+kjZG25s{{iEnHy>b~UO-UWlYizJJ zFxMIJ&*&ocsfEY$H6Y{VW*~cp8`5F)V`1)Ox^^y8Mp_h@aU5VaQd{31Zthd?}0bK?C@P10d*dPGZ+o`!Off{W5U^9ngJ$^MC`K&L9;* zFfB;w`f3`T_)>$JK`p$=`tHm{ulVluJqCdJm6xH$r9~Gj1IsI0i z1mGvb_>p}J76TZW0nab!V0z-rO?fef^ba-Q<4fN~8iRSK-2-pg3qcP3gX~io(InID zFG2MYFSjYqI9Ha9fAxb}`QS963^b|gwV#FgqpRRgg7Ua`R_mQWfC`WsY%7&vzg*i- zY~L6n?CipKhd0y18HdPl;wnZwS;h2!9Nc2eXGcs98hlWV({TI*@#OKRL!5W44ctE| zci3h;Ij<1oGLL<%gOxnIK9sJSTlBP6o8l-)pEjipeI8|QMIIh7F{Q6|LCN0S?(k+T zHVfYWMVfK`j17uJBryl-_JKKt6=6?hshFAU39HhDD%xvwftd*s`{0Krn0)umb&&3c zc7S*23L?S-b(mLwpQ@;2KZg?G%g;d5Q3F?0*go4)@`^^J2LaMI+}|yX7a>tsioe|$ zE=o81D_aBKAlk+xU8I5&nECu7PL*uQsft9^rQzaZIou z;3Z5MT<)bx)MMSY&<&QYi*Fb>-E|qb4CjT6>DAeOymr(RC}n}W?7yBa{0#ksc`=O2 z?(MvyX&rBYVqV;z@lWg?IP8`+Ll*bcf1`@VM^oLUyV!uROLdwDZ`y#yLxNi&i|kXu z4IAE}B}~F&J|k>_dx+~bqMA%H86+Km%LhG;@#q41H49mHb?LpmLZz21-iaBK%^jSB zQ*}U^8pacAo^iBsltn>eW0UmC{VJ)_Q@w4>CLyrL>J(&@EKyM6Wc`MIGR#j0Ec*Iw z=`HjvV#D{5WSiJt%JchJJoS|!%i0yEYm8Bx0YlirY?l*=7oS=bizsgeC%CE${nR7( zuNThm0?vwz+=N_&9};gWQy1*G%{$?N+h|vkPcXGx3815x4n%GNo_wOSD|cvjUfabx ziaXhf>`x1-gvIaR-XNcZundV(1gf#ZMno$T-clFDA*1p)5S2yq#|ke&HDYSST(r>x z9_cM29pY`mZPFhF#a)MkKY1VCD0L9KL5lEst%hblp&R*0Z$=SZkuF`fy$BJIYIktH zw;F-A!d_yH#EkUsiQga}59mb4KaLjfN#3A5C+B@BVz{5xN)K@fttwKT&z^fdM(Bu{ zn?7Ro*Bn72?9 zyu@W!b-KvHJz80EbdmLtHGSi5(CHXa^ajt_X8~~;$4-1(&WUxvu3Eh25fh5AyUgY?9-}yZyqE8eNcZ)fLY&uk6Ix8R0y~ zdZf;eAmuMTf*c-LE08}!Re{0+?gB->&Ae^B?X?|wg|lHVj{&;{;Tg46@}rnR2qRZYrHCwQENjeWKQ$Mk^%mq8h{xOy3U(SRREt1u zJ1}aL&O5j}xRL34{VqB`!s0p7Q5JXZ1W8-xx_O%Nk;Q4ol zQ`jdY+(GCwIP~7`fS2Mr1ifyv>!Y;dI?rN$x!3GJ9~nj(ohL&pNG=fZB#7BgWb`bj5ZN);*?Z6`T5AJu_%PIf*ESwu`IMF$aAKt8WPHWEo_aY3mO!iDeYtcEViW@NHW=M!li{5J(K zkR5wKGDQ#~J=(4`nX*Z))LK-#2i};U1t3!88tX_S*p=#sxWm(N$dm0;M< z0M0`khcu>O+_<5E*Ljr}k}Q$SE;}##Ca6%bkLX9oRCGTUxAG^nR8ZyXwOt>Pi;Don z2c3oQyW8J*_78vcv*lt*c#zCBJ)r~LSKrY{h4CW5!K0uKrsRV1eu*JRoRBAM8KS=- z_1rkkNt21HMoITT-R1fnR^Q{9@q^6A21PZDHEgrzyyfsx#O)UUBBR*;u%>gG=HQh% zO-az!P}XEwSehTiJ&BlN1o`_IBL0|vBxoqKN&YpMhTgL98mmAx0eScY1=&#*cm+#n zc+MBbJF2pmP229}SVWW>FXEN1kyX_m6NY=6-kz$6rfNWYVhVKESLh_@JRp>!ujwmq zz(huW?!;eBfDr|%(u-e5gPv}&X;b@#XP&J}ck_Tjfi=^>vJGvlR>?c_wVh_Q3&b5p zoVm2Zp90X7q8yP?KPtA=yi=2|{xt7gGj}<5f(^GqFJ29egi$6^oW&0&yJy$#tp|MN z$Lz!TjHMWA`ARrS1!C&#W{p~}o=Sz78EE$WN;?P^;NIS#Drd^QV-&w??9&!O^B465 z1t^W$wK_FtegS$j)*4hpvZ(MY_LSAE=Bz?vB5L3tUEkUC_5$X1c~A_CrsdpjG92PS zRsjW;M>2WDCxEr*-ub!yz&&#scMjVz-F*2afqT~5Z*#LfNXl8e!3*yWGoF!=2x*yK z(GNOk5wu=#Qb>Rk86==n)9%lF4*9AHTG!Jm{56B5k`_VB=g)$zGDm=N=@?h(2J|X$NrKm9J_cS5U9i@v-DXrjw%rdC-@tbuUr<|MVADt5prMQXw$&!-gt{ z!C29NUk9YsQjj073jhID>w~Xh$6a~E5CzgI*3_`EHz`Hl_dtSX0T$=wZ?7ue*Un%i zC1ewn@H6R(F z;m#&EQ5((L=eyQid*2t8+y#h185OLrz;zO{&u4J|r?|Hci?aLLhDD?sBqXF$Vwhrv zl6M^Q_;F$YyO;7~(Nr&mE%y9}!D{1Ky%{iNwmqn#Sgbf}?(Vig5khY##<`3C)`9Vm zD2#E|5L6u>(i;*QV;L^B@S&q{%Ha`jVS&};&EgLGFGz7fYb)OE^}uksZ(%DhW_;Wd zL(U_qpH5~cu-8jOQU=PZSHb(fAN|sq5kN9+8Zc6w7QUY zoTF^EouK+le?~q)%s$@Q^%b+eelxl`fl`Gs&xB=dA<9ZmTce4B`VWfzE3cdn%eJEX z@lLkoiAh|Gmal}c{5WoZXNf~N%WP!L<_*~g z%rXL&?bS(J3az-A{OmEZ%cdH(@d1fyOS#TG{5}I?0f|^fJl^FGa&0NhnIIim`FbYJ zPWG^z)e+?*ka>j5_m8EmKsz$LSfYg>)z#|P3raY1N}0N})wYgu z7;70PRtD<#%icxC0E-ehVrnY#|g=EY`Q5wloHZDL!3I$GTtHHL<+lrA)@i%CP` z9c;#i>aRL&Xe4~OEn7KLm_s;G-ajfU&838OIy*lu2!966YUY#VBOJ?LmPt6zRCY3%^CwC61ZE zH%uAJ6+Sl{ zb7fQMZ^d%iN0rFz)>=CabPB~e9-DTY=#XWp9K^-HAI}aImk4nG)2* zS>$AyKGOl$iJx#QDqGY{!pV}ze6Av4D!%V(#+4GPh}X-KN^gO!)Wk!P0>I~fe##Dx z9El&fI#rO`Oq|M@x78tEtp9C>J=%cgo+Yl(GDy+=qv7Kq+tybTy#QSQw{Pip=&8+m zDVPR#`+4F1?6JqrmQ3KXOkFRW4AX_`Y-*T+us}7$Sdpz6Mb-u-Up@!6YUBPSV_|fE zaIh3}GOTlMin7{f0B@tbPW$%sdzMNK+WXHLbjIJ|!ie|u4Mx@Q7GEjZaGHear5)C z%D)w5;#M=`Wy^waf`Qh1rcqC~@%#PE0RG5JhwdTUAgMRBEhhaX_-+7k9-;|c(%t(nD| zK06bjH+~oEjrHuj#Dwe^SFw^fIdEtv)3(#n%|J0l5WRA)YYkAp7FAWI z`^@IlrVS5>4K81CQ(wx3g>_*<#poUoU}qBcKSzTnk&sf;{N7Ba!9XL5dXDz+l%DX2 zOs0LnNbT)3?DiowVL|>($_p%^CDZq>_sgFuZ$#!&;F}SCz4qyr-UwAZgJruTDgZAN zSkxwF1P@^N47Pr>b&DT>;c({2HmDMA3Pr2~-|X^XsMv;7`BXPAW1@J3wrRncGbZFp z+rPS-p>e92&@Z+tT->j-v!lp@N19;(i%I3x^VP0LTP|rHQzGw!X2{_janItZ-y08y z5~*It1g{l*(*S^!HnUp(c-G|Px9#OjyB1)4e2oufCJ zEGBG<;_~7STVg_RMPFd{+f%H+45lceU@-@LDn3|LBo~@~`t(V;*ObVo*S+zez>K@R zp?6cSeQr2zX%dZlVHn%uXK&7P9%y7Q^6BeH_v`exP>eBOWheMc(-}FIVYnVX#Ej+D zFwF=6ACKA+abgz>J zkm~o|h?Pa}^Ii?7K;6uCmW~TPexFTbPS@ceWQH5I$0Ldmj4ws;66S$vcpn*_1q=NS z4?dBVm#tlvdN-)sMrr-cF6T{^Xo+?MRTt6HVjzMpIt=7x44!Ug`xMeNfiewDYZO$_ z%aR?#E3pLGRxojCC#PfD{!B@yo+f7Ix*k!SZyyT1SbbUl)n5;aC z?FcKEsM^zmqSk}g=_ln8(lm1pGp7C{n5n|htXNQ1tYCgDaFec&kzz}bRIDWAM{3#SE_r>C7l!k~csRlHG;lu-}517;P%!#~Au;^4aC0@e05 zdyaNKMbuJ=lSV92Kur<8G9Gz~hK~J=SbTK^V-VdihvJe6mmvVf`J4>)dRM9e(oHrs zh~<41%@wII8ol?)?Q`S|etYk_Bxn1*pp4$h51PIPVPE2}i+C&o_@uXdm}@VBF) zx?&R1aP{?`|2kC?hiA+@p%65e@+H@Od{DOfcJ^6HD!p9vwDO4NLpj8cr*qIFML{}v zR-twP3X4#i0(1bZeQT(g=$ySkeRqR?lp&O12r^1{y`C5?Y*qkxYW75o>uoMHd3LaE zPxN5bWPiL-g9X{R11hp5fnP?kIUeKriou z#;fyQWszK=dU~zCpFY$-mlu^6RmY7^nBkhB7d*dNV=2F1U^5QChN$ay0n9wa#U05j zwmk@$?j`swa)aFXQSEG{Fhs=@l)Uqmv|s*8;?9?pu?CBwlsyAb!gFOP3|F#lvZfq= z|IQht34`QV#S3I8xtBk%#m0ukSE1p%W{KC3Ns&cPDTq<+G5qsDLE9B zbq(2>e?0QGgEcs(?B@?~`nD|Pm}^P&O}qB#uuPZ-u5$)oER8uN+%Ah3Jm93?J>1WE zVzSZ^@!_{ti|t{DB&Sq%BmJx(Ka>Z|zX`w1%!hsiBjumkn1t zS5VYA2MUOMqCmN?Q%YBYscXbM2BIVh z>s$yjWOzE@C5p4QAzB2t;HtJIG=smNVV4X07A;;FV57rpSXYWd>w*{k3NivE?oW_- zu8iupYoXK59n8FI=EyK_ZXV3BQ>FoZ;uTdLB{M9isVxonWkkz)5!aWm|=#=bc8YKRnk}Evv|f-TQ5(* z>-}9AQTgW12fz6oSi-CTjEyhR3e&`?bcpOs#BHQ6Y4n=B!k&D7{xu9YEEBUEjT}bQ zMo&_Rv8j6;LiLmLnBg##Gb|9lp*IqMar4vpQh-Zqj zLyyaNL;hF{)0B2tdXc;jGZq&2-1G+bEL0ft+8y>FhLBAB(dP57i7teF?_93X={Up9 z!Yl!RKuUCX*dug$&PcT|@j}kKe3jl!07aY&EHVx7Xp>nb!Q~OIqz)SCPab;genPE& zmoUac;!U=&`>-h&tUgMLU>97C0p(tuC|F>~HN}!LVmA1FX|++I|ijsTN8y27~@hJ)Ot*nDf16VLwc< z`l^TmF&BE&!l+E(efFCiVGFJ;L|SwmPqi32P_zb=dsy)GP4N0AYRNX^Yq=-8CiD`I zt?-+B=6+smlC_|3YAwEWp)!a))@tFtd)nA171rGQE5lu&@8Ywx3u>Q$2}z%TDX8xN zGqFE$Q!326R}nMlA>YtOc)r^uXffp2X))$_uNF`KNc56>6{ne@gFtWlsE6k>H0+}P z05fQ06V(NykH&?y55rWTFOskekDx!1Ncf>Qz5nCDkYnCU+Z*R&*bV2Mw$H;usY|9C z>P>ZOVY~~v8`9O-<0qGBeb#V){6py$lE7#HIsu)7_$66mKYkd^F&}sg2pb`6R46*qZ2$EKmIM z;eK2<3Xd4>=1~FHowZMN|La1U&7(rbKwP6>rLag7@;+@-zP<$$g1-Jw;l~8Etl{S0+=AmJNg?!e8wBhyO+o2Fv@#W|Gv$# zW9hJakDXn#Dg=ormUb`5m(uP5Z(*;$4c%jmp7Gs_B!3&a(=NS#r*KcpI&)vP^6lQ; z@@ioJ>^|+={j-@MoznZedkkQ1K>0)Bb-I@i83owk^v?{>)@{&bwy;n%Bn3r#>|ebh z(SSY22u@m+M}Ns$lv^RF4ObN~gl`%!YtYvOM4Ei+G4QMDe1L*N)P;k+wjs$(EvB+> z)g72mbg$DWzgA9KFRSbzU(yx-opuoMPH!@3$jp_heJkH%*}(%{yvQgPjaMK;7r$lP zD$FV!V<1Up2N2S);#vQFry#fs+UhM|R>z$A{!F!OpfBlTu~CYwm7*PIir z6aVa~=%S7^Cy--9r&(HD%!s%>kb8{!h~`Un9`7^vbni;%iuzeFkGbxynsbUXYNwu& zbK88AW|wrUzTdzpS%7$8|CzSFmYvKTr5)yMDpL$_A-?{pr}e}8tZz!h@ykC}?c=6a zRhFJJq7++|4BC-CW5$YS!-a3=@o%5MTyubWC)rr%uGs;a^4C>_ny@Cpw;9T;K zB+1}pd_N)YQeQ|&h)2-xVJc#= z#z~H<{3vOsR@CY#HfzSC&*4<$J?)3L1!CY0;Z*HqBLXo;Y6!P;=(E!8_lMV9{!~&F zAKZ_*7qZ*i|Gu|x_hmn(f%F&9O2LhKuZy$c@%zP5rup==_smHJkJHL`AP0MXz8xI?SM>BC@;yE(zcpmq5pLeiX8YQ5o$(yrn-uZgXZ;aAoO zma+O3_=)dqxoy-J*c<95)wMV}*2uKo%eOko=2prXGm;nE85+$36rc7}(NSTkTjmbW z2OgF0S$`A4Ed8S>(MzG8#E<;vzS;I8Xf3|j#CNn6 zL&cRtJG*xM@3WA@1r*Gc6AO{GIP|wt5mFQ9hMFEwLs34}q{HIhgmm6bKNXjKu9$%0 zZ@lz2a@pLgl=AEaO}znu&ui!S>C8Hf{D??~X`;EPAXnh-^tWGZPTox^Xt)$p0-$Cx zhYN*xpJXVtw`(lr?SHbzgztJ_y~!ObU$Wh7U&vhSJjeE9S7NW%5Vdk@p?+dF{HoWo z#o6+W3+BpfrjiBth9vE1w4(iU(sh^5$@&kcj{N*0oUH|LXWpFJQ39os` z8D0fh_ELIrWdO+i#!Sh$dv<}iK10apVM4(m)Kmov#BI8>X~wcmK;A$_O{%H6EPKEt zJU;Te@ijH+a%>VY8AT9oDkrym{1>uV9rNzhu60%gPp+AC*k1d*E)?cm*U0buOUO!9 z(JEF`1M^&(g0VJH_JZWR!3*cfsx8zyCNJPj^>|uRl`%o7Z&R0={5YI3o`>4juBXn* z%SG}Px{w1cntmz{2fJ-rYNOm}7GQzK^r0!2!p{ojBhz2~E7yK)!=Jp4ept{x!G4)y zEoU2XaN9O)h_xG&v$LN@cvr?4&raiV_-I9n6*6hhU-f3O$`Bj7MIb4jG6Tj?ML~i> zZ#L{uS1~Nmp1$O8*TrDwm;UR$kI>T~mOVC+z4GKOwLy)6r0HbrIJrzOHg8@8+M67^ za-l4`Idv%jv#`U((E78rJl}!;<<<094*pD5jea_3*VsI4gS}yMmrio_c#+`2QkmP_9>bXg4iMWBRF>k4dJaJNTo1_xMU}}>rLkzvBgA9Y5ngA6pdsdho zkco&rdRX>Dh6M2oPCcW&ay}m5hIQcRO^j}vLd*Dxx~faT@WTd9wq!fv$FmV+WAvgP z*dc5>FSEFc81~Dqr~1owddsnkqL^G{NZY@L2ql+DHK1DBsZCV0DGnrkY;}F(m2^@r z8NC}mnwq}aJL*Mc={IZPnvODO^9nmv)5?<&UY9*r*j{b8<2CsrpLZqHwsl5!=KSv&^H!r5pP$Z#Z-UJM2|vMOJ>U{Bv6p#ExU6ze?x`*qW&4@L#=P>(0kv=JV zX;GH7Ik;`hSX$Ew15(*fC1?v(DmkIv4j$CRvVslKeQ&Fj!!SqNdF1-s;>RzZ?_{G! z{yp1%mn)_rC{bn)LS?Wl$JI3l zU=(nS%!oz#1A4RWd&}TMzu)aoZ8w^;2NbP`qPRAi3UFUMu>1tyA;a+*elW;0m1A|S z#`<>7E?3(|8zz|oAF_HMvXauj3jpBh)CB=Acw)`|qO6tY%(qNj1i2VV=J4;te) zF+^0Gko9(RCWf<+EhQUx#oFyA59nEAB?mdTPDFnZ&NetyANg{QpP$yXn&uzCYF9<+ zJO9XV4={t?Ozq8)srB={?u1R^zOL1KVgMn**1_22j@0G+j(fKL)?{I(QdYLTbPjub zp9|Xs%JM}G*4UxlWyfAxp5sm%DgoFC`gJ!?|4o3F^y%T3Yrn}{KPkFq=PXb4(s0}0 zpFfo)x?vBmp0~al(k{rKGUGhatB<+Ti;3aj6bFt4^v7^>*)@X6xav5$?I;)RTHhQ6 z)EHX`S&r-%Q=i5>O=_g#->0=)b#E_|o_N7Qv>j7M;G&M$eo%HzfAISZXoY4g9t|Og1R9 z_Szr~ur&^2``=&!})ui1ooI~y_kH|9GJq!y}Wf4spc>gJ=F_Kh92xssNhZwsC5lfV9l_$gy(;xCWPik-Ei5N z^-u1h4xV}EjGVN8B~`UIP1P0YJ?=T4tknpn>YA~W9DDcdE+S!HTArhhr!SPF1$Rue zxT2^%L|8|ZV|ColEWX|IEj47m6-Ur_K$clQN8{(f)$a55D%gF2zeFiYt6XV4sNyo0 zUFdBy=z${&^cE=6_eyAg(*ooN%se7p8l8W>`?N^V#>Otxr8#lM98-lus--OO#H0Sz zQT}iwEl}X#(F<6HVBxi3#b_14aj!3B#qlc;Soa>AQRmAFsu+_QRR7uw>vrkvyJ}Hu?*Ut!(PkqwhCwnP<`THbljtDwXl}% znbvCdc!oGbq1)X$vj9PyA;{@?x|u9_I?FK|YB40JP1EVQGLr%+7C3sjA#^c7+8~$C zV|3;MyDoiV9{ApJYd2b{iuqah^Ulh9X1prFDyORW$tNP8v(z`7S}oXo+Y^m{fC_yK zW=K=GTeA+f^<8K|omHYx&*K1pnxye2f7@COMp?~ZotNkjeecxnW$s6N&R+_07Efzt zdS?Epua*)oezQLRwGC(=ZJKGBbilEosk;`;H{sm6anhClGxHjBgt0V)`tv0p8|g|+ zF6tW&eT}wpsIDGeXWDI=j~2*2Q%kk<^XVA2D(F@#1;blhjCvdYxa7%cUdeF6?ws#Q zVpfz@OwpDjZ#2r`Va8=1#1}TX!?{f*q4cxUMDD43W`^&84ubCQHgr+XtPG2#@rOc7 z`=k+e!p`r=^6c0rQQs)D#`e_cM>fU!^3LY5&{Dlf>T?BU%yu3Vp_arbFg(0674n~9 zI57lgJM#3kX1ffDDbyq;6{Wxr$FgMZ;&O-@gv z$VY+T@u0&#yk6MT`+d^YB}@GM%DLfBxe{~LnX5;&SrSV_1cesi4`)6kVef2l+zOV= zCagc=z{R_b66^gYd}QL9h765){~RmpL^5Hb`pO`>;xYboYlsn#+}1$RD6aBGlg5dEsPuZACZ%%Rq2j@hHGRzlC($kw(_&}rRr z_3a@r+i+KZoK~ebi*Kc=uW5v3@zX>AKjl+Q2NgwF^}#V6b)>qvDk4GOA z6Lf2?Gt5jV)5)X8dO$Ylgr?J%WV)o+O*G;=U267TqV-^ zYpEN}>jmG$>iJnQA5UwjgXivLAsHAd zKN`SmuG|M#)(Jqu9)X*8kr(3J zM25l7nPQ`-mN{9}(@?-0z#d2(e$(tU|kpk|hBtbzw~Ql} z2~4ly9^5O2d&Am|C5i98iFx|0iGGPXsUg;u7z{{xEIP8OpFxE#m(cYdF739hFtSDc zZGt^JhlO?N8=yHuy(r0A%Pt22kiwz-)vP`_{4~T(lW}we8jLkk9`hovK)Nu?L)KQ! zp{=Bv!&Bq9|7x{YVW2o+p%w27i)-HNw7yTf56~Fc=zWW?}ayEML19DCvEzb3QmpU~qbJ&%8()IAcC1`5RF_khN zq%hH^W*c6&WHD?pPn&NiQKbGP{lL2R)6Y_md0!TJ>K%$*nw@uE3d5D>%C6%lO20n3 za(>L(?w0CeImH#)p6ZcwAZzxkuNrwj&D?U+gun-&oC8noX_GEW=Ue$fDhAq${VO1; zaFMa+@Ij;HoU3=n%O10>#bjVv1QCzy(Shh)+o4QbJqxBMA8h)}}HCm14=+rXqzN%awA0#M?4mJ|;$Ox;2;7TNkBSgSa8iG4LmJJFxgC4PHk2bq!i_XFIVDIER(-k`8spy>$ zJH`T^>3V+}aro=woL7xL|8MCuo2~#~?d{@={A@+q0yQGdv~Q-M=SK^SJeUP4 zY57yC5MFUH;-r+Q5SjO{d4RnEe(SwLiSo8B86O0Gl(XAvvl79h*`i7)grHyfZ6vuXSsr)rAv)p+wEA5x@I{;h z>E=lc8cUtlyBLH0lLI16*$B41vg-bvTp;>uE9_yl6@CGMfgo!5iDN0n-8t7P%P>#h z!Y~g@Z(;t|t-#7jnT|pc9#mZ07N2z|)fb(@G94;WS3fKa=f*rw6pBq6Zpu8Q$l|P^ zLO}Pk#g6hnm*quW*VJycJbHt-YLV3A!(5<($i+=IP7qL;$UO1`$jw*k%xXMIQkD3N z+qRA>$E)kAU*G5Y_XQq{rLkG4hsp;5z^&eb{`!KC32Gwh{e+NmoV zxCMEFB(^y&#EyQcMwILO9?OR{iyYs0*a7Fq7qu}~6#C z+J0Wnd*(vB7UtHRGh$fZ+C2NV$-rPRP&vI+Cg{0apt4x$`(^p3hZQL;i{`Wz9;pOh zXstX_@#eRKL(gFEp5L1kKX63Le*DTy=16Xf=}{RIJ>A<>y^zs zTClGaB>6QK=WXY;NaIrGXqAlx&l4pXlBM0+SCePR%!89`6fo>x@5??8*sUbSw_qF#bO3{;PzqDv# zf1Aq!!+6$4)sQ0zZ6tV5U4T;gMxvRc^(IrCc<=qH&lU#u`CEc_e(m21N3xc68$DLD zSU((p^q#NIQE|I%g`A~VrE72eT5d%h9xtBCekS2m_wx0JC*Av#I~!aUwchl&b-Z|U z;{YBW7q-d;L9M6OuUX%9xw-fz z7t#gN+jsqHSTdz_>ka4?UYAyBXS~LmP-|!#uWq|7GP}rDP_k$~<=j;eAaW@cPW|*f z=eO|T?KP~Oy&|#c@!`BRS!Y`qtT!EWJDp~xxj`Q#KK{snvk;h3*=bU8jNmbOZ#P7!6e9~)}H*S}x zn)^^`!YPB=+qJ9WC2J*nKD?jSdm!2mxBzVUT=*D=ZepKuUT|&@_p6Fc+C~L%t)F9Byfv5dOi$tfB z9FWQvU)aGOakAihnpi2JUTl}LTofZZsnu(15$(kgb-MB5hck_k?K@Qs_ z@8DoM_nxUZH9b#6MJ}e~!-(3f{vO+d%T1EsJE9%wUWD%qT?m7AuQ7h!d|`C`it#hJ z?#olRURnR|bi!^|5=S7PKuqU%EytKotG%jXgO1H1g~Lg=hGO^UmTqc01^t6Q;aIsJ zFogD>eR3%@lrhhEn~2|TKh;z$Ki}!MHZFj%NNXH4@h(rNz4Wbh-I@Q7RQBefBj1v} zl@)F(uS5OKseYcWt37RkTeL6V$sSx0yT#|S&DYLiega~uK|6u~2Sv*~N=<3#yXArp)0#|J^{ zb-=dI_Sc)Xj@^#n!pmihH|@1m1S=&DnJ39IY|%RicWDz(FEIVDza7p4q8ZD~N(*ays$+C} zT}o{zU*!%MRqgm*{|vQtPV-LoZt^a>h|+HIMO`Od_wF?7@hf}%B3~Lhx^o{yE{g5} zbc>h3nj2O%86}3jvreaZAeY-6SH%KT9hKqTq?S zLn(buHZpo41roGmu6}_qa|< z##1hksHu6(*tIe0ab1lrNOHva7T%Y|ZssIxUttsEHYM;qrv6gL4JURqORi1cMpITE zi^~+F@%QJcTzFSN$Q7_))e@76Ui`dP6rF^BUXy&h*;UnMo4^bQ_<{;FpW{FWeMS`? zfBhMHYu{boIhlUpG#!72FPD=8t;urXSF|o-iOw+);{EL=OsqRFsf_qtol-sdbE5Ox zpB#5qc}v@Da=sJ9qcJ;)C zhjDbrBf2UR&)C70ZW3pr&&RC1jKf+>_&>jU9m9~#=Ntj{otzY-{AdkeFxEg5t5@7~ zIe&1gK7qpGtfgfIT{zB^TQ18wpFRpI)1~01eva|FPC2-hDAS+*i+;_S&~EFARoCAjwzntS#?uVnj9gNxG8!xK zL*NIoZ0eLwGW}^_1Eqe=RpCN_0Q0wmUB>Ax=I7&NX_%j<YZGB%!bBYuc z{5sk$@+~izV5*_8i-RbR%Ds_Xs)>4uz7;B`@J%a$qrUGDMnKac%XFh4=_H&qqF>>_^X}-57pCJP55hc=KlY z**Kp8)9<7$zZS&KKYdp7gWpq5 zk6Z@Z>Au#SG@L)$%@*)F7>zm`@wJJB7X3EmKk_Q#{PBD0U@s6@XiPQ(;w#L9Pu?X$ z>ZL_OKbpOh`&3uji>sX(e{a{f$r)?$%3nNUOaW-XqA}x@6U63e_*uJc+5xPcg?KUW zxFr)cW1v%>@8a1SK6L1C)>_J`rg)7#ae6{X&ii}Gnxoasfz{JD;flViifwBjgm`1? zqGI7Gx@GlWN2@U!%yfTpCUq(9q&d>s3~_d|*r97A$_X z|Dfl$yV~xPTmA#f7-rY5GUb|d!MP;0y>+l>2cv;Y$Ei2X5dR2IizVFC#zG! z8m-^Tq&jSx4R?=y@lGC}2eLaGT*AV-K^0X|%xS)?nhyD0#l1h8Q{+-|J3r=l%#)Ow87}pn(Z9HNqg}CZiBS1-g}%!<2Js;OQj)pykl|A6JBDHnvGSQ zrpj`H0@oFjrU&u;%e?2}9XqWIS*_o)MlIcw8S3824XwPZ-7qCz?03EY=5z9;=jV?6 zwz{f0U9-Ze^$+RIDWTvSpemFKWRXAhxe7oQz99C-ON2ifnN*Ixt+ zr;FLs>K7I-!XJ;)Xj3`yt}@=N-aPV67Pft{+JWOWc3s^~zVT`U9LNx8cD?ATCv1O~ zZ2>g{MP^k8B~(x`+R>aX{1BMb{(k6&puOueqd}a$^B-Hoko9 zYWz_w=SjU?edJtJKpRXm*V5Q(!^Zi2m6zt@m$hF$k?-DU@VQ+S!Q3eCb@T*!oz`S} zMT}?JWr*eQB!QKcy%x}_thI#twkGk17+D6drO3;n_Qz=LW|$mak&F!NO0sIzEt61P92?(r?U*_=;wo>1Hro;d}rGr<)Twmngb6a}=8}=Isuf;{akCmr!R`iNw z=h4Y8S8pUV@RZa>usu`c=D7J8?Q$$wpY3Pw&rYhbC^9JC$Y{NK+vp%s z;)A~Ubko<(c?AC;BA2^uAFY2cN$R&W;m>`39g1~Rb@~=nu#<6T^sUx`*~FU5 z#iuD{W*Yf)C}MpN$LAcE<@qr0UF;f5L)o?^y^#tIQU!B?~Dtyt4Duy@w%nl@5Gg+MPnTXtDggsSWOK{4D zRs6D0XUFSF4Me=iuv9t2lJTf}VfU4yo7Ai+PFB%wLA;+P)Y+Bk#{uWZP0n|N42L`J zu6sXfe@Dl|W9@H919Ci@aw`enOE}Jw?SpC+%%Ag8(QwBOsoHRW$@L;KB6ZO9kKSir z!LBUg+#xVZASIAofXte6a+U5~vqP=%j}EAN?3=m3_U-dH{oIRkx1i@AZ-z^ zKudU8z;@iVJN1*NRh~O>VYRN788^aH&}FX%#adr=f7#cb z#^RnreqK}1wiY*_;%iCelYK_-lyS-j-MeK2ccFpbkBT(g9bk;A*5tWQA)4?aeEt>J zPogx27CTNC-smIsUiF^(|t#>yG;)uA^~N9b#!qZm;SpYAvH?L23my??3mz|(L#UeSr(gQb$6WWi2a4=Vqb1sb z@32-J@RD}CTn0Cm42=qR)3kL|Ne)M=Yxll&W7?X`lULhWy!*&);rpCw#eQ z3s&ly!r9|l9CII)aDKfj{y8|Yxz!$8o39pe0)oF1Ow`TR)Im`L0o?N!5gQx;;Rf=7z+h~iKLc1gc_8?}{+pZ&n@8Ql(ou^J z3_;L#Auz&V|AGiZU{QhofLmen$an1D zt++r4)-65&9{@xL1ONbZya<}G|N066LiDEx0#V2khyeNegE^%3KS7B8AApgN(82yN zL8<*ubg;jd{vRl%{~v(C_#lA);!{I_enFtzybvG=Ob3S3>Hi@aLon+h_{|UiU{EMG z91i4#|AQWeK>zx`O%b4J`VatO3CPR?q{bvkBBf9_mZ%Bury@UPF zDPa%MU^wGLeDzObJ_IQn2#DC1|2rrG73|+b{%?3-|AP(i{|yZa1o#^d48eFt z*m3;_4~)U3k1>rW69qeg#BRZgVQ2V~r-uH^>QPDFi z4AtULC0kopYL;h&dL8T&m-r>bhY5Y!XYr;<@QRpF#pe>P z{W>StD7Rs9>RTgJ!)o4DCw)L?Wr;;BaCEks@w!wxD#SrwmR8$o{l$dw;E)5M7mE9L zDO_Ud8O+A`F8XI?L2_(0cd5AVZ^)Hp=DfD5>g3P!uJ>U|+?LO;Urxgc&L~v!Nca(` zU|rsk`wPxoA4fv=HkVS=lU35heSk_k(K06!_!34@9mKvx)3X+G^G|+dl}aRAceOW5 z#&ZUBIoQxtWmNwn!L!FLHi#$(*JMLObv4FrQDWsY^N=I|e~`@mfdixaCvXr^>S^Zj z&%a0*VSk6f|7Uoxe~1wOf(QGDc z0w9nr|L%)mef- z0zMO|FBsWYP#Cfg{lkFzmkkiCkVy9910eev420~bd=R8O3FHGK+lmj7VE)#bj}O^a zFka;NfB`^A`oR$i`tR{z5D1b@5!EEJ3Z~#&s2O&gA{sM9Mm9SnILh%*_<28i^6 z)E5Xq+H=H30rt0Ffe`r_$$lUx(m9QQv4tb|}D^k^BV$1S8oG0zq6*{_-mb7%8?u2s&z{wLuW~p}+e=d6DBBan2yw z8ODoL(;z^Ok!lMN6o`~h5i3LXNkmzPWK$>~QcVa#ga?u?P&jgIL19Qa48(_ExBh#* zd;nxS^MR0R0T3S$**Ez97eC+w!~V|qAU*_MFVehx0HpOI@;%a?^TBzM`ojL;fd94U z2r_RZ-+;l8V;atjoY&w8@BMo`M49;a9Eds_$^XDW;yV3TUtSneT>|}Iavc;1MyeU0K=>ax^go~fjv!t>V_WuE+_"; - "-"; - "e:/Project/Digial-IDE/digital-ide/src/test/vlog/dependence_test/hello.v"; diff --git a/src/test/vlog/formatter_test/formatter_test.v b/src/test/vlog/formatter_test/formatter_test.v deleted file mode 100644 index 8766fd4..0000000 --- a/src/test/vlog/formatter_test/formatter_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module formatter_vlog #( - parameter INPUT_WIDTH = 12, - parameter OUTPUT_WIDTH = 12 -) ( - input clk_in, - input rst_n, - input [INPUT_WIDTH - 1 : 0]data_in, - output [OUTPUT_WIDTH - 1 : 0]data_out -); - -reg [3:0] cnt; always @(posedge clk_in or posedge rst_n) begin if(rst_n) begin cnt<=4'h0; end else begin cnt<=cnt+4'h1; end end endmodule //module_name \ No newline at end of file diff --git a/src/test/vlog/fsm_test/fsm_test.v b/src/test/vlog/fsm_test/fsm_test.v deleted file mode 100644 index 95b2134..0000000 --- a/src/test/vlog/fsm_test/fsm_test.v +++ /dev/null @@ -1,58 +0,0 @@ -module fsm_test( - input clock, - input reset, - input [2 : 0] req_0, - input [2 : 0] req_1, - output reg [2 : 0] gnt_0, - output reg [2 : 0] gnt_1 - ); - - reg [2:0] state; - - parameter IDLE = 3'h1; - parameter GNT0 = 3'd2; - parameter GNT1 = 3'b100; - - always @ (posedge clock) begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end - else - case(state) - IDLE : - if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end - else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT1; - end - else begin - state <= #1 IDLE; //example comment - end - GNT0 : - if (req_0 == 1'b1) begin - state <= #1 GNT0; - end - else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : - if (req_1 == 1'b1) begin - state <= #1 GNT1; - end - else begin - gnt_1 <= 0; - state <= #1 IDLE; - end - default : - state <= #1 IDLE; - endcase - end - - -endmodule //module_name diff --git a/src/test/vlog/netlist_test/netlist_test.v b/src/test/vlog/netlist_test/netlist_test.v deleted file mode 100644 index 0abc1fd..0000000 --- a/src/test/vlog/netlist_test/netlist_test.v +++ /dev/null @@ -1,33 +0,0 @@ -// borrowed with some modifications from -// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html -module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out); - -input [8:0] data_in; -input clock, up, down; - -output reg [8:0] count_out; -output reg carry_out, borrow_out, parity_out; - -reg [9:0] cnt_up, cnt_dn; -reg [8:0] count_nxt; - -always @(posedge clock) -begin - cnt_dn = count_out - 3'b 101; - cnt_up = count_out + 2'b 11; - - case ({up,down}) - 2'b 00 : count_nxt = data_in; - 2'b 01 : count_nxt = cnt_dn; - 2'b 10 : count_nxt = cnt_up; - 2'b 11 : count_nxt = count_out; - default : count_nxt = 9'bX; - endcase - - parity_out <= ^count_nxt; - carry_out <= up & cnt_up[9]; - borrow_out <= down & cnt_dn[9]; - count_out <= count_nxt; -end - -endmodule \ No newline at end of file diff --git a/src/test/vlog/parse_test/Cordic.v b/src/test/vlog/parse_test/Cordic.v deleted file mode 100644 index d52576a..0000000 --- a/src/test/vlog/parse_test/Cordic.v +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps - -module Cordic #( - parameter XY_BITS = 12, - parameter PH_BITS = 32, - parameter ITERATIONS = 32, - parameter CORDIC_STYLE = "ROTATE", - parameter PHASE_ACC = "ON" -)( - input clk, - input RST, - input signed [XY_BITS-1:0] x_i, - input signed [XY_BITS-1:0] y_i, - input signed [PH_BITS-1:0] phase_in, - input valid_in, - - output valid_out, - output signed [XY_BITS-1:0] x_o, - output signed [XY_BITS-1:0] y_o, - output signed [PH_BITS-1:0] phase_out -); - -localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2; - -/* -//360°--2^16,phase_in = 16bits (input [15:0] phase_in) -//1°--2^16/360 -*/ -function [PH_BITS-1:0] tanangle; -input [4:0] i; -begin - case (i) - 5'b00000: tanangle = (32'h20000000 >> (32 - PH_BITS)); //tan = 1/2^1 = 1/2 - 5'b00001: tanangle = (32'h12e4051e >> (32 - PH_BITS)); //tan = 1/2^2 = 1/4 - 5'b00010: tanangle = (32'h09fb385b >> (32 - PH_BITS)); //tan = 1/2^3 = 1/8 - 5'b00011: tanangle = (32'h051111d4 >> (32 - PH_BITS)); //tan = 1/2^4 = 1/16 - 5'b00100: tanangle = (32'h028b0d43 >> (32 - PH_BITS)); //tan = 1/2^5 = 1/32 - 5'b00101: tanangle = (32'h0145d7e1 >> (32 - PH_BITS)); //tan = 1/2^6 = 1/64 - 5'b00110: tanangle = (32'h00a2f61e >> (32 - PH_BITS)); //tan = 1/2^7 = 1/128 - 5'b00111: tanangle = (32'h00517c55 >> (32 - PH_BITS)); //tan = 1/2^8 = 1/256 - 5'b01000: tanangle = (32'h0028be53 >> (32 - PH_BITS)); //tan = 1/2^9 = 1/512 - 5'b01001: tanangle = (32'h00145f2f >> (32 - PH_BITS)); //tan = 1/2^10 = 1/1024 - 5'b01010: tanangle = (32'h000a2f98 >> (32 - PH_BITS)); //tan = 1/2^11 = 1/2048 - 5'b01011: tanangle = (32'h000517cc >> (32 - PH_BITS)); //tan = 1/2^12 = 1/4096 - 5'b01100: tanangle = (32'h00028be6 >> (32 - PH_BITS)); //tan = 1/2^13 = 1/8192 - 5'b01101: tanangle = (32'h000145f3 >> (32 - PH_BITS)); //tan = 1/2^14 = 1/16384 - 5'b01110: tanangle = (32'h0000a2fa >> (32 - PH_BITS)); //tan = 1/2^15 = 1/32768 - 5'b01111: tanangle = (32'h0000517d >> (32 - PH_BITS)); //tan = 1/2^16 = 1/65536 - 5'b10000: tanangle = (32'h000028be >> (32 - PH_BITS)); //tan = 1/2^17 = 1/131072 - 5'b10001: tanangle = (32'h0000145f >> (32 - PH_BITS)); //tan = 1/2^18 = 1/262144 - 5'b10010: tanangle = (32'h00000a30 >> (32 - PH_BITS)); //tan = 1/2^19 = 1/524288 - 5'b10011: tanangle = (32'h00000518 >> (32 - PH_BITS)); //tan = 1/2^20 = 1/1048576 - 5'b10100: tanangle = (32'h0000028c >> (32 - PH_BITS)); //tan = 1/2^21 = 1/2097152 - 5'b10101: tanangle = (32'h00000146 >> (32 - PH_BITS)); //tan = 1/2^22 = 1/4194304 - 5'b10110: tanangle = (32'h000000a3 >> (32 - PH_BITS)); //tan = 1/2^23 = 1/8388608 - 5'b10111: tanangle = (32'h00000051 >> (32 - PH_BITS)); //tan = 1/2^24 = 1/16777216 - 5'b11000: tanangle = (32'h00000029 >> (32 - PH_BITS)); //tan = 1/2^25 = 1/33554432 - 5'b11001: tanangle = (32'h00000014 >> (32 - PH_BITS)); //tan = 1/2^26 = 1/67108864 - 5'b11010: tanangle = (32'h0000000a >> (32 - PH_BITS)); //tan = 1/2^27 = 1/134217728 - 5'b11011: tanangle = (32'h00000005 >> (32 - PH_BITS)); //tan = 1/2^28 = 1/268435456 - 5'b11100: tanangle = (32'h00000003 >> (32 - PH_BITS)); //tan = 1/2^29 = 1/536870912 - 5'b11101: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^30 = 1/1073741824 - 5'b11110: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^31 = 1/2147483648 - 5'b11111: tanangle = (32'h00000000 >> (32 - PH_BITS)); //tan = 1/2^32 = 1/4294967296 - endcase -end -endfunction - -reg [1:0] data_in_buff [ITERATIONS:0]; -reg signed [XY_BITS-1:0] x [ITERATIONS:0]; -reg signed [XY_BITS-1:0] y [ITERATIONS:0]; -reg signed [PH_BITS-1:0] z [ITERATIONS:0]; - -integer m; -initial begin - for (m = 0; m<=ITERATIONS; m=m+1) begin - x[m] = 0; - end -end - -integer n; -initial begin - for (n = 0; n<=ITERATIONS; n=n+1) begin - y[n] = 0; - end -end - -integer s; -initial begin - for (s = 0; s<=ITERATIONS; s=s+1) begin - z[s] = 0; - end -end - -integer k; -initial begin - for (k = 0; k<=ITERATIONS; k=k+1) begin - data_in_buff[k] = 0; - end -end - -genvar i; -generate for(i=0;i>>i); - y[i+1] <= y[i] - (x[i]>>>i); - z[i+1] <= z[i] + tanangle(i); - end - else begin - x[i+1] <= x[i] - (y[i]>>>i); - y[i+1] <= y[i] + (x[i]>>>i); - z[i+1] <= z[i] - tanangle(i); - end - end - else if(CORDIC_STYLE == "VECTOR") begin - if (y[i] > 0) begin - x[i+1] <= x[i] + (y[i]>>>i); - y[i+1] <= y[i] - (x[i]>>>i); - z[i+1] <= z[i] + tanangle(i); - end else begin - x[i+1] <= x[i] - (y[i]>>>i); - y[i+1] <= y[i] + (x[i]>>>i); - z[i+1] <= z[i] - tanangle(i); - end - end - end -end -always @ (posedge clk) begin - data_in_buff[i+1] <= data_in_buff[i]; -end -end -endgenerate - -generate if (CORDIC_STYLE == "ROTATE") begin : IQ_Gen -reg [PH_BITS - 1 : 0] Phase_input = 0; -if (PHASE_ACC == "ON") begin - reg [PH_BITS - 1 : 0] addr_r0 = 0; - always @(posedge clk) begin - addr_r0 <= addr_r0 + phase_in; - end - always @(posedge clk) begin - Phase_input <= addr_r0; - end -end -else if (PHASE_ACC == "OFF") begin - always @(posedge clk) begin - Phase_input <= phase_in; - end -end -always @(posedge clk) begin - if(valid_in & (~RST)) begin - x[0] <= K_COS; - y[0] <= 0; - z[0] <= Phase_input[PH_BITS - 3 : 0]; - data_in_buff[0] <= Phase_input[PH_BITS - 1 : PH_BITS - 2]; - end - else begin - x[0] <= 0; - y[0] <= 0; - z[0] <= 0; - data_in_buff[0] <= 0; - end -end -reg signed [XY_BITS-1:0] cos = 0; -reg signed [XY_BITS-1:0] sin = 0; -always @ (posedge clk) begin - case(data_in_buff[ITERATIONS]) - 2'b00:begin //if the phase is in first quadrant,the sin(X)=sin(A),cos(X)=cos(A) - cos <= x[ITERATIONS]; - sin <= y[ITERATIONS]; - end - 2'b01:begin //if the phase is in second quadrant,the sin(X)=sin(A+90)=cosA,cos(X)=cos(A+90)=-sinA - cos <= ~(y[ITERATIONS]) + 1'b1;//-sin - sin <= x[ITERATIONS];//cos - end - 2'b10:begin //if the phase is in third quadrant,the sin(X)=sin(A+180)=-sinA,cos(X)=cos(A+180)=-cosA - cos <= ~(x[ITERATIONS]) + 1'b1;//-cos - sin <= ~(y[ITERATIONS]) + 1'b1;//-sin - end - 2'b11:begin //if the phase is in forth quadrant,the sin(X)=sin(A+270)=-cosA,cos(X)=cos(A+270)=sinA - cos <= y[ITERATIONS];//sin - sin <= ~(x[ITERATIONS]) + 1'b1;//-cos - end - endcase -end -assign x_o = cos; -assign y_o = sin; -assign phase_out = z[ITERATIONS]; -end -endgenerate - -generate if (CORDIC_STYLE == "VECTOR") begin : Demodule_Gen -localparam signed [PH_BITS-1:0] PHASE_COE = (2**(PH_BITS-2)) - 1; -//localparam MODUIUS_COE = ; -always @(posedge clk) begin - if(valid_in & (~RST)) begin - case ({x_i[XY_BITS-1],y_i[XY_BITS-1]}) - 2'b00 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - 2'b01 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - 2'b10 : begin x[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; - y[0] <= -{x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end - 2'b11 : begin x[0] <= -{y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; - y[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end - default : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; - y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end - endcase - z[0] <= phase_in; - data_in_buff[0] <= {x_i[XY_BITS-1],y_i[XY_BITS-1]}; - end - else begin - x[0] <= 0; - y[0] <= 0; - z[0] <= 0; - data_in_buff[0] <= 0; - end -end -reg [XY_BITS*2-1:0] Modulus = 0; -wire [XY_BITS*2-1:0] Modulus_buf; -reg signed [PH_BITS - 1:0] phase_r = 0; -always @ (posedge clk) begin - case(data_in_buff[ITERATIONS]) - 2'b00:begin phase_r <= $signed(z[ITERATIONS]); end - 2'b01:begin phase_r <= $signed(z[ITERATIONS]); end - 2'b10:begin phase_r <= $signed(z[ITERATIONS]) + $signed(PHASE_COE); end - 2'b11:begin phase_r <= $signed(z[ITERATIONS]) - $signed(PHASE_COE); end - endcase - Modulus[XY_BITS:0] <= x[ITERATIONS]; -end -assign Modulus_buf = (Modulus * 32'd39797)>>15; -assign x_o = Modulus_buf[XY_BITS-1:0]; -assign y_o = y[ITERATIONS]; -assign phase_out = phase_r; -end -endgenerate - -reg [ITERATIONS+1:0] v = 0; -always @ (posedge clk) begin - if (RST) - v <= 0; - else begin - v <= v << 1; - v[0] <= valid_in; - end -end -assign valid_out = v[ITERATIONS+1]; - -endmodule diff --git a/src/test/vlog/parse_test/instance_test.v b/src/test/vlog/parse_test/instance_test.v deleted file mode 100644 index cea48e2..0000000 --- a/src/test/vlog/parse_test/instance_test.v +++ /dev/null @@ -1,11 +0,0 @@ -`include "./Cordic.v" -module instance_test ( - input input_a, - input input_b, - output output_c -); - - assign output_c = input_a & input_b; - - -endmodule \ No newline at end of file diff --git a/src/test/vlog/parse_test/mult_module.v b/src/test/vlog/parse_test/mult_module.v deleted file mode 100644 index d202dd5..0000000 --- a/src/test/vlog/parse_test/mult_module.v +++ /dev/null @@ -1,80 +0,0 @@ -// template -module template #( - parameter INPUT_WIDTH = 12, - parameter OUTPUT_WIDTH = 12 - )( - input [INPUT_WIDTH - - 1 : 0]data_in, - output reg clk_in = (INPUT_WIDTH - - OUTPUT_WIDTH) , - clk=9'hd0, - input rst_n, RST, - output [OUTPUT_WIDTH - 1 : 0] data_out - ); - -endmodule //template - - -module test # ( - parameter INPUT_WIDTH = 12, - parameter OUTPUT_WIDTH = 12 - )( - input clk_in, - input rst_n, - input [INPUT_WIDTH - 1 : 0] data_in , - input [3:2] dasta_ff, - - output reg signed [OUTPUT_WIDTH - 1 : 0] data_out, - output reg signed [OUTPUT_WIDTH - 1 : 0] data_ff - ); - - wire valid_out; - - Cordic #( - .XY_BITS ( 12 ), - .PH_BITS ( 32 ), - .ITERATIONS ( 32 ), - .CORDIC_STYLE ( "ROTATE" ), - .PHASE_ACC ( "ON" )) - u_Cordic( - //input - .clk_in ( clk_in ), - .RST ( RST ), - .x_i ( x_i ), - .y_i ( y_i ), - .phase_in ( phase_in ), - .valid_in ( valid_in ), - - //output - .x_o ( x_o ), - .y_o ( y_o ), - .phase_out ( phase_out ), - .valid_out ( valid_out ) - - //inout - ); - - wire [3 : 0] count_high; - wire [3 : 0] count_low; - wire over; - - template u_template( - //input - .clk ( clk ), - .data ( data ), - .en ( en ), - .load ( load ), - .rst ( rst ), - .switch ( switch ), - - //output - .count_high ( count_high ), - .count_low ( count_low ), - .over ( over ) - - //inout - ); - - - -endmodule //test diff --git a/src/test/vlog/wavedrom_test/sample.v b/src/test/vlog/wavedrom_test/sample.v deleted file mode 100644 index 742e92c..0000000 --- a/src/test/vlog/wavedrom_test/sample.v +++ /dev/null @@ -1,35 +0,0 @@ -module dependence_1 ( - input a, b, c, - output Q -); - - // a & b | ((b & c) & (b | c)) - // &=*, |=+ AB + BC(B+C) - // Distribute AB + BBC + BCC - // Simplify AA = A AB + BC + BC - // Simplify A + A = A AB + BC - // Factor B(A+C) - - assign Q = a & (b | c); - -endmodule - -`include "adwada" - -`define main dwwds -`define ada wss - -/* - -*/ - -`main - -module dependence_2 ( - input a, b, c, - output Q -); - - assign Q = a & b | ((b & c) & (b | c)); - -endmodule \ No newline at end of file