update readme & engine version & support vscodium
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parent
3838196cca
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@ -13,6 +13,7 @@ script
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resources/**/*.js
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resources/**/*.d.ts
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resources/**/*.wasm
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resources/**/*.tar.gz
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resources/dide-lsp/server
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tsconfig.json
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design
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42
README.md
42
README.md
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## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
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[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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@ -13,39 +12,38 @@
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</div>
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## 0.4.0 新增内容
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## New in 0.4.0
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**使用 Rust 重写全新的解析器与语言服务**：支持 verilog, vhdl, system verilog，性能更快，服务更加稳定。
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**Rewritten Parser and Language Services in Rust**: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services.
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**修缮内容的文档化**：提供更加直接快速的，关于当前 HDL 文件的基本信息和依赖信息。支持 wavedrom 风格的注释并支持将其渲染成可视化的图表。
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**Improved Documentation**: Provides more direct and faster access to basic information and dependencies of the current HDL file. Supports Wavedrom-style comments and renders them into visual diagrams.
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**新增内容的 Vcd 渲染器**：增加顶部工具栏、系统信标等组件；支持左侧面板选定信号的拖拽、分组等功能、支持按住 shift 连续选中一片信号并进行增加和删除操作；支持基于系统信标建立相对坐标系；顶部工具栏支持选中信号的显示数字的进制转换，渲染模态切换，支持将信号渲染为模拟量。
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**New VCD Renderer**: Added top toolbar, system beacon, and other components; supports drag-and-drop and grouping of selected signals in the left panel, as well as selecting multiple signals by holding Shift for addition and deletion; supports establishing a relative coordinate system based on system beacons; the top toolbar supports base conversion for displayed numbers of selected signals, rendering mode switching, and rendering signals as analog values.
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- 全新的 Netlist 渲染器
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- Brand New Netlist Renderer
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## Feature
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- 增加对于 vhdl 的 全面支持（文件树、LSP等）
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- 增加 verilog, vhdl, xdc, tcl, vvp, vcd 等语言或生成文件的工作区图标
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- 增加对于 vivado, modelsim, verilator 的支持，用户可以通过设置 `function.lsp.linter.vhdl.diagnostor`(设置 vhdl) 和 `function.lsp.linter.vlog.diagnostor`(设置 verilog) 来使用这些第三方工具的仿真和自动纠错。
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- 增加对于 TCL, XDC, VVP 等脚本的 LSP 和 语法高亮 支持。
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## Features
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- Added comprehensive support for VHDL (file tree, LSP, etc.)
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- Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc.
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- Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog).
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- Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP.
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## Change
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- 将插件的工作状态显示在 vscode 下侧的状态栏上，利于用户了解目前的设置状态
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- 状态栏右下角现在可以看到目前选择的linter以及是否正常工作了
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- 优化项目配置目录
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- 优化自动补全的性能
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## Changes
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- Display the plugin's working status in the status bar at the bottom of VSCode, making it easier for users to understand the current settings.
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- The bottom-right corner of the status bar now shows the currently selected linter and whether it is functioning properly.
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- Optimized project configuration directory.
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- Improved auto-completion performance.
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## Bug 修复
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- 修复文档化 input, output 处注释无法正常显示到文档的 bug
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- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
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- 修复 iverilog 仿真功能中，将 <code>`include</code> 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
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- 修复其他已知 bug
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## Bug Fixes
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- Fixed a bug where comments on `input` and `output` were not displayed correctly in the documentation.
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- Fixed a bug in the Icarus Verilog simulation feature where duplicate paths were included as compilation parameters.
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- Fixed a bug in the Icarus Verilog simulation feature where adding or removing <code>`include</code> would cause simulation compilation to fail (the `instModPathStatus` property of the instance was not updated).
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- Fixed other known bugs.
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51
README_CN.md
Normal file
51
README_CN.md
Normal file
@ -0,0 +1,51 @@
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<div align="center">
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<img src="./images/icon.png"/>
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## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
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[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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</div>
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## 0.4.0 新增内容
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**使用 Rust 重写全新的解析器与语言服务**：支持 verilog, vhdl, system verilog，性能更快，服务更加稳定。
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**修缮内容的文档化**：提供更加直接快速的，关于当前 HDL 文件的基本信息和依赖信息。支持 wavedrom 风格的注释并支持将其渲染成可视化的图表。
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**新增内容的 Vcd 渲染器**：增加顶部工具栏、系统信标等组件；支持左侧面板选定信号的拖拽、分组等功能、支持按住 shift 连续选中一片信号并进行增加和删除操作；支持基于系统信标建立相对坐标系；顶部工具栏支持选中信号的显示数字的进制转换，渲染模态切换，支持将信号渲染为模拟量。
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- 全新的 Netlist 渲染器
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## Feature
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- 增加对于 vhdl 的 全面支持（文件树、LSP等）
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- 增加 verilog, vhdl, xdc, tcl, vvp, vcd 等语言或生成文件的工作区图标
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- 增加对于 vivado, modelsim, verilator 的支持，用户可以通过设置 `function.lsp.linter.vhdl.diagnostor`(设置 vhdl) 和 `function.lsp.linter.vlog.diagnostor`(设置 verilog) 来使用这些第三方工具的仿真和自动纠错。
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- 增加对于 TCL, XDC, VVP 等脚本的 LSP 和 语法高亮 支持。
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## Change
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- 将插件的工作状态显示在 vscode 下侧的状态栏上，利于用户了解目前的设置状态
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- 状态栏右下角现在可以看到目前选择的linter以及是否正常工作了
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- 优化项目配置目录
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- 优化自动补全的性能
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## Bug 修复
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- 修复文档化 input, output 处注释无法正常显示到文档的 bug
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- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
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- 修复 iverilog 仿真功能中，将 <code>`include</code> 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
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- 修复其他已知 bug
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@ -9,7 +9,7 @@
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"l10n": "./l10n",
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"icon": "images/icon.png",
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"engines": {
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"vscode": "^1.94.0"
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"vscode": "^1.85.0"
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},
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"keywords": [
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"FPGA Develop Support",
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@ -107,6 +107,6 @@ pipe.add_command('make vsix installer', 'vsce package')
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pipe.add_command('modify vsix installer', lambda : modify_vsix())
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# pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
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# pipe.add_command('remove out', lambda : remove_folder('out'))
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pipe.add_command('install', lambda : install_extension())
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# pipe.add_command('install', lambda : install_extension())
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pipe.run()
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