From 46674383afa404068c74a49e9bc9bd05d64472b1 Mon Sep 17 00:00:00 2001
From: Kirigaya <1193466151@qq.com>
Date: Tue, 31 Dec 2024 16:25:45 +0800
Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=96=B0=20readme?=
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---
 README.md | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/README.md b/README.md
index e44873d..3748b6f 100644
--- a/README.md
+++ b/README.md
@@ -1,10 +1,8 @@
-<center>
+<div align="center">
 <img src="./images/icon.png"/>
 
-### Digital IDE <div style="color: #cb81da;background-color:#2d323b;width: fit-content;padding: 2px 7px;border-radius: .7rem"></div>
-All in one vscode plugin for Verilog/VHDL development
+## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
 
-<br>
 
 [Document (New)](https://sterben.nitcloud.cn/) | [中文文档 (New)](https://sterben.nitcloud.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
 
@@ -14,7 +12,7 @@ All in one vscode plugin for Verilog/VHDL development
 ![](https://img.shields.io/badge/VHDL-support-green)
 ![](https://img.shields.io/badge/SystemVerilog-building-black)
 
-</center>
+</div>
 
 ## 0.4.0 新增内容