From 4cf74020d2e71db4354ec6bad547b39b545b70fe Mon Sep 17 00:00:00 2001 From: LSTM-Kirigaya <1193466151@qq.com> Date: Mon, 3 Mar 2025 22:29:45 +0800 Subject: [PATCH] fix simulate --- .vscodeignore | 2 + README.md | 6 +- README_CN.md | 51 ------------- design/lsp.drawio | 120 ------------------------------- package.json | 2 +- project/property-schema.json | 3 +- resources/dide-netlist/README.md | 12 ++-- scripts/command/make_package.py | 6 +- src/function/index.ts | 6 +- src/function/lsp-client/cdn.ts | 5 +- src/function/sim/simulate.ts | 35 ++++++--- src/manager/PL/xilinx.ts | 26 +++---- src/manager/prj.ts | 1 - 13 files changed, 59 insertions(+), 216 deletions(-) delete mode 100644 README_CN.md delete mode 100644 design/lsp.drawio diff --git a/.vscodeignore b/.vscodeignore index 11a8cac..cb616f7 100644 --- a/.vscodeignore +++ b/.vscodeignore @@ -2,6 +2,8 @@ .gitignore **/.gitignore .git +.github +doc **/*.map .eslintrc.json dist diff --git a/README.md b/README.md index da1adf9..a4677f4 100644 --- a/README.md +++ b/README.md @@ -13,7 +13,7 @@ -## New in 0.4.0 +## Features **Rewritten Parser and Language Services in Rust**: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services. @@ -31,8 +31,8 @@ ![](./figures/netlist.png) -## Features -- Added comprehensive support for VHDL (file tree, LSP, etc.) +## New 0.4.1 +- Added comprehensive support for VHDL & SV (file tree, LSP, etc.) - Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc. - Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog). - Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP. diff --git a/README_CN.md b/README_CN.md deleted file mode 100644 index 4f231f0..0000000 --- a/README_CN.md +++ /dev/null @@ -1,51 +0,0 @@ -
- - -## Digital IDE | All in one vscode plugin for Verilog/VHDL development - - -[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0) - -![](https://img.shields.io/badge/version-0.4.0-purple) -![](https://img.shields.io/badge/Verilog-support-green) -![](https://img.shields.io/badge/VHDL-support-green) -![](https://img.shields.io/badge/SystemVerilog-support-green) - -
- -## 0.4.0 新增内容 - -**使用 Rust 重写全新的解析器与语言服务**：支持 verilog, vhdl, system verilog，性能更快，服务更加稳定。 - -![](./figures/lsp.png) - -**修缮内容的文档化**：提供更加直接快速的，关于当前 HDL 文件的基本信息和依赖信息。支持 wavedrom 风格的注释并支持将其渲染成可视化的图表。 - -![](./figures/doc.png) - -**新增内容的 Vcd 渲染器**：增加顶部工具栏、系统信标等组件；支持左侧面板选定信号的拖拽、分组等功能、支持按住 shift 连续选中一片信号并进行增加和删除操作；支持基于系统信标建立相对坐标系；顶部工具栏支持选中信号的显示数字的进制转换，渲染模态切换，支持将信号渲染为模拟量。 - -![](./figures/vcd.png) - - -- 全新的 Netlist 渲染器 - -![](./figures/netlist.png) - -## Feature -- 增加对于 vhdl 的 全面支持（文件树、LSP等） -- 增加 verilog, vhdl, xdc, tcl, vvp, vcd 等语言或生成文件的工作区图标 -- 增加对于 vivado, modelsim, verilator 的支持，用户可以通过设置 `function.lsp.linter.vhdl.diagnostor`(设置 vhdl) 和 `function.lsp.linter.vlog.diagnostor`(设置 verilog) 来使用这些第三方工具的仿真和自动纠错。 -- 增加对于 TCL, XDC, VVP 等脚本的 LSP 和 语法高亮 支持。 - -## Change -- 将插件的工作状态显示在 vscode 下侧的状态栏上，利于用户了解目前的设置状态 -- 状态栏右下角现在可以看到目前选择的linter以及是否正常工作了 -- 优化项目配置目录 -- 优化自动补全的性能 - -## Bug 修复 -- 修复文档化 input, output 处注释无法正常显示到文档的 bug -- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug -- 修复 iverilog 仿真功能中，将 `include 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性） -- 修复其他已知 bug \ No newline at end of file diff --git a/design/lsp.drawio b/design/lsp.drawio deleted file mode 100644 index d39d93f..0000000 --- a/design/lsp.drawio +++ /dev/null @@ -1,120 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/package.json b/package.json index 3e15364..dc5ff24 100644 --- a/package.json +++ b/package.json @@ -4,7 +4,7 @@ "description": "all in one vscode plugin for Verilog/VHDL development", "publisher": "sterben", "homepage": "https://digital-eda.github.io/DIDE-doc-Cn", - "version": "0.4.0", + "version": "0.4.1", "main": "./out/extension", "l10n": "./l10n", "icon": "images/icon.png", diff --git a/project/property-schema.json b/project/property-schema.json index 2a329ee..364c338 100644 --- a/project/property-schema.json +++ b/project/property-schema.json @@ -198,8 +198,7 @@ "xc7a35tftg256-1", "xc7a35tcsg324-1", "xc7z035ffg676-2", - "xc7z020clg484-1", - "hello-world" + "xc7z020clg484-1" ] } }, diff --git a/resources/dide-netlist/README.md b/resources/dide-netlist/README.md index aea4421..8e3eb96 100644 --- a/resources/dide-netlist/README.md +++ b/resources/dide-netlist/README.md @@ -1,7 +1,7 @@ -dide-netlist - - view - - index.html - - css - - js - - ... +dide-netlist + - view + - index.html + - css + - js + - ... - static \ No newline at end of file diff --git a/scripts/command/make_package.py b/scripts/command/make_package.py index 4ee3468..c875cef 100644 --- a/scripts/command/make_package.py +++ b/scripts/command/make_package.py @@ -64,7 +64,7 @@ def modify_vsix(): os.remove(dist_path) # move public - copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public')) + # copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public')) # webview copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view')) @@ -101,7 +101,7 @@ pipe.add_command('webpack', 'webpack --mode production') pipe.add_command('make vsix installer', 'vsce package') pipe.add_command('modify vsix installer', lambda : modify_vsix()) pipe.add_command('remove out-js', lambda : remove_folder('out-js')) -pipe.add_command('remove out', lambda : remove_folder('out')) -pipe.add_command('install', lambda : install_extension()) +# pipe.add_command('remove out', lambda : remove_folder('out')) +# pipe.add_command('install', lambda : install_extension()) pipe.run() \ No newline at end of file diff --git a/src/function/index.ts b/src/function/index.ts index ec70de7..8e9dd07 100644 --- a/src/function/index.ts +++ b/src/function/index.ts @@ -2,13 +2,13 @@ import * as vscode from 'vscode'; import * as path from 'path'; import * as hdlDoc from './dide-doc'; +import { makeDocWebview } from './dide-doc/html'; import * as sim from './sim'; import * as treeView from './treeView'; import { tclCompletionProvider } from './lsp/completion/tcl'; import * as lspFormatter from '../../resources/formatter'; import * as lspTranslator from '../../resources/translator'; - import * as tool from './tool'; // special function @@ -27,7 +27,7 @@ function registerDocumentation(context: vscode.ExtensionContext) { // 展示 webview item.panel.reveal(vscode.ViewColumn.Two); } else { - const panel = await hdlDoc.makeDocWebview(uri, context); + const panel = await makeDocWebview(uri, context); // TODO: 注册文件变动监听 const fileChangeDisposer = vscode.window.onDidChangeActiveTextEditor(async event => { // const client = LspClient.DigitalIDE; @@ -46,7 +46,7 @@ function registerDocumentation(context: vscode.ExtensionContext) { // } }); hdlDoc.docManager.set(standardPath, { panel, fileChangeDisposer }); - panel.onDidDispose(event => { + panel.onDidDispose(() => { hdlDoc.docManager.delete(standardPath); fileChangeDisposer.dispose(); }); diff --git a/src/function/lsp-client/cdn.ts b/src/function/lsp-client/cdn.ts index b35c8c5..efe2073 100644 --- a/src/function/lsp-client/cdn.ts +++ b/src/function/lsp-client/cdn.ts @@ -51,8 +51,9 @@ function measureRequestTimecost(url: string, timeout: number = 5): Promise[] = []; for (const link of links) { diff --git a/src/function/sim/simulate.ts b/src/function/sim/simulate.ts index 42e8ce7..5926a58 100644 --- a/src/function/sim/simulate.ts +++ b/src/function/sim/simulate.ts @@ -13,6 +13,7 @@ import { ModuleDataItem } from '../treeView/tree'; import { defaultMacro, doFastApi } from '../../hdlParser/util'; import { t } from '../../i18n'; import { openWaveViewer } from '../dide-viewer'; +import { HdlDependence } from '../../hdlParser/common'; type Path = string; @@ -68,7 +69,7 @@ class Simulate { rst : '', // 设置的复位信号 end : '', // wave : '', // wave存放的路径 - simulationHome : '', // sim运行的路径 + simulationHome : '', // sim运行的路径 gtkwavePath : '', // gtkwave安装路径 installPath : '', // 第三方仿真工具的安装路径 iverilogPath: 'iverilog', // iverilog仿真器所在路径 @@ -100,7 +101,6 @@ class Simulate { simConfig.simulationHome = defaultSimulationDir; } - if (!hdlFile.isDir(simConfig.simulationHome)) { MainOutput.report('create dir ' + simConfig.simulationHome, { level: ReportType.Info @@ -239,7 +239,7 @@ export class IcarusSimulate extends Simulate { * @description 获取 iverilog 仿真的命令 * @returns */ - private getCommand(name: string, path: AbsPath, dependences: string[]): string | undefined { + private getCommand(name: string, path: AbsPath, dependences?: HdlDependence): string | undefined { MainOutput.clear(); const simConfig = this.getConfig(path, 'iverilog'); @@ -263,7 +263,17 @@ export class IcarusSimulate extends Simulate { const simLibPaths = this.getSimLibArr(this.toolChain); const macroIncludeArgs = this.makeMacroIncludeArguments(iverilogCompileOptions.includes); - const dependenceArgs = this.makeDependenceArguments(dependences); + let otherdeps: string[] = []; + let alldeps: string[] = []; + if (dependences) { + otherdeps = dependences.others; + alldeps = dependences.include; + } + else { + otherdeps = []; + alldeps = []; + } + const dependenceArgs = this.makeDependenceArguments(otherdeps); const thirdLibraryArgs = this.makeThirdLibraryArguments(simLibPaths); const thirdLibraryFileArgs = thirdLibraryArgs.fileArgsString; @@ -302,8 +312,12 @@ export class IcarusSimulate extends Simulate { command += ' ' + extaArgs; } - const parent = fspath.dirname(path); - command += ' ' + '-I"' + parent + '"'; + // const parent = fspath.dirname(path); + command += ' ' + '-I'; + for (let index = 0; index < alldeps.length; index++) { + const element = alldeps[index]; + command += ' ' + '"' + hdlPath.resolve(element, '..') + '"'; + } return command; } @@ -361,7 +375,7 @@ export class IcarusSimulate extends Simulate { * @description 运行 iverilog xxx 的命令 */ private runIverilog(simConfig: SimulateConfig, command: string, cwd: string, hdlModule: HdlModule) { - child_process.exec(command, (error, stdout, stderr) => { + child_process.exec(command, { cwd }, (error, stdout, stderr) => { if (error) { this.reportCommandError(command, stderr); return; @@ -391,7 +405,7 @@ export class IcarusSimulate extends Simulate { } /** - * @description 陨星 vvp xxx 的命令 + * @description 运行 vvp xxx 的命令 */ private runVvp(command: string, cwd: string) { child_process.exec(command, { cwd }, (error, stdout, stderr) => { @@ -496,11 +510,10 @@ export class IcarusSimulate extends Simulate { // MainOutput.report(warningMsg, ReportType.Warn, true); // return; // } - - const dependences = this.getAllOtherDependences(path, name); + const dependences = hdlParam.getAllDependences(path, name); const simulationCommand = this.getCommand(name, path, dependences); if (simulationCommand) { - const cwd = hdlPath.resolve(path, '..'); + const cwd = hdlPath.resolve(path, '..'); this.exec(simulationCommand, cwd, hdlModule); } else { const errorMsg = 'Fail to generate command'; diff --git a/src/manager/PL/xilinx.ts b/src/manager/PL/xilinx.ts index a75e68f..a72337b 100644 --- a/src/manager/PL/xilinx.ts +++ b/src/manager/PL/xilinx.ts @@ -75,7 +75,7 @@ class XilinxOperation { } public get xbdPath(): AbsPath { - return hdlPath.join(opeParam.extensionPath, 'lib', 'xilinx', 'bd'); + return hdlPath.join(opeParam.extensionPath, 'library', 'Factory', 'xilinx', 'bd'); } public get xilinxPath(): AbsPath { @@ -355,19 +355,7 @@ class XilinxOperation { vscode.window.showErrorMessage(`cp ${bd} failed, can not find ${bdSrcPath}`); } } - - const bdPaths = [ - hdlPath.join(this.HWPath, 'bd'), - hdlPath.join(this.prjInfo.path, this.prjInfo.name + '.src', 'sources_1', 'bd') - ]; - hdlFile.pickFileRecursive(bdPaths, filePath => { - if (filePath.endsWith('.bd')) { - scripts.push(`add_files ${filePath} -quiet`); - scripts.push(`add_files ${fspath.dirname(filePath)}/hdl -quiet`); - } - }); - if (bd) { const loadBdPath = hdlPath.join(this.HWPath, 'bd', bd, bdFile); scripts.push(`generate_target all [get_files ${loadBdPath}] -quiet`); @@ -375,6 +363,18 @@ class XilinxOperation { scripts.push(`open_bd_design ${loadBdPath} -quiet`); } } + + const bdPaths = [ + hdlPath.join(this.HWPath, 'bd'), + hdlPath.join(this.prjInfo.path, this.prjInfo.name + '.src', 'sources_1', 'bd') + ]; + + hdlFile.pickFileRecursive(bdPaths, filePath => { + if (filePath.endsWith('.bd')) { + scripts.push(`add_files ${filePath} -quiet`); + scripts.push(`add_files ${fspath.dirname(filePath)}/hdl -quiet`); + } + }); const mrefPath = hdlPath.join(this.HWPath, 'bd', 'mref'); hdlFile.pickFileRecursive(mrefPath, filePath => { diff --git a/src/manager/prj.ts b/src/manager/prj.ts index 8bb8e10..4feacd7 100644 --- a/src/manager/prj.ts +++ b/src/manager/prj.ts @@ -270,7 +270,6 @@ class PrjManage { } } - public async createFolderByDefault(rawPrjInfo: RawPrjInfo) { // create prj first const defaultPrjPath = hdlPath.join(opeParam.workspacePath, 'prj');