update PL

package.json

@@ -62,7 +62,23 @@
 					"default": "",
 					"description": "set the xilinx install path. \n e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin \n This applies only to WIN For other systems, add it to environment variables"
 				},
-				"prj.xsdk.install.path": {},
+                "prj.xilinx.IP.repo.path": {
+                    "scope": "window",
+                    "type": "string",
+                    "default": "",
+                    "description": "User-designed IP libraries from xilinx After configuring this property, the plugin will automatically add the path to the IP repo of vivado."
+                },
+                "prj.xilinx.BD.repo.path": {
+                    "scope": "window",
+                    "type": "string",
+                    "default": "",
+                    "description": "User-defined placement path for xilinx block design files"
+                },
+				"prj.xsdk.install.path": {
+                    "scope": "window",
+                    "type": "string",
+                    "default": ""
+                },
 				"function.doc.webview.backgroundImage": {
 					"type": "string",
 					"default": "",

src/manager/PL/xilinx.ts

@@ -104,8 +104,8 @@ class XilinxOperation {
 
     public get custom(): XilinxCustom {
         return {
-            ipRepo: vscode.workspace.getConfiguration().get('PRJ.xilinx.IP.repo.path', ''),
+            ipRepo: vscode.workspace.getConfiguration().get('prj.xilinx.IP.repo.path', ''),
-            bdRepo: vscode.workspace.getConfiguration().get('PRJ.xilinx.BD.repo.path', '')
+            bdRepo: vscode.workspace.getConfiguration().get('prj.xilinx.BD.repo.path', '')
         };
     }
     

src/test/user/Hardware/sim/testbench.v

@@ -0,0 +1,51 @@
+module testbench();
+
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 32;
+parameter MAIN_FRE   = 100; //unit MHz
+reg                   sys_clk = 0;
+reg                   sys_rst = 1;
+reg [DATA_WIDTH-1:0]  data = 0;
+reg [ADDR_WIDTH-1:0]  addr = 0;
+
+always begin
+    #(500/MAIN_FRE) sys_clk = ~sys_clk;
+end
+
+always begin
+    #50 sys_rst = 0;
+end
+
+always @(posedge sys_clk) begin
+    if (sys_rst) 
+        addr = 0;
+    else      
+        addr = addr + 1;
+end
+always @(posedge sys_clk) begin
+    if (sys_rst) 
+        data = 0;
+    else      
+        data = data + 1;
+end
+
+//Instance 
+// outports wire
+wire   	outp;
+
+mux2to1 u_mux2to1(
+	.a    	( a     ),
+	.b    	( b     ),
+	.sel  	( sel   ),
+	.outp 	( outp  )
+);
+
+
+
+initial begin            
+    $dumpfile("wave.vcd");        
+    $dumpvars(0, testbench);    
+    #50000 $finish;
+end
+
+endmodule  //TOP

src/test/user/Hardware/src/hello.v

@@ -7,7 +7,24 @@ module mux2to1(
         output wire outp
     );
 
+    // outports wire
+wire [XY_BITS-1:0] 	x_o;
+wire [XY_BITS-1:0] 	y_o;
+wire [PH_BITS-1:0] 	phase_out;
+wire               	valid_out;
 
+Cordic u_Cordic(
+	.clk       	( clk        ),
+	.RST       	( RST        ),
+	.x_i       	( x_i        ),
+	.y_i       	( y_i        ),
+	.phase_in  	( phase_in   ),
+	.x_o       	( x_o        ),
+	.y_o       	( y_o        ),
+	.phase_out 	( phase_out  ),
+	.valid_in  	( valid_in   ),
+	.valid_out 	( valid_out  )
+);