diff --git a/.vscodeignore b/.vscodeignore
index 252fec8..503c866 100644
--- a/.vscodeignore
+++ b/.vscodeignore
@@ -14,6 +14,4 @@ resources/**/*.js
 resources/**/*.d.ts
 resources/**/*.wasm
 vsixmake.js
-CHANGELOG.md
-README.md
 tsconfig.json
\ No newline at end of file
diff --git a/README.md b/README.md
index 59fb4cc..6e67ab3 100644
--- a/README.md
+++ b/README.md
@@ -1,28 +1,36 @@
-# Digital-IDE
+# Digital IDE - version 0.3.0
 
 ![](https://img.shields.io/badge/version-0.3.0-blue)
+![](https://img.shields.io/badge/engine-wasm-blue)
+![](https://img.shields.io/badge/Verilog-support-green)
+![](https://img.shields.io/badge/VHDL-building-black)
+![](https://img.shields.io/badge/SystemVerilog-building-black)
+
+<center>
+<img src="./images/DIDE.png">
+</center>
+
+> ASIC & FPGA develop Platform on VS code (IDE for development of verilog, vhdl and system verilog)
+
+- If you have any questions, please post them under [issues](https://github.com/Bestduan/Digital-IDE/issues).
+- If you like it, please [star](https://github.com/Bestduan/Digital-IDE).
 
 
+[English](https://bestduan.github.io/Digital-IDE-doc/#/)
 
----
+[中文教程](https://digital-eda.github.io/DIDE-doc-Cn/#/)
 
-## Developer
+You are free to use it. Finally, if you like this extension and have some great idea, please connact with me. I am look foward to your joining.
 
-make pakage:
+- Email: sterben.661214@gmail.com.
+- QQ群: 932987873
 
-```bash
-python script/command/make_package.py
-```
+--------------------------------------------------------------------------------------------
 
-make package.json command title token:
+## Thanks
 
-```bash
-python script/command/make_title_token.py
-```
-
-
-translate title token:
-
-```bash
-python script/command/translate_from_en.py
-```
\ No newline at end of file
+* [VHDL](https://github.com/puorc/awesome-vhdl)
+* [TerosHDL](https://github.com/TerosTechnology/vscode-terosHDL)
+* [TCL Language Support](https://github.com/go2sh/tcl-language-support)
+* [Verilog HDL/SystemVerilog](https://github.com/mshr-h/vscode-verilog-hdl-support)
+* [SystemVerilog - Language Support](https://github.com/eirikpre/VSCode-SystemVerilog)
\ No newline at end of file