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fix xilinx ip import issues

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This commit is contained in:
Nitcloud 2025-03-14 23:28:38 +08:00
parent 99b1860f40
commit 63fcb7a163
3 changed files with 17 additions and 10 deletions
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8
src/manager/PL/efinity.ts
View File

@ -147,7 +147,7 @@ export class EfinityOperation {
private getSynthInfo(): string {
return ` <efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="work_dir" value="${opeParam.prjInfo.prjPath}/efinix/work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
@ -183,7 +183,7 @@ export class EfinityOperation {
private getPnRInfo(): string {
return ` <efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="work_dir" value="${opeParam.prjInfo.prjPath}/efinix/work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
@ -196,7 +196,7 @@ export class EfinityOperation {
}
private getBitstreamInfo(): string {
return ` <efx:bitstream_generation tool_name="efx_pgm">
return ` <efx:bitstream_generation tool_name="${opeParam.prjInfo.prjPath}/efinix/efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
@ -220,7 +220,7 @@ export class EfinityOperation {
private getDebugInfo(): string {
return ` <efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="work_dir" value="${opeParam.prjInfo.prjPath}/efinix/work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="NONE" value_type="e_string"/>
</efx:debugger>`;

10
src/manager/PL/xilinx.ts
View File

@ -286,8 +286,13 @@ class XilinxOperation {
const plName = opeParam.prjInfo.prjName.PL;
const targetPath = fspath.dirname(opeParam.prjInfo.arch.hardware.src);
const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/ip`;
const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/bd`;
let type = 'srcs';
if (hdlDir.isDir(`${workspacePath}/prj/xilinx/${plName}.gen`)) {
type = 'gen'
}
const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/ip`;
const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/bd`;
hdlDir.mvdir(sourceIpPath, targetPath, true);
HardwareOutput.report("move dir from " + sourceIpPath + " to " + targetPath);
@ -1082,7 +1087,6 @@ const tools = {
}
};
export {
XilinxOperation,
tools,

7
src/manager/prj.ts
View File

@ -398,11 +398,14 @@ class PrjManage {
workspace: string,
plname: string
) {
const xilinxSrcsPath = hdlPath.join(workspace, plname + '.srcs');
const standardIpPath = hdlPath.join(workspace, 'user', 'ip');
let standardIpPath = hdlPath.join(workspace, 'user', 'ip');
let xilinxSrcsPath = hdlPath.join(workspace, plname + '.gen');
if (!fs.existsSync(xilinxSrcsPath)) {
xilinxSrcsPath = hdlPath.join(workspace, plname + '.srcs');
if (!fs.existsSync(xilinxSrcsPath)) {
return;
}
}
const sourceNames = fs.readdirSync(xilinxSrcsPath).filter(filename => filename.startsWith(matchPrefix));
for (const sn of sourceNames) {
const ipPath = hdlPath.join(xilinxSrcsPath, sn, 'ip');