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支持新的 netlist

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锦恢 2024-12-31 23:43:50 +08:00
parent cc3d8fcfba
commit 67aaa39dfe
252 changed files with 217 additions and 145597 deletions
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1
.gitignore vendored
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@ -17,3 +17,4 @@ resources/hdlParser/parser.wasm
resources/dide-viewer/view/*
resources/dide-lsp/server/*
resources/dide-lsp/static/*
resources/dide-netlist/static/*

6
l10n/bundle.l10n.de.json
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@ -96,5 +96,9 @@
"warning.linter.cannot-get-valid-linter-invoker": "Die digitale IDE kann keinen Aufrufpfad für {0} abrufen. Bitte installieren Sie den entsprechenden Diagnose-Tool und konfigurieren Sie ihn entweder in der Umgebungsvariablen PATH oder im digitalen IDE-Diagnosetool-Installationspfad.",
"info.linter.config-linter-install-path": "Installationsverzeichnis konfigurieren",
"info.progress.doing-diagnostic": "Diagnostizierung",
"error.common.fail-to-launch-lsp": "Start des Sprachservers fehlgeschlagen!"
"error.common.fail-to-launch-lsp": "Start des Sprachservers fehlgeschlagen!",
"info.netlist.launch-netlist": "Netlist wird gestartet",
"info.netlist.not-found-payload": "Die Lastressource des Netlists konnte nicht gefunden werden. Bitte überprüfen Sie, ob das Installationsverzeichnis beschädigt ist!",
"info.netlist.not-support-vhdl": "Das aktuelle Netlist unterstützt vorübergehend kein VHDL und andere Sprachen!",
"info.netlist.generate-network": "Netzwerktopologie wird generiert"
}

6
l10n/bundle.l10n.en.json
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@ -96,5 +96,9 @@
"warning.linter.cannot-get-valid-linter-invoker": "The Digital IDE cannot retrieve the call path for {0}. Please install the corresponding diagnostic tool and configure it either in the environment variable PATH or in the Digital IDE's diagnostic tool installation path.",
"info.linter.config-linter-install-path": "Configure installation directory",
"info.progress.doing-diagnostic": "Diagnosing",
"error.common.fail-to-launch-lsp": "Language server startup failed!"
"error.common.fail-to-launch-lsp": "Language server startup failed!",
"info.netlist.launch-netlist": "Starting Netlist",
"info.netlist.not-found-payload": "Unable to find the load resource of the netlist, please check if the installation directory is corrupted!",
"info.netlist.not-support-vhdl": "The current netlist temporarily does not support VHDL and other languages!",
"info.netlist.generate-network": "Generating network topology"
}

6
l10n/bundle.l10n.ja.json
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@ -96,5 +96,9 @@
"warning.linter.cannot-get-valid-linter-invoker": "デジタルIDEは{0}の呼び出しパスを取得できません。対応する診断ツールをインストールし、環境変数PATHに設定するか、デジタルIDEの診断ツールインストールパスを設定してください。",
"info.linter.config-linter-install-path": "インストールディレクトリを設定",
"info.progress.doing-diagnostic": "診断中",
"error.common.fail-to-launch-lsp": "言語サーバーの起動に失敗しました！"
"error.common.fail-to-launch-lsp": "言語サーバーの起動に失敗しました！",
"info.netlist.launch-netlist": "Netlistを起動中",
"info.netlist.not-found-payload": "ネットリストのロードリソースが見つかりません。インストールディレクトリが破損していないか確認してください！",
"info.netlist.not-support-vhdl": "現在のネットリストは一時的にVHDLやその他の言語をサポートしていません！",
"info.netlist.generate-network": "ネットワークトポロジを生成中"
}

6
l10n/bundle.l10n.zh-cn.json
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@ -96,5 +96,9 @@
"warning.linter.cannot-get-valid-linter-invoker": "Digital IDE 无法获取到关于 {0} 的调用路径，请安装对应诊断器后，配置到环境变量 PATH 或者配置 Digital IDE 对应的诊断工具安装路径",
"info.linter.config-linter-install-path": "配置安装目录",
"info.progress.doing-diagnostic": "诊断中",
"error.common.fail-to-launch-lsp": "语言服务器启动失败！"
"error.common.fail-to-launch-lsp": "语言服务器启动失败！",
"info.netlist.launch-netlist": "正在启动 Netlist",
"info.netlist.not-found-payload": "无法找到 netlist 的负载资源，请检查安装目录是否损坏！",
"info.netlist.not-support-vhdl": "当前 netlist 暂时不支持 VHDL 和其他语言！",
"info.netlist.generate-network": "正在生成网络拓扑"
}

6
l10n/bundle.l10n.zh-tw.json
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@ -96,5 +96,9 @@
"warning.linter.cannot-get-valid-linter-invoker": "Digital IDE 無法取得關於 {0} 的呼叫路徑，請安裝對應診斷器後，配置到環境變數 PATH 或者配置 Digital IDE 對應的診斷工具安裝路徑。",
"info.linter.config-linter-install-path": "配置安裝目錄",
"info.progress.doing-diagnostic": "診斷中",
"error.common.fail-to-launch-lsp": "語言伺服器啟動失敗！"
"error.common.fail-to-launch-lsp": "語言伺服器啟動失敗！",
"info.netlist.launch-netlist": "正在啟動Netlist",
"info.netlist.not-found-payload": "無法找到 netlist 的負載資源，請檢查安裝目錄是否損壞！",
"info.netlist.not-support-vhdl": "當前 netlist 暫時不支援 VHDL 和其他語言！",
"info.netlist.generate-network": "正在生成網路拓撲"
}

15
package.json
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@ -333,6 +333,21 @@
"type": "integer",
"default": 1,
"description": "%digital-ide.function.lsp.file-parse-maxsize.title%"
},
"digital-ide.function.netlist.schema-mode": {
"type": "string",
"default": "before",
"enum": [
"before",
"after",
"RTL"
],
"enumDescriptions": [
"%digital-ide.function.netlist.schema-mode.0.title%",
"%digital-ide.function.netlist.schema-mode.1.title%",
"%digital-ide.function.netlist.schema-mode.2.title%"
],
"description": "%digital-ide.function.netlist.schema-mode.title%"
}
}
},

6
package.nls.de.json
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@ -100,5 +100,9 @@
"digital-ide.function.lsp.linter.mode.2.title": "Global deaktiviert, d.h. für das gesamte Projekt werden keine Projektfehler gemeldet.",
"digital-ide.function.lsp.linter.linter-level.title": "Diagnoselevel-Einstellungen des Linters",
"digital-ide.function.lsp.linter.linter-level.error.title": "Nur Fehler anzeigen",
"digital-ide.function.lsp.linter.linter-level.warning.title": "Fehler und Warnungen anzeigen"
"digital-ide.function.lsp.linter.linter-level.warning.title": "Fehler und Warnungen anzeigen",
"%digital-ide.function.netlist.schema-mode.title%": "Netlist-Synthesemodus auswählen",
"%digital-ide.function.netlist.schema-mode.0.title%": "Prä-Verhaltenssynthese",
"%digital-ide.function.netlist.schema-mode.1.title%": "Post-Verhaltenssynthese",
"%digital-ide.function.netlist.schema-mode.2.title%": "Post-RTL-Synthese"
}

6
package.nls.ja.json
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@ -100,5 +100,9 @@
"digital-ide.function.lsp.linter.mode.2.title": "グローバルに無効化され、プロジェクト全体でプロジェクトエラーが報告されません。",
"digital-ide.function.lsp.linter.linter-level.title": "診断器の診断レベル設定",
"digital-ide.function.lsp.linter.linter-level.error.title": "エラーのみ表示",
"digital-ide.function.lsp.linter.linter-level.warning.title": "エラーと警告を表示"
"digital-ide.function.lsp.linter.linter-level.warning.title": "エラーと警告を表示",
"%digital-ide.function.netlist.schema-mode.title%": "Netlist 合成モードを選択",
"%digital-ide.function.netlist.schema-mode.0.title%": "ビヘイビア前合成",
"%digital-ide.function.netlist.schema-mode.1.title%": "ビヘイビア後合成",
"%digital-ide.function.netlist.schema-mode.2.title%": "RTL後合成"
}

6
package.nls.json
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@ -100,5 +100,9 @@
"digital-ide.function.lsp.linter.mode.2.title": "Globally disabled, meaning no project errors are reported for the entire project.",
"digital-ide.function.lsp.linter.linter-level.title": "Diagnostic Level Settings for the Linter",
"digital-ide.function.lsp.linter.linter-level.error.title": "Show Only Errors",
"digital-ide.function.lsp.linter.linter-level.warning.title": "Show Errors and Warnings"
"digital-ide.function.lsp.linter.linter-level.warning.title": "Show Errors and Warnings",
"%digital-ide.function.netlist.schema-mode.title%": "Select Netlist Synthesis Mode",
"%digital-ide.function.netlist.schema-mode.0.title%": "Pre-Behavioral Synthesis",
"%digital-ide.function.netlist.schema-mode.1.title%": "Post-Behavioral Synthesis",
"%digital-ide.function.netlist.schema-mode.2.title%": "Post-RTL Synthesis"
}

6
package.nls.zh-cn.json
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@ -100,5 +100,9 @@
"digital-ide.function.lsp.linter.mode.2.title": "全局关闭，即整个工程都不进行工程报错。",
"digital-ide.function.lsp.linter.linter-level.title": "诊断器诊断等级设置",
"digital-ide.function.lsp.linter.linter-level.error.title": "只显示错误",
"digital-ide.function.lsp.linter.linter-level.warning.title": "显示错误和警告"
"digital-ide.function.lsp.linter.linter-level.warning.title": "显示错误和警告",
"%digital-ide.function.netlist.schema-mode.title%": "选择 Netlist 综合模式",
"%digital-ide.function.netlist.schema-mode.0.title%": "行为前综合",
"%digital-ide.function.netlist.schema-mode.1.title%": "行为后综合",
"%digital-ide.function.netlist.schema-mode.2.title%": "RTL后综合"
}

6
package.nls.zh-tw.json
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@ -100,5 +100,9 @@
"digital-ide.function.lsp.linter.mode.2.title": "全局關閉，即整個工程都不進行工程報錯。",
"digital-ide.function.lsp.linter.linter-level.title": "診斷器診斷等級設置",
"digital-ide.function.lsp.linter.linter-level.error.title": "只顯示錯誤",
"digital-ide.function.lsp.linter.linter-level.warning.title": "顯示錯誤和警告"
"digital-ide.function.lsp.linter.linter-level.warning.title": "顯示錯誤和警告",
"%digital-ide.function.netlist.schema-mode.title%": "選擇 Netlist 綜合模式",
"%digital-ide.function.netlist.schema-mode.0.title%": "行為前綜合",
"%digital-ide.function.netlist.schema-mode.1.title%": "行為後綜合",
"%digital-ide.function.netlist.schema-mode.2.title%": "RTL後綜合"
}

1
project/property-init.json
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@ -6,6 +6,5 @@
"soc": {
"core": "none"
},
"enableShowLog": false,
"device": "none"
}

7
resources/dide-netlist/README.md Normal file
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@ -0,0 +1,7 @@
dide-netlist
- view
- index.html
- css
- js
- ...
- static

28
resources/netlist/index.d.ts vendored
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@ -1,28 +0,0 @@
interface SynthOptions {
path: string
type: string
argu: string
}
interface ExportOptions {
path?: string
type?: string
argu?: string
}
declare module Netlist {
export class NetlistKernel {
public async launch();
public exec(command: string);
public printHelp(): string;
public setInnerOutput(params: boolean);
public setMessageCallback(callback: (message: string, type: string) => void);
public load(files: string[]): string;
public synth(options: SynthOptions);
public export(options: ExportOptions): string;
public reset();
public exit();
}
}
export = Netlist;

151
resources/netlist/index.js
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@ -1,151 +0,0 @@
/* eslint-disable @typescript-eslint/naming-convention */
const os = require('os');
const kernel = require('./utils/kernel');
const Vrfs = require('./utils/vrfs');
class NetlistKernel {
constructor() {
this.kernel = null;
this.vrfs = null;
}
async launch() {
this.kernel = await kernel();
this.vrfs = new Vrfs(this.kernel);
this.vrfs.diskMount();
}
/**
* @state finish-test
* @descriptionCn 直接执行指令
* @param {String} command
*/
exec(command) {
this.kernel.ccall('run', '', ['string'], [command]);
}
/**
* @state finish-test
* @descriptionCn 输出帮助界面
*/
printHelp() {
this.kernel.TTY.message = '';
this.exec("help");
return this.kernel.TTY.message;
}
/**
* @state finish-test
* @descriptionCn 设置内置log输出的使能
* @param {Boolean} params (true : 打开内置log输出 | false : 关闭内置log输出)
*/
setInnerOutput(params) {
this.kernel.TTY.innerOutput = params;
}
/**
* @state finish-test
* @descriptionCn 设置message的回调函数
* @param {*} callback 对message操作的回调函数
*/
setMessageCallback(callback) {
this.kernel.TTY.innerOutput = false;
this.kernel.TTY.callbackOutput = true;
this.kernel.TTY.callback = callback;
}
/**
* @state finish-test
* @descriptionCn 导入文件到工程之中(仅适用于nodefs) 默认支持sv且覆盖
* @param {Array} files 数组形式输入 输入所需导入工程的文件数组
* @returns {String} 导入过程中所输出的日志(仅适用与message回调关闭的时候)
*/
load(files) {
this.kernel.TTY.message = "";
const command = 'read_verilog -sv -formal -overwrite';
for (let i = 0; i < files.length; i++) {
const file = files[i];
if (os.platform().toLowerCase() === 'win32') {
// console.log(this.kernel.FS.readdir('/'));
this.exec(`${command} /${file}`);
} else {
this.exec(`${command} /host/${file}`);
}
}
return this.kernel.TTY.message;
}
synth(options) {
options.argu = options.argu ? options.argu : '';
let command = '';
switch (options.type) {
case 'json':
command = 'write_json';
break;
case 'verilog':
command = 'write_verilog';
break;
case 'aiger':
command = 'write_aiger';
break;
case 'blif':
command = 'write_blif';
break;
case 'edif':
command = 'write_edif';
break;
default: break;
}
this.exec(`${command} ${options.argu} /${options.path}`);
}
/**
* @descriptionCn 以指定的模式导出设计
* @param {{
* path : '' // 在虚拟文件系统中存放的路径
* type : '' // 指定的模式
* argu : '' // 指定导出的参数
* }} options
* @returns {String} 设计的内容
*/
export(options) {
options.path = options.path ? options.path : 'output';
options.argu = options.argu ? options.argu : '';
let command = '';
switch (options.type) {
case 'json':
command = 'write_json';
break;
case 'verilog':
command = 'write_verilog';
break;
case 'aiger':
command = 'write_aiger';
break;
case 'blif':
command = 'write_blif';
break;
case 'edif':
command = 'write_edif';
break;
default: break;
}
this.exec(`${command} ${options.argu} /${options.path}`);
return this.vrfs.readFileToText(options.path);
}
reset() {
this.exec('design -reset');
}
exit() {
this.kernel = null;
this.vrfs = null;
}
}
module.exports = {
NetlistKernel
};

BIN
resources/netlist/resources/kernel/kernel.wasm
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27
resources/netlist/resources/kernel/share/abc9_map.v
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@ -1,27 +0,0 @@
`ifdef DFF
(* techmap_celltype = "$_DFF_[PN]_" *)
module $_DFF_x_(input C, D, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
parameter _TECHMAP_CELLTYPE_ = "";
wire D_;
generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
$__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
$_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
end
else
(* abc9_keep *) $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
end
else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
$__DFF_P__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
$_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
end
else
(* abc9_keep *) $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
end
else if (_TECHMAP_CELLTYPE_ != "")
$error("Unrecognised _TECHMAP_CELLTYPE_");
endgenerate
endmodule
`endif

29
resources/netlist/resources/kernel/share/abc9_model.v
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@ -1,29 +0,0 @@
(* abc9_box *)
module $__ABC9_DELAY (input I, output O);
parameter DELAY = 0;
specify
(I => O) = DELAY;
endspecify
endmodule
module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O);
parameter WIDTH = 0;
endmodule
(* abc9_flop, abc9_box, lib_whitebox *)
module $__DFF_N__$abc9_flop (input C, D, Q, output n1);
assign n1 = D;
specify
$setup(D, posedge C, 0);
(posedge C => (n1:D)) = 0;
endspecify
endmodule
(* abc9_flop, abc9_box, lib_whitebox *)
module $__DFF_P__$abc9_flop (input C, D, Q, output n1);
assign n1 = D;
specify
$setup(D, posedge C, 0);
(posedge C => (n1:D)) = 0;
endspecify
endmodule

16
resources/netlist/resources/kernel/share/abc9_unmap.v
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@ -1,16 +0,0 @@
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
module $__DFF_x__$abc9_flop (input C, D, (* init = 1'b0 *) input Q, output n1);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
else if (_TECHMAP_CELLTYPE_ == "$__DFF_P__$abc9_flop")
$_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
else if (_TECHMAP_CELLTYPE_ != "")
$error("Unrecognised _TECHMAP_CELLTYPE_");
endgenerate
endmodule
module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O);
parameter WIDTH = 0;
assign O = I;
endmodule

73
resources/netlist/resources/kernel/share/achronix/speedster22i/cells_map.v
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@ -1,73 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Input/Output buffers <
// Input buffer map
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule
// > end buffers <
// > Look-Up table <
// > VT: I still think Achronix folks would have chosen a better \
// > logic architecture.
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
end else
if (WIDTH == 2) begin
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
end else
if(WIDTH == 3) begin
LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
end else
if(WIDTH == 4) begin
LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
// > end LUT <
// > Flops <
// DFF flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule

79
resources/netlist/resources/kernel/share/achronix/speedster22i/cells_sim.v
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@ -1,79 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology sim models. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Changelog: 1) Removed unused VCC/GND modules
// > 2) Altera comments here (?). Removed.
// > 3) Reusing LUT sim model, removed wrong wires and parameters.
module PADIN (output padout, input padin);
assign padout = padin;
endmodule
module PADOUT (output padout, input padin, input oe);
assign padout = padin;
assign oe = oe;
endmodule
module LUT4 (output dout,
input din0, din1, din2, din3);
parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output reg q,
input d, ck);
always @(posedge ck)
q <= d;
endmodule

30
resources/netlist/resources/kernel/share/adff2dff.v
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@ -1,30 +0,0 @@
(* techmap_celltype = "$adff" *)
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
(* force_downto *)
input [WIDTH-1:0] D;
(* force_downto *)
output reg [WIDTH-1:0] Q;
(* force_downto *)
reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
always @*
if (ARST == ARST_POLARITY)
NEXT_Q <= ARST_VALUE;
else
NEXT_Q <= D;
if (CLK_POLARITY)
always @(posedge CLK)
Q <= NEXT_Q;
else
always @(negedge CLK)
Q <= NEXT_Q;
endmodule

93
resources/netlist/resources/kernel/share/anlogic/arith_map.v
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@ -1,93 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
wire dummy;
AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY"))
adder_cin (
.a(CI),
.b(1'b0),
.c(1'b0),
.o({CIx, dummy})
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
AL_MAP_ADDER #(
.ALUTYPE("ADD")
) adder_i (
.a(AA[i]),
.b(BB[i]),
.c(C[i]),
.o({COx[i],Y[i]})
);
wire cout;
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.a(1'b0),
.b(1'b0),
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

69
resources/netlist/resources/kernel/share/anlogic/brams.txt
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@ -1,69 +0,0 @@
ram block $__ANLOGIC_BRAM_TDP_ {
abits 13;
widths 1 2 4 9 per_port;
cost 64;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
portoption "WRITEMODE" "READBEFOREWRITE" {
rdwr old;
}
option "RESETMODE" "SYNC" {
rdsrst zero ungated block_wr;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
}
ram block $__ANLOGIC_BRAM_SDP_ {
abits 13;
widths 1 2 4 9 18 per_port;
byte 9;
cost 64;
init no_undef;
port sr "R" {
clock anyedge;
clken;
option "RESETMODE" "SYNC" {
rdsrst zero ungated;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
clock anyedge;
clken;
}
}
ram block $__ANLOGIC_BRAM32K_ {
abits 12;
widths 8 16 per_port;
byte 8;
cost 192;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
# no reset - it doesn't really work without the pipeline
# output registers
}
}

474
resources/netlist/resources/kernel/share/anlogic/brams_map.v
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@ -1,474 +0,0 @@
module $__ANLOGIC_BRAM_TDP_ (...);
parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";
parameter PORT_A_WIDTH = 9;
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [12:0] PORT_A_ADDR;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
parameter PORT_B_WIDTH = 9;
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input PORT_B_RD_SRST;
input PORT_B_RD_ARST;
input [12:0] PORT_B_ADDR;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
function [255:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 32; i = i + 1) begin
init_slice[i*8+:8] = INIT[(idx * 32 + i) * 9 +: 8];
end
endfunction
function [255:0] initp_slice;
input integer idx;
integer i;
for (i = 0; i < 256; i = i + 1) begin
initp_slice[i] = INIT[(idx * 256 + i) * 9 + 8];
end
endfunction
wire [8:0] DOA;
wire [8:0] DOB;
// the replication is important — the BRAM behaves in... unexpected ways for
// width 1 and 2
wire [8:0] DIA = {9{PORT_A_WR_DATA}};
wire [8:0] DIB = {9{PORT_B_WR_DATA}};
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
EG_PHY_BRAM #(
.INIT_00(init_slice('h00)),
.INIT_01(init_slice('h01)),
.INIT_02(init_slice('h02)),
.INIT_03(init_slice('h03)),
.INIT_04(init_slice('h04)),
.INIT_05(init_slice('h05)),
.INIT_06(init_slice('h06)),
.INIT_07(init_slice('h07)),
.INIT_08(init_slice('h08)),
.INIT_09(init_slice('h09)),
.INIT_0A(init_slice('h0a)),
.INIT_0B(init_slice('h0b)),
.INIT_0C(init_slice('h0c)),
.INIT_0D(init_slice('h0d)),
.INIT_0E(init_slice('h0e)),
.INIT_0F(init_slice('h0f)),
.INIT_10(init_slice('h10)),
.INIT_11(init_slice('h11)),
.INIT_12(init_slice('h12)),
.INIT_13(init_slice('h13)),
.INIT_14(init_slice('h14)),
.INIT_15(init_slice('h15)),
.INIT_16(init_slice('h16)),
.INIT_17(init_slice('h17)),
.INIT_18(init_slice('h18)),
.INIT_19(init_slice('h19)),
.INIT_1A(init_slice('h1a)),
.INIT_1B(init_slice('h1b)),
.INIT_1C(init_slice('h1c)),
.INIT_1D(init_slice('h1d)),
.INIT_1E(init_slice('h1e)),
.INIT_1F(init_slice('h1f)),
.INITP_00(initp_slice('h00)),
.INITP_01(initp_slice('h01)),
.INITP_02(initp_slice('h02)),
.INITP_03(initp_slice('h03)),
.MODE("DP8K"),
.DATA_WIDTH_A($sformatf("%d", PORT_A_WIDTH)),
.DATA_WIDTH_B($sformatf("%d", PORT_B_WIDTH)),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.RESETMODE(OPTION_RESETMODE),
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
.CLKAMUX(PORT_A_CLK_POL ? "SIG" : "INV"),
.CLKBMUX(PORT_B_CLK_POL ? "SIG" : "INV"),
.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
) _TECHMAP_REPLACE_ (
.clka(PORT_A_CLK),
.wea(PORT_A_WR_EN),
.cea(PORT_A_CLK_EN),
.ocea(1'b1),
.rsta(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
.csa(3'b111),
.addra(PORT_A_WIDTH == 9 ? {PORT_A_ADDR[12:1], 1'b1} : PORT_A_ADDR),
.dia(DIA),
.doa(DOA),
.clkb(PORT_B_CLK),
.web(PORT_B_WR_EN),
.ceb(PORT_B_CLK_EN),
.oceb(1'b1),
.rstb(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
.csb(3'b111),
.addrb(PORT_B_WIDTH == 9 ? {PORT_B_ADDR[12:1], 1'b1} : PORT_B_ADDR),
.dib(DIB),
.dob(DOB),
);
endmodule
module $__ANLOGIC_BRAM_SDP_ (...);
parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";
parameter PORT_R_WIDTH = 18;
parameter PORT_R_CLK_POL = 1;
input PORT_R_CLK;
input PORT_R_CLK_EN;
input PORT_R_RD_SRST;
input PORT_R_RD_ARST;
input [12:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
parameter PORT_W_WIDTH = 18;
parameter PORT_W_WR_EN_WIDTH = 2;
parameter PORT_W_CLK_POL = 1;
input PORT_W_CLK;
input PORT_W_CLK_EN;
input [12:0] PORT_W_ADDR;
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
function [255:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 32; i = i + 1) begin
init_slice[i*8+:8] = INIT[(idx * 32 + i) * 9 +: 8];
end
endfunction
function [255:0] initp_slice;
input integer idx;
integer i;
for (i = 0; i < 256; i = i + 1) begin
initp_slice[i] = INIT[(idx * 256 + i) * 9 + 8];
end
endfunction
wire [17:0] DI = {18{PORT_W_WR_DATA}};
wire [17:0] DO;
assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9];
EG_PHY_BRAM #(
.INIT_00(init_slice('h00)),
.INIT_01(init_slice('h01)),
.INIT_02(init_slice('h02)),
.INIT_03(init_slice('h03)),
.INIT_04(init_slice('h04)),
.INIT_05(init_slice('h05)),
.INIT_06(init_slice('h06)),
.INIT_07(init_slice('h07)),
.INIT_08(init_slice('h08)),
.INIT_09(init_slice('h09)),
.INIT_0A(init_slice('h0a)),
.INIT_0B(init_slice('h0b)),
.INIT_0C(init_slice('h0c)),
.INIT_0D(init_slice('h0d)),
.INIT_0E(init_slice('h0e)),
.INIT_0F(init_slice('h0f)),
.INIT_10(init_slice('h10)),
.INIT_11(init_slice('h11)),
.INIT_12(init_slice('h12)),
.INIT_13(init_slice('h13)),
.INIT_14(init_slice('h14)),
.INIT_15(init_slice('h15)),
.INIT_16(init_slice('h16)),
.INIT_17(init_slice('h17)),
.INIT_18(init_slice('h18)),
.INIT_19(init_slice('h19)),
.INIT_1A(init_slice('h1a)),
.INIT_1B(init_slice('h1b)),
.INIT_1C(init_slice('h1c)),
.INIT_1D(init_slice('h1d)),
.INIT_1E(init_slice('h1e)),
.INIT_1F(init_slice('h1f)),
.INITP_00(initp_slice('h00)),
.INITP_01(initp_slice('h01)),
.INITP_02(initp_slice('h02)),
.INITP_03(initp_slice('h03)),
.MODE("PDPW8K"),
.DATA_WIDTH_A($sformatf("%d", PORT_W_WIDTH)),
.DATA_WIDTH_B($sformatf("%d", PORT_R_WIDTH)),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.RESETMODE(OPTION_RESETMODE),
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
.CLKAMUX(PORT_W_CLK_POL ? "SIG" : "INV"),
.CLKBMUX(PORT_R_CLK_POL ? "SIG" : "INV"),
) _TECHMAP_REPLACE_ (
.clka(PORT_W_CLK),
.wea(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]),
.cea(PORT_W_CLK_EN),
.ocea(1'b1),
.rsta(1'b0),
.csa(3'b111),
.addra(PORT_W_WIDTH == 18 ? {PORT_W_ADDR[12:2], PORT_W_WR_EN[1:0]} : (PORT_W_WIDTH == 9 ? {PORT_W_ADDR[12:1], PORT_W_WR_EN[0]} : PORT_W_ADDR)),
.dia(DI[8:0]),
.doa(DO[8:0]),
.clkb(PORT_R_CLK),
.web(1'b0),
.ceb(PORT_R_CLK_EN),
.oceb(1'b1),
.rstb(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
.csb(3'b111),
.addrb(PORT_R_ADDR),
.dib(DI[17:9]),
.dob(DO[17:9]),
);
endmodule
module $__ANLOGIC_BRAM32K_ (...);
parameter INIT = 0;
parameter PORT_A_WIDTH = 16;
parameter PORT_A_WR_EN_WIDTH = 2;
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
input PORT_A_CLK;
input PORT_A_CLK_EN;
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
input [11:0] PORT_A_ADDR;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
parameter PORT_B_WIDTH = 16;
parameter PORT_B_WR_EN_WIDTH = 2;
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
input PORT_B_CLK;
input PORT_B_CLK_EN;
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
input [11:0] PORT_B_ADDR;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
function [255:0] init_slice;
input integer idx;
init_slice = INIT[256 * idx +: 256];
endfunction
wire [15:0] DOA;
wire [15:0] DOB;
wire [15:0] DIA = PORT_A_WR_DATA;
wire [15:0] DIB = PORT_B_WR_DATA;
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
wire BYTE_A, BYTEWE_A;
wire BYTE_B, BYTEWE_B;
generate
if (PORT_A_WIDTH == 8) begin
assign BYTE_A = PORT_A_ADDR[0];
assign BYTEWE_A = 1;
end else begin
assign BYTE_A = PORT_A_WR_EN == 2;
assign BYTEWE_A = ^PORT_A_WR_EN;
end
if (PORT_B_WIDTH == 8) begin
assign BYTE_B = PORT_B_ADDR[0];
assign BYTEWE_B = 1;
end else begin
assign BYTE_B = PORT_B_WR_EN == 2;
assign BYTEWE_B = ^PORT_B_WR_EN;
end
endgenerate
EG_PHY_BRAM32K #(
.INIT_00(init_slice('h00)),
.INIT_01(init_slice('h01)),
.INIT_02(init_slice('h02)),
.INIT_03(init_slice('h03)),
.INIT_04(init_slice('h04)),
.INIT_05(init_slice('h05)),
.INIT_06(init_slice('h06)),
.INIT_07(init_slice('h07)),
.INIT_08(init_slice('h08)),
.INIT_09(init_slice('h09)),
.INIT_0A(init_slice('h0a)),
.INIT_0B(init_slice('h0b)),
.INIT_0C(init_slice('h0c)),
.INIT_0D(init_slice('h0d)),
.INIT_0E(init_slice('h0e)),
.INIT_0F(init_slice('h0f)),
.INIT_10(init_slice('h10)),
.INIT_11(init_slice('h11)),
.INIT_12(init_slice('h12)),
.INIT_13(init_slice('h13)),
.INIT_14(init_slice('h14)),
.INIT_15(init_slice('h15)),
.INIT_16(init_slice('h16)),
.INIT_17(init_slice('h17)),
.INIT_18(init_slice('h18)),
.INIT_19(init_slice('h19)),
.INIT_1A(init_slice('h1a)),
.INIT_1B(init_slice('h1b)),
.INIT_1C(init_slice('h1c)),
.INIT_1D(init_slice('h1d)),
.INIT_1E(init_slice('h1e)),
.INIT_1F(init_slice('h1f)),
.INIT_20(init_slice('h20)),
.INIT_21(init_slice('h21)),
.INIT_22(init_slice('h22)),
.INIT_23(init_slice('h23)),
.INIT_24(init_slice('h24)),
.INIT_25(init_slice('h25)),
.INIT_26(init_slice('h26)),
.INIT_27(init_slice('h27)),
.INIT_28(init_slice('h28)),
.INIT_29(init_slice('h29)),
.INIT_2A(init_slice('h2a)),
.INIT_2B(init_slice('h2b)),
.INIT_2C(init_slice('h2c)),
.INIT_2D(init_slice('h2d)),
.INIT_2E(init_slice('h2e)),
.INIT_2F(init_slice('h2f)),
.INIT_30(init_slice('h30)),
.INIT_31(init_slice('h31)),
.INIT_32(init_slice('h32)),
.INIT_33(init_slice('h33)),
.INIT_34(init_slice('h34)),
.INIT_35(init_slice('h35)),
.INIT_36(init_slice('h36)),
.INIT_37(init_slice('h37)),
.INIT_38(init_slice('h38)),
.INIT_39(init_slice('h39)),
.INIT_3A(init_slice('h3a)),
.INIT_3B(init_slice('h3b)),
.INIT_3C(init_slice('h3c)),
.INIT_3D(init_slice('h3d)),
.INIT_3E(init_slice('h3e)),
.INIT_3F(init_slice('h3f)),
.INIT_40(init_slice('h40)),
.INIT_41(init_slice('h41)),
.INIT_42(init_slice('h42)),
.INIT_43(init_slice('h43)),
.INIT_44(init_slice('h44)),
.INIT_45(init_slice('h45)),
.INIT_46(init_slice('h46)),
.INIT_47(init_slice('h47)),
.INIT_48(init_slice('h48)),
.INIT_49(init_slice('h49)),
.INIT_4A(init_slice('h4a)),
.INIT_4B(init_slice('h4b)),
.INIT_4C(init_slice('h4c)),
.INIT_4D(init_slice('h4d)),
.INIT_4E(init_slice('h4e)),
.INIT_4F(init_slice('h4f)),
.INIT_50(init_slice('h50)),
.INIT_51(init_slice('h51)),
.INIT_52(init_slice('h52)),
.INIT_53(init_slice('h53)),
.INIT_54(init_slice('h54)),
.INIT_55(init_slice('h55)),
.INIT_56(init_slice('h56)),
.INIT_57(init_slice('h57)),
.INIT_58(init_slice('h58)),
.INIT_59(init_slice('h59)),
.INIT_5A(init_slice('h5a)),
.INIT_5B(init_slice('h5b)),
.INIT_5C(init_slice('h5c)),
.INIT_5D(init_slice('h5d)),
.INIT_5E(init_slice('h5e)),
.INIT_5F(init_slice('h5f)),
.INIT_60(init_slice('h60)),
.INIT_61(init_slice('h61)),
.INIT_62(init_slice('h62)),
.INIT_63(init_slice('h63)),
.INIT_64(init_slice('h64)),
.INIT_65(init_slice('h65)),
.INIT_66(init_slice('h66)),
.INIT_67(init_slice('h67)),
.INIT_68(init_slice('h68)),
.INIT_69(init_slice('h69)),
.INIT_6A(init_slice('h6a)),
.INIT_6B(init_slice('h6b)),
.INIT_6C(init_slice('h6c)),
.INIT_6D(init_slice('h6d)),
.INIT_6E(init_slice('h6e)),
.INIT_6F(init_slice('h6f)),
.INIT_70(init_slice('h70)),
.INIT_71(init_slice('h71)),
.INIT_72(init_slice('h72)),
.INIT_73(init_slice('h73)),
.INIT_74(init_slice('h74)),
.INIT_75(init_slice('h75)),
.INIT_76(init_slice('h76)),
.INIT_77(init_slice('h77)),
.INIT_78(init_slice('h78)),
.INIT_79(init_slice('h79)),
.INIT_7A(init_slice('h7a)),
.INIT_7B(init_slice('h7b)),
.INIT_7C(init_slice('h7c)),
.INIT_7D(init_slice('h7d)),
.INIT_7E(init_slice('h7e)),
.INIT_7F(init_slice('h7f)),
.MODE("DP16K"),
.DATA_WIDTH_A($sformatf("%d", PORT_A_WIDTH)),
.DATA_WIDTH_B($sformatf("%d", PORT_B_WIDTH)),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
.CLKAMUX(PORT_A_CLK_POL ? "SIG" : "INV"),
.CLKBMUX(PORT_B_CLK_POL ? "SIG" : "INV"),
) _TECHMAP_REPLACE_ (
.clka(PORT_A_CLK),
.csa(PORT_A_CLK_EN),
.wea(|PORT_A_WR_EN),
.ocea(1'b1),
.rsta(1'b0),
.addra(PORT_A_ADDR[11:1]),
.bytea(BYTE_A),
.bytewea(BYTEWE_A),
.dia(DIA),
.doa(DOA),
.clkb(PORT_B_CLK),
.csb(PORT_B_CLK_EN),
.web(|PORT_B_WR_EN),
.ocea(1'b1),
.rsta(1'b0),
.addrb(PORT_B_ADDR[11:1]),
.byteb(BYTE_B),
.byteweb(BYTEWE_B),
.dib(DIB),
.dob(DOB),
);
endmodule

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module \$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
AL_MAP_LUT1 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]));
end else
if (WIDTH == 2) begin
AL_MAP_LUT2 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]));
end else
if (WIDTH == 3) begin
AL_MAP_LUT3 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]));
end else
if (WIDTH == 4) begin
AL_MAP_LUT4 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]));
end else
if (WIDTH == 5) begin
AL_MAP_LUT5 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]));
end else
if (WIDTH == 6) begin
AL_MAP_LUT6 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]), .f(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

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module AL_MAP_SEQ (
output reg q,
input ce,
input clk,
input sr,
input d
);
parameter DFFMODE = "FF"; //FF,LATCH
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
wire srmux;
generate
case (SRMUX)
"SR": assign srmux = sr;
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
endgenerate
wire regset;
generate
case (REGSET)
"RESET": assign regset = 1'b0;
"SET": assign regset = 1'b1;
default: assign regset = 1'b0;
endcase
endgenerate
initial q = regset;
generate
if (DFFMODE == "FF")
begin
if (SRMODE == "ASYNC")
begin
always @(posedge clk, posedge srmux)
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
else
begin
always @(posedge clk)
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
if (SRMODE == "ASYNC")
begin
always @*
if (srmux)
q <= regset;
else if (~clk & ce)
q <= d;
end
else
begin
always @*
if (~clk) begin
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
end
end
endgenerate
endmodule
module AL_MAP_LUT1 (
output o,
input a
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
output o,
input a,
input b
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
output o,
input a,
input b,
input c
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
output o,
input a,
input b,
input c,
input d
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
output o,
input a,
input b,
input c,
input d,
input e
);
parameter [31:0] INIT = 32'h0;
parameter EQN = "(A)";
assign o = INIT >> {e, d, c, b, a};
endmodule
module AL_MAP_LUT6 (
output o,
input a,
input b,
input c,
input d,
input e,
input f
);
parameter [63:0] INIT = 64'h0;
parameter EQN = "(A)";
assign o = INIT >> {f, e, d, c, b, a};
endmodule
module AL_MAP_ALU2B (
input cin,
input a0, b0, c0, d0,
input a1, b1, c1, d1,
output s0, s1, cout
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter FUNC0 = "NO";
parameter FUNC1 = "NO";
endmodule
module AL_MAP_ADDER (
input a,
input b,
input c,
output [1:0] o
);
parameter ALUTYPE = "ADD";
generate
case (ALUTYPE)
"ADD": assign o = a + b + c;
"SUB": assign o = a - b - c;
"A_LE_B": assign o = a - b - c;
"ADD_CARRY": assign o = { a, 1'b0 };
"SUB_CARRY": assign o = { ~a, 1'b0 };
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endmodule

1028
resources/netlist/resources/kernel/share/anlogic/eagle_bb.v
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12
resources/netlist/resources/kernel/share/anlogic/lutrams.txt
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@ -1,12 +0,0 @@
ram distributed $__ANLOGIC_DRAM16X4_ {
abits 4;
width 4;
cost 4;
init no_undef;
prune_rom;
port sw "W" {
clock posedge;
}
port ar "R" {
}
}

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resources/netlist/resources/kernel/share/anlogic/lutrams_map.v
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@ -1,32 +0,0 @@
module $__ANLOGIC_DRAM16X4_ (...);
parameter INIT = 64'b0;
input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input [3:0] PORT_W_WR_DATA;
input PORT_W_WR_EN;
input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
function [15:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 16; i = i + 1)
init_slice[i] = INIT[i * 4 + idx];
endfunction
EG_LOGIC_DRAM16X4 #(
.INIT_D0(init_slice(0)),
.INIT_D1(init_slice(1)),
.INIT_D2(init_slice(2)),
.INIT_D3(init_slice(3))
) _TECHMAP_REPLACE_ (
.di(PORT_W_WR_DATA),
.waddr(PORT_W_ADDR),
.wclk(PORT_W_CLK),
.we(PORT_W_WR_EN),
.raddr(PORT_R_ADDR),
.do(PORT_R_RD_DATA)
);
endmodule

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library(yosys_cells) {
cell(DFF_N) {
ff(IQ, IQN) {
clocked_on: "!C";
next_state: "D";
}
pin(D) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_P) {
ff(IQ, IQN) {
clocked_on: "C";
next_state: "D";
}
pin(D) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_NN0) {
ff(IQ, IQN) {
clocked_on: "!C";
next_state: "D";
clear: "!R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_NN1) {
ff(IQ, IQN) {
clocked_on: "!C";
next_state: "D";
preset: "!R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_NP0) {
ff(IQ, IQN) {
clocked_on: "!C";
next_state: "D";
clear: "R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_NP1) {
ff(IQ, IQN) {
clocked_on: "!C";
next_state: "D";
preset: "R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_PN0) {
ff(IQ, IQN) {
clocked_on: "C";
next_state: "D";
clear: "!R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_PN1) {
ff(IQ, IQN) {
clocked_on: "C";
next_state: "D";
preset: "!R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_PP0) {
ff(IQ, IQN) {
clocked_on: "C";
next_state: "D";
clear: "R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
cell(DFF_PP1) {
ff(IQ, IQN) {
clocked_on: "C";
next_state: "D";
preset: "R";
}
pin(D) { direction: input; }
pin(R) { direction: input; }
pin(C) { direction: input; clock: true; }
pin(Q) { direction: output; function: "IQ"; }
}
}

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resources/netlist/resources/kernel/share/cmp2lcu.v
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// This pass performs an optimisation that decomposes wide arithmetic
// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH
// macro) connected to a single lookahead-carry-unit $lcu cell,
// which is typically mapped to dedicated (and fast) FPGA
// carry-chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _80_lcu_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
generate
if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2)
wire _TECHMAP_FAIL_ = 1;
else if (_TECHMAP_CELLTYPE_ == "$lt") begin
// Transform $lt into $gt by swapping A and B
$gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else if (_TECHMAP_CELLTYPE_ == "$le") begin
// Transform $le into $ge by swapping A and B
$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else begin
// Perform sign extension on A and B
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
(* force_downto *)
wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
(* force_downto *)
wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
// For $ge operation, start with the assumption that A and B are
// equal (propagating this equality if A and B turn out to be so)
localparam CI = _TECHMAP_CELLTYPE_ == "$ge";
$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
end
endgenerate
endmodule
module $__CMP2LCU (A, B, P, G, Y);
parameter AB_WIDTH = 0;
parameter AB_SIGNED = 0;
parameter LCU_WIDTH = 1;
parameter BUDGET = 0;
parameter CI = 0;
(* force_downto *)
input [AB_WIDTH-1:0] A; // A from original $gt/$ge
(* force_downto *)
input [AB_WIDTH-1:0] B; // B from original $gt/$ge
(* force_downto *)
input [LCU_WIDTH-1:0] P; // P of $lcu
(* force_downto *)
input [LCU_WIDTH-1:0] G; // G of $lcu
output Y;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
generate
if (AB_WIDTH == 0) begin
(* force_downto *)
wire [LCU_WIDTH-1:0] CO;
$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
assign Y = CO[LCU_WIDTH-1];
end
else begin
localparam COST =
_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
? 0
: (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
? 1
: 2);
if (BUDGET < COST)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));
else begin
wire PP, GG;
// Bit-wise equality (xnor) of A and B
assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];
if (AB_SIGNED)
assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];
else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant
assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];
else
// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
// from MSB down, deferring to less significant bits if the
// MSBs are equal
assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
(* force_downto *)
wire [LCU_WIDTH-1:0] P_, G_;
if (LCU_WIDTH == 1) begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
assign P_ = P[0] & PP;
// Generate if any comparisons call for it
assign G_ = G[0] | GG;
end
else begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
// Generate if any comparisons call for it
assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
if (AB_WIDTH == 1)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
else
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
end
end
endgenerate
endmodule

98
resources/netlist/resources/kernel/share/cmp2lut.v
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// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
// cannot be optimized further.
//
// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
// with n <= k inputs should be techmapped in this way, because this shortens the critical path
// from n to 1 by avoiding carry chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B_ = 0;
function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
input integer width;
input integer operation;
input integer swap;
input integer sign;
input integer operand;
integer n, i_var, i_cst, lhs, rhs, o_bit;
begin
gen_lut = width'b0;
for (n = 0; n < (1 << width); n++) begin
if (sign)
i_var = n[width-1:0];
else
i_var = n;
i_cst = operand;
if (swap) begin
lhs = i_cst;
rhs = i_var;
end else begin
lhs = i_var;
rhs = i_cst;
end
if (operation == 0)
o_bit = (lhs < rhs);
if (operation == 1)
o_bit = (lhs <= rhs);
if (operation == 2)
o_bit = (lhs > rhs);
if (operation == 3)
o_bit = (lhs >= rhs);
gen_lut = gen_lut | (o_bit << n);
end
end
endfunction
generate
localparam operation =
_TECHMAP_CELLTYPE_ == "$lt" ? 0 :
_TECHMAP_CELLTYPE_ == "$le" ? 1 :
_TECHMAP_CELLTYPE_ == "$gt" ? 2 :
_TECHMAP_CELLTYPE_ == "$ge" ? 3 :
-1;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
else if (&_TECHMAP_CONSTMSK_B_)
\$lut #(
.WIDTH(A_WIDTH),
.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
) _TECHMAP_REPLACE_ (
.A(A),
.Y(Y)
);
else if (&_TECHMAP_CONSTMSK_A_)
\$lut #(
.WIDTH(B_WIDTH),
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
) _TECHMAP_REPLACE_ (
.A(B),
.Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule

162
resources/netlist/resources/kernel/share/coolrunner2/cells_counter_map.v
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@ -1,162 +0,0 @@
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output wire OUT;
(* force_downto *)
output wire[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = 0;
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
if (DIRECTION == "UP") begin
if (WIDTH < 2) begin
initial begin
$display("ERROR: \$__COUNT_ must be at least 2 bits wide (bug in extract_counter pass?).");
$finish;
end
end
// FIXME: Max width?
assign OUT = POUT == COUNT_TO;
if (HAS_CE) begin
genvar i;
for (i = 0; i < WIDTH; i++) begin: countbits
// each bit = (cur & !reset) ^ (all prev & !reset)
wire xor_to_mc_bitn;
FDCP #(
.INIT(0)
) bitn_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bitn),
.PRE(0),
.Q(POUT[i])
);
wire orterm_to_xor_bitn;
wire pterm0_to_or_bitn;
wire pterm1_to_or_bitn;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bitn_xor (
.IN_ORTERM(orterm_to_xor_bitn),
.IN_PTC(pterm1_to_or_bitn),
.OUT(xor_to_mc_bitn)
);
ORTERM #(
.WIDTH(1)
) bitn_or (
.IN(pterm0_to_or_bitn),
.OUT(orterm_to_xor_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(1)
) bitn_pterm0 (
.IN(POUT[i]),
.IN_B(OUT),
.OUT(pterm0_to_or_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(i + 1)
) bitn_pterm1 (
.IN({POUT[i-1:0], CE}),
.IN_B(OUT),
.OUT(pterm1_to_or_bitn)
);
end
end else begin
// Bit0 is special; toggle unless reset
// cur reset out
// 0 0 1
// 0 1 0
// 1 0 0
// 1 1 0
wire xor_to_mc_bit0;
FDCP #(
.INIT(0)
) bit0_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bit0),
.PRE(0),
.Q(POUT[0])
);
wire pterm_to_xor_bit0;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bit0_xor (
.IN_PTC(pterm_to_xor_bit0),
.OUT(xor_to_mc_bit0)
);
ANDTERM #(
.COMP_INP(2),
.TRUE_INP(0)
) bit0_pterm (
.IN(),
.IN_B({POUT[0], OUT}),
.OUT(pterm_to_xor_bit0)
);
genvar i;
for (i = 1; i < WIDTH; i++) begin: countbits
// each bit = (cur & !reset) ^ (all prev & !reset)
wire xor_to_mc_bitn;
FDCP #(
.INIT(0)
) bitn_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bitn),
.PRE(0),
.Q(POUT[i])
);
wire orterm_to_xor_bitn;
wire pterm0_to_or_bitn;
wire pterm1_to_or_bitn;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bitn_xor (
.IN_ORTERM(orterm_to_xor_bitn),
.IN_PTC(pterm1_to_or_bitn),
.OUT(xor_to_mc_bitn)
);
ORTERM #(
.WIDTH(1)
) bitn_or (
.IN(pterm0_to_or_bitn),
.OUT(orterm_to_xor_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(1)
) bitn_pterm0 (
.IN(POUT[i]),
.IN_B(OUT),
.OUT(pterm0_to_or_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(i)
) bitn_pterm1 (
.IN(POUT[i-1:0]),
.IN_B(OUT),
.OUT(pterm1_to_or_bitn)
);
end
end
end
// FIXME: down counters
endmodule

19
resources/netlist/resources/kernel/share/coolrunner2/cells_latch.v
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@ -1,19 +0,0 @@
module $_DLATCH_P_(input E, input D, output Q);
LDCP _TECHMAP_REPLACE_ (
.D(D),
.G(E),
.Q(Q),
.PRE(1'b0),
.CLR(1'b0)
);
endmodule
module $_DLATCH_N_(input E, input D, output Q);
LDCP_N _TECHMAP_REPLACE_ (
.D(D),
.G(E),
.Q(Q),
.PRE(1'b0),
.CLR(1'b0)
);
endmodule

310
resources/netlist/resources/kernel/share/coolrunner2/cells_sim.v
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@ -1,310 +0,0 @@
module IBUF(input I, output O);
assign O = I;
endmodule
module IOBUFE(input I, input E, output O, inout IO);
assign O = IO;
assign IO = E ? I : 1'bz;
endmodule
module ANDTERM(IN, IN_B, OUT);
parameter TRUE_INP = 0;
parameter COMP_INP = 0;
input [TRUE_INP-1:0] IN;
input [COMP_INP-1:0] IN_B;
output reg OUT;
integer i;
always @(*) begin
OUT = 1;
for (i = 0; i < TRUE_INP; i=i+1)
OUT = OUT & IN[i];
for (i = 0; i < COMP_INP; i=i+1)
OUT = OUT & ~IN_B[i];
end
endmodule
module ORTERM(IN, OUT);
parameter WIDTH = 0;
input [WIDTH-1:0] IN;
output reg OUT;
integer i;
always @(*) begin
OUT = 0;
for (i = 0; i < WIDTH; i=i+1) begin
OUT = OUT | IN[i];
end
end
endmodule
module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
parameter INVERT_OUT = 0;
input IN_PTC;
input IN_ORTERM;
output wire OUT;
wire xor_intermed;
assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
assign xor_intermed = IN_ORTERM ^ IN_PTC;
endmodule
module FDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FDCP_N (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module LDCP (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 1)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule
module LDCP_N (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 0)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule
module BUFG(I, O);
input I;
output O;
assign O = I;
endmodule
module BUFGSR(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = INVERT ? ~I : I;
endmodule
module BUFGTS(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = INVERT ? ~I : I;
endmodule
module FDDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FTCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTCP_N (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTDCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDCPE_N (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule

41
resources/netlist/resources/kernel/share/coolrunner2/tff_extract.v
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@ -1,41 +0,0 @@
module FTCP (C, PRE, CLR, T, Q);
input C, PRE, CLR, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_PPP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(PRE),
.R(CLR),
);
endmodule
module FTCP_N (C, PRE, CLR, T, Q);
input C, PRE, CLR, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_NPP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(PRE),
.R(CLR),
);
endmodule

31
resources/netlist/resources/kernel/share/coolrunner2/xc2_dff.lib
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@ -1,31 +0,0 @@
library(xc2_dff) {
cell(FDCP) {
area: 1;
ff("IQ", "IQN") { clocked_on: C;
next_state: D;
clear: "CLR";
preset: "PRE"; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(CLR) { direction: input; }
pin(PRE) { direction: input; }
}
cell(FDCP_N) {
area: 1;
ff("IQ", "IQN") { clocked_on: "!C";
next_state: D;
clear: "CLR";
preset: "PRE"; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(CLR) { direction: input; }
pin(PRE) { direction: input; }
}
}

16
resources/netlist/resources/kernel/share/dff2ff.v
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@ -1,16 +0,0 @@
(* techmap_celltype = "$dff" *)
module dff2ff (CLK, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
input CLK;
(* force_downto *)
input [WIDTH-1:0] D;
(* force_downto *)
output reg [WIDTH-1:0] Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
always @($global_clock)
Q <= D;
endmodule

90
resources/netlist/resources/kernel/share/ecp5/arith_map.v
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@ -1,90 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N + 1) / 2) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH2-1:0] FCO, Y1;
genvar i;
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2C #(
.INIT0(16'b1001011010101010),
.INIT1(16'b1001011010101010),
.INJECT1_0("NO"),
.INJECT1_1("NO")
) ccu2c_i (
.CIN(C[i]),
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
.S0(Y[i]), .S1(Y1[i]),
.COUT(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
assign CO[i+1] = FCO[i];
assign Y[i+1] = Y1[i];
end
end endgenerate
assign X = AA ^ BB;
endmodule

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resources/netlist/resources/kernel/share/ecp5/brams.txt
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@ -1,52 +0,0 @@
ram block $__ECP5_DP16KD_ {
abits 14;
widths 1 2 4 9 18 per_port;
byte 9;
cost 128;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
wrbe_separate;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
portoption "WRITEMODE" "READBEFOREWRITE" {
rdwr old;
}
option "RESETMODE" "SYNC" {
rdsrst zero ungated block_wr;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
}
ram block $__ECP5_PDPW16KD_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
byte 9;
cost 128;
init no_undef;
port sr "R" {
clock anyedge;
clken;
option "RESETMODE" "SYNC" {
rdsrst zero ungated;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
width 36;
clock anyedge;
clken;
}
}

489
resources/netlist/resources/kernel/share/ecp5/brams_map.v
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@ -1,489 +0,0 @@
module $__ECP5_DP16KD_ (...);
parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";
parameter PORT_A_WIDTH = 18;
parameter PORT_A_WR_BE_WIDTH = 2;
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [13:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
parameter PORT_B_WIDTH = 18;
parameter PORT_B_WR_BE_WIDTH = 2;
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input PORT_B_RD_SRST;
input PORT_B_RD_ARST;
input [13:0] PORT_B_ADDR;
input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
function [319:0] init_slice;
input integer idx;
integer i, j;
init_slice = 0;
for (i = 0; i < 16; i = i + 1) begin
init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
end
endfunction
wire [17:0] DOA;
wire [17:0] DOB;
wire [17:0] DIA = PORT_A_WR_DATA;
wire [17:0] DIB = PORT_B_WR_DATA;
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
DP16KD #(
.INITVAL_00(init_slice('h00)),
.INITVAL_01(init_slice('h01)),
.INITVAL_02(init_slice('h02)),
.INITVAL_03(init_slice('h03)),
.INITVAL_04(init_slice('h04)),
.INITVAL_05(init_slice('h05)),
.INITVAL_06(init_slice('h06)),
.INITVAL_07(init_slice('h07)),
.INITVAL_08(init_slice('h08)),
.INITVAL_09(init_slice('h09)),
.INITVAL_0A(init_slice('h0a)),
.INITVAL_0B(init_slice('h0b)),
.INITVAL_0C(init_slice('h0c)),
.INITVAL_0D(init_slice('h0d)),
.INITVAL_0E(init_slice('h0e)),
.INITVAL_0F(init_slice('h0f)),
.INITVAL_10(init_slice('h10)),
.INITVAL_11(init_slice('h11)),
.INITVAL_12(init_slice('h12)),
.INITVAL_13(init_slice('h13)),
.INITVAL_14(init_slice('h14)),
.INITVAL_15(init_slice('h15)),
.INITVAL_16(init_slice('h16)),
.INITVAL_17(init_slice('h17)),
.INITVAL_18(init_slice('h18)),
.INITVAL_19(init_slice('h19)),
.INITVAL_1A(init_slice('h1a)),
.INITVAL_1B(init_slice('h1b)),
.INITVAL_1C(init_slice('h1c)),
.INITVAL_1D(init_slice('h1d)),
.INITVAL_1E(init_slice('h1e)),
.INITVAL_1F(init_slice('h1f)),
.INITVAL_20(init_slice('h20)),
.INITVAL_21(init_slice('h21)),
.INITVAL_22(init_slice('h22)),
.INITVAL_23(init_slice('h23)),
.INITVAL_24(init_slice('h24)),
.INITVAL_25(init_slice('h25)),
.INITVAL_26(init_slice('h26)),
.INITVAL_27(init_slice('h27)),
.INITVAL_28(init_slice('h28)),
.INITVAL_29(init_slice('h29)),
.INITVAL_2A(init_slice('h2a)),
.INITVAL_2B(init_slice('h2b)),
.INITVAL_2C(init_slice('h2c)),
.INITVAL_2D(init_slice('h2d)),
.INITVAL_2E(init_slice('h2e)),
.INITVAL_2F(init_slice('h2f)),
.INITVAL_30(init_slice('h30)),
.INITVAL_31(init_slice('h31)),
.INITVAL_32(init_slice('h32)),
.INITVAL_33(init_slice('h33)),
.INITVAL_34(init_slice('h34)),
.INITVAL_35(init_slice('h35)),
.INITVAL_36(init_slice('h36)),
.INITVAL_37(init_slice('h37)),
.INITVAL_38(init_slice('h38)),
.INITVAL_39(init_slice('h39)),
.INITVAL_3A(init_slice('h3a)),
.INITVAL_3B(init_slice('h3b)),
.INITVAL_3C(init_slice('h3c)),
.INITVAL_3D(init_slice('h3d)),
.INITVAL_3E(init_slice('h3e)),
.INITVAL_3F(init_slice('h3f)),
.DATA_WIDTH_A(PORT_A_WIDTH),
.DATA_WIDTH_B(PORT_B_WIDTH),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.RESETMODE(OPTION_RESETMODE),
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
.CSDECODE_A("0b000"),
.CSDECODE_B("0b000"),
.CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"),
.CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"),
.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
.CLKA(PORT_A_CLK),
.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),
.CEA(PORT_A_CLK_EN),
.OCEA(1'b1),
.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
.CSA0(1'b0),
.CSA1(1'b0),
.CSA2(1'b0),
.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),
.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),
.ADA2(PORT_A_ADDR[2]),
.ADA3(PORT_A_ADDR[3]),
.ADA4(PORT_A_ADDR[4]),
.ADA5(PORT_A_ADDR[5]),
.ADA6(PORT_A_ADDR[6]),
.ADA7(PORT_A_ADDR[7]),
.ADA8(PORT_A_ADDR[8]),
.ADA9(PORT_A_ADDR[9]),
.ADA10(PORT_A_ADDR[10]),
.ADA11(PORT_A_ADDR[11]),
.ADA12(PORT_A_ADDR[12]),
.ADA13(PORT_A_ADDR[13]),
.DIA0(DIA[0]),
.DIA1(DIA[1]),
.DIA2(DIA[2]),
.DIA3(DIA[3]),
.DIA4(DIA[4]),
.DIA5(DIA[5]),
.DIA6(DIA[6]),
.DIA7(DIA[7]),
.DIA8(DIA[8]),
.DIA9(DIA[9]),
.DIA10(DIA[10]),
.DIA11(DIA[11]),
.DIA12(DIA[12]),
.DIA13(DIA[13]),
.DIA14(DIA[14]),
.DIA15(DIA[15]),
.DIA16(DIA[16]),
.DIA17(DIA[17]),
.DOA0(DOA[0]),
.DOA1(DOA[1]),
.DOA2(DOA[2]),
.DOA3(DOA[3]),
.DOA4(DOA[4]),
.DOA5(DOA[5]),
.DOA6(DOA[6]),
.DOA7(DOA[7]),
.DOA8(DOA[8]),
.DOA9(DOA[9]),
.DOA10(DOA[10]),
.DOA11(DOA[11]),
.DOA12(DOA[12]),
.DOA13(DOA[13]),
.DOA14(DOA[14]),
.DOA15(DOA[15]),
.DOA16(DOA[16]),
.DOA17(DOA[17]),
.CLKB(PORT_B_CLK),
.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),
.CEB(PORT_B_CLK_EN),
.OCEB(1'b1),
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
.CSB0(1'b0),
.CSB1(1'b0),
.CSB2(1'b0),
.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),
.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),
.ADB2(PORT_B_ADDR[2]),
.ADB3(PORT_B_ADDR[3]),
.ADB4(PORT_B_ADDR[4]),
.ADB5(PORT_B_ADDR[5]),
.ADB6(PORT_B_ADDR[6]),
.ADB7(PORT_B_ADDR[7]),
.ADB8(PORT_B_ADDR[8]),
.ADB9(PORT_B_ADDR[9]),
.ADB10(PORT_B_ADDR[10]),
.ADB11(PORT_B_ADDR[11]),
.ADB12(PORT_B_ADDR[12]),
.ADB13(PORT_B_ADDR[13]),
.DIB0(DIB[0]),
.DIB1(DIB[1]),
.DIB2(DIB[2]),
.DIB3(DIB[3]),
.DIB4(DIB[4]),
.DIB5(DIB[5]),
.DIB6(DIB[6]),
.DIB7(DIB[7]),
.DIB8(DIB[8]),
.DIB9(DIB[9]),
.DIB10(DIB[10]),
.DIB11(DIB[11]),
.DIB12(DIB[12]),
.DIB13(DIB[13]),
.DIB14(DIB[14]),
.DIB15(DIB[15]),
.DIB16(DIB[16]),
.DIB17(DIB[17]),
.DOB0(DOB[0]),
.DOB1(DOB[1]),
.DOB2(DOB[2]),
.DOB3(DOB[3]),
.DOB4(DOB[4]),
.DOB5(DOB[5]),
.DOB6(DOB[6]),
.DOB7(DOB[7]),
.DOB8(DOB[8]),
.DOB9(DOB[9]),
.DOB10(DOB[10]),
.DOB11(DOB[11]),
.DOB12(DOB[12]),
.DOB13(DOB[13]),
.DOB14(DOB[14]),
.DOB15(DOB[15]),
.DOB16(DOB[16]),
.DOB17(DOB[17]),
);
endmodule
module $__ECP5_PDPW16KD_ (...);
parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";
parameter PORT_R_WIDTH = 36;
parameter PORT_R_CLK_POL = 1;
input PORT_R_CLK;
input PORT_R_CLK_EN;
input PORT_R_RD_SRST;
input PORT_R_RD_ARST;
input [13:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
parameter PORT_W_WIDTH = 36;
parameter PORT_W_WR_EN_WIDTH = 4;
parameter PORT_W_CLK_POL = 1;
input PORT_W_CLK;
input PORT_W_CLK_EN;
input [13:0] PORT_W_ADDR;
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
function [319:0] init_slice;
input integer idx;
integer i, j;
init_slice = 0;
for (i = 0; i < 16; i = i + 1) begin
init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
end
endfunction
wire [35:0] DI = PORT_W_WR_DATA;
wire [35:0] DO;
assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];
DP16KD #(
.INITVAL_00(init_slice('h00)),
.INITVAL_01(init_slice('h01)),
.INITVAL_02(init_slice('h02)),
.INITVAL_03(init_slice('h03)),
.INITVAL_04(init_slice('h04)),
.INITVAL_05(init_slice('h05)),
.INITVAL_06(init_slice('h06)),
.INITVAL_07(init_slice('h07)),
.INITVAL_08(init_slice('h08)),
.INITVAL_09(init_slice('h09)),
.INITVAL_0A(init_slice('h0a)),
.INITVAL_0B(init_slice('h0b)),
.INITVAL_0C(init_slice('h0c)),
.INITVAL_0D(init_slice('h0d)),
.INITVAL_0E(init_slice('h0e)),
.INITVAL_0F(init_slice('h0f)),
.INITVAL_10(init_slice('h10)),
.INITVAL_11(init_slice('h11)),
.INITVAL_12(init_slice('h12)),
.INITVAL_13(init_slice('h13)),
.INITVAL_14(init_slice('h14)),
.INITVAL_15(init_slice('h15)),
.INITVAL_16(init_slice('h16)),
.INITVAL_17(init_slice('h17)),
.INITVAL_18(init_slice('h18)),
.INITVAL_19(init_slice('h19)),
.INITVAL_1A(init_slice('h1a)),
.INITVAL_1B(init_slice('h1b)),
.INITVAL_1C(init_slice('h1c)),
.INITVAL_1D(init_slice('h1d)),
.INITVAL_1E(init_slice('h1e)),
.INITVAL_1F(init_slice('h1f)),
.INITVAL_20(init_slice('h20)),
.INITVAL_21(init_slice('h21)),
.INITVAL_22(init_slice('h22)),
.INITVAL_23(init_slice('h23)),
.INITVAL_24(init_slice('h24)),
.INITVAL_25(init_slice('h25)),
.INITVAL_26(init_slice('h26)),
.INITVAL_27(init_slice('h27)),
.INITVAL_28(init_slice('h28)),
.INITVAL_29(init_slice('h29)),
.INITVAL_2A(init_slice('h2a)),
.INITVAL_2B(init_slice('h2b)),
.INITVAL_2C(init_slice('h2c)),
.INITVAL_2D(init_slice('h2d)),
.INITVAL_2E(init_slice('h2e)),
.INITVAL_2F(init_slice('h2f)),
.INITVAL_30(init_slice('h30)),
.INITVAL_31(init_slice('h31)),
.INITVAL_32(init_slice('h32)),
.INITVAL_33(init_slice('h33)),
.INITVAL_34(init_slice('h34)),
.INITVAL_35(init_slice('h35)),
.INITVAL_36(init_slice('h36)),
.INITVAL_37(init_slice('h37)),
.INITVAL_38(init_slice('h38)),
.INITVAL_39(init_slice('h39)),
.INITVAL_3A(init_slice('h3a)),
.INITVAL_3B(init_slice('h3b)),
.INITVAL_3C(init_slice('h3c)),
.INITVAL_3D(init_slice('h3d)),
.INITVAL_3E(init_slice('h3e)),
.INITVAL_3F(init_slice('h3f)),
.DATA_WIDTH_A(PORT_W_WIDTH),
.DATA_WIDTH_B(PORT_R_WIDTH),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.RESETMODE(OPTION_RESETMODE),
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
.CSDECODE_A("0b000"),
.CSDECODE_B("0b000"),
.CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"),
.CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
.CLKA(PORT_W_CLK),
.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),
.CEA(PORT_W_CLK_EN),
.OCEA(1'b0),
.RSTA(1'b0),
.CSA0(1'b0),
.CSA1(1'b0),
.CSA2(1'b0),
.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),
.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),
.ADA4(PORT_W_ADDR[4]),
.ADA5(PORT_W_ADDR[5]),
.ADA6(PORT_W_ADDR[6]),
.ADA7(PORT_W_ADDR[7]),
.ADA8(PORT_W_ADDR[8]),
.ADA9(PORT_W_ADDR[9]),
.ADA10(PORT_W_ADDR[10]),
.ADA11(PORT_W_ADDR[11]),
.ADA12(PORT_W_ADDR[12]),
.ADA13(PORT_W_ADDR[13]),
.DIA0(DI[0]),
.DIA1(DI[1]),
.DIA2(DI[2]),
.DIA3(DI[3]),
.DIA4(DI[4]),
.DIA5(DI[5]),
.DIA6(DI[6]),
.DIA7(DI[7]),
.DIA8(DI[8]),
.DIA9(DI[9]),
.DIA10(DI[10]),
.DIA11(DI[11]),
.DIA12(DI[12]),
.DIA13(DI[13]),
.DIA14(DI[14]),
.DIA15(DI[15]),
.DIA16(DI[16]),
.DIA17(DI[17]),
.DIB0(DI[18]),
.DIB1(DI[19]),
.DIB2(DI[20]),
.DIB3(DI[21]),
.DIB4(DI[22]),
.DIB5(DI[23]),
.DIB6(DI[24]),
.DIB7(DI[25]),
.DIB8(DI[26]),
.DIB9(DI[27]),
.DIB10(DI[28]),
.DIB11(DI[29]),
.DIB12(DI[30]),
.DIB13(DI[31]),
.DIB14(DI[32]),
.DIB15(DI[33]),
.DIB16(DI[34]),
.DIB17(DI[35]),
.CLKB(PORT_R_CLK),
.WEB(1'b0),
.CEB(PORT_R_CLK_EN),
.OCEB(1'b1),
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
.CSB0(1'b0),
.CSB1(1'b0),
.CSB2(1'b0),
.ADB0(PORT_R_ADDR[0]),
.ADB1(PORT_R_ADDR[1]),
.ADB2(PORT_R_ADDR[2]),
.ADB3(PORT_R_ADDR[3]),
.ADB4(PORT_R_ADDR[4]),
.ADB5(PORT_R_ADDR[5]),
.ADB6(PORT_R_ADDR[6]),
.ADB7(PORT_R_ADDR[7]),
.ADB8(PORT_R_ADDR[8]),
.ADB9(PORT_R_ADDR[9]),
.ADB10(PORT_R_ADDR[10]),
.ADB11(PORT_R_ADDR[11]),
.ADB12(PORT_R_ADDR[12]),
.ADB13(PORT_R_ADDR[13]),
.DOA0(DO[0]),
.DOA1(DO[1]),
.DOA2(DO[2]),
.DOA3(DO[3]),
.DOA4(DO[4]),
.DOA5(DO[5]),
.DOA6(DO[6]),
.DOA7(DO[7]),
.DOA8(DO[8]),
.DOA9(DO[9]),
.DOA10(DO[10]),
.DOA11(DO[11]),
.DOA12(DO[12]),
.DOA13(DO[13]),
.DOA14(DO[14]),
.DOA15(DO[15]),
.DOA16(DO[16]),
.DOA17(DO[17]),
.DOB0(DO[18]),
.DOB1(DO[19]),
.DOB2(DO[20]),
.DOB3(DO[21]),
.DOB4(DO[22]),
.DOB5(DO[23]),
.DOB6(DO[24]),
.DOB7(DO[25]),
.DOB8(DO[26]),
.DOB9(DO[27]),
.DOB10(DO[28]),
.DOB11(DO[29]),
.DOB12(DO[30]),
.DOB13(DO[31]),
.DOB14(DO[32]),
.DOB15(DO[33]),
.DOB16(DO[34]),
.DOB17(DO[35]),
);
endmodule

832
resources/netlist/resources/kernel/share/ecp5/cells_bb.v
View File

@ -1,832 +0,0 @@
// ECP5 Blackbox cells
// FIXME: Create sim models
(* blackbox *)
module MULT18X18D(
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
input CLK0, CLK1, CLK2, CLK3,
input CE0, CE1, CE2, CE3,
input RST0, RST1, RST2, RST3,
input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
output SIGNEDP
);
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_INPUTC_CE = "CE0";
parameter REG_INPUTC_RST = "RST0";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter [127:0] CLK0_DIV = "ENABLED";
parameter [127:0] CLK1_DIV = "ENABLED";
parameter [127:0] CLK2_DIV = "ENABLED";
parameter [127:0] CLK3_DIV = "ENABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter [127:0] GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter [127:0] SOURCEB_MODE = "B_SHIFT";
parameter [127:0] MULT_BYPASS = "DISABLED";
parameter [127:0] RESETMODE = "SYNC";
endmodule
(* blackbox *)
module ALU54B(
input CLK0, CLK1, CLK2, CLK3,
input CE0, CE1, CE2, CE3,
input RST0, RST1, RST2, RST3,
input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
output EQZ, EQZM, EQOM, EQPAT, EQPATB,
output OVER, UNDER, OVERUNDER,
output SIGNEDR
);
parameter REG_INPUTC0_CLK = "NONE";
parameter REG_INPUTC0_CE = "CE0";
parameter REG_INPUTC0_RST = "RST0";
parameter REG_INPUTC1_CLK = "NONE";
parameter REG_INPUTC1_CE = "CE0";
parameter REG_INPUTC1_RST = "RST0";
parameter REG_OPCODEOP0_0_CLK = "NONE";
parameter REG_OPCODEOP0_0_CE = "CE0";
parameter REG_OPCODEOP0_0_RST = "RST0";
parameter REG_OPCODEOP1_0_CLK = "NONE";
parameter REG_OPCODEOP0_1_CLK = "NONE";
parameter REG_OPCODEOP0_1_CE = "CE0";
parameter REG_OPCODEOP0_1_RST = "RST0";
parameter REG_OPCODEOP1_1_CLK = "NONE";
parameter REG_OPCODEIN_0_CLK = "NONE";
parameter REG_OPCODEIN_0_CE = "CE0";
parameter REG_OPCODEIN_0_RST = "RST0";
parameter REG_OPCODEIN_1_CLK = "NONE";
parameter REG_OPCODEIN_1_CE = "CE0";
parameter REG_OPCODEIN_1_RST = "RST0";
parameter REG_OUTPUT0_CLK = "NONE";
parameter REG_OUTPUT0_CE = "CE0";
parameter REG_OUTPUT0_RST = "RST0";
parameter REG_OUTPUT1_CLK = "NONE";
parameter REG_OUTPUT1_CE = "CE0";
parameter REG_OUTPUT1_RST = "RST0";
parameter REG_FLAG_CLK = "NONE";
parameter REG_FLAG_CE = "CE0";
parameter REG_FLAG_RST = "RST0";
parameter REG_INPUTCFB_CLK = "NONE";
parameter REG_INPUTCFB_CE = "CE0";
parameter REG_INPUTCFB_RST = "RST0";
parameter [127:0] MCPAT_SOURCE = "STATIC";
parameter [127:0] MASKPAT_SOURCE = "STATIC";
parameter MASK01 = "0x00000000000000";
parameter [127:0] CLK0_DIV = "ENABLED";
parameter [127:0] CLK1_DIV = "ENABLED";
parameter [127:0] CLK2_DIV = "ENABLED";
parameter [127:0] CLK3_DIV = "ENABLED";
parameter MCPAT = "0x00000000000000";
parameter MASKPAT = "0x00000000000000";
parameter RNDPAT = "0x00000000000000";
parameter [127:0] GSR = "ENABLED";
parameter [127:0] RESETMODE = "SYNC";
parameter MULT9_MODE = "DISABLED";
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
parameter LEGACY = "DISABLED";
endmodule
(* blackbox *)
module EHXPLLL (
input CLKI, CLKFB,
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
input STDBY, PLLWAKESYNC,
input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
output CLKOP, CLKOS, CLKOS2, CLKOS3,
output LOCK, INTLOCK,
output REFCLK, CLKINTFB
);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
parameter CLKOS_DIV = 8;
parameter CLKOS2_DIV = 8;
parameter CLKOS3_DIV = 8;
parameter CLKOP_ENABLE = "ENABLED";
parameter CLKOS_ENABLE = "DISABLED";
parameter CLKOS2_ENABLE = "DISABLED";
parameter CLKOS3_ENABLE = "DISABLED";
parameter CLKOP_CPHASE = 0;
parameter CLKOS_CPHASE = 0;
parameter CLKOS2_CPHASE = 0;
parameter CLKOS3_CPHASE = 0;
parameter CLKOP_FPHASE = 0;
parameter CLKOS_FPHASE = 0;
parameter CLKOS2_FPHASE = 0;
parameter CLKOS3_FPHASE = 0;
parameter FEEDBK_PATH = "CLKOP";
parameter CLKOP_TRIM_POL = "RISING";
parameter CLKOP_TRIM_DELAY = 0;
parameter CLKOS_TRIM_POL = "RISING";
parameter CLKOS_TRIM_DELAY = 0;
parameter OUTDIVIDER_MUXA = "DIVA";
parameter OUTDIVIDER_MUXB = "DIVB";
parameter OUTDIVIDER_MUXC = "DIVC";
parameter OUTDIVIDER_MUXD = "DIVD";
parameter PLL_LOCK_MODE = 0;
parameter PLL_LOCK_DELAY = 200;
parameter STDBY_ENABLE = "DISABLED";
parameter REFIN_RESET = "DISABLED";
parameter SYNC_ENABLE = "DISABLED";
parameter INT_LOCK_STICKY = "ENABLED";
parameter DPHASE_SOURCE = "DISABLED";
parameter PLLRST_ENA = "DISABLED";
parameter INTFB_WAKE = "DISABLED";
endmodule
(* blackbox *)
module DTR(
input STARTPULSE,
output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
);
endmodule
(* blackbox *)
module OSCG(
output OSC
);
parameter DIV = 128;
endmodule
(* blackbox *) (* keep *)
module USRMCLK(
input USRMCLKI, USRMCLKTS,
output USRMCLKO
);
endmodule
(* blackbox *) (* keep *)
module JTAGG(
input TCK, TMS, TDI, JTDO2, JTDO1,
output TDO, JTDI, JTCK, JRTI2, JRTI1,
output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
);
parameter ER1 = "ENABLED";
parameter ER2 = "ENABLED";
endmodule
(* blackbox *)
module DELAYF(
input A, LOADN, MOVE, DIRECTION,
output Z, CFLAG
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
(* blackbox *)
module DELAYG(
input A,
output Z
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
(* blackbox *)
module IDDRX1F(
input D, SCLK, RST,
output Q0, Q1
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDRX2F(
input D, SCLK, ECLK, RST, ALIGNWD,
output Q0, Q1, Q2, Q3
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDR71B(
input D, SCLK, ECLK, RST, ALIGNWD,
output Q0, Q1, Q2, Q3, Q4, Q5, Q6
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDRX2DQA(
input D, DQSR90, ECLK, SCLK, RST,
input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
output Q0, Q1, Q2, Q3, QWL
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX1F(
input SCLK, RST, D0, D1,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2F(
input SCLK, ECLK, RST, D0, D1, D2, D3,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDR71B(
input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module OSHX2A(
input D0, D1, RST, ECLK, SCLK,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2DQA(
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2DQSB(
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module TSHX2DQA(
input T0, T1, SCLK, ECLK, DQSW270, RST,
output Q
);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
endmodule
(* blackbox *)
module TSHX2DQSA(
input T0, T1, SCLK, ECLK, DQSW, RST,
output Q
);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
endmodule
(* blackbox *)
module DQSBUFM(
input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
input ECLK, SCLK,
input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0,
input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
output DQSR90, DQSW, DQSW270,
output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
);
parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
parameter DQS_LI_DEL_VAL = 0;
parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
parameter DQS_LO_DEL_VAL = 0;
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module DDRDLLA(
input CLK, RST, UDDCNTLN, FREEZE,
output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
);
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module DLLDELD(
input A, DDRDEL, LOADN, MOVE, DIRECTION,
output Z, CFLAG
);
parameter DEL_ADJ = "PLUS";
parameter DEL_VAL = 0;
endmodule
(* blackbox *)
module CLKDIVF(
input CLKI, RST, ALIGNWD,
output CDIVX
);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
endmodule
(* blackbox *)
module ECLKSYNCB(
input ECLKI, STOP,
output ECLKO
);
endmodule
(* blackbox *)
module ECLKBRIDGECS(
input CLK0, CLK1, SEL,
output ECSOUT
);
endmodule
(* blackbox *)
module DCCA(
input CLKI, CE,
output CLKO
);
endmodule
(* blackbox *)
module DCSC(
input CLK1, CLK0,
input SEL1, SEL0,
input MODESEL,
output DCSOUT
);
parameter DCSMODE = "POS";
endmodule
(* blackbox *) (* keep *)
module DCUA(
input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
input D_REFCLKI,
output D_FFS_PLOL
);
parameter CH0_AUTO_CALIB_EN = "0b0";
parameter CH0_AUTO_FACQ_EN = "0b0";
parameter CH0_BAND_THRESHOLD = "0b000000";
parameter CH0_CALIB_CK_MODE = "0b0";
parameter CH0_CC_MATCH_1 = "0b0000000000";
parameter CH0_CC_MATCH_2 = "0b0000000000";
parameter CH0_CC_MATCH_3 = "0b0000000000";
parameter CH0_CC_MATCH_4 = "0b0000000000";
parameter CH0_CDR_CNT4SEL = "0b00";
parameter CH0_CDR_CNT8SEL = "0b00";
parameter CH0_CTC_BYPASS = "0b0";
parameter CH0_DCOATDCFG = "0b00";
parameter CH0_DCOATDDLY = "0b00";
parameter CH0_DCOBYPSATD = "0b0";
parameter CH0_DCOCALDIV = "0b000";
parameter CH0_DCOCTLGI = "0b000";
parameter CH0_DCODISBDAVOID = "0b0";
parameter CH0_DCOFLTDAC = "0b00";
parameter CH0_DCOFTNRG = "0b000";
parameter CH0_DCOIOSTUNE = "0b000";
parameter CH0_DCOITUNE = "0b00";
parameter CH0_DCOITUNE4LSB = "0b000";
parameter CH0_DCOIUPDNX2 = "0b0";
parameter CH0_DCONUOFLSB = "0b000";
parameter CH0_DCOSCALEI = "0b00";
parameter CH0_DCOSTARTVAL = "0b000";
parameter CH0_DCOSTEP = "0b00";
parameter CH0_DEC_BYPASS = "0b0";
parameter CH0_ENABLE_CG_ALIGN = "0b0";
parameter CH0_ENC_BYPASS = "0b0";
parameter CH0_FF_RX_F_CLK_DIS = "0b0";
parameter CH0_FF_RX_H_CLK_EN = "0b0";
parameter CH0_FF_TX_F_CLK_DIS = "0b0";
parameter CH0_FF_TX_H_CLK_EN = "0b0";
parameter CH0_GE_AN_ENABLE = "0b0";
parameter CH0_INVERT_RX = "0b0";
parameter CH0_INVERT_TX = "0b0";
parameter CH0_LDR_CORE2TX_SEL = "0b0";
parameter CH0_LDR_RX2CORE_SEL = "0b0";
parameter CH0_LEQ_OFFSET_SEL = "0b0";
parameter CH0_LEQ_OFFSET_TRIM = "0b000";
parameter CH0_LSM_DISABLE = "0b0";
parameter CH0_MATCH_2_ENABLE = "0b0";
parameter CH0_MATCH_4_ENABLE = "0b0";
parameter CH0_MIN_IPG_CNT = "0b00";
parameter CH0_PCIE_EI_EN = "0b0";
parameter CH0_PCIE_MODE = "0b0";
parameter CH0_PCS_DET_TIME_SEL = "0b00";
parameter CH0_PDEN_SEL = "0b0";
parameter CH0_PRBS_ENABLE = "0b0";
parameter CH0_PRBS_LOCK = "0b0";
parameter CH0_PRBS_SELECTION = "0b0";
parameter CH0_RATE_MODE_RX = "0b0";
parameter CH0_RATE_MODE_TX = "0b0";
parameter CH0_RCV_DCC_EN = "0b0";
parameter CH0_REG_BAND_OFFSET = "0b0000";
parameter CH0_REG_BAND_SEL = "0b000000";
parameter CH0_REG_IDAC_EN = "0b0";
parameter CH0_REG_IDAC_SEL = "0b0000000000";
parameter CH0_REQ_EN = "0b0";
parameter CH0_REQ_LVL_SET = "0b00";
parameter CH0_RIO_MODE = "0b0";
parameter CH0_RLOS_SEL = "0b0";
parameter CH0_RPWDNB = "0b0";
parameter CH0_RTERM_RX = "0b00000";
parameter CH0_RTERM_TX = "0b00000";
parameter CH0_RXIN_CM = "0b00";
parameter CH0_RXTERM_CM = "0b00";
parameter CH0_RX_DCO_CK_DIV = "0b000";
parameter CH0_RX_DIV11_SEL = "0b0";
parameter CH0_RX_GEAR_BYPASS = "0b0";
parameter CH0_RX_GEAR_MODE = "0b0";
parameter CH0_RX_LOS_CEQ = "0b00";
parameter CH0_RX_LOS_EN = "0b0";
parameter CH0_RX_LOS_HYST_EN = "0b0";
parameter CH0_RX_LOS_LVL = "0b000";
parameter CH0_RX_RATE_SEL = "0b0000";
parameter CH0_RX_SB_BYPASS = "0b0";
parameter CH0_SB_BYPASS = "0b0";
parameter CH0_SEL_SD_RX_CLK = "0b0";
parameter CH0_TDRV_DAT_SEL = "0b00";
parameter CH0_TDRV_POST_EN = "0b0";
parameter CH0_TDRV_PRE_EN = "0b0";
parameter CH0_TDRV_SLICE0_CUR = "0b000";
parameter CH0_TDRV_SLICE0_SEL = "0b00";
parameter CH0_TDRV_SLICE1_CUR = "0b000";
parameter CH0_TDRV_SLICE1_SEL = "0b00";
parameter CH0_TDRV_SLICE2_CUR = "0b00";
parameter CH0_TDRV_SLICE2_SEL = "0b00";
parameter CH0_TDRV_SLICE3_CUR = "0b00";
parameter CH0_TDRV_SLICE3_SEL = "0b00";
parameter CH0_TDRV_SLICE4_CUR = "0b00";
parameter CH0_TDRV_SLICE4_SEL = "0b00";
parameter CH0_TDRV_SLICE5_CUR = "0b00";
parameter CH0_TDRV_SLICE5_SEL = "0b00";
parameter CH0_TPWDNB = "0b0";
parameter CH0_TX_CM_SEL = "0b00";
parameter CH0_TX_DIV11_SEL = "0b0";
parameter CH0_TX_GEAR_BYPASS = "0b0";
parameter CH0_TX_GEAR_MODE = "0b0";
parameter CH0_TX_POST_SIGN = "0b0";
parameter CH0_TX_PRE_SIGN = "0b0";
parameter CH0_UC_MODE = "0b0";
parameter CH0_UDF_COMMA_A = "0b0000000000";
parameter CH0_UDF_COMMA_B = "0b0000000000";
parameter CH0_UDF_COMMA_MASK = "0b0000000000";
parameter CH0_WA_BYPASS = "0b0";
parameter CH0_WA_MODE = "0b0";
parameter CH1_AUTO_CALIB_EN = "0b0";
parameter CH1_AUTO_FACQ_EN = "0b0";
parameter CH1_BAND_THRESHOLD = "0b000000";
parameter CH1_CALIB_CK_MODE = "0b0";
parameter CH1_CC_MATCH_1 = "0b0000000000";
parameter CH1_CC_MATCH_2 = "0b0000000000";
parameter CH1_CC_MATCH_3 = "0b0000000000";
parameter CH1_CC_MATCH_4 = "0b0000000000";
parameter CH1_CDR_CNT4SEL = "0b00";
parameter CH1_CDR_CNT8SEL = "0b00";
parameter CH1_CTC_BYPASS = "0b0";
parameter CH1_DCOATDCFG = "0b00";
parameter CH1_DCOATDDLY = "0b00";
parameter CH1_DCOBYPSATD = "0b0";
parameter CH1_DCOCALDIV = "0b000";
parameter CH1_DCOCTLGI = "0b000";
parameter CH1_DCODISBDAVOID = "0b0";
parameter CH1_DCOFLTDAC = "0b00";
parameter CH1_DCOFTNRG = "0b000";
parameter CH1_DCOIOSTUNE = "0b000";
parameter CH1_DCOITUNE = "0b00";
parameter CH1_DCOITUNE4LSB = "0b000";
parameter CH1_DCOIUPDNX2 = "0b0";
parameter CH1_DCONUOFLSB = "0b000";
parameter CH1_DCOSCALEI = "0b00";
parameter CH1_DCOSTARTVAL = "0b000";
parameter CH1_DCOSTEP = "0b00";
parameter CH1_DEC_BYPASS = "0b0";
parameter CH1_ENABLE_CG_ALIGN = "0b0";
parameter CH1_ENC_BYPASS = "0b0";
parameter CH1_FF_RX_F_CLK_DIS = "0b0";
parameter CH1_FF_RX_H_CLK_EN = "0b0";
parameter CH1_FF_TX_F_CLK_DIS = "0b0";
parameter CH1_FF_TX_H_CLK_EN = "0b0";
parameter CH1_GE_AN_ENABLE = "0b0";
parameter CH1_INVERT_RX = "0b0";
parameter CH1_INVERT_TX = "0b0";
parameter CH1_LDR_CORE2TX_SEL = "0b0";
parameter CH1_LDR_RX2CORE_SEL = "0b0";
parameter CH1_LEQ_OFFSET_SEL = "0b0";
parameter CH1_LEQ_OFFSET_TRIM = "0b000";
parameter CH1_LSM_DISABLE = "0b0";
parameter CH1_MATCH_2_ENABLE = "0b0";
parameter CH1_MATCH_4_ENABLE = "0b0";
parameter CH1_MIN_IPG_CNT = "0b00";
parameter CH1_PCIE_EI_EN = "0b0";
parameter CH1_PCIE_MODE = "0b0";
parameter CH1_PCS_DET_TIME_SEL = "0b00";
parameter CH1_PDEN_SEL = "0b0";
parameter CH1_PRBS_ENABLE = "0b0";
parameter CH1_PRBS_LOCK = "0b0";
parameter CH1_PRBS_SELECTION = "0b0";
parameter CH1_RATE_MODE_RX = "0b0";
parameter CH1_RATE_MODE_TX = "0b0";
parameter CH1_RCV_DCC_EN = "0b0";
parameter CH1_REG_BAND_OFFSET = "0b0000";
parameter CH1_REG_BAND_SEL = "0b000000";
parameter CH1_REG_IDAC_EN = "0b0";
parameter CH1_REG_IDAC_SEL = "0b0000000000";
parameter CH1_REQ_EN = "0b0";
parameter CH1_REQ_LVL_SET = "0b00";
parameter CH1_RIO_MODE = "0b0";
parameter CH1_RLOS_SEL = "0b0";
parameter CH1_RPWDNB = "0b0";
parameter CH1_RTERM_RX = "0b00000";
parameter CH1_RTERM_TX = "0b00000";
parameter CH1_RXIN_CM = "0b00";
parameter CH1_RXTERM_CM = "0b00";
parameter CH1_RX_DCO_CK_DIV = "0b000";
parameter CH1_RX_DIV11_SEL = "0b0";
parameter CH1_RX_GEAR_BYPASS = "0b0";
parameter CH1_RX_GEAR_MODE = "0b0";
parameter CH1_RX_LOS_CEQ = "0b00";
parameter CH1_RX_LOS_EN = "0b0";
parameter CH1_RX_LOS_HYST_EN = "0b0";
parameter CH1_RX_LOS_LVL = "0b000";
parameter CH1_RX_RATE_SEL = "0b0000";
parameter CH1_RX_SB_BYPASS = "0b0";
parameter CH1_SB_BYPASS = "0b0";
parameter CH1_SEL_SD_RX_CLK = "0b0";
parameter CH1_TDRV_DAT_SEL = "0b00";
parameter CH1_TDRV_POST_EN = "0b0";
parameter CH1_TDRV_PRE_EN = "0b0";
parameter CH1_TDRV_SLICE0_CUR = "0b000";
parameter CH1_TDRV_SLICE0_SEL = "0b00";
parameter CH1_TDRV_SLICE1_CUR = "0b000";
parameter CH1_TDRV_SLICE1_SEL = "0b00";
parameter CH1_TDRV_SLICE2_CUR = "0b00";
parameter CH1_TDRV_SLICE2_SEL = "0b00";
parameter CH1_TDRV_SLICE3_CUR = "0b00";
parameter CH1_TDRV_SLICE3_SEL = "0b00";
parameter CH1_TDRV_SLICE4_CUR = "0b00";
parameter CH1_TDRV_SLICE4_SEL = "0b00";
parameter CH1_TDRV_SLICE5_CUR = "0b00";
parameter CH1_TDRV_SLICE5_SEL = "0b00";
parameter CH1_TPWDNB = "0b0";
parameter CH1_TX_CM_SEL = "0b00";
parameter CH1_TX_DIV11_SEL = "0b0";
parameter CH1_TX_GEAR_BYPASS = "0b0";
parameter CH1_TX_GEAR_MODE = "0b0";
parameter CH1_TX_POST_SIGN = "0b0";
parameter CH1_TX_PRE_SIGN = "0b0";
parameter CH1_UC_MODE = "0b0";
parameter CH1_UDF_COMMA_A = "0b0000000000";
parameter CH1_UDF_COMMA_B = "0b0000000000";
parameter CH1_UDF_COMMA_MASK = "0b0000000000";
parameter CH1_WA_BYPASS = "0b0";
parameter CH1_WA_MODE = "0b0";
parameter D_BITCLK_FROM_ND_EN = "0b0";
parameter D_BITCLK_LOCAL_EN = "0b0";
parameter D_BITCLK_ND_EN = "0b0";
parameter D_BUS8BIT_SEL = "0b0";
parameter D_CDR_LOL_SET = "0b00";
parameter D_CMUSETBIASI = "0b00";
parameter D_CMUSETI4CPP = "0b0000";
parameter D_CMUSETI4CPZ = "0b0000";
parameter D_CMUSETI4VCO = "0b00";
parameter D_CMUSETICP4P = "0b00";
parameter D_CMUSETICP4Z = "0b000";
parameter D_CMUSETINITVCT = "0b00";
parameter D_CMUSETISCL4VCO = "0b000";
parameter D_CMUSETP1GM = "0b000";
parameter D_CMUSETP2AGM = "0b000";
parameter D_CMUSETZGM = "0b000";
parameter D_DCO_CALIB_TIME_SEL = "0b00";
parameter D_HIGH_MARK = "0b0000";
parameter D_IB_PWDNB = "0b0";
parameter D_ISETLOS = "0b00000000";
parameter D_LOW_MARK = "0b0000";
parameter D_MACROPDB = "0b0";
parameter D_PD_ISET = "0b00";
parameter D_PLL_LOL_SET = "0b00";
parameter D_REFCK_MODE = "0b000";
parameter D_REQ_ISET = "0b000";
parameter D_RG_EN = "0b0";
parameter D_RG_SET = "0b00";
parameter D_SETICONST_AUX = "0b00";
parameter D_SETICONST_CH = "0b00";
parameter D_SETIRPOLY_AUX = "0b00";
parameter D_SETIRPOLY_CH = "0b00";
parameter D_SETPLLRC = "0b000000";
parameter D_SYNC_LOCAL_EN = "0b0";
parameter D_SYNC_ND_EN = "0b0";
parameter D_TXPLL_PWDNB = "0b0";
parameter D_TX_VCO_CK_DIV = "0b000";
parameter D_XGE_MODE = "0b0";
// These parameters don't do anything but are
// needed for compatibility with Diamond
parameter D_TX_MAX_RATE = "2.5";
parameter D_RX_MAX_RATE = "2.5";
parameter CH0_TXAMPLITUDE = "0d1300";
parameter CH1_TXAMPLITUDE = "0d1300";
parameter CH0_PROTOCOL = "8B10B";
parameter CH1_PROTOCOL = "8B10B";
parameter CH0_CDR_MAX_RATE = "2.5";
parameter CH1_CDR_MAX_RATE = "2.5";
parameter CH0_TXDEPRE = "DISABLED";
parameter CH1_TXDEPRE = "DISABLED";
parameter CH0_TXDEPOST = "DISABLED";
parameter CH1_TXDEPOST = "DISABLED";
endmodule
(* blackbox *)
module EXTREFB (
input REFCLKP, REFCLKN,
output REFCLKO
);
parameter REFCK_PWDNB = "0b0";
parameter REFCK_RTERM = "0b0";
parameter REFCK_DCBIAS_EN = "0b0";
endmodule
(* blackbox *)
module PCSCLKDIV (
input CLKI, RST, SEL2, SEL1, SEL0,
output CDIV1, CDIVX
);
parameter GSR = "DISABLED";
endmodule
// Note: this module is not marked keep as we want it swept away in synth (sim use only)
(* blackbox *)
module PUR (
input PUR
);
parameter RST_PULSE = 1;
endmodule
(* blackbox, keep *)
module GSR (
input GSR
);
endmodule
(* blackbox, keep *)
module SGSR (
input GSR, CLK
);
endmodule
(* blackbox *)
module PDPW16KD (
input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
);
parameter DATA_WIDTH_W = 36;
parameter DATA_WIDTH_R = 36;
parameter GSR = "ENABLED";
parameter REGMODE = "NOREG";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CSDECODE_W = "0b000";
parameter CSDECODE_R = "0b000";
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_DATA = "STATIC";
parameter CLKWMUX = "CLKW";
parameter CLKRMUX = "CLKR";
endmodule

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@ -1,40 +0,0 @@
// Diamond flip-flops
module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
// TODO: Diamond latches
// module FL1P3AY(); endmodule
// module FL1P3AZ(); endmodule
// module FL1P3BX(); endmodule
// module FL1P3DX(); endmodule
// module FL1P3IY(); endmodule
// module FL1P3JY(); endmodule
// module FL1S3AX(); endmodule
// module FL1S3AY(); endmodule
// Diamond I/O registers
module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
// TODO: Diamond I/O latches
// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
// module IFS1S1J(input CD, D, SCLK, output Q); endmodule

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// Diamond I/O buffers
module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
module ILVDS(input A, AN, output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule

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@ -1,191 +0,0 @@
module \$_DFF_N_ (input D, C, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFF_P_ (input D, C, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFFE_NN_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFFE_PN_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFFE_NP_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFFE_PP_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
else
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
`include "cells_ff.vh"
`include "cells_io.vh"
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
.A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
end else
if (WIDTH == 2) begin
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
.A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));
end else
if (WIDTH == 3) begin
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
.A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
`ifndef NO_PFUMUX
end else
if (WIDTH == 5) begin
wire f0, f1;
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
end else
if (WIDTH == 6) begin
wire f0, f1, f2, f3, g0, g1;
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
end else
if (WIDTH == 7) begin
wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
`endif
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

810
resources/netlist/resources/kernel/share/ecp5/cells_sim.v
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@ -1,810 +0,0 @@
// ---------------------------------------
(* abc9_lut=1, lib_whitebox *)
module LUT4(input A, B, C, D, output Z);
parameter [15:0] INIT = 16'h0000;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
specify
(A => Z) = 141;
(B => Z) = 275;
(C => Z) = 379;
(D => Z) = 379;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 5-input LUTs and is not intended to be instantiated
// LUT5 = 2x LUT4 + PFUMX
(* abc9_lut=2 *)
module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
specify
(M0 => Z) = 151;
(D => Z) = 239;
(C => Z) = 373;
(B => Z) = 477;
(A => Z) = 477;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// of 6-input LUTs and is not intended to be instantiated
// LUT6 = 2x LUT5 + MUX2
(* abc9_lut=4 *)
module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
specify
(M1 => Z) = 148;
(M0 => Z) = 292;
(D => Z) = 380;
(C => Z) = 514;
(B => Z) = 618;
(A => Z) = 618;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// of 7-input LUTs and is not intended to be instantiated
// LUT7 = 2x LUT6 + MUX2
(* abc9_lut=8 *)
module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
specify
(M2 => Z) = 148;
(M1 => Z) = 289;
(M0 => Z) = 433;
(D => Z) = 521;
(C => Z) = 655;
(B => Z) = 759;
(A => Z) = 759;
endspecify
endmodule
// ---------------------------------------
(* abc9_box, lib_whitebox *)
module L6MUX21 (input D0, D1, SD, output Z);
assign Z = SD ? D1 : D0;
specify
(D0 => Z) = 140;
(D1 => Z) = 141;
(SD => Z) = 148;
endspecify
endmodule
// ---------------------------------------
(* abc9_box, lib_whitebox *)
module CCU2C(
(* abc9_carry *)
input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc9_carry *)
output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
parameter INJECT1_1 = "YES";
// First half
wire LUT4_0, LUT2_0;
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
assign S0 = LUT4_0 ^ gated_cin_0;
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
// Second half
wire LUT4_1, LUT2_1;
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
assign S1 = LUT4_1 ^ gated_cin_1;
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
specify
(A0 => S0) = 379;
(B0 => S0) = 379;
(C0 => S0) = 275;
(D0 => S0) = 141;
(CIN => S0) = 257;
(A0 => S1) = 630;
(B0 => S1) = 630;
(C0 => S1) = 526;
(D0 => S1) = 392;
(A1 => S1) = 379;
(B1 => S1) = 379;
(C1 => S1) = 275;
(D1 => S1) = 141;
(CIN => S1) = 273;
(A0 => COUT) = 516;
(B0 => COUT) = 516;
(C0 => COUT) = 412;
(D0 => COUT) = 278;
(A1 => COUT) = 516;
(B1 => COUT) = 516;
(C1 => COUT) = 412;
(D1 => COUT) = 278;
(CIN => COUT) = 43;
endspecify
endmodule
// ---------------------------------------
module TRELLIS_RAM16X2 (
input DI0, DI1,
input WAD0, WAD1, WAD2, WAD3,
input WRE, WCK,
input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000;
reg [1:0] mem[15:0];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
reg muxwre;
always @(*)
case (WREMUX)
"1": muxwre = 1'b1;
"0": muxwre = 1'b0;
"INV": muxwre = ~WRE;
default: muxwre = WRE;
endcase
always @(posedge muxwck)
if (muxwre)
mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
endmodule
// ---------------------------------------
(* abc9_box, lib_whitebox *)
module PFUMX (input ALUT, BLUT, C0, output Z);
assign Z = C0 ? ALUT : BLUT;
specify
(ALUT => Z) = 98;
(BLUT => Z) = 98;
(C0 => Z) = 151;
endspecify
endmodule
// ---------------------------------------
(* abc9_box, lib_whitebox *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
reg [3:0] mem[15:0];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= INITVAL[4*i +: 4];
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
reg muxwre;
always @(*)
case (WREMUX)
"1": muxwre = 1'b1;
"0": muxwre = 1'b0;
"INV": muxwre = ~WRE;
default: muxwre = WRE;
endcase
always @(posedge muxwck)
if (muxwre)
mem[WAD] <= DI;
assign DO = mem[RAD];
specify
// TODO
(RAD *> DO) = 0;
endspecify
endmodule
// ---------------------------------------
(* abc9_box, lib_whitebox *)
module DPR16X4C (
input [3:0] DI,
input WCK, WRE,
input [3:0] RAD,
input [3:0] WAD,
output [3:0] DO
);
// For legacy Lattice compatibility, INITIVAL is a hex
// string rather than a numeric parameter
parameter INITVAL = "0x0000000000000000";
function [63:0] convert_initval;
input [143:0] hex_initval;
reg done;
reg [63:0] temp;
reg [7:0] char;
integer i;
begin
done = 1'b0;
temp = 0;
for (i = 0; i < 16; i = i + 1) begin
if (!done) begin
char = hex_initval[8*i +: 8];
if (char == "x") begin
done = 1'b1;
end else begin
if (char >= "0" && char <= "9")
temp[4*i +: 4] = char - "0";
else if (char >= "A" && char <= "F")
temp[4*i +: 4] = 10 + char - "A";
else if (char >= "a" && char <= "f")
temp[4*i +: 4] = 10 + char - "a";
end
end
end
convert_initval = temp;
end
endfunction
localparam conv_initval = convert_initval(INITVAL);
reg [3:0] ram[0:15];
integer i;
initial begin
for (i = 0; i < 15; i = i + 1) begin
ram[i] <= conv_initval[4*i +: 4];
end
end
always @(posedge WCK)
if (WRE)
ram[WAD] <= DI;
assign DO = ram[RAD];
specify
// TODO
(RAD *> DO) = 0;
endspecify
endmodule
// ---------------------------------------
(* lib_whitebox *)
module LUT2(input A, B, output Z);
parameter [3:0] INIT = 4'h0;
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
assign Z = A ? s1[1] : s1[0];
endmodule
// ---------------------------------------
`ifdef YOSYS
(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
`endif
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
wire muxce;
generate
case (CEMUX)
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval;
generate
if (LSRMODE == "PRLD")
assign srval = M;
else
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
endgenerate
initial Q = srval;
generate
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
endgenerate
specify
$setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
$setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
$setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
$setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
$setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
$setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
`ifndef YOSYS
if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
`else
if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
endspecify
endmodule
// ---------------------------------------
(* keep *)
module TRELLIS_IO(
inout B,
input I,
input T,
output O
);
parameter DIR = "INPUT";
reg T_pd;
always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
generate
if (DIR == "INPUT") begin
assign B = 1'bz;
assign O = B;
end else if (DIR == "OUTPUT") begin
assign B = T_pd ? 1'bz : I;
assign O = 1'bx;
end else if (DIR == "BIDIR") begin
assign B = T_pd ? 1'bz : I;
assign O = B;
end else begin
ERROR_UNKNOWN_IO_MODE error();
end
endgenerate
endmodule
// ---------------------------------------
module INV(input A, output Z);
assign Z = !A;
endmodule
// ---------------------------------------
module TRELLIS_SLICE(
input A0, B0, C0, D0,
input A1, B1, C1, D1,
input M0, M1,
input FCI, FXA, FXB,
input CLK, LSR, CE,
input DI0, DI1,
input WD0, WD1,
input WAD0, WAD1, WAD2, WAD3,
input WRE, WCK,
output F0, Q0,
output F1, Q1,
output FCO, OFX0, OFX1,
output WDO0, WDO1, WDO2, WDO3,
output WADO0, WADO1, WADO2, WADO3
);
parameter MODE = "LOGIC";
parameter GSR = "ENABLED";
parameter SRMODE = "LSR_OVER_CE";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter LUT0_INITVAL = 16'h0000;
parameter LUT1_INITVAL = 16'h0000;
parameter REG0_SD = "0";
parameter REG1_SD = "0";
parameter REG0_REGSET = "RESET";
parameter REG1_REGSET = "RESET";
parameter REG0_LSRMODE = "LSR";
parameter REG1_LSRMODE = "LSR";
parameter [127:0] CCU2_INJECT1_0 = "NO";
parameter [127:0] CCU2_INJECT1_1 = "NO";
parameter WREMUX = "WRE";
parameter WCKMUX = "WCK";
parameter A0MUX = "A0";
parameter A1MUX = "A1";
parameter B0MUX = "B0";
parameter B1MUX = "B1";
parameter C0MUX = "C0";
parameter C1MUX = "C1";
parameter D0MUX = "D0";
parameter D1MUX = "D1";
wire A0m, B0m, C0m, D0m;
wire A1m, B1m, C1m, D1m;
generate
if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
endgenerate
function [15:0] permute_initval;
input [15:0] initval;
integer i;
begin
for (i = 0; i < 16; i = i + 1) begin
permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
end
end
endfunction
generate
if (MODE == "LOGIC") begin
// LUTs
LUT4 #(
.INIT(LUT0_INITVAL)
) lut4_0 (
.A(A0m), .B(B0m), .C(C0m), .D(D0m),
.Z(F0)
);
LUT4 #(
.INIT(LUT1_INITVAL)
) lut4_1 (
.A(A1m), .B(B1m), .C(C1m), .D(D1m),
.Z(F1)
);
// LUT expansion muxes
PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
end else if (MODE == "CCU2") begin
CCU2C #(
.INIT0(LUT0_INITVAL),
.INIT1(LUT1_INITVAL),
.INJECT1_0(CCU2_INJECT1_0),
.INJECT1_1(CCU2_INJECT1_1)
) ccu2c_i (
.CIN(FCI),
.A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
.A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
.S0(F0), .S1(F1),
.COUT(FCO)
);
end else if (MODE == "RAMW") begin
assign WDO0 = C1m;
assign WDO1 = A1m;
assign WDO2 = D1m;
assign WDO3 = B1m;
assign WADO0 = D0m;
assign WADO1 = B0m;
assign WADO2 = C0m;
assign WADO3 = A0m;
end else if (MODE == "DPRAM") begin
TRELLIS_RAM16X2 #(
.INITVAL_0(permute_initval(LUT0_INITVAL)),
.INITVAL_1(permute_initval(LUT1_INITVAL)),
.WREMUX(WREMUX)
) ram_i (
.DI0(WD0), .DI1(WD1),
.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
.WRE(WRE), .WCK(WCK),
.RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
.DO0(F0), .DO1(F1)
);
// TODO: confirm RAD and INITVAL ordering
// DPRAM mode contract?
`ifdef FORMAL
always @(*) begin
assert(A0m==A1m);
assert(B0m==B1m);
assert(C0m==C1m);
assert(D0m==D1m);
end
`endif
end else begin
ERROR_UNKNOWN_SLICE_MODE error();
end
endgenerate
// FF input selection muxes
wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
// Flipflops
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG0_REGSET),
.LSRMODE(REG0_LSRMODE)
) ff_0 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi0), .M(M0),
.Q(Q0)
);
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG1_REGSET),
.LSRMODE(REG1_LSRMODE)
) ff_1 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi1), .M(M1),
.Q(Q1)
);
endmodule
(* blackbox *)
module DP16KD(
input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
input CEA, OCEA, CLKA, WEA, RSTA,
input CSA2, CSA1, CSA0,
output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
input CEB, OCEB, CLKB, WEB, RSTB,
input CSB2, CSB1, CSB0,
output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
);
parameter DATA_WIDTH_A = 18;
parameter DATA_WIDTH_B = 18;
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CSDECODE_A = "0b000";
parameter CSDECODE_B = "0b000";
parameter WRITEMODE_A = "NORMAL";
parameter WRITEMODE_B = "NORMAL";
parameter DIA17MUX = "DIA17";
parameter DIA16MUX = "DIA16";
parameter DIA15MUX = "DIA15";
parameter DIA14MUX = "DIA14";
parameter DIA13MUX = "DIA13";
parameter DIA12MUX = "DIA12";
parameter DIA11MUX = "DIA11";
parameter DIA10MUX = "DIA10";
parameter DIA9MUX = "DIA9";
parameter DIA8MUX = "DIA8";
parameter DIA7MUX = "DIA7";
parameter DIA6MUX = "DIA6";
parameter DIA5MUX = "DIA5";
parameter DIA4MUX = "DIA4";
parameter DIA3MUX = "DIA3";
parameter DIA2MUX = "DIA2";
parameter DIA1MUX = "DIA1";
parameter DIA0MUX = "DIA0";
parameter ADA13MUX = "ADA13";
parameter ADA12MUX = "ADA12";
parameter ADA11MUX = "ADA11";
parameter ADA10MUX = "ADA10";
parameter ADA9MUX = "ADA9";
parameter ADA8MUX = "ADA8";
parameter ADA7MUX = "ADA7";
parameter ADA6MUX = "ADA6";
parameter ADA5MUX = "ADA5";
parameter ADA4MUX = "ADA4";
parameter ADA3MUX = "ADA3";
parameter ADA2MUX = "ADA2";
parameter ADA1MUX = "ADA1";
parameter ADA0MUX = "ADA0";
parameter CEAMUX = "CEA";
parameter OCEAMUX = "OCEA";
parameter CLKAMUX = "CLKA";
parameter WEAMUX = "WEA";
parameter RSTAMUX = "RSTA";
parameter CSA2MUX = "CSA2";
parameter CSA1MUX = "CSA1";
parameter CSA0MUX = "CSA0";
parameter DOA17MUX = "DOA17";
parameter DOA16MUX = "DOA16";
parameter DOA15MUX = "DOA15";
parameter DOA14MUX = "DOA14";
parameter DOA13MUX = "DOA13";
parameter DOA12MUX = "DOA12";
parameter DOA11MUX = "DOA11";
parameter DOA10MUX = "DOA10";
parameter DOA9MUX = "DOA9";
parameter DOA8MUX = "DOA8";
parameter DOA7MUX = "DOA7";
parameter DOA6MUX = "DOA6";
parameter DOA5MUX = "DOA5";
parameter DOA4MUX = "DOA4";
parameter DOA3MUX = "DOA3";
parameter DOA2MUX = "DOA2";
parameter DOA1MUX = "DOA1";
parameter DOA0MUX = "DOA0";
parameter DIB17MUX = "DIB17";
parameter DIB16MUX = "DIB16";
parameter DIB15MUX = "DIB15";
parameter DIB14MUX = "DIB14";
parameter DIB13MUX = "DIB13";
parameter DIB12MUX = "DIB12";
parameter DIB11MUX = "DIB11";
parameter DIB10MUX = "DIB10";
parameter DIB9MUX = "DIB9";
parameter DIB8MUX = "DIB8";
parameter DIB7MUX = "DIB7";
parameter DIB6MUX = "DIB6";
parameter DIB5MUX = "DIB5";
parameter DIB4MUX = "DIB4";
parameter DIB3MUX = "DIB3";
parameter DIB2MUX = "DIB2";
parameter DIB1MUX = "DIB1";
parameter DIB0MUX = "DIB0";
parameter ADB13MUX = "ADB13";
parameter ADB12MUX = "ADB12";
parameter ADB11MUX = "ADB11";
parameter ADB10MUX = "ADB10";
parameter ADB9MUX = "ADB9";
parameter ADB8MUX = "ADB8";
parameter ADB7MUX = "ADB7";
parameter ADB6MUX = "ADB6";
parameter ADB5MUX = "ADB5";
parameter ADB4MUX = "ADB4";
parameter ADB3MUX = "ADB3";
parameter ADB2MUX = "ADB2";
parameter ADB1MUX = "ADB1";
parameter ADB0MUX = "ADB0";
parameter CEBMUX = "CEB";
parameter OCEBMUX = "OCEB";
parameter CLKBMUX = "CLKB";
parameter WEBMUX = "WEB";
parameter RSTBMUX = "RSTB";
parameter CSB2MUX = "CSB2";
parameter CSB1MUX = "CSB1";
parameter CSB0MUX = "CSB0";
parameter DOB17MUX = "DOB17";
parameter DOB16MUX = "DOB16";
parameter DOB15MUX = "DOB15";
parameter DOB14MUX = "DOB14";
parameter DOB13MUX = "DOB13";
parameter DOB12MUX = "DOB12";
parameter DOB11MUX = "DOB11";
parameter DOB10MUX = "DOB10";
parameter DOB9MUX = "DOB9";
parameter DOB8MUX = "DOB8";
parameter DOB7MUX = "DOB7";
parameter DOB6MUX = "DOB6";
parameter DOB5MUX = "DOB5";
parameter DOB4MUX = "DOB4";
parameter DOB3MUX = "DOB3";
parameter DOB2MUX = "DOB2";
parameter DOB1MUX = "DOB1";
parameter DOB0MUX = "DOB0";
parameter WID = 0;
parameter GSR = "ENABLED";
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_DATA = "STATIC";
endmodule
`ifndef NO_INCLUDES
`include "cells_ff.vh"
`include "cells_io.vh"
`endif

17
resources/netlist/resources/kernel/share/ecp5/dsp_map.v
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@ -1,17 +0,0 @@
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter Y_WIDTH = 36;
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
MULT18X18D _TECHMAP_REPLACE_ (
.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
);
endmodule

11
resources/netlist/resources/kernel/share/ecp5/latches_map.v
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@ -1,11 +0,0 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

12
resources/netlist/resources/kernel/share/ecp5/lutrams.txt
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@ -1,12 +0,0 @@
ram distributed $__TRELLIS_DPR16X4_ {
abits 4;
width 4;
cost 4;
init any;
prune_rom;
port sw "W" {
clock anyedge;
}
port ar "R" {
}
}

30
resources/netlist/resources/kernel/share/ecp5/lutrams_map.v
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@ -1,30 +0,0 @@
module $__TRELLIS_DPR16X4_(...);
parameter INIT = 64'bx;
parameter PORT_W_CLK_POL = 1;
input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input [3:0] PORT_W_WR_DATA;
input PORT_W_WR_EN;
input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
TRELLIS_DPR16X4 #(
.INITVAL(INIT),
.WCKMUX(WCKMUX),
.WREMUX("WRE")
) _TECHMAP_REPLACE_ (
.RAD(PORT_R_ADDR),
.DO(PORT_R_RD_DATA),
.WAD(PORT_W_ADDR),
.DI(PORT_W_WR_DATA),
.WCK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endmodule

88
resources/netlist/resources/kernel/share/efinix/arith_map.v
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@ -1,88 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cin (
.I0(CI),
.I1(1'b1),
.CI(1'b0),
.CO(CIx)
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_i (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

19
resources/netlist/resources/kernel/share/efinix/brams.txt
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@ -1,19 +0,0 @@
ram block $__EFINIX_5K_ {
abits 12;
widths 1 2 5 10 20 per_port;
cost 32;
init no_undef;
port sr "R" {
clock anyedge;
rden;
}
port sw "W" {
clock anyedge;
option "WRITE_MODE" "READ_FIRST" {
wrtrans "R" old;
}
option "WRITE_MODE" "WRITE_FIRST" {
wrtrans "R" new;
}
}
}

149
resources/netlist/resources/kernel/share/efinix/brams_map.v
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@ -1,149 +0,0 @@
module $__EFINIX_5K_ (...);
parameter INIT = 0;
parameter OPTION_WRITE_MODE = "READ_FIRST";
parameter PORT_R_WIDTH = 20;
parameter PORT_R_CLK_POL = 1;
parameter PORT_W_WIDTH = 20;
parameter PORT_W_CLK_POL = 1;
input PORT_R_CLK;
input PORT_R_RD_EN;
input [11:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
input PORT_W_CLK;
input PORT_W_WR_EN;
input [11:0] PORT_W_ADDR;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
localparam IS_5BIT = PORT_R_WIDTH >= 5 && PORT_W_WIDTH >= 5;
localparam RADDR_WIDTH =
PORT_R_WIDTH == 1 ? 12 :
PORT_R_WIDTH == 2 ? 11 :
PORT_R_WIDTH == 5 ? 10 :
PORT_R_WIDTH == 10 ? 9 :
8;
localparam WADDR_WIDTH =
PORT_W_WIDTH == 1 ? 12 :
PORT_W_WIDTH == 2 ? 11 :
PORT_W_WIDTH == 5 ? 10 :
PORT_W_WIDTH == 10 ? 9 :
8;
localparam READ_WIDTH =
PORT_R_WIDTH == 1 ? 1 :
PORT_R_WIDTH == 2 ? 2 :
PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
(IS_5BIT ? 20 : 16);
localparam WRITE_WIDTH =
PORT_W_WIDTH == 1 ? 1 :
PORT_W_WIDTH == 2 ? 2 :
PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
PORT_W_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
(IS_5BIT ? 20 : 16);
wire [RADDR_WIDTH-1:0] RADDR = PORT_R_ADDR[11:12-RADDR_WIDTH];
wire [WADDR_WIDTH-1:0] WADDR = PORT_W_ADDR[11:12-WADDR_WIDTH];
wire [WRITE_WIDTH-1:0] WDATA;
wire [READ_WIDTH-1:0] RDATA;
generate
case (WRITE_WIDTH)
1: assign WDATA = PORT_W_WR_DATA;
2: assign WDATA = PORT_W_WR_DATA;
4: assign WDATA = PORT_W_WR_DATA[3:0];
5: assign WDATA = PORT_W_WR_DATA;
8: assign WDATA = {
PORT_W_WR_DATA[8:5],
PORT_W_WR_DATA[3:0]
};
10: assign WDATA = PORT_W_WR_DATA;
16: assign WDATA = {
PORT_W_WR_DATA[18:15],
PORT_W_WR_DATA[13:10],
PORT_W_WR_DATA[8:5],
PORT_W_WR_DATA[3:0]
};
20: assign WDATA = PORT_W_WR_DATA;
endcase
case (READ_WIDTH)
1: assign PORT_R_RD_DATA = RDATA;
2: assign PORT_R_RD_DATA = RDATA;
4: assign PORT_R_RD_DATA[3:0] = RDATA;
5: assign PORT_R_RD_DATA = RDATA;
8: assign {
PORT_R_RD_DATA[8:5],
PORT_R_RD_DATA[3:0]
} = RDATA;
10: assign PORT_R_RD_DATA = RDATA;
16: assign {
PORT_R_RD_DATA[18:15],
PORT_R_RD_DATA[13:10],
PORT_R_RD_DATA[8:5],
PORT_R_RD_DATA[3:0]
} = RDATA;
20: assign PORT_R_RD_DATA = RDATA;
endcase
endgenerate
function [255:0] init_slice;
input integer idx;
integer i;
if (IS_5BIT)
init_slice = INIT[idx * 256 +: 256];
else if (idx > 16)
init_slice = 0;
else
for (i = 0; i < 64; i = i + 1)
init_slice[i*4+:4] = INIT[(idx * 64 + i) * 5+:4];
endfunction
EFX_RAM_5K #(
.READ_WIDTH(READ_WIDTH),
.WRITE_WIDTH(WRITE_WIDTH),
.OUTPUT_REG(1'b0),
.RCLK_POLARITY(PORT_R_CLK_POL),
.RE_POLARITY(1'b1),
.WCLK_POLARITY(PORT_W_CLK_POL),
.WE_POLARITY(1'b1),
.WCLKE_POLARITY(1'b1),
.WRITE_MODE(OPTION_WRITE_MODE),
.INIT_0(init_slice('h00)),
.INIT_1(init_slice('h01)),
.INIT_2(init_slice('h02)),
.INIT_3(init_slice('h03)),
.INIT_4(init_slice('h04)),
.INIT_5(init_slice('h05)),
.INIT_6(init_slice('h06)),
.INIT_7(init_slice('h07)),
.INIT_8(init_slice('h08)),
.INIT_9(init_slice('h09)),
.INIT_A(init_slice('h0a)),
.INIT_B(init_slice('h0b)),
.INIT_C(init_slice('h0c)),
.INIT_D(init_slice('h0d)),
.INIT_E(init_slice('h0e)),
.INIT_F(init_slice('h0f)),
.INIT_10(init_slice('h10)),
.INIT_11(init_slice('h11)),
.INIT_12(init_slice('h12)),
.INIT_13(init_slice('h13)),
) _TECHMAP_REPLACE_ (
.WDATA(WDATA),
.WADDR(WADDR),
.WE(PORT_W_WR_EN),
.WCLK(PORT_W_CLK),
.WCLKE(1'b1),
.RDATA(RDATA),
.RADDR(RADDR),
.RE(PORT_R_RD_EN),
.RCLK(PORT_R_CLK)
);
endmodule

96
resources/netlist/resources/kernel/share/efinix/cells_map.v
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@ -1,96 +0,0 @@
(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b0),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b1)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *)
module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b1),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b1)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *)
module \$_SDFFCE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b1),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b0)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 2) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 3) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
end else
if (WIDTH == 4) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

179
resources/netlist/resources/kernel/share/efinix/cells_sim.v
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@ -1,179 +0,0 @@
module EFX_LUT4(
output O,
input I0,
input I1,
input I2,
input I3
);
parameter LUTMASK = 16'h0000;
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
output O,
output CO,
input I0,
input I1,
input CI
);
parameter I0_POLARITY = 1;
parameter I1_POLARITY = 1;
wire i0;
wire i1;
assign i0 = I0_POLARITY ? I0 : ~I0;
assign i1 = I1_POLARITY ? I1 : ~I1;
assign {CO, O} = i0 + i1 + CI;
endmodule
module EFX_FF(
output reg Q,
input D,
input CE,
(* clkbuf_sink *)
input CLK,
input SR
);
parameter CLK_POLARITY = 1;
parameter CE_POLARITY = 1;
parameter SR_POLARITY = 1;
parameter SR_SYNC = 0;
parameter SR_VALUE = 0;
parameter SR_SYNC_PRIORITY = 0;
parameter D_POLARITY = 1;
wire clk;
wire ce;
wire sr;
wire d;
wire prio;
wire sync;
wire async;
assign clk = CLK_POLARITY ? CLK : ~CLK;
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
initial Q = 1'b0;
generate
if (SR_SYNC == 1)
begin
if (SR_SYNC_PRIORITY == 1)
begin
always @(posedge clk)
if (sr)
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
else
begin
always @(posedge clk)
if (ce)
begin
if (sr)
Q <= SR_VALUE;
else
Q <= d;
end
end
end
else
begin
always @(posedge clk or posedge sr)
if (sr)
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
endgenerate
endmodule
module EFX_GBUFCE(
input CE,
input I,
(* clkbuf_driver *)
output O
);
parameter CE_POLARITY = 1'b1;
wire ce;
assign ce = CE_POLARITY ? CE : ~CE;
assign O = I & ce;
endmodule
module EFX_RAM_5K(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
(* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
(* clkbuf_sink *)
input RCLK
);
parameter READ_WIDTH = 20;
parameter WRITE_WIDTH = 20;
parameter OUTPUT_REG = 1'b0;
parameter RCLK_POLARITY = 1'b1;
parameter RE_POLARITY = 1'b1;
parameter WCLK_POLARITY = 1'b1;
parameter WE_POLARITY = 1'b1;
parameter WCLKE_POLARITY = 1'b1;
parameter WRITE_MODE = "READ_FIRST";
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
localparam READ_ADDR_WIDTH =
(READ_WIDTH == 16) ? 8 : // 256x16
(READ_WIDTH == 8) ? 9 : // 512x8
(READ_WIDTH == 4) ? 10 : // 1024x4
(READ_WIDTH == 2) ? 11 : // 2048x2
(READ_WIDTH == 1) ? 12 : // 4096x1
(READ_WIDTH == 20) ? 8 : // 256x20
(READ_WIDTH == 10) ? 9 : // 512x10
(READ_WIDTH == 5) ? 10 : -1; // 1024x5
localparam WRITE_ADDR_WIDTH =
(WRITE_WIDTH == 16) ? 8 : // 256x16
(WRITE_WIDTH == 8) ? 9 : // 512x8
(WRITE_WIDTH == 4) ? 10 : // 1024x4
(WRITE_WIDTH == 2) ? 11 : // 2048x2
(WRITE_WIDTH == 1) ? 12 : // 4096x1
(WRITE_WIDTH == 20) ? 8 : // 256x20
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
endmodule

3
resources/netlist/resources/kernel/share/efinix/gbuf_map.v
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@ -1,3 +0,0 @@
module \$__EFX_GBUF (input I, output O);
EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));
endmodule

87
resources/netlist/resources/kernel/share/gate2lut.v
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@ -1,87 +0,0 @@
(* techmap_celltype = "$_NOT_" *)
module _90_lut_not (A, Y);
input A;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b01)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_OR_" *)
module _90_lut_or (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_AND_" *)
module _90_lut_and (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1000)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_XOR_" *)
module _90_lut_xor (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b0110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_MUX_" *)
module _90_lut_mux (A, B, S, Y);
input A, B, S;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {S, B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
// A 1010 1010
// B 1100 1100
// S 1111 0000
.LUT(8'b 1100_1010)
) lut (
.A(AA),
.Y(Y)
);
endmodule

69
resources/netlist/resources/kernel/share/gatemate/arith_map.v
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@ -1,69 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule

80
resources/netlist/resources/kernel/share/gatemate/brams.txt
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@ -1,80 +0,0 @@
ram block $__CC_BRAM_TDP_ {
option "MODE" "20K" {
abits 14;
widths 1 2 5 10 20 per_port;
cost 129;
}
option "MODE" "40K" {
abits 15;
widths 1 2 5 10 20 40 per_port;
cost 257;
}
option "MODE" "CASCADE" {
abits 16;
# hack to enforce same INIT layout as in the other modes
widths 1 2 5 per_port;
cost 513;
}
byte 1;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
option "MODE" "20K" {
width mix;
}
option "MODE" "40K" {
width mix;
}
option "MODE" "CASCADE" {
width mix 1;
}
portoption "WR_MODE" "NO_CHANGE" {
rdwr no_change;
}
portoption "WR_MODE" "WRITE_THROUGH" {
rdwr new;
wrtrans all new;
}
wrbe_separate;
optional_rw;
}
}
ram block $__CC_BRAM_SDP_ {
option "MODE" "20K" {
abits 14;
widths 1 2 5 10 20 40 per_port;
cost 129;
}
option "MODE" "40K" {
abits 15;
widths 1 2 5 10 20 40 80 per_port;
cost 257;
}
byte 1;
init no_undef;
port sr "R" {
option "MODE" "20K" {
width 40;
}
option "MODE" "40K" {
width 80;
}
clock anyedge;
clken;
optional;
}
port sw "W" {
option "MODE" "20K" {
width 40;
}
option "MODE" "40K" {
width 80;
}
clock anyedge;
clken;
wrbe_separate;
optional;
}
}

64
resources/netlist/resources/kernel/share/gatemate/brams_init_20.vh
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@ -1,64 +0,0 @@
.INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),

260
resources/netlist/resources/kernel/share/gatemate/brams_init_40.vh
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@ -1,260 +0,0 @@
`ifdef INIT_LOWER
.INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_40(permute_init(INIT[ 64*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_41(permute_init(INIT[ 65*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_42(permute_init(INIT[ 66*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_43(permute_init(INIT[ 67*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_44(permute_init(INIT[ 68*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_45(permute_init(INIT[ 69*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_46(permute_init(INIT[ 70*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_47(permute_init(INIT[ 71*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_48(permute_init(INIT[ 72*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_49(permute_init(INIT[ 73*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4A(permute_init(INIT[ 74*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4B(permute_init(INIT[ 75*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4C(permute_init(INIT[ 76*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4D(permute_init(INIT[ 77*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4E(permute_init(INIT[ 78*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4F(permute_init(INIT[ 79*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_50(permute_init(INIT[ 80*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_51(permute_init(INIT[ 81*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_52(permute_init(INIT[ 82*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_53(permute_init(INIT[ 83*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_54(permute_init(INIT[ 84*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_55(permute_init(INIT[ 85*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_56(permute_init(INIT[ 86*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_57(permute_init(INIT[ 87*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_58(permute_init(INIT[ 88*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_59(permute_init(INIT[ 89*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5A(permute_init(INIT[ 90*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5B(permute_init(INIT[ 91*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5C(permute_init(INIT[ 92*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5D(permute_init(INIT[ 93*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5E(permute_init(INIT[ 94*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5F(permute_init(INIT[ 95*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_60(permute_init(INIT[ 96*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_61(permute_init(INIT[ 97*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_62(permute_init(INIT[ 98*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_63(permute_init(INIT[ 99*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_64(permute_init(INIT[100*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_65(permute_init(INIT[101*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_66(permute_init(INIT[102*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_67(permute_init(INIT[103*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_68(permute_init(INIT[104*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_69(permute_init(INIT[105*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6A(permute_init(INIT[106*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6B(permute_init(INIT[107*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6C(permute_init(INIT[108*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6D(permute_init(INIT[109*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6E(permute_init(INIT[110*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6F(permute_init(INIT[111*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_70(permute_init(INIT[112*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_71(permute_init(INIT[113*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_72(permute_init(INIT[114*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_73(permute_init(INIT[115*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_74(permute_init(INIT[116*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_75(permute_init(INIT[117*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_76(permute_init(INIT[118*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_77(permute_init(INIT[119*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_78(permute_init(INIT[120*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_79(permute_init(INIT[121*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7A(permute_init(INIT[122*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7B(permute_init(INIT[123*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7C(permute_init(INIT[124*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7D(permute_init(INIT[125*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7E(permute_init(INIT[126*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7F(permute_init(INIT[127*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
`endif
`ifdef INIT_UPPER
.INIT_00(permute_init(INIT[128*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_01(permute_init(INIT[129*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_02(permute_init(INIT[130*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_03(permute_init(INIT[131*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_04(permute_init(INIT[132*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_05(permute_init(INIT[133*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_06(permute_init(INIT[134*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_07(permute_init(INIT[135*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_08(permute_init(INIT[136*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_09(permute_init(INIT[137*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0A(permute_init(INIT[138*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0B(permute_init(INIT[139*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0C(permute_init(INIT[140*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0D(permute_init(INIT[141*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0E(permute_init(INIT[142*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0F(permute_init(INIT[143*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_10(permute_init(INIT[144*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_11(permute_init(INIT[145*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_12(permute_init(INIT[146*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_13(permute_init(INIT[147*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_14(permute_init(INIT[148*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_15(permute_init(INIT[149*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_16(permute_init(INIT[150*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_17(permute_init(INIT[151*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_18(permute_init(INIT[152*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_19(permute_init(INIT[153*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1A(permute_init(INIT[154*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1B(permute_init(INIT[155*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1C(permute_init(INIT[156*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1D(permute_init(INIT[157*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1E(permute_init(INIT[158*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1F(permute_init(INIT[159*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_20(permute_init(INIT[160*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_21(permute_init(INIT[161*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_22(permute_init(INIT[162*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_23(permute_init(INIT[163*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_24(permute_init(INIT[164*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_25(permute_init(INIT[165*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_26(permute_init(INIT[166*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_27(permute_init(INIT[167*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_28(permute_init(INIT[168*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_29(permute_init(INIT[169*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2A(permute_init(INIT[170*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2B(permute_init(INIT[171*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2C(permute_init(INIT[172*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2D(permute_init(INIT[173*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2E(permute_init(INIT[174*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2F(permute_init(INIT[175*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_30(permute_init(INIT[176*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_31(permute_init(INIT[177*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_32(permute_init(INIT[178*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_33(permute_init(INIT[179*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_34(permute_init(INIT[180*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_35(permute_init(INIT[181*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_36(permute_init(INIT[182*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_37(permute_init(INIT[183*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_38(permute_init(INIT[184*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_39(permute_init(INIT[185*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3A(permute_init(INIT[186*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3B(permute_init(INIT[187*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3C(permute_init(INIT[188*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3D(permute_init(INIT[189*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3E(permute_init(INIT[190*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3F(permute_init(INIT[191*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_40(permute_init(INIT[192*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_41(permute_init(INIT[193*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_42(permute_init(INIT[194*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_43(permute_init(INIT[195*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_44(permute_init(INIT[196*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_45(permute_init(INIT[197*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_46(permute_init(INIT[198*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_47(permute_init(INIT[199*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_48(permute_init(INIT[200*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_49(permute_init(INIT[201*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4A(permute_init(INIT[202*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4B(permute_init(INIT[203*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4C(permute_init(INIT[204*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4D(permute_init(INIT[205*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4E(permute_init(INIT[206*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4F(permute_init(INIT[207*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_50(permute_init(INIT[208*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_51(permute_init(INIT[209*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_52(permute_init(INIT[210*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_53(permute_init(INIT[211*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_54(permute_init(INIT[212*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_55(permute_init(INIT[213*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_56(permute_init(INIT[214*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_57(permute_init(INIT[215*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_58(permute_init(INIT[216*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_59(permute_init(INIT[217*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5A(permute_init(INIT[218*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5B(permute_init(INIT[219*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5C(permute_init(INIT[220*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5D(permute_init(INIT[221*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5E(permute_init(INIT[222*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5F(permute_init(INIT[223*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_60(permute_init(INIT[224*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_61(permute_init(INIT[225*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_62(permute_init(INIT[226*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_63(permute_init(INIT[227*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_64(permute_init(INIT[228*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_65(permute_init(INIT[229*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_66(permute_init(INIT[230*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_67(permute_init(INIT[231*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_68(permute_init(INIT[232*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_69(permute_init(INIT[233*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6A(permute_init(INIT[234*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6B(permute_init(INIT[235*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6C(permute_init(INIT[236*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6D(permute_init(INIT[237*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6E(permute_init(INIT[238*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6F(permute_init(INIT[239*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_70(permute_init(INIT[240*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_71(permute_init(INIT[241*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_72(permute_init(INIT[242*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_73(permute_init(INIT[243*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_74(permute_init(INIT[244*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_75(permute_init(INIT[245*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_76(permute_init(INIT[246*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_77(permute_init(INIT[247*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_78(permute_init(INIT[248*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_79(permute_init(INIT[249*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7A(permute_init(INIT[250*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7B(permute_init(INIT[251*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7C(permute_init(INIT[252*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7D(permute_init(INIT[253*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7E(permute_init(INIT[254*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7F(permute_init(INIT[255*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
`endif

882
resources/netlist/resources/kernel/share/gatemate/brams_map.v
View File

@ -1,882 +0,0 @@
module $__CC_BRAM_TDP_(...);
parameter INIT = 0;
parameter OPTION_MODE = "20K";
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_RD_USED = 1;
parameter PORT_A_WR_USED = 1;
parameter PORT_A_RD_WIDTH = 1;
parameter PORT_A_WR_WIDTH = 1;
parameter PORT_A_WR_BE_WIDTH = 1;
parameter PORT_A_OPTION_WR_MODE = "NO_CHANGE";
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_RD_USED = 1;
parameter PORT_B_WR_USED = 1;
parameter PORT_B_RD_WIDTH = 1;
parameter PORT_B_WR_WIDTH = 1;
parameter PORT_B_WR_BE_WIDTH = 1;
parameter PORT_B_OPTION_WR_MODE = "NO_CHANGE";
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input [15:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input [15:0] PORT_B_ADDR;
input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
generate
if (OPTION_MODE == "20K") begin
CC_BRAM_20K #(
.INIT_00(INIT['h00*320+:320]),
.INIT_01(INIT['h01*320+:320]),
.INIT_02(INIT['h02*320+:320]),
.INIT_03(INIT['h03*320+:320]),
.INIT_04(INIT['h04*320+:320]),
.INIT_05(INIT['h05*320+:320]),
.INIT_06(INIT['h06*320+:320]),
.INIT_07(INIT['h07*320+:320]),
.INIT_08(INIT['h08*320+:320]),
.INIT_09(INIT['h09*320+:320]),
.INIT_0A(INIT['h0a*320+:320]),
.INIT_0B(INIT['h0b*320+:320]),
.INIT_0C(INIT['h0c*320+:320]),
.INIT_0D(INIT['h0d*320+:320]),
.INIT_0E(INIT['h0e*320+:320]),
.INIT_0F(INIT['h0f*320+:320]),
.INIT_10(INIT['h10*320+:320]),
.INIT_11(INIT['h11*320+:320]),
.INIT_12(INIT['h12*320+:320]),
.INIT_13(INIT['h13*320+:320]),
.INIT_14(INIT['h14*320+:320]),
.INIT_15(INIT['h15*320+:320]),
.INIT_16(INIT['h16*320+:320]),
.INIT_17(INIT['h17*320+:320]),
.INIT_18(INIT['h18*320+:320]),
.INIT_19(INIT['h19*320+:320]),
.INIT_1A(INIT['h1a*320+:320]),
.INIT_1B(INIT['h1b*320+:320]),
.INIT_1C(INIT['h1c*320+:320]),
.INIT_1D(INIT['h1d*320+:320]),
.INIT_1E(INIT['h1e*320+:320]),
.INIT_1F(INIT['h1f*320+:320]),
.INIT_20(INIT['h20*320+:320]),
.INIT_21(INIT['h21*320+:320]),
.INIT_22(INIT['h22*320+:320]),
.INIT_23(INIT['h23*320+:320]),
.INIT_24(INIT['h24*320+:320]),
.INIT_25(INIT['h25*320+:320]),
.INIT_26(INIT['h26*320+:320]),
.INIT_27(INIT['h27*320+:320]),
.INIT_28(INIT['h28*320+:320]),
.INIT_29(INIT['h29*320+:320]),
.INIT_2A(INIT['h2a*320+:320]),
.INIT_2B(INIT['h2b*320+:320]),
.INIT_2C(INIT['h2c*320+:320]),
.INIT_2D(INIT['h2d*320+:320]),
.INIT_2E(INIT['h2e*320+:320]),
.INIT_2F(INIT['h2f*320+:320]),
.INIT_30(INIT['h30*320+:320]),
.INIT_31(INIT['h31*320+:320]),
.INIT_32(INIT['h32*320+:320]),
.INIT_33(INIT['h33*320+:320]),
.INIT_34(INIT['h34*320+:320]),
.INIT_35(INIT['h35*320+:320]),
.INIT_36(INIT['h36*320+:320]),
.INIT_37(INIT['h37*320+:320]),
.INIT_38(INIT['h38*320+:320]),
.INIT_39(INIT['h39*320+:320]),
.INIT_3A(INIT['h3a*320+:320]),
.INIT_3B(INIT['h3b*320+:320]),
.INIT_3C(INIT['h3c*320+:320]),
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
.A_CLK_INV(!PORT_A_CLK_POL),
.B_CLK_INV(!PORT_B_CLK_POL),
) _TECHMAP_REPLACE_ (
.A_CLK(PORT_A_CLK),
.A_EN(PORT_A_CLK_EN),
.A_WE(PORT_A_WR_EN),
.A_BM(PORT_A_WR_BE),
.A_DI(PORT_A_WR_DATA),
.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),
.A_DO(PORT_A_RD_DATA),
.B_CLK(PORT_B_CLK),
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),
.B_DO(PORT_B_RD_DATA),
);
end else if (OPTION_MODE == "40K") begin
CC_BRAM_40K #(
.INIT_00(INIT['h00*320+:320]),
.INIT_01(INIT['h01*320+:320]),
.INIT_02(INIT['h02*320+:320]),
.INIT_03(INIT['h03*320+:320]),
.INIT_04(INIT['h04*320+:320]),
.INIT_05(INIT['h05*320+:320]),
.INIT_06(INIT['h06*320+:320]),
.INIT_07(INIT['h07*320+:320]),
.INIT_08(INIT['h08*320+:320]),
.INIT_09(INIT['h09*320+:320]),
.INIT_0A(INIT['h0a*320+:320]),
.INIT_0B(INIT['h0b*320+:320]),
.INIT_0C(INIT['h0c*320+:320]),
.INIT_0D(INIT['h0d*320+:320]),
.INIT_0E(INIT['h0e*320+:320]),
.INIT_0F(INIT['h0f*320+:320]),
.INIT_10(INIT['h10*320+:320]),
.INIT_11(INIT['h11*320+:320]),
.INIT_12(INIT['h12*320+:320]),
.INIT_13(INIT['h13*320+:320]),
.INIT_14(INIT['h14*320+:320]),
.INIT_15(INIT['h15*320+:320]),
.INIT_16(INIT['h16*320+:320]),
.INIT_17(INIT['h17*320+:320]),
.INIT_18(INIT['h18*320+:320]),
.INIT_19(INIT['h19*320+:320]),
.INIT_1A(INIT['h1a*320+:320]),
.INIT_1B(INIT['h1b*320+:320]),
.INIT_1C(INIT['h1c*320+:320]),
.INIT_1D(INIT['h1d*320+:320]),
.INIT_1E(INIT['h1e*320+:320]),
.INIT_1F(INIT['h1f*320+:320]),
.INIT_20(INIT['h20*320+:320]),
.INIT_21(INIT['h21*320+:320]),
.INIT_22(INIT['h22*320+:320]),
.INIT_23(INIT['h23*320+:320]),
.INIT_24(INIT['h24*320+:320]),
.INIT_25(INIT['h25*320+:320]),
.INIT_26(INIT['h26*320+:320]),
.INIT_27(INIT['h27*320+:320]),
.INIT_28(INIT['h28*320+:320]),
.INIT_29(INIT['h29*320+:320]),
.INIT_2A(INIT['h2a*320+:320]),
.INIT_2B(INIT['h2b*320+:320]),
.INIT_2C(INIT['h2c*320+:320]),
.INIT_2D(INIT['h2d*320+:320]),
.INIT_2E(INIT['h2e*320+:320]),
.INIT_2F(INIT['h2f*320+:320]),
.INIT_30(INIT['h30*320+:320]),
.INIT_31(INIT['h31*320+:320]),
.INIT_32(INIT['h32*320+:320]),
.INIT_33(INIT['h33*320+:320]),
.INIT_34(INIT['h34*320+:320]),
.INIT_35(INIT['h35*320+:320]),
.INIT_36(INIT['h36*320+:320]),
.INIT_37(INIT['h37*320+:320]),
.INIT_38(INIT['h38*320+:320]),
.INIT_39(INIT['h39*320+:320]),
.INIT_3A(INIT['h3a*320+:320]),
.INIT_3B(INIT['h3b*320+:320]),
.INIT_3C(INIT['h3c*320+:320]),
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.INIT_40(INIT['h40*320+:320]),
.INIT_41(INIT['h41*320+:320]),
.INIT_42(INIT['h42*320+:320]),
.INIT_43(INIT['h43*320+:320]),
.INIT_44(INIT['h44*320+:320]),
.INIT_45(INIT['h45*320+:320]),
.INIT_46(INIT['h46*320+:320]),
.INIT_47(INIT['h47*320+:320]),
.INIT_48(INIT['h48*320+:320]),
.INIT_49(INIT['h49*320+:320]),
.INIT_4A(INIT['h4a*320+:320]),
.INIT_4B(INIT['h4b*320+:320]),
.INIT_4C(INIT['h4c*320+:320]),
.INIT_4D(INIT['h4d*320+:320]),
.INIT_4E(INIT['h4e*320+:320]),
.INIT_4F(INIT['h4f*320+:320]),
.INIT_50(INIT['h50*320+:320]),
.INIT_51(INIT['h51*320+:320]),
.INIT_52(INIT['h52*320+:320]),
.INIT_53(INIT['h53*320+:320]),
.INIT_54(INIT['h54*320+:320]),
.INIT_55(INIT['h55*320+:320]),
.INIT_56(INIT['h56*320+:320]),
.INIT_57(INIT['h57*320+:320]),
.INIT_58(INIT['h58*320+:320]),
.INIT_59(INIT['h59*320+:320]),
.INIT_5A(INIT['h5a*320+:320]),
.INIT_5B(INIT['h5b*320+:320]),
.INIT_5C(INIT['h5c*320+:320]),
.INIT_5D(INIT['h5d*320+:320]),
.INIT_5E(INIT['h5e*320+:320]),
.INIT_5F(INIT['h5f*320+:320]),
.INIT_60(INIT['h60*320+:320]),
.INIT_61(INIT['h61*320+:320]),
.INIT_62(INIT['h62*320+:320]),
.INIT_63(INIT['h63*320+:320]),
.INIT_64(INIT['h64*320+:320]),
.INIT_65(INIT['h65*320+:320]),
.INIT_66(INIT['h66*320+:320]),
.INIT_67(INIT['h67*320+:320]),
.INIT_68(INIT['h68*320+:320]),
.INIT_69(INIT['h69*320+:320]),
.INIT_6A(INIT['h6a*320+:320]),
.INIT_6B(INIT['h6b*320+:320]),
.INIT_6C(INIT['h6c*320+:320]),
.INIT_6D(INIT['h6d*320+:320]),
.INIT_6E(INIT['h6e*320+:320]),
.INIT_6F(INIT['h6f*320+:320]),
.INIT_70(INIT['h70*320+:320]),
.INIT_71(INIT['h71*320+:320]),
.INIT_72(INIT['h72*320+:320]),
.INIT_73(INIT['h73*320+:320]),
.INIT_74(INIT['h74*320+:320]),
.INIT_75(INIT['h75*320+:320]),
.INIT_76(INIT['h76*320+:320]),
.INIT_77(INIT['h77*320+:320]),
.INIT_78(INIT['h78*320+:320]),
.INIT_79(INIT['h79*320+:320]),
.INIT_7A(INIT['h7a*320+:320]),
.INIT_7B(INIT['h7b*320+:320]),
.INIT_7C(INIT['h7c*320+:320]),
.INIT_7D(INIT['h7d*320+:320]),
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
.A_CLK_INV(!PORT_A_CLK_POL),
.B_CLK_INV(!PORT_B_CLK_POL),
) _TECHMAP_REPLACE_ (
.A_CLK(PORT_A_CLK),
.A_EN(PORT_A_CLK_EN),
.A_WE(PORT_A_WR_EN),
.A_BM(PORT_A_WR_BE),
.A_DI(PORT_A_WR_DATA),
.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),
.A_DO(PORT_A_RD_DATA),
.B_CLK(PORT_B_CLK),
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),
.B_DO(PORT_B_RD_DATA),
);
end else begin
wire CAS_A, CAS_B;
CC_BRAM_40K #(
.INIT_00(INIT['h00*320+:320]),
.INIT_01(INIT['h01*320+:320]),
.INIT_02(INIT['h02*320+:320]),
.INIT_03(INIT['h03*320+:320]),
.INIT_04(INIT['h04*320+:320]),
.INIT_05(INIT['h05*320+:320]),
.INIT_06(INIT['h06*320+:320]),
.INIT_07(INIT['h07*320+:320]),
.INIT_08(INIT['h08*320+:320]),
.INIT_09(INIT['h09*320+:320]),
.INIT_0A(INIT['h0a*320+:320]),
.INIT_0B(INIT['h0b*320+:320]),
.INIT_0C(INIT['h0c*320+:320]),
.INIT_0D(INIT['h0d*320+:320]),
.INIT_0E(INIT['h0e*320+:320]),
.INIT_0F(INIT['h0f*320+:320]),
.INIT_10(INIT['h10*320+:320]),
.INIT_11(INIT['h11*320+:320]),
.INIT_12(INIT['h12*320+:320]),
.INIT_13(INIT['h13*320+:320]),
.INIT_14(INIT['h14*320+:320]),
.INIT_15(INIT['h15*320+:320]),
.INIT_16(INIT['h16*320+:320]),
.INIT_17(INIT['h17*320+:320]),
.INIT_18(INIT['h18*320+:320]),
.INIT_19(INIT['h19*320+:320]),
.INIT_1A(INIT['h1a*320+:320]),
.INIT_1B(INIT['h1b*320+:320]),
.INIT_1C(INIT['h1c*320+:320]),
.INIT_1D(INIT['h1d*320+:320]),
.INIT_1E(INIT['h1e*320+:320]),
.INIT_1F(INIT['h1f*320+:320]),
.INIT_20(INIT['h20*320+:320]),
.INIT_21(INIT['h21*320+:320]),
.INIT_22(INIT['h22*320+:320]),
.INIT_23(INIT['h23*320+:320]),
.INIT_24(INIT['h24*320+:320]),
.INIT_25(INIT['h25*320+:320]),
.INIT_26(INIT['h26*320+:320]),
.INIT_27(INIT['h27*320+:320]),
.INIT_28(INIT['h28*320+:320]),
.INIT_29(INIT['h29*320+:320]),
.INIT_2A(INIT['h2a*320+:320]),
.INIT_2B(INIT['h2b*320+:320]),
.INIT_2C(INIT['h2c*320+:320]),
.INIT_2D(INIT['h2d*320+:320]),
.INIT_2E(INIT['h2e*320+:320]),
.INIT_2F(INIT['h2f*320+:320]),
.INIT_30(INIT['h30*320+:320]),
.INIT_31(INIT['h31*320+:320]),
.INIT_32(INIT['h32*320+:320]),
.INIT_33(INIT['h33*320+:320]),
.INIT_34(INIT['h34*320+:320]),
.INIT_35(INIT['h35*320+:320]),
.INIT_36(INIT['h36*320+:320]),
.INIT_37(INIT['h37*320+:320]),
.INIT_38(INIT['h38*320+:320]),
.INIT_39(INIT['h39*320+:320]),
.INIT_3A(INIT['h3a*320+:320]),
.INIT_3B(INIT['h3b*320+:320]),
.INIT_3C(INIT['h3c*320+:320]),
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.INIT_40(INIT['h40*320+:320]),
.INIT_41(INIT['h41*320+:320]),
.INIT_42(INIT['h42*320+:320]),
.INIT_43(INIT['h43*320+:320]),
.INIT_44(INIT['h44*320+:320]),
.INIT_45(INIT['h45*320+:320]),
.INIT_46(INIT['h46*320+:320]),
.INIT_47(INIT['h47*320+:320]),
.INIT_48(INIT['h48*320+:320]),
.INIT_49(INIT['h49*320+:320]),
.INIT_4A(INIT['h4a*320+:320]),
.INIT_4B(INIT['h4b*320+:320]),
.INIT_4C(INIT['h4c*320+:320]),
.INIT_4D(INIT['h4d*320+:320]),
.INIT_4E(INIT['h4e*320+:320]),
.INIT_4F(INIT['h4f*320+:320]),
.INIT_50(INIT['h50*320+:320]),
.INIT_51(INIT['h51*320+:320]),
.INIT_52(INIT['h52*320+:320]),
.INIT_53(INIT['h53*320+:320]),
.INIT_54(INIT['h54*320+:320]),
.INIT_55(INIT['h55*320+:320]),
.INIT_56(INIT['h56*320+:320]),
.INIT_57(INIT['h57*320+:320]),
.INIT_58(INIT['h58*320+:320]),
.INIT_59(INIT['h59*320+:320]),
.INIT_5A(INIT['h5a*320+:320]),
.INIT_5B(INIT['h5b*320+:320]),
.INIT_5C(INIT['h5c*320+:320]),
.INIT_5D(INIT['h5d*320+:320]),
.INIT_5E(INIT['h5e*320+:320]),
.INIT_5F(INIT['h5f*320+:320]),
.INIT_60(INIT['h60*320+:320]),
.INIT_61(INIT['h61*320+:320]),
.INIT_62(INIT['h62*320+:320]),
.INIT_63(INIT['h63*320+:320]),
.INIT_64(INIT['h64*320+:320]),
.INIT_65(INIT['h65*320+:320]),
.INIT_66(INIT['h66*320+:320]),
.INIT_67(INIT['h67*320+:320]),
.INIT_68(INIT['h68*320+:320]),
.INIT_69(INIT['h69*320+:320]),
.INIT_6A(INIT['h6a*320+:320]),
.INIT_6B(INIT['h6b*320+:320]),
.INIT_6C(INIT['h6c*320+:320]),
.INIT_6D(INIT['h6d*320+:320]),
.INIT_6E(INIT['h6e*320+:320]),
.INIT_6F(INIT['h6f*320+:320]),
.INIT_70(INIT['h70*320+:320]),
.INIT_71(INIT['h71*320+:320]),
.INIT_72(INIT['h72*320+:320]),
.INIT_73(INIT['h73*320+:320]),
.INIT_74(INIT['h74*320+:320]),
.INIT_75(INIT['h75*320+:320]),
.INIT_76(INIT['h76*320+:320]),
.INIT_77(INIT['h77*320+:320]),
.INIT_78(INIT['h78*320+:320]),
.INIT_79(INIT['h79*320+:320]),
.INIT_7A(INIT['h7a*320+:320]),
.INIT_7B(INIT['h7b*320+:320]),
.INIT_7C(INIT['h7c*320+:320]),
.INIT_7D(INIT['h7d*320+:320]),
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
.A_CLK_INV(!PORT_A_CLK_POL),
.B_CLK_INV(!PORT_B_CLK_POL),
.CAS("LOWER"),
) lower (
.A_CO(CAS_A),
.B_CO(CAS_B),
.A_CLK(PORT_A_CLK),
.A_EN(PORT_A_CLK_EN),
.A_WE(PORT_A_WR_EN),
.A_BM(PORT_A_WR_BE),
.A_DI(PORT_A_WR_DATA),
.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
.B_CLK(PORT_B_CLK),
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
);
CC_BRAM_40K #(
.INIT_00(INIT['h80*320+:320]),
.INIT_01(INIT['h81*320+:320]),
.INIT_02(INIT['h82*320+:320]),
.INIT_03(INIT['h83*320+:320]),
.INIT_04(INIT['h84*320+:320]),
.INIT_05(INIT['h85*320+:320]),
.INIT_06(INIT['h86*320+:320]),
.INIT_07(INIT['h87*320+:320]),
.INIT_08(INIT['h88*320+:320]),
.INIT_09(INIT['h89*320+:320]),
.INIT_0A(INIT['h8a*320+:320]),
.INIT_0B(INIT['h8b*320+:320]),
.INIT_0C(INIT['h8c*320+:320]),
.INIT_0D(INIT['h8d*320+:320]),
.INIT_0E(INIT['h8e*320+:320]),
.INIT_0F(INIT['h8f*320+:320]),
.INIT_10(INIT['h90*320+:320]),
.INIT_11(INIT['h91*320+:320]),
.INIT_12(INIT['h92*320+:320]),
.INIT_13(INIT['h93*320+:320]),
.INIT_14(INIT['h94*320+:320]),
.INIT_15(INIT['h95*320+:320]),
.INIT_16(INIT['h96*320+:320]),
.INIT_17(INIT['h97*320+:320]),
.INIT_18(INIT['h98*320+:320]),
.INIT_19(INIT['h99*320+:320]),
.INIT_1A(INIT['h9a*320+:320]),
.INIT_1B(INIT['h9b*320+:320]),
.INIT_1C(INIT['h9c*320+:320]),
.INIT_1D(INIT['h9d*320+:320]),
.INIT_1E(INIT['h9e*320+:320]),
.INIT_1F(INIT['h9f*320+:320]),
.INIT_20(INIT['ha0*320+:320]),
.INIT_21(INIT['ha1*320+:320]),
.INIT_22(INIT['ha2*320+:320]),
.INIT_23(INIT['ha3*320+:320]),
.INIT_24(INIT['ha4*320+:320]),
.INIT_25(INIT['ha5*320+:320]),
.INIT_26(INIT['ha6*320+:320]),
.INIT_27(INIT['ha7*320+:320]),
.INIT_28(INIT['ha8*320+:320]),
.INIT_29(INIT['ha9*320+:320]),
.INIT_2A(INIT['haa*320+:320]),
.INIT_2B(INIT['hab*320+:320]),
.INIT_2C(INIT['hac*320+:320]),
.INIT_2D(INIT['had*320+:320]),
.INIT_2E(INIT['hae*320+:320]),
.INIT_2F(INIT['haf*320+:320]),
.INIT_30(INIT['hb0*320+:320]),
.INIT_31(INIT['hb1*320+:320]),
.INIT_32(INIT['hb2*320+:320]),
.INIT_33(INIT['hb3*320+:320]),
.INIT_34(INIT['hb4*320+:320]),
.INIT_35(INIT['hb5*320+:320]),
.INIT_36(INIT['hb6*320+:320]),
.INIT_37(INIT['hb7*320+:320]),
.INIT_38(INIT['hb8*320+:320]),
.INIT_39(INIT['hb9*320+:320]),
.INIT_3A(INIT['hba*320+:320]),
.INIT_3B(INIT['hbb*320+:320]),
.INIT_3C(INIT['hbc*320+:320]),
.INIT_3D(INIT['hbd*320+:320]),
.INIT_3E(INIT['hbe*320+:320]),
.INIT_3F(INIT['hbf*320+:320]),
.INIT_40(INIT['hc0*320+:320]),
.INIT_41(INIT['hc1*320+:320]),
.INIT_42(INIT['hc2*320+:320]),
.INIT_43(INIT['hc3*320+:320]),
.INIT_44(INIT['hc4*320+:320]),
.INIT_45(INIT['hc5*320+:320]),
.INIT_46(INIT['hc6*320+:320]),
.INIT_47(INIT['hc7*320+:320]),
.INIT_48(INIT['hc8*320+:320]),
.INIT_49(INIT['hc9*320+:320]),
.INIT_4A(INIT['hca*320+:320]),
.INIT_4B(INIT['hcb*320+:320]),
.INIT_4C(INIT['hcc*320+:320]),
.INIT_4D(INIT['hcd*320+:320]),
.INIT_4E(INIT['hce*320+:320]),
.INIT_4F(INIT['hcf*320+:320]),
.INIT_50(INIT['hd0*320+:320]),
.INIT_51(INIT['hd1*320+:320]),
.INIT_52(INIT['hd2*320+:320]),
.INIT_53(INIT['hd3*320+:320]),
.INIT_54(INIT['hd4*320+:320]),
.INIT_55(INIT['hd5*320+:320]),
.INIT_56(INIT['hd6*320+:320]),
.INIT_57(INIT['hd7*320+:320]),
.INIT_58(INIT['hd8*320+:320]),
.INIT_59(INIT['hd9*320+:320]),
.INIT_5A(INIT['hda*320+:320]),
.INIT_5B(INIT['hdb*320+:320]),
.INIT_5C(INIT['hdc*320+:320]),
.INIT_5D(INIT['hdd*320+:320]),
.INIT_5E(INIT['hde*320+:320]),
.INIT_5F(INIT['hdf*320+:320]),
.INIT_60(INIT['he0*320+:320]),
.INIT_61(INIT['he1*320+:320]),
.INIT_62(INIT['he2*320+:320]),
.INIT_63(INIT['he3*320+:320]),
.INIT_64(INIT['he4*320+:320]),
.INIT_65(INIT['he5*320+:320]),
.INIT_66(INIT['he6*320+:320]),
.INIT_67(INIT['he7*320+:320]),
.INIT_68(INIT['he8*320+:320]),
.INIT_69(INIT['he9*320+:320]),
.INIT_6A(INIT['hea*320+:320]),
.INIT_6B(INIT['heb*320+:320]),
.INIT_6C(INIT['hec*320+:320]),
.INIT_6D(INIT['hed*320+:320]),
.INIT_6E(INIT['hee*320+:320]),
.INIT_6F(INIT['hef*320+:320]),
.INIT_70(INIT['hf0*320+:320]),
.INIT_71(INIT['hf1*320+:320]),
.INIT_72(INIT['hf2*320+:320]),
.INIT_73(INIT['hf3*320+:320]),
.INIT_74(INIT['hf4*320+:320]),
.INIT_75(INIT['hf5*320+:320]),
.INIT_76(INIT['hf6*320+:320]),
.INIT_77(INIT['hf7*320+:320]),
.INIT_78(INIT['hf8*320+:320]),
.INIT_79(INIT['hf9*320+:320]),
.INIT_7A(INIT['hfa*320+:320]),
.INIT_7B(INIT['hfb*320+:320]),
.INIT_7C(INIT['hfc*320+:320]),
.INIT_7D(INIT['hfd*320+:320]),
.INIT_7E(INIT['hfe*320+:320]),
.INIT_7F(INIT['hff*320+:320]),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
.A_CLK_INV(!PORT_A_CLK_POL),
.B_CLK_INV(!PORT_B_CLK_POL),
.CAS("UPPER"),
) upper (
.A_CI(CAS_A),
.B_CI(CAS_B),
.A_CLK(PORT_A_CLK),
.A_EN(PORT_A_CLK_EN),
.A_WE(PORT_A_WR_EN),
.A_BM(PORT_A_WR_BE),
.A_DI(PORT_A_WR_DATA),
.A_DO(PORT_A_RD_DATA),
.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
.B_CLK(PORT_B_CLK),
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_B_WR_DATA),
.B_DO(PORT_B_RD_DATA),
.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
);
end
endgenerate
endmodule
module $__CC_BRAM_SDP_(...);
parameter INIT = 0;
parameter OPTION_MODE = "20K";
parameter OPTION_WR_MODE = "NO_CHANGE";
parameter PORT_W_CLK_POL = 1;
parameter PORT_W_USED = 1;
parameter PORT_W_WIDTH = 40;
parameter PORT_W_WR_BE_WIDTH = 40;
parameter PORT_R_CLK_POL = 1;
parameter PORT_R_USED = 1;
parameter PORT_R_WIDTH = 40;
input PORT_W_CLK;
input PORT_W_CLK_EN;
input PORT_W_WR_EN;
input [15:0] PORT_W_ADDR;
input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
input PORT_R_CLK;
input PORT_R_CLK_EN;
input [15:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
generate
if (OPTION_MODE == "20K") begin
CC_BRAM_20K #(
.INIT_00(INIT['h00*320+:320]),
.INIT_01(INIT['h01*320+:320]),
.INIT_02(INIT['h02*320+:320]),
.INIT_03(INIT['h03*320+:320]),
.INIT_04(INIT['h04*320+:320]),
.INIT_05(INIT['h05*320+:320]),
.INIT_06(INIT['h06*320+:320]),
.INIT_07(INIT['h07*320+:320]),
.INIT_08(INIT['h08*320+:320]),
.INIT_09(INIT['h09*320+:320]),
.INIT_0A(INIT['h0a*320+:320]),
.INIT_0B(INIT['h0b*320+:320]),
.INIT_0C(INIT['h0c*320+:320]),
.INIT_0D(INIT['h0d*320+:320]),
.INIT_0E(INIT['h0e*320+:320]),
.INIT_0F(INIT['h0f*320+:320]),
.INIT_10(INIT['h10*320+:320]),
.INIT_11(INIT['h11*320+:320]),
.INIT_12(INIT['h12*320+:320]),
.INIT_13(INIT['h13*320+:320]),
.INIT_14(INIT['h14*320+:320]),
.INIT_15(INIT['h15*320+:320]),
.INIT_16(INIT['h16*320+:320]),
.INIT_17(INIT['h17*320+:320]),
.INIT_18(INIT['h18*320+:320]),
.INIT_19(INIT['h19*320+:320]),
.INIT_1A(INIT['h1a*320+:320]),
.INIT_1B(INIT['h1b*320+:320]),
.INIT_1C(INIT['h1c*320+:320]),
.INIT_1D(INIT['h1d*320+:320]),
.INIT_1E(INIT['h1e*320+:320]),
.INIT_1F(INIT['h1f*320+:320]),
.INIT_20(INIT['h20*320+:320]),
.INIT_21(INIT['h21*320+:320]),
.INIT_22(INIT['h22*320+:320]),
.INIT_23(INIT['h23*320+:320]),
.INIT_24(INIT['h24*320+:320]),
.INIT_25(INIT['h25*320+:320]),
.INIT_26(INIT['h26*320+:320]),
.INIT_27(INIT['h27*320+:320]),
.INIT_28(INIT['h28*320+:320]),
.INIT_29(INIT['h29*320+:320]),
.INIT_2A(INIT['h2a*320+:320]),
.INIT_2B(INIT['h2b*320+:320]),
.INIT_2C(INIT['h2c*320+:320]),
.INIT_2D(INIT['h2d*320+:320]),
.INIT_2E(INIT['h2e*320+:320]),
.INIT_2F(INIT['h2f*320+:320]),
.INIT_30(INIT['h30*320+:320]),
.INIT_31(INIT['h31*320+:320]),
.INIT_32(INIT['h32*320+:320]),
.INIT_33(INIT['h33*320+:320]),
.INIT_34(INIT['h34*320+:320]),
.INIT_35(INIT['h35*320+:320]),
.INIT_36(INIT['h36*320+:320]),
.INIT_37(INIT['h37*320+:320]),
.INIT_38(INIT['h38*320+:320]),
.INIT_39(INIT['h39*320+:320]),
.INIT_3A(INIT['h3a*320+:320]),
.INIT_3B(INIT['h3b*320+:320]),
.INIT_3C(INIT['h3c*320+:320]),
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.A_RD_WIDTH(0),
.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),
.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),
.B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE(OPTION_WR_MODE),
.B_WR_MODE(OPTION_WR_MODE),
.A_CLK_INV(!PORT_W_CLK_POL),
.B_CLK_INV(!PORT_R_CLK_POL),
) _TECHMAP_REPLACE_ (
.A_CLK(PORT_W_CLK),
.A_EN(PORT_W_CLK_EN),
.A_WE(PORT_W_WR_EN),
.A_BM(PORT_W_WR_BE[19:0]),
.B_BM(PORT_W_WR_BE[39:20]),
.A_DI(PORT_W_WR_DATA[19:0]),
.B_DI(PORT_W_WR_DATA[39:20]),
.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),
.B_CLK(PORT_R_CLK),
.B_EN(PORT_R_CLK_EN),
.B_WE(1'b0),
.B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}),
.A_DO(PORT_R_RD_DATA[19:0]),
.B_DO(PORT_R_RD_DATA[39:20]),
);
end else if (OPTION_MODE == "40K") begin
CC_BRAM_40K #(
.INIT_00(INIT['h00*320+:320]),
.INIT_01(INIT['h01*320+:320]),
.INIT_02(INIT['h02*320+:320]),
.INIT_03(INIT['h03*320+:320]),
.INIT_04(INIT['h04*320+:320]),
.INIT_05(INIT['h05*320+:320]),
.INIT_06(INIT['h06*320+:320]),
.INIT_07(INIT['h07*320+:320]),
.INIT_08(INIT['h08*320+:320]),
.INIT_09(INIT['h09*320+:320]),
.INIT_0A(INIT['h0a*320+:320]),
.INIT_0B(INIT['h0b*320+:320]),
.INIT_0C(INIT['h0c*320+:320]),
.INIT_0D(INIT['h0d*320+:320]),
.INIT_0E(INIT['h0e*320+:320]),
.INIT_0F(INIT['h0f*320+:320]),
.INIT_10(INIT['h10*320+:320]),
.INIT_11(INIT['h11*320+:320]),
.INIT_12(INIT['h12*320+:320]),
.INIT_13(INIT['h13*320+:320]),
.INIT_14(INIT['h14*320+:320]),
.INIT_15(INIT['h15*320+:320]),
.INIT_16(INIT['h16*320+:320]),
.INIT_17(INIT['h17*320+:320]),
.INIT_18(INIT['h18*320+:320]),
.INIT_19(INIT['h19*320+:320]),
.INIT_1A(INIT['h1a*320+:320]),
.INIT_1B(INIT['h1b*320+:320]),
.INIT_1C(INIT['h1c*320+:320]),
.INIT_1D(INIT['h1d*320+:320]),
.INIT_1E(INIT['h1e*320+:320]),
.INIT_1F(INIT['h1f*320+:320]),
.INIT_20(INIT['h20*320+:320]),
.INIT_21(INIT['h21*320+:320]),
.INIT_22(INIT['h22*320+:320]),
.INIT_23(INIT['h23*320+:320]),
.INIT_24(INIT['h24*320+:320]),
.INIT_25(INIT['h25*320+:320]),
.INIT_26(INIT['h26*320+:320]),
.INIT_27(INIT['h27*320+:320]),
.INIT_28(INIT['h28*320+:320]),
.INIT_29(INIT['h29*320+:320]),
.INIT_2A(INIT['h2a*320+:320]),
.INIT_2B(INIT['h2b*320+:320]),
.INIT_2C(INIT['h2c*320+:320]),
.INIT_2D(INIT['h2d*320+:320]),
.INIT_2E(INIT['h2e*320+:320]),
.INIT_2F(INIT['h2f*320+:320]),
.INIT_30(INIT['h30*320+:320]),
.INIT_31(INIT['h31*320+:320]),
.INIT_32(INIT['h32*320+:320]),
.INIT_33(INIT['h33*320+:320]),
.INIT_34(INIT['h34*320+:320]),
.INIT_35(INIT['h35*320+:320]),
.INIT_36(INIT['h36*320+:320]),
.INIT_37(INIT['h37*320+:320]),
.INIT_38(INIT['h38*320+:320]),
.INIT_39(INIT['h39*320+:320]),
.INIT_3A(INIT['h3a*320+:320]),
.INIT_3B(INIT['h3b*320+:320]),
.INIT_3C(INIT['h3c*320+:320]),
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.INIT_40(INIT['h40*320+:320]),
.INIT_41(INIT['h41*320+:320]),
.INIT_42(INIT['h42*320+:320]),
.INIT_43(INIT['h43*320+:320]),
.INIT_44(INIT['h44*320+:320]),
.INIT_45(INIT['h45*320+:320]),
.INIT_46(INIT['h46*320+:320]),
.INIT_47(INIT['h47*320+:320]),
.INIT_48(INIT['h48*320+:320]),
.INIT_49(INIT['h49*320+:320]),
.INIT_4A(INIT['h4a*320+:320]),
.INIT_4B(INIT['h4b*320+:320]),
.INIT_4C(INIT['h4c*320+:320]),
.INIT_4D(INIT['h4d*320+:320]),
.INIT_4E(INIT['h4e*320+:320]),
.INIT_4F(INIT['h4f*320+:320]),
.INIT_50(INIT['h50*320+:320]),
.INIT_51(INIT['h51*320+:320]),
.INIT_52(INIT['h52*320+:320]),
.INIT_53(INIT['h53*320+:320]),
.INIT_54(INIT['h54*320+:320]),
.INIT_55(INIT['h55*320+:320]),
.INIT_56(INIT['h56*320+:320]),
.INIT_57(INIT['h57*320+:320]),
.INIT_58(INIT['h58*320+:320]),
.INIT_59(INIT['h59*320+:320]),
.INIT_5A(INIT['h5a*320+:320]),
.INIT_5B(INIT['h5b*320+:320]),
.INIT_5C(INIT['h5c*320+:320]),
.INIT_5D(INIT['h5d*320+:320]),
.INIT_5E(INIT['h5e*320+:320]),
.INIT_5F(INIT['h5f*320+:320]),
.INIT_60(INIT['h60*320+:320]),
.INIT_61(INIT['h61*320+:320]),
.INIT_62(INIT['h62*320+:320]),
.INIT_63(INIT['h63*320+:320]),
.INIT_64(INIT['h64*320+:320]),
.INIT_65(INIT['h65*320+:320]),
.INIT_66(INIT['h66*320+:320]),
.INIT_67(INIT['h67*320+:320]),
.INIT_68(INIT['h68*320+:320]),
.INIT_69(INIT['h69*320+:320]),
.INIT_6A(INIT['h6a*320+:320]),
.INIT_6B(INIT['h6b*320+:320]),
.INIT_6C(INIT['h6c*320+:320]),
.INIT_6D(INIT['h6d*320+:320]),
.INIT_6E(INIT['h6e*320+:320]),
.INIT_6F(INIT['h6f*320+:320]),
.INIT_70(INIT['h70*320+:320]),
.INIT_71(INIT['h71*320+:320]),
.INIT_72(INIT['h72*320+:320]),
.INIT_73(INIT['h73*320+:320]),
.INIT_74(INIT['h74*320+:320]),
.INIT_75(INIT['h75*320+:320]),
.INIT_76(INIT['h76*320+:320]),
.INIT_77(INIT['h77*320+:320]),
.INIT_78(INIT['h78*320+:320]),
.INIT_79(INIT['h79*320+:320]),
.INIT_7A(INIT['h7a*320+:320]),
.INIT_7B(INIT['h7b*320+:320]),
.INIT_7C(INIT['h7c*320+:320]),
.INIT_7D(INIT['h7d*320+:320]),
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(0),
.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),
.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),
.B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE(OPTION_WR_MODE),
.B_WR_MODE(OPTION_WR_MODE),
.A_CLK_INV(!PORT_W_CLK_POL),
.B_CLK_INV(!PORT_R_CLK_POL),
) _TECHMAP_REPLACE_ (
.A_CLK(PORT_W_CLK),
.A_EN(PORT_W_CLK_EN),
.A_WE(PORT_W_WR_EN),
.A_BM(PORT_W_WR_BE[39:0]),
.B_BM(PORT_W_WR_BE[79:40]),
.A_DI(PORT_W_WR_DATA[39:0]),
.B_DI(PORT_W_WR_DATA[79:40]),
.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),
.B_CLK(PORT_R_CLK),
.B_EN(PORT_R_CLK_EN),
.B_WE(1'b0),
.B_ADDR({PORT_R_ADDR[14:0], 1'b0}),
.A_DO(PORT_R_RD_DATA[39:0]),
.B_DO(PORT_R_RD_DATA[79:40]),
);
end
endgenerate
endmodule

191
resources/netlist/resources/kernel/share/gatemate/cells_bb.v
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@ -1,191 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter SERDES_CFG = ""
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWERDOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input CLK_CORE_TX_I,
input CLK_CORE_RX_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWERDOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input CLK_REG_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output RX_DETECT_DONE_O,
output RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESETDONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESETDONE_O,
output RX_EI_EN_O,
output CLK_CORE_RX_O,
output CLK_CORE_PLL_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *)
module CC_FIFO_40K (
output A_ECC_1B_ERR,
output B_ECC_1B_ERR,
output A_ECC_2B_ERR,
output B_ECC_2B_ERR,
// FIFO pop port
output [39:0] A_DO,
output [39:0] B_DO,
(* clkbuf_sink *)
input A_CLK,
input A_EN,
// FIFO push port
input [39:0] A_DI,
input [39:0] B_DI,
input [39:0] A_BM,
input [39:0] B_BM,
(* clkbuf_sink *)
input B_CLK,
input B_EN,
input B_WE,
// FIFO control
input F_RST_N,
input [12:0] F_ALMOST_FULL_OFFSET,
input [12:0] F_ALMOST_EMPTY_OFFSET,
// FIFO status signals
output F_FULL,
output F_EMPTY,
output F_ALMOST_FULL,
output F_ALMOST_EMPTY,
output F_RD_ERROR,
output F_WR_ERROR,
output [15:0] F_RD_PTR,
output [15:0] F_WR_PTR
);
// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
parameter LOC = "UNPLACED";
// Offset configuration
parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
// Port Widths
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
// RAM and Write Modes
parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
// Inverting Control Pins
parameter A_CLK_INV = 1'b0;
parameter B_CLK_INV = 1'b0;
parameter A_EN_INV = 1'b0;
parameter B_EN_INV = 1'b0;
parameter A_WE_INV = 1'b0;
parameter B_WE_INV = 1'b0;
// Output Register
parameter A_DO_REG = 1'b0;
parameter B_DO_REG = 1'b0;
// Error Checking and Correction
parameter A_ECC_EN = 1'b0;
parameter B_ECC_EN = 1'b0;
endmodule

1455
resources/netlist/resources/kernel/share/gatemate/cells_sim.v
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File diff suppressed because it is too large Load Diff

4
resources/netlist/resources/kernel/share/gatemate/inv_map.v
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@ -1,4 +0,0 @@
// Any inverters not folded into LUTs are mapped to a LUT of their own
module \$__CC_NOT (input A, output Y);
CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));
endmodule

45
resources/netlist/resources/kernel/share/gatemate/lut_map.v
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@ -1,45 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

221
resources/netlist/resources/kernel/share/gatemate/lut_tree_cells.genlib
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@ -1,221 +0,0 @@
GATE $__ZERO 0 Y=CONST0;
GATE $__ONE 0 Y=CONST1;
GATE $__CC_BUF 5 Y=A;
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC_NOT 0 Y=!A;
PIN * INV 1 9999 10 5 10 5
GATE $__CC_MUX 5 Y=((A*!C)+(B*C));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC2_A 10 Y=(A*B);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC3_A_O 12 Y=(E+(A*B));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC3_A_X 12 Y=((E*(!A+!B))+(!E*(A*B)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC2_O 10 Y=(A+B);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC3_O_A 12 Y=(E*(A+B));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC3_O_X 12 Y=((E*(!A*!B))+(!E*(A+B)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC2_X 10 Y=((A*!B)+(!A*B));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_X_A 12 Y=(E*((A*!B)+(!A*B)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_X_O 12 Y=(E+((A*!B)+(!A*B)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_AA 10 Y=((A*B)*C);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_AA_O 12 Y=(E+((A*B)*C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_AA_X 12 Y=((E*((!A+!B)+!C))+(!E*((A*B)*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_OO 10 Y=((A+B)+C);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_OO_A 12 Y=(E*((A+B)+C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_OO_X 12 Y=((E*((!A*!B)*!C))+(!E*((A+B)+C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_XX 10 Y=((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XX_A 12 Y=(E*((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XX_O 12 Y=(E+((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_AO 10 Y=((A*B)+C);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_AO_A 12 Y=(E*((A*B)+C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_AO_O 12 Y=(E+((A*B)+C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_AO_X 12 Y=((E*((!A+!B)*!C))+(!E*((A*B)+C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_OA 10 Y=((A+B)*C);
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_OA_A 12 Y=(E*((A+B)*C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_OA_O 12 Y=(E+((A+B)*C));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC4_OA_X 12 Y=((E*((!A*!B)+!C))+(!E*((A+B)*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_AX 10 Y=(((A*B)*!C)+((!A+!B)*C));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AX_A 12 Y=(E*(((A*B)*!C)+((!A+!B)*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AX_O 12 Y=(E+(((A*B)*!C)+((!A+!B)*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AX_X 12 Y=((E*(((!A+!B)+C)*((A*B)+!C)))+(!E*(((A*B)*!C)+((!A+!B)*C))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC3_XA 10 Y=(((A*!B)+(!A*B))*C);
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XA_A 12 Y=(E*(((A*!B)+(!A*B))*C));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XA_O 12 Y=(E+(((A*!B)+(!A*B))*C));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XA_X 12 Y=((E*(((!A+B)*(A+!B))+!C))+(!E*(((A*!B)+(!A*B))*C)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AAA 10 Y=((A*B)*(C*D));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAA_A 12 Y=(E*((A*B)*(C*D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAA_O 12 Y=(E+((A*B)*(C*D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAA_X 12 Y=((E*((!A+!B)+(!C+!D)))+(!E*((A*B)*(C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AXA 10 Y=(((A*B)*(!C+!D))+((!A+!B)*(C*D)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXA_A 12 Y=(E*(((A*B)*(!C+!D))+((!A+!B)*(C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXA_O 12 Y=(E+(((A*B)*(!C+!D))+((!A+!B)*(C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXA_X 12 Y=((E*(((!A+!B)+(C*D))*((A*B)+(!C+!D))))+(!E*(((A*B)*(!C+!D))+((!A+!B)*(C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XAX 10 Y=(((A*!B)+(!A*B))*((C*!D)+(!C*D)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XAX_A 12 Y=(E*(((A*!B)+(!A*B))*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XAX_O 12 Y=(E+(((A*!B)+(!A*B))*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XAX_X 12 Y=((E*(((!A+B)*(A+!B))+((!C+D)*(C+!D))))+(!E*(((A*!B)+(!A*B))*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AAX 10 Y=((A*B)*((C*!D)+(!C*D)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AAX_A 12 Y=(E*((A*B)*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AAX_O 12 Y=(E+((A*B)*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AAX_X 12 Y=((E*((!A+!B)+((!C+D)*(C+!D))))+(!E*((A*B)*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AXX 10 Y=(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXX_A 12 Y=(E*(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXX_O 12 Y=(E+(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AXX_X 12 Y=((E*(((!A+!B)+((C*!D)+(!C*D)))*((A*B)+((!C+D)*(C+!D)))))+(!E*(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D))))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_XXX 10 Y=((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XXX_A 12 Y=(E*((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XXX_O 12 Y=(E+((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_XXX_X 12 Y=((E*((((!A+B)*(A+!B))+((C*!D)+(!C*D)))*(((A*!B)+(!A*B))+((!C+D)*(C+!D)))))+(!E*((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D))))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AAO 10 Y=((A*B)*(C+D));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAO_A 12 Y=(E*((A*B)*(C+D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAO_O 12 Y=(E+((A*B)*(C+D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AAO_X 12 Y=((E*((!A+!B)+(!C*!D)))+(!E*((A*B)*(C+D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AOA 10 Y=((A*B)+(C*D));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AOA_A 12 Y=(E*((A*B)+(C*D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AOA_O 12 Y=(E+((A*B)+(C*D)));
PIN * NONINV 1 9999 10 5 10 5
GATE $__CC5_AOA_X 12 Y=((E*((!A+!B)*(!C+!D)))+(!E*((A*B)+(C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC4_AOX 10 Y=((A*B)+((C*!D)+(!C*D)));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AOX_A 12 Y=(E*((A*B)+((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AOX_O 12 Y=(E+((A*B)+((C*!D)+(!C*D))));
PIN * UNKNOWN 1 9999 10 5 10 5
GATE $__CC5_AOX_X 12 Y=((E*((!A+!B)*((!C+D)*(C+!D))))+(!E*((A*B)+((C*!D)+(!C*D)))));
PIN * UNKNOWN 1 9999 10 5 10 5

822
resources/netlist/resources/kernel/share/gatemate/lut_tree_map.v
View File

@ -1,822 +0,0 @@
module \$__ZERO (output Y); assign Y = 1'b0; endmodule
module \$__ONE (output Y); assign Y = 1'b1; endmodule
module \$__CC_BUF (input A, output Y); assign Y = A; endmodule
module \$__CC_MUX (input A, B, C, output Y);
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(C),
.Y(Y)
);
endmodule
module \$__CC2_A (input A, B, output Y);
CC_LUT2 #(
.INIT(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B),
.O(Y)
);
endmodule
module \$__CC3_A_O (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b1000),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC3_A_X (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b1000),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC2_O (input A, B, output Y);
CC_LUT2 #(
.INIT(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B),
.O(Y)
);
endmodule
module \$__CC3_O_A (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b1110),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC3_O_X (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b1110),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC2_X (input A, B, output Y);
CC_LUT2 #(
.INIT(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B),
.O(Y)
);
endmodule
module \$__CC3_X_A (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b0110),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC3_X_O (input A, B, E, output Y);
CC_L2T4 #(
.INIT_L00(4'b1010),
.INIT_L01(4'b0110),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(E), .I1(), .I2(A), .I3(B),
.O(Y)
);
endmodule
module \$__CC3_AA (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1010),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_AA_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AA_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_OO (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b1110),
.INIT_L01(4'b1010),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_OO_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_OO_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_XX (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b0110),
.INIT_L01(4'b1010),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_XX_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b1010),
.INIT_L11(4'b0110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_XX_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b1010),
.INIT_L11(4'b0110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_AO (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1010),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_AO_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b1110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AO_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b1110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AO_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b1110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_OA (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b1110),
.INIT_L01(4'b1010),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_OA_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_OA_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_OA_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_AX (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1010),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_AX_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b0110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AX_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b0110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AX_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1010),
.INIT_L11(4'b0110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC3_XA (input A, B, C, output Y);
CC_L2T4 #(
.INIT_L00(4'b0110),
.INIT_L01(4'b1010),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(),
.O(Y)
);
endmodule
module \$__CC4_XA_A (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_XA_O (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_XA_X (input A, B, C, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b1010),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AAA (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1000),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AAA_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAA_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAA_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AXA (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1000),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AXA_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b0110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AXA_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b0110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AXA_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b0110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_XAX (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b0110),
.INIT_L01(4'b0110),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_XAX_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_XAX_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_XAX_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AAX (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b0110),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AAX_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAX_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAX_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AXX (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b0110),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AXX_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AXX_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AXX_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_XXX (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b0110),
.INIT_L01(4'b0110),
.INIT_L10(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_XXX_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_XXX_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_XXX_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b0110),
.INIT_L03(4'b0110),
.INIT_L11(4'b0110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AAO (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1110),
.INIT_L10(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AAO_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAO_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1110),
.INIT_L11(4'b1000),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AAO_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1110),
.INIT_L11(4'b1000),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AOA (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b1000),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AOA_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AOA_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AOA_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b1000),
.INIT_L11(4'b1110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC4_AOX (input A, B, C, D, output Y);
CC_L2T4 #(
.INIT_L00(4'b1000),
.INIT_L01(4'b0110),
.INIT_L10(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D),
.O(Y)
);
endmodule
module \$__CC5_AOX_A (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1110),
.INIT_L20(4'b1000),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AOX_O (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1110),
.INIT_L20(4'b1110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule
module \$__CC5_AOX_X (input A, B, C, D, E, output Y);
CC_L2T5 #(
.INIT_L02(4'b1000),
.INIT_L03(4'b0110),
.INIT_L11(4'b1110),
.INIT_L20(4'b0110),
) _TECHMAP_REPLACE_ (
.I0(A), .I1(B), .I2(C), .I3(D), .I4(E),
.O(Y)
);
endmodule

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@ -1,77 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$mul $__mul" *)
module \$__MULMXN (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
localparam A_ADJWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
localparam B_ADJWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);
generate
if (A_SIGNED) begin: blkA
wire signed [A_ADJWIDTH-1:0] Aext = $signed(A);
end
else begin: blkA
wire [A_ADJWIDTH-1:0] Aext = A;
end
if (B_SIGNED) begin: blkB
wire signed [B_ADJWIDTH-1:0] Bext = $signed(B);
end
else begin: blkB
wire [B_ADJWIDTH-1:0] Bext = B;
end
if (A_WIDTH >= B_WIDTH) begin
CC_MULT #(
.A_WIDTH(A_ADJWIDTH),
.B_WIDTH(B_ADJWIDTH),
.P_WIDTH(Y_WIDTH),
) _TECHMAP_REPLACE_ (
.A(blkA.Aext),
.B(blkB.Bext),
.P(Y)
);
end
else begin // swap A,B
CC_MULT #(
.A_WIDTH(B_ADJWIDTH),
.B_WIDTH(A_ADJWIDTH),
.P_WIDTH(Y_WIDTH),
) _TECHMAP_REPLACE_ (
.A(blkB.Bext),
.B(blkA.Aext),
.P(Y)
);
end
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1")
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
alu(.I0(AA[i]),
.I1(BB[i]),
.I3(~BI),
.CIN(C[i]),
.COUT(CO[i]),
.SUM(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule

81
resources/netlist/resources/kernel/share/gowin/brams.txt
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@ -1,81 +0,0 @@
ram block $__GOWIN_SP_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
byte 9;
cost 128;
init no_undef;
port srsw "A" {
clock posedge;
clken;
wrbe_separate;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
portoption "WRITE_MODE" 0 {
rdwr no_change;
}
portoption "WRITE_MODE" 1 {
rdwr new;
}
portoption "WRITE_MODE" 2 {
rdwr old;
}
}
}
ram block $__GOWIN_DP_ {
abits 14;
widths 1 2 4 9 18 per_port;
byte 9;
cost 128;
init no_undef;
port srsw "A" "B" {
clock posedge;
clken;
wrbe_separate;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
portoption "WRITE_MODE" 0 {
rdwr no_change;
}
portoption "WRITE_MODE" 1 {
rdwr new;
}
portoption "WRITE_MODE" 2 {
rdwr old;
}
}
}
ram block $__GOWIN_SDP_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
byte 9;
cost 128;
init no_undef;
port sr "R" {
clock posedge;
clken;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
clock posedge;
clken;
wrbe_separate;
}
}

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resources/netlist/resources/kernel/share/gowin/brams_map.v
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@ -1,410 +0,0 @@
`define DEF_FUNCS \
function [255:0] init_slice_x8; \
input integer idx; \
integer i; \
for (i = 0; i < 32; i = i + 1) begin \
init_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \
end \
endfunction \
function [287:0] init_slice_x9; \
input integer idx; \
init_slice_x9 = INIT[idx * 288+:288]; \
endfunction \
`define x8_width(width) (width / 9 * 8 + width % 9)
`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)
`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})
`define INIT(func) \
.INIT_RAM_00(func('h00)), \
.INIT_RAM_01(func('h01)), \
.INIT_RAM_02(func('h02)), \
.INIT_RAM_03(func('h03)), \
.INIT_RAM_04(func('h04)), \
.INIT_RAM_05(func('h05)), \
.INIT_RAM_06(func('h06)), \
.INIT_RAM_07(func('h07)), \
.INIT_RAM_08(func('h08)), \
.INIT_RAM_09(func('h09)), \
.INIT_RAM_0A(func('h0a)), \
.INIT_RAM_0B(func('h0b)), \
.INIT_RAM_0C(func('h0c)), \
.INIT_RAM_0D(func('h0d)), \
.INIT_RAM_0E(func('h0e)), \
.INIT_RAM_0F(func('h0f)), \
.INIT_RAM_10(func('h10)), \
.INIT_RAM_11(func('h11)), \
.INIT_RAM_12(func('h12)), \
.INIT_RAM_13(func('h13)), \
.INIT_RAM_14(func('h14)), \
.INIT_RAM_15(func('h15)), \
.INIT_RAM_16(func('h16)), \
.INIT_RAM_17(func('h17)), \
.INIT_RAM_18(func('h18)), \
.INIT_RAM_19(func('h19)), \
.INIT_RAM_1A(func('h1a)), \
.INIT_RAM_1B(func('h1b)), \
.INIT_RAM_1C(func('h1c)), \
.INIT_RAM_1D(func('h1d)), \
.INIT_RAM_1E(func('h1e)), \
.INIT_RAM_1F(func('h1f)), \
.INIT_RAM_20(func('h20)), \
.INIT_RAM_21(func('h21)), \
.INIT_RAM_22(func('h22)), \
.INIT_RAM_23(func('h23)), \
.INIT_RAM_24(func('h24)), \
.INIT_RAM_25(func('h25)), \
.INIT_RAM_26(func('h26)), \
.INIT_RAM_27(func('h27)), \
.INIT_RAM_28(func('h28)), \
.INIT_RAM_29(func('h29)), \
.INIT_RAM_2A(func('h2a)), \
.INIT_RAM_2B(func('h2b)), \
.INIT_RAM_2C(func('h2c)), \
.INIT_RAM_2D(func('h2d)), \
.INIT_RAM_2E(func('h2e)), \
.INIT_RAM_2F(func('h2f)), \
.INIT_RAM_30(func('h30)), \
.INIT_RAM_31(func('h31)), \
.INIT_RAM_32(func('h32)), \
.INIT_RAM_33(func('h33)), \
.INIT_RAM_34(func('h34)), \
.INIT_RAM_35(func('h35)), \
.INIT_RAM_36(func('h36)), \
.INIT_RAM_37(func('h37)), \
.INIT_RAM_38(func('h38)), \
.INIT_RAM_39(func('h39)), \
.INIT_RAM_3A(func('h3a)), \
.INIT_RAM_3B(func('h3b)), \
.INIT_RAM_3C(func('h3c)), \
.INIT_RAM_3D(func('h3d)), \
.INIT_RAM_3E(func('h3e)), \
.INIT_RAM_3F(func('h3f)),
module $__GOWIN_SP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_A_WIDTH = 36;
parameter PORT_A_WR_BE_WIDTH = 4;
parameter PORT_A_OPTION_WRITE_MODE = 0;
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [13:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
`DEF_FUNCS
wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
generate
if (PORT_A_WIDTH < 9) begin
wire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);
wire [31:0] DO;
assign PORT_A_RD_DATA = `x8_rd_data(DO);
SP #(
`INIT(init_slice_x8)
.READ_MODE(1'b0),
.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLK(PORT_A_CLK),
.CE(PORT_A_CLK_EN),
.WRE(WRE),
.RESET(RST),
.OCE(1'b0),
.AD(AD),
.DI(DI),
.DO(DO),
);
end else begin
wire [35:0] DI = PORT_A_WR_DATA;
wire [35:0] DO;
assign PORT_A_RD_DATA = DO;
SPX9 #(
`INIT(init_slice_x9)
.READ_MODE(1'b0),
.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
.BIT_WIDTH(PORT_A_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLK(PORT_A_CLK),
.CE(PORT_A_CLK_EN),
.WRE(WRE),
.RESET(RST),
.OCE(1'b0),
.AD(AD),
.DI(DI),
.DO(DO),
);
end
endgenerate
endmodule
module $__GOWIN_DP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_A_WIDTH = 18;
parameter PORT_A_WR_BE_WIDTH = 2;
parameter PORT_A_OPTION_WRITE_MODE = 0;
parameter PORT_B_WIDTH = 18;
parameter PORT_B_WR_BE_WIDTH = 2;
parameter PORT_B_OPTION_WRITE_MODE = 0;
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [13:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input PORT_B_RD_SRST;
input PORT_B_RD_ARST;
input [13:0] PORT_B_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
`DEF_FUNCS
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
wire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate
if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
wire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);
wire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);
wire [15:0] DOA;
wire [15:0] DOB;
assign PORT_A_RD_DATA = `x8_rd_data(DOA);
assign PORT_B_RD_DATA = `x8_rd_data(DOB);
DP #(
`INIT(init_slice_x8)
.READ_MODE0(1'b0),
.READ_MODE1(1'b0),
.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),
.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_A_CLK),
.CEA(PORT_A_CLK_EN),
.WREA(WREA),
.RESETA(RSTA),
.OCEA(1'b0),
.ADA(ADA),
.DIA(DIA),
.DOA(DOA),
.CLKB(PORT_B_CLK),
.CEB(PORT_B_CLK_EN),
.WREB(WREB),
.RESETB(RSTB),
.OCEB(1'b0),
.ADB(ADB),
.DIB(DIB),
.DOB(DOB),
);
end else begin
wire [17:0] DIA = PORT_A_WR_DATA;
wire [17:0] DIB = PORT_B_WR_DATA;
wire [17:0] DOA;
wire [17:0] DOB;
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
DPX9 #(
`INIT(init_slice_x9)
.READ_MODE0(1'b0),
.READ_MODE1(1'b0),
.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
.BIT_WIDTH_0(PORT_A_WIDTH),
.BIT_WIDTH_1(PORT_B_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_A_CLK),
.CEA(PORT_A_CLK_EN),
.WREA(WREA),
.RESETA(RSTA),
.OCEA(1'b0),
.ADA(ADA),
.DIA(DIA),
.DOA(DOA),
.CLKB(PORT_B_CLK),
.CEB(PORT_B_CLK_EN),
.WREB(WREB),
.RESETB(RSTB),
.OCEB(1'b0),
.ADB(ADB),
.DIB(DIB),
.DOB(DOB),
);
end
endgenerate
endmodule
module $__GOWIN_SDP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_R_WIDTH = 18;
parameter PORT_W_WIDTH = 18;
parameter PORT_W_WR_BE_WIDTH = 2;
input PORT_R_CLK;
input PORT_R_CLK_EN;
input PORT_R_RD_SRST;
input PORT_R_RD_ARST;
input [13:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
input PORT_W_CLK;
input PORT_W_CLK_EN;
input PORT_W_WR_EN;
input [13:0] PORT_W_ADDR;
input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
`DEF_FUNCS
wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
wire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);
wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
generate
if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
wire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);
wire [31:0] DO;
assign PORT_R_RD_DATA = `x8_rd_data(DO);
SDP #(
`INIT(init_slice_x8)
.READ_MODE(1'b0),
.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),
.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN),
.WREA(WRE),
.RESETA(1'b0),
.ADA(ADW),
.DI(DI),
.CLKB(PORT_R_CLK),
.CEB(PORT_R_CLK_EN),
.WREB(1'b0),
.RESETB(RST),
.OCE(1'b0),
.ADB(PORT_R_ADDR),
.DO(DO),
);
end else begin
wire [35:0] DI = PORT_W_WR_DATA;
wire [35:0] DO;
assign PORT_R_RD_DATA = DO;
SDPX9 #(
`INIT(init_slice_x9)
.READ_MODE(1'b0),
.BIT_WIDTH_0(PORT_W_WIDTH),
.BIT_WIDTH_1(PORT_R_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN),
.WREA(WRE),
.RESETA(1'b0),
.ADA(ADW),
.DI(DI),
.CLKB(PORT_R_CLK),
.CEB(PORT_R_CLK_EN),
.WREB(1'b0),
.RESETB(RST),
.OCE(1'b0),
.ADB(PORT_R_ADDR),
.DO(DO),
);
end
endgenerate
endmodule

177
resources/netlist/resources/kernel/share/gowin/cells_map.v
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@ -1,177 +0,0 @@
`default_nettype none
//All DFF* have INIT, but the hardware is always initialised to the reset
//value regardless. The parameter is ignored.
// DFFN D Flip-Flop with Negative-Edge Clock
module \$_DFF_N_ (input D, C, output Q);
DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFF D Flip-Flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFE D Flip-Flop with Clock Enable
module \$_DFFE_PP_ (input D, C, E, output Q);
DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
module \$_DFFE_NP_ (input D, C, E, output Q);
DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFR D Flip-Flop with Synchronous Reset
module \$_SDFF_PP0_ (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
module \$_SDFF_NP0_ (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFS D Flip-Flop with Synchronous Set
module \$_SDFF_PP1_ (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
module \$_SDFF_NP1_ (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFP D Flip-Flop with Asynchronous Preset
module \$_DFF_PP1_ (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
module \$_DFF_NP1_ (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFC D Flip-Flop with Asynchronous Clear
module \$_DFF_PP0_ (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
module \$_DFF_NP0_ (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
end else
if (WIDTH == 6) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

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resources/netlist/resources/kernel/share/gowin/cells_sim.v
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resources/netlist/resources/kernel/share/gowin/lutrams.txt
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ram distributed $__GOWIN_LUTRAM_ {
abits 4;
width 4;
cost 4;
widthscale;
init no_undef;
prune_rom;
port sw "W" {
clock posedge;
}
port ar "R" {
}
}

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resources/netlist/resources/kernel/share/gowin/lutrams_map.v
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module $__GOWIN_LUTRAM_(...);
parameter INIT = 64'bx;
parameter BITS_USED = 0;
input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input PORT_W_WR_EN;
input [3:0] PORT_W_WR_DATA;
input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
function [15:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 16; i = i + 1)
init_slice[i] = INIT[4*i+idx];
endfunction
generate
casez(BITS_USED)
4'b000z:
RAM16SDP1 #(
.INIT_0(init_slice(0)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA[0]),
.DO(PORT_R_RD_DATA[0]),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
4'b00zz:
RAM16SDP2 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA[1:0]),
.DO(PORT_R_RD_DATA[1:0]),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
default:
RAM16SDP4 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
.INIT_2(init_slice(2)),
.INIT_3(init_slice(3)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA),
.DO(PORT_R_RD_DATA),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endcase
endgenerate
endmodule

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resources/netlist/resources/kernel/share/greenpak4/cells_blackbox.v
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module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output reg OUT;
output reg[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = "1";
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
endmodule

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resources/netlist/resources/kernel/share/greenpak4/cells_latch.v
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module $_DLATCH_P_(input E, input D, output Q);
GP_DLATCH _TECHMAP_REPLACE_ (
.D(D),
.nCLK(!E),
.Q(Q)
);
endmodule
module $_DLATCH_N_(input E, input D, output Q);
GP_DLATCH _TECHMAP_REPLACE_ (
.D(D),
.nCLK(E),
.Q(Q)
);
endmodule

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resources/netlist/resources/kernel/share/greenpak4/cells_map.v
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module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DFFSR #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.CLK(CLK),
.nSR(nSET),
.Q(Q)
);
endmodule
module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DFFSR #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.CLK(CLK),
.nSR(nRST),
.Q(Q)
);
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DFFSRI #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.CLK(CLK),
.nSR(nSET),
.nQ(nQ)
);
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DFFSRI #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.CLK(CLK),
.nSR(nRST),
.nQ(nQ)
);
endmodule
module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSR #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nSET),
.Q(Q)
);
endmodule
module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSR #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nRST),
.Q(Q)
);
endmodule
module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSRI #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nSET),
.nQ(nQ)
);
endmodule
module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSRI #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nRST),
.nQ(nQ)
);
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
GP_IOBUF _TECHMAP_REPLACE_ (
.IN(IN),
.OE(OE),
.IO(OUT),
.OUT()
);
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
if(LUT == 2'b01) begin
GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
end
else begin
GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
.IN0(A[0]), .IN1(1'b0));
end
end else
if (WIDTH == 2) begin
GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
.IN0(A[0]), .IN1(A[1]));
end else
if (WIDTH == 3) begin
GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
end else
if (WIDTH == 4) begin
GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output reg OUT;
(* force_downto *)
output reg[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = 0;
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
//If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
if(DIRECTION != "DOWN") begin
initial begin
$display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
$finish;
end
end
//If counter is more than 14 bits wide, complain (also shouldn't happen)
else if(WIDTH > 14) begin
initial begin
$display("ERROR: \$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
$finish;
end
end
//If counter is more than 8 bits wide and has parallel output, we have a problem
else if(WIDTH > 8 && HAS_POUT) begin
initial begin
$display("ERROR: \$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
$finish;
end
end
//Looks like a legal counter! Do something with it
else if(WIDTH <= 8) begin
if(HAS_CE) begin
wire ce_not;
GP_INV ceinv(
.IN(CE),
.OUT(ce_not)
);
GP_COUNT8_ADV #(
.COUNT_TO(COUNT_TO),
.RESET_MODE(RESET_MODE),
.RESET_VALUE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
.CLKIN_DIVIDE(1)
) _TECHMAP_REPLACE_ (
.CLK(CLK),
.RST(RST),
.OUT(OUT),
.UP(1'b0), //always count down for now
.KEEP(ce_not),
.POUT(POUT)
);
end
else begin
GP_COUNT8 #(
.COUNT_TO(COUNT_TO),
.RESET_MODE(RESET_MODE),
.CLKIN_DIVIDE(1)
) _TECHMAP_REPLACE_ (
.CLK(CLK),
.RST(RST),
.OUT(OUT),
.POUT(POUT)
);
end
end
else begin
if(HAS_CE) begin
wire ce_not;
GP_INV ceinv(
.IN(CE),
.OUT(ce_not)
);
GP_COUNT14_ADV #(
.COUNT_TO(COUNT_TO),
.RESET_MODE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
.RESET_VALUE("COUNT_TO"),
.CLKIN_DIVIDE(1)
) _TECHMAP_REPLACE_ (
.CLK(CLK),
.RST(RST),
.OUT(OUT),
.UP(1'b0), //always count down for now
.KEEP(ce_not),
.POUT(POUT)
);
end
else begin
GP_COUNT14 #(
.COUNT_TO(COUNT_TO),
.RESET_MODE(RESET_MODE),
.CLKIN_DIVIDE(1)
) _TECHMAP_REPLACE_ (
.CLK(CLK),
.RST(RST),
.OUT(OUT)
);
end
end
endmodule

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resources/netlist/resources/kernel/share/greenpak4/cells_sim.v
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`timescale 1ns/1ps
`include "cells_sim_ams.v"
`include "cells_sim_digital.v"
`include "cells_sim_wip.v"

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resources/netlist/resources/kernel/share/greenpak4/cells_sim_ams.v
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`timescale 1ns/1ps
/*
This file contains analog / mixed signal cells, or other things that are not possible to fully model
in behavioral Verilog.
It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
TODO: do we want a third file for those cells?
*/
module GP_ABUF(input wire IN, output wire OUT);
assign OUT = IN;
//must be 1, 5, 20, 50
//values >1 only available with Vdd > 2.7V
parameter BANDWIDTH_KHZ = 1;
endmodule
module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
parameter BANDWIDTH = "HIGH";
parameter VIN_ATTEN = 1;
parameter VIN_ISRC_EN = 0;
parameter HYSTERESIS = 0;
initial OUT = 0;
endmodule
module GP_BANDGAP(output reg OK);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;
parameter OUT_DELAY = 100;
endmodule
module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
initial VOUT = 0;
//analog hard IP is not supported for simulation
endmodule
module GP_LFOSC(input PWRDN, output reg CLKOUT);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;
initial CLKOUT = 0;
//auto powerdown not implemented for simulation
//output dividers not implemented for simulation
always begin
if(PWRDN)
CLKOUT = 0;
else begin
//half period of 1730 Hz
#289017;
CLKOUT = ~CLKOUT;
end
end
endmodule
module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
parameter GAIN = 1;
parameter INPUT_MODE = "SINGLE";
initial VOUT = 0;
//cannot simulate mixed signal IP
endmodule
module GP_PWRDET(output reg VDD_LOW);
initial VDD_LOW = 0;
endmodule
module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500;
initial begin
RST_DONE = 0;
if(POR_TIME == 4)
#4000;
else if(POR_TIME == 500)
#500000;
else begin
$display("ERROR: bad POR_TIME for GP_POR cell");
$finish;
end
RST_DONE = 1;
end
endmodule

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resources/netlist/resources/kernel/share/greenpak4/cells_sim_digital.v
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`timescale 1ns/1ps
/*
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
behavioral Verilog constructs only.
*/
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule
module GP_3LUT(input IN0, IN1, IN2, output OUT);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule
module GP_4LUT(
input wire IN0,
input wire IN1,
input wire IN2,
input wire IN3,
output wire OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
reg[13:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 14'h0);
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[13:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 14'h3fff);
else
OUT <= (count == 14'h0);
POUT <= count[7:0];
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
reg[7:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 8'hff);
else
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8(
input wire CLK,
input wire RST,
output reg OUT,
output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[7:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_DCMPREF(output reg[7:0]OUT);
parameter[7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule
module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
always @(*) begin
case(SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end
2'd01: begin
OUTA <= IN1;
OUTB <= IN2;
end
2'd02: begin
OUTA <= IN2;
OUTB <= IN1;
end
2'd03: begin
OUTA <= IN3;
OUTB <= IN0;
end
endcase
end
endmodule
module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
initial OUT = 0;
generate
if(GLITCH_FILTER) begin
initial begin
$display("ERROR: GP_DELAY glitch filter mode not implemented");
$finish;
end
end
//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
always @(*) begin
case(DELAY_STEPS)
1: #166 OUT = IN;
2: #318 OUT = IN;
2: #471 OUT = IN;
3: #622 OUT = IN;
default: begin
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
$finish;
end
endcase
end
endgenerate
endmodule
module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule
module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK) begin
nQ <= ~D;
end
endmodule
module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
nQ <= 1'b1;
else
nQ <= ~D;
end
endmodule
module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
nQ <= 1'b0;
else
nQ <= ~D;
end
endmodule
module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule
module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
nQ <= ~SRMODE;
else
nQ <= ~D;
end
endmodule
module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nRST)
nQ <= 1'b1;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSET)
nQ <= 1'b0;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSR)
nQ <= ~SRMODE;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule
module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule
module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg[3:0] count = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
count <= 0;
else begin
count <= count - 1'h1;
if(count == 0)
count <= COUNT_MAX;
end
end
always @(*)
OUT = PATTERN_DATA[count];
endmodule
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;
reg[15:0] shreg = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
shreg = 0;
else
shreg <= {shreg[14:0], IN};
end
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_TAP - 1];
endmodule
module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP_VSS(output OUT);
assign OUT = 0;
endmodule

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//Cells still in this file have INCOMPLETE simulation models, need to finish them
module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
parameter PWRDN_SYNC = 1'b0;
parameter CLK_EDGE = "RISING";
parameter GREATER_OR_EQUAL = 1'b0;
//TODO implement power-down mode
initial GREATER = 0;
initial EQUAL = 0;
wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
always @(posedge clk_minv) begin
if(GREATER_OR_EQUAL)
GREATER <= (INP >= INN);
else
GREATER <= (INP > INN);
EQUAL <= (INP == INN);
end
endmodule
module GP_EDGEDET(input IN, output reg OUT);
parameter EDGE_DIRECTION = "RISING";
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
//not implemented for simulation
endmodule
module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
parameter OSC_FREQ = "25k";
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
if(OSC_FREQ == "25k") begin
//half period of 25 kHz
#20000;
end
else begin
//half period of 2 MHz
#250;
end
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
//half period of 27 MHz
#18.518;
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_SPI(
input SCK,
inout SDAT,
input CSN,
input[7:0] TXD_HIGH,
input[7:0] TXD_LOW,
output reg[7:0] RXD_HIGH,
output reg[7:0] RXD_LOW,
output reg INT);
initial RXD_HIGH = 0;
initial RXD_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width
parameter SPI_CPHA = 0; //SPI clock phase
parameter SPI_CPOL = 0; //SPI clock polarity
parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
//parallel output to fabric not yet implemented
//TODO: write sim model
//TODO: SPI SDIO control... can we use ADC output while SPI is input??
//TODO: clock sync
endmodule
//keep constraint needed to prevent optimization since we have no outputs
(* keep *)
module GP_SYSRESET(input RST);
parameter RESET_MODE = "EDGE";
parameter EDGE_SPEED = 4;
//cannot simulate whole system reset
endmodule

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library(gp_dff) {
cell(GP_DFF) {
area: 1;
ff("IQ", "IQN") { clocked_on: CLK;
next_state: D; }
pin(CLK) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
cell(GP_DFFS) {
area: 1;
ff("IQ", "IQN") { clocked_on: CLK;
next_state: D;
preset: "nSET'"; }
pin(CLK) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(nSET) { direction: input; }
}
cell(GP_DFFR) {
area: 1;
ff("IQ", "IQN") { clocked_on: CLK;
next_state: D;
clear: "nRST'"; }
pin(CLK) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(nRST) { direction: input; }
}
}

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resources/netlist/resources/kernel/share/ice40/abc9_model.v
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(* abc9_box, lib_whitebox *)
module \$__ICE40_CARRY_WRAPPER (
(* abc9_carry *)
output CO,
output O,
input A, B,
(* abc9_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
parameter I3_IS_CI = 0;
wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3_OR_CI),
.O(O)
);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
(CI => CO) = (126, 105);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (449, 386);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
(A => CO) = (259, 245);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
(A => O) = (400, 379);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
(B => CO) = (231, 133);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
(B => O) = (379, 351);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (316, 288);
(CI => O) = (316, 288);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
(CI => CO) = (186, 155);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (662, 569);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
(A => CO) = (382, 362);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
(A => O) = (589, 558);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
(B => CO) = (341, 196);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
(B => O) = (558, 517);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (465, 423);
(CI => O) = (465, 423);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
(CI => CO) = (278, 278);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
(I0 => O) = (1245, 1285);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
(A => CO) = (675, 662);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
(A => O) = (1179, 1232);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
(B => CO) = (609, 358);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
(B => O) = (1179, 1205);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
(I3 => O) = (861, 874);
(CI => O) = (861, 874);
endspecify
`endif
endmodule

75
resources/netlist/resources/kernel/share/ice40/arith_map.v
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@ -1,75 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
\$__ICE40_CARRY_WRAPPER #(
// A[0]: 1010 1010 1010 1010
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(16'b 0110_1001_1001_0110),
.I3_IS_CI(1'b1)
) carry (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.I0(1'b0),
.I3(1'bx),
.CO(CO[i]),
.O(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule

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resources/netlist/resources/kernel/share/ice40/brams.txt
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@ -1,23 +0,0 @@
ram block $__ICE40_RAM4K_ {
abits 11;
widths 2 4 8 16 per_port;
cost 64;
option "HAS_BE" 1 {
byte 1;
}
init any;
port sw "W" {
option "HAS_BE" 0 {
width 2 4 8;
}
option "HAS_BE" 1 {
width 16;
wrbe_separate;
}
clock anyedge;
}
port sr "R" {
clock anyedge;
rden;
}
}

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resources/netlist/resources/kernel/share/ice40/brams_map.v
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@ -1,218 +0,0 @@
module $__ICE40_RAM4K_ (...);
parameter INIT = 0;
parameter OPTION_HAS_BE = 1;
parameter PORT_R_WIDTH = 16;
parameter PORT_W_WIDTH = 16;
parameter PORT_W_WR_BE_WIDTH = 16;
parameter PORT_R_CLK_POL = 1;
parameter PORT_W_CLK_POL = 1;
input PORT_R_CLK;
input PORT_R_RD_EN;
input [10:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
input PORT_W_CLK;
input PORT_W_WR_EN;
input [15:0] PORT_W_WR_BE;
input [10:0] PORT_W_ADDR;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
wire [15:0] RDATA;
wire [15:0] WDATA;
wire [15:0] MASK;
wire [10:0] RADDR = {PORT_R_ADDR[0], PORT_R_ADDR[1], PORT_R_ADDR[2], PORT_R_ADDR[10:3]};
wire [10:0] WADDR = {PORT_W_ADDR[0], PORT_W_ADDR[1], PORT_W_ADDR[2], PORT_W_ADDR[10:3]};
function [1:0] mode;
input integer width;
case (width)
16: mode = 0;
8: mode = 1;
4: mode = 2;
2: mode = 3;
endcase
endfunction
function [255:0] slice_init;
input [3:0] idx;
integer i;
reg [7:0] ri;
reg [11:0] a;
for (i = 0; i < 256; i = i + 1) begin
ri = i;
a = {idx, ri[7:4], ri[0], ri[1], ri[2], ri[3]};
slice_init[i] = INIT[a];
end
endfunction
`define INSTANCE(type, rclk, wclk) \
type #( \
.INIT_0(slice_init(0)), \
.INIT_1(slice_init(1)), \
.INIT_2(slice_init(2)), \
.INIT_3(slice_init(3)), \
.INIT_4(slice_init(4)), \
.INIT_5(slice_init(5)), \
.INIT_6(slice_init(6)), \
.INIT_7(slice_init(7)), \
.INIT_8(slice_init(8)), \
.INIT_9(slice_init(9)), \
.INIT_A(slice_init(10)), \
.INIT_B(slice_init(11)), \
.INIT_C(slice_init(12)), \
.INIT_D(slice_init(13)), \
.INIT_E(slice_init(14)), \
.INIT_F(slice_init(15)), \
.READ_MODE(mode(PORT_R_WIDTH)), \
.WRITE_MODE(mode(PORT_W_WIDTH)) \
) _TECHMAP_REPLACE_ ( \
.RDATA(RDATA), \
.rclk(PORT_R_CLK), \
.RCLKE(PORT_R_RD_EN), \
.RE(1'b1), \
.RADDR(RADDR), \
.WDATA(WDATA), \
.wclk(PORT_W_CLK), \
.WCLKE(PORT_W_WR_EN), \
.WE(1'b1), \
.WADDR(WADDR), \
.MASK(MASK), \
);
generate
case(PORT_R_WIDTH)
2: begin
assign PORT_R_RD_DATA = {
RDATA[11],
RDATA[3]
};
end
4: begin
assign PORT_R_RD_DATA = {
RDATA[13],
RDATA[5],
RDATA[9],
RDATA[1]
};
end
8: begin
assign PORT_R_RD_DATA = {
RDATA[14],
RDATA[6],
RDATA[10],
RDATA[2],
RDATA[12],
RDATA[4],
RDATA[8],
RDATA[0]
};
end
16: begin
assign PORT_R_RD_DATA = {
RDATA[15],
RDATA[7],
RDATA[11],
RDATA[3],
RDATA[13],
RDATA[5],
RDATA[9],
RDATA[1],
RDATA[14],
RDATA[6],
RDATA[10],
RDATA[2],
RDATA[12],
RDATA[4],
RDATA[8],
RDATA[0]
};
end
endcase
case(PORT_W_WIDTH)
2: begin
assign {
WDATA[11],
WDATA[3]
} = PORT_W_WR_DATA;
end
4: begin
assign {
WDATA[13],
WDATA[5],
WDATA[9],
WDATA[1]
} = PORT_W_WR_DATA;
end
8: begin
assign {
WDATA[14],
WDATA[6],
WDATA[10],
WDATA[2],
WDATA[12],
WDATA[4],
WDATA[8],
WDATA[0]
} = PORT_W_WR_DATA;
end
16: begin
assign WDATA = {
PORT_W_WR_DATA[15],
PORT_W_WR_DATA[7],
PORT_W_WR_DATA[11],
PORT_W_WR_DATA[3],
PORT_W_WR_DATA[13],
PORT_W_WR_DATA[5],
PORT_W_WR_DATA[9],
PORT_W_WR_DATA[1],
PORT_W_WR_DATA[14],
PORT_W_WR_DATA[6],
PORT_W_WR_DATA[10],
PORT_W_WR_DATA[2],
PORT_W_WR_DATA[12],
PORT_W_WR_DATA[4],
PORT_W_WR_DATA[8],
PORT_W_WR_DATA[0]
};
assign MASK = ~{
PORT_W_WR_BE[15],
PORT_W_WR_BE[7],
PORT_W_WR_BE[11],
PORT_W_WR_BE[3],
PORT_W_WR_BE[13],
PORT_W_WR_BE[5],
PORT_W_WR_BE[9],
PORT_W_WR_BE[1],
PORT_W_WR_BE[14],
PORT_W_WR_BE[6],
PORT_W_WR_BE[10],
PORT_W_WR_BE[2],
PORT_W_WR_BE[12],
PORT_W_WR_BE[4],
PORT_W_WR_BE[8],
PORT_W_WR_BE[0]
};
end
endcase
if (PORT_R_CLK_POL) begin
if (PORT_W_CLK_POL) begin
`INSTANCE(SB_RAM40_4K, RCLK, WCLK)
end else begin
`INSTANCE(SB_RAM40_4KNW, RCLK, WCLKN)
end
end else begin
if (PORT_W_CLK_POL) begin
`INSTANCE(SB_RAM40_4KNR, RCLKN, WCLK)
end else begin
`INSTANCE(SB_RAM40_4KNRNW, RCLKN, WCLKN)
end
end
endgenerate
endmodule

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resources/netlist/resources/kernel/share/ice40/cells_map.v
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@ -1,32 +0,0 @@
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
end else
if (WIDTH == 2) begin
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(1'b0), .I2(A[0]), .I3(A[1]));
end else
if (WIDTH == 3) begin
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(A[0]), .I2(A[1]), .I3(A[2]));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

3502
resources/netlist/resources/kernel/share/ice40/cells_sim.v
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34
resources/netlist/resources/kernel/share/ice40/dsp_map.v
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@ -1,34 +0,0 @@
module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
SB_MAC16 #(
.NEG_TRIGGER(1'b0),
.C_REG(1'b0),
.A_REG(1'b0),
.B_REG(1'b0),
.D_REG(1'b0),
.TOP_8x8_MULT_REG(1'b0),
.BOT_8x8_MULT_REG(1'b0),
.PIPELINE_16x16_MULT_REG1(1'b0),
.PIPELINE_16x16_MULT_REG2(1'b0),
.TOPOUTPUT_SELECT(2'b11),
.TOPADDSUB_LOWERINPUT(2'b0),
.TOPADDSUB_UPPERINPUT(1'b0),
.TOPADDSUB_CARRYSELECT(2'b0),
.BOTOUTPUT_SELECT(2'b11),
.BOTADDSUB_LOWERINPUT(2'b0),
.BOTADDSUB_UPPERINPUT(1'b0),
.BOTADDSUB_CARRYSELECT(2'b0),
.MODE_8x8(1'b0),
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED)
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.O(Y),
);
endmodule

25
resources/netlist/resources/kernel/share/ice40/ff_map.v
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@ -1,25 +0,0 @@
module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_NP0P_ (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_NP1P_ (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_PP0P_ (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_DFFE_PP1P_ (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFF_NP0_ (input D, C, R, output Q); SB_DFFNSR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFF_NP1_ (input D, C, R, output Q); SB_DFFNSS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFF_PP0_ (input D, C, R, output Q); SB_DFFSR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFF_PP1_ (input D, C, R, output Q); SB_DFFSS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFFCE_NP0P_ (input D, C, E, R, output Q); SB_DFFNESR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFFCE_NP1P_ (input D, C, E, R, output Q); SB_DFFNESS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); SB_DFFESR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule
module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); SB_DFFESS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule

11
resources/netlist/resources/kernel/share/ice40/latches_map.v
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module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

12
resources/netlist/resources/kernel/share/ice40/spram.txt
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@ -1,12 +0,0 @@
ram huge $__ICE40_SPRAM_ {
abits 14;
width 16;
cost 2048;
byte 4;
port srsw "A" {
clock posedge;
clken;
wrbe_separate;
rdwr no_change;
}
}

24
resources/netlist/resources/kernel/share/ice40/spram_map.v
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@ -1,24 +0,0 @@
module $__ICE40_SPRAM_ (...);
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input [3:0] PORT_A_WR_BE;
input [13:0] PORT_A_ADDR;
input [15:0] PORT_A_WR_DATA;
output [15:0] PORT_A_RD_DATA;
SB_SPRAM256KA _TECHMAP_REPLACE_ (
.ADDRESS(PORT_A_ADDR),
.DATAIN(PORT_A_WR_DATA),
.MASKWREN(PORT_A_WR_BE),
.WREN(PORT_A_WR_EN),
.CHIPSELECT(PORT_A_CLK_EN),
.CLOCK(PORT_A_CLK),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(PORT_A_RD_DATA),
);
endmodule

1616
resources/netlist/resources/kernel/share/include/backends/cxxrtl/cxxrtl.h
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