fix bug of non await

This commit is contained in:
锦恢 2023-11-27 20:23:52 +08:00
parent 6773a3df94
commit 6e95e656f0
2 changed files with 6 additions and 6 deletions

View File

@ -1,8 +1,8 @@
const { vlogFast } = require('../resources/hdlParser'); const { vlogFast } = require('../../resources/hdlParser');
const testFile = 'c:/Users/11934/Project/Digital-IDE/Digital-Test/Verilog/dependence_test/parent.v'; const testFile = 'c:/Users/11934/Project/Digital-IDE/Digital-Test/Verilog/dependence_test/parent.v';
(async () => { (async () => {
const fast = vlogFast(testFile); const fast = await vlogFast(testFile);
console.log(JSON.stringify(fast, null, ' ')); console.log(JSON.stringify(fast, null, ' '));
})(); })();

View File

@ -4,23 +4,23 @@ import { HdlLangID } from '../global/enum';
import { AbsPath } from '../global'; import { AbsPath } from '../global';
namespace HdlSymbol { namespace HdlSymbol {
export async function fast(path: AbsPath): Promise<Fast | undefined> { export function fast(path: AbsPath): Promise<Fast | undefined> {
const langID = hdlFile.getLanguageId(path); const langID = hdlFile.getLanguageId(path);
switch (langID) { switch (langID) {
case HdlLangID.Verilog: return vlogFast(path); case HdlLangID.Verilog: return vlogFast(path);
case HdlLangID.Vhdl: return vhdlFast(path); case HdlLangID.Vhdl: return vhdlFast(path);
case HdlLangID.SystemVerilog: return svFast(path); case HdlLangID.SystemVerilog: return svFast(path);
default: return undefined; default: return new Promise(resolve => resolve(undefined));
} }
} }
export async function all(path: AbsPath): Promise<All | undefined> { export function all(path: AbsPath): Promise<All | undefined> {
const langID = hdlFile.getLanguageId(path); const langID = hdlFile.getLanguageId(path);
switch (langID) { switch (langID) {
case HdlLangID.Verilog: return vlogAll(path); case HdlLangID.Verilog: return vlogAll(path);
case HdlLangID.Vhdl: return vhdlAll(path); case HdlLangID.Vhdl: return vhdlAll(path);
case HdlLangID.SystemVerilog: return svAll(path); case HdlLangID.SystemVerilog: return svAll(path);
default: return undefined; default: return new Promise(resolve => resolve(undefined));
} }
} }
} }