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完成 SSI 计算逻辑修复 | 修复 TCL 刷新 XPR 的设计源添加逻辑漏洞

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锦恢 2024-11-26 21:38:23 +08:00
parent 70088a0a24
commit 951f831f63
26 changed files with 526 additions and 393 deletions
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4
l10n/bundle.l10n.de.json
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@ -69,5 +69,7 @@
"info.pl.xilinx.update-addfiles": "Datei zu Xilinx-Projekt hinzufügen", "info.pl.xilinx.update-addfiles": "Datei zu Xilinx-Projekt hinzufügen",
"info.pl.xilinx.update-delfiles": "Löschen Sie die folgenden Dateien aus dem Xilinx-Projekt.", "info.pl.xilinx.update-delfiles": "Löschen Sie die folgenden Dateien aus dem Xilinx-Projekt.",
"info.pl.xilinx.no-need-add-files": "Keine Dateien zum Hinzufügen zum Xilinx-Projekt", "info.pl.xilinx.no-need-add-files": "Keine Dateien zum Hinzufügen zum Xilinx-Projekt",
"info.pl.xilinx.no-need-del-files": "Es müssen keine Dateien aus Xilinx gelöscht werden." "info.pl.xilinx.no-need-del-files": "Es müssen keine Dateien aus Xilinx gelöscht werden.",
"error.pl.launch.not-valid-vivado-path": "Fehler beim Starten des Vivado TCL-Skriptinterpreters: {0}. Bitte überprüfen Sie, ob der Startpfad für Vivado korrekt ist. Derzeit eingestellter Startordnerpfad für Vivado: {1}",
"info.pl.launch.set-vivado-path": "Zur Einstellung des Vivado-Installationspfads gehen"
} }

4
l10n/bundle.l10n.en.json
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@ -69,5 +69,7 @@
"info.pl.xilinx.update-addfiles": "Add file to Xilinx project", "info.pl.xilinx.update-addfiles": "Add file to Xilinx project",
"info.pl.xilinx.update-delfiles": "Delete the following files from the Xilinx project.", "info.pl.xilinx.update-delfiles": "Delete the following files from the Xilinx project.",
"info.pl.xilinx.no-need-add-files": "No files need to be added to the Xilinx project", "info.pl.xilinx.no-need-add-files": "No files need to be added to the Xilinx project",
"info.pl.xilinx.no-need-del-files": "There are no files to be deleted from Xilinx." "info.pl.xilinx.no-need-del-files": "There are no files to be deleted from Xilinx.",
"error.pl.launch.not-valid-vivado-path": "Error encountered while starting the Vivado TCL script interpreter: {0}. Please check if your Vivado startup path is correct. Currently set Vivado startup folder path: {1}",
"info.pl.launch.set-vivado-path": "Go to set the Vivado installation path"
} }

4
l10n/bundle.l10n.ja.json
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@ -69,5 +69,7 @@
"info.pl.xilinx.update-addfiles": "ファイルを Xilinx プロジェクトに追加", "info.pl.xilinx.update-addfiles": "ファイルを Xilinx プロジェクトに追加",
"info.pl.xilinx.update-delfiles": "以下のファイルをXilinxプロジェクトから削除してください。", "info.pl.xilinx.update-delfiles": "以下のファイルをXilinxプロジェクトから削除してください。",
"info.pl.xilinx.no-need-add-files": "Xilinx プロジェクトに追加するファイルはありません", "info.pl.xilinx.no-need-add-files": "Xilinx プロジェクトに追加するファイルはありません",
"info.pl.xilinx.no-need-del-files": "Xilinx から削除するファイルはありません。" "info.pl.xilinx.no-need-del-files": "Xilinx から削除するファイルはありません。",
"error.pl.launch.not-valid-vivado-path": "Vivado TCL スクリプトインタプリタの起動中にエラーが発生しました：{0}。Vivado の起動パスが正しいか確認してください。現在設定されている Vivado 起動フォルダパス：{1}",
"info.pl.launch.set-vivado-path": "Vivado インストールパスの設定に移動"
} }

4
l10n/bundle.l10n.zh-cn.json
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@ -69,5 +69,7 @@
"info.pl.xilinx.update-addfiles": "添加文件到 Xilinx 工程", "info.pl.xilinx.update-addfiles": "添加文件到 Xilinx 工程",
"info.pl.xilinx.update-delfiles": "将下方文件从 Xilinx 工程中删除", "info.pl.xilinx.update-delfiles": "将下方文件从 Xilinx 工程中删除",
"info.pl.xilinx.no-need-add-files": "没有需要添加到 Xilinx 工程的文件", "info.pl.xilinx.no-need-add-files": "没有需要添加到 Xilinx 工程的文件",
"info.pl.xilinx.no-need-del-files": "没有需要从 Xilinx 中删除的文件" "info.pl.xilinx.no-need-del-files": "没有需要从 Xilinx 中删除的文件",
"error.pl.launch.not-valid-vivado-path": "启动 Vivado TCL 脚本解释器遇到错误：{0} 。请检查你的 Vivado 启动路径是否正确，当前设置的 Vivado 启动文件夹路径：{1}",
"info.pl.launch.set-vivado-path": "前往设置 Vivado 安装路径"
} }

4
l10n/bundle.l10n.zh-tw.json
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@ -69,5 +69,7 @@
"info.pl.xilinx.update-addfiles": "將檔案新增到 Xilinx 專案", "info.pl.xilinx.update-addfiles": "將檔案新增到 Xilinx 專案",
"info.pl.xilinx.update-delfiles": "從 Xilinx 專案中刪除以下檔案。", "info.pl.xilinx.update-delfiles": "從 Xilinx 專案中刪除以下檔案。",
"info.pl.xilinx.no-need-add-files": "沒有需要添加到 Xilinx 工程的文件", "info.pl.xilinx.no-need-add-files": "沒有需要添加到 Xilinx 工程的文件",
"info.pl.xilinx.no-need-del-files": "沒有需要從 Xilinx 中刪除的檔案。" "info.pl.xilinx.no-need-del-files": "沒有需要從 Xilinx 中刪除的檔案。",
"error.pl.launch.not-valid-vivado-path": "啟動 Vivado TCL 腳本解釋器遇到錯誤：{0} 。請檢查你的 Vivado 啟動路徑是否正確，目前設定的 Vivado 啟動資料夾路徑：{1}",
"info.pl.launch.set-vivado-path": "前往設定 Vivado 安裝路徑"
} }

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resources/dide-lsp/static/xilinx/primitive.bin
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11
snippets/sdc.json
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@ -1,4 +1,13 @@
{ {
"clock": {
"prefix": "create_pll",
"body": [
"create_clock -period 20.000 [get_ports clock]",
"set_input_jitter [get_clocks -of_objects [get_ports clock]] 0.200",
"set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]"
]
},
"ILA_CORE": { "ILA_CORE": {
"prefix": "create_ILA_CORE", "prefix": "create_ILA_CORE",
"body": [ "body": [
@ -8,6 +17,7 @@
"connect_debug_port dbg_hub/clk [get_nets [list CLK_Global_u/clk_out${2:3}]]" "connect_debug_port dbg_hub/clk [get_nets [list CLK_Global_u/clk_out${2:3}]]"
] ]
}, },
"Debug_CORE": { "Debug_CORE": {
"prefix": "create_Debug_CORE", "prefix": "create_Debug_CORE",
"body": [ "body": [
@ -24,6 +34,7 @@
"connect_debug_port u_ila_$1/clk [get_nets [list CLK_Global_u/clk_out${3:3}]]" "connect_debug_port u_ila_$1/clk [get_nets [list CLK_Global_u/clk_out${3:3}]]"
] ]
}, },
"Debug_add_port": { "Debug_add_port": {
"prefix": "add_port", "prefix": "add_port",
"body": [ "body": [

291
snippets/svlog.json
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@ -1,210 +1,18 @@
{ {
"IDDR": { "counter": {
"prefix": "iddr", "prefix": "counter",
"body" : [
"IDDR #(",
" // \"OPPOSITE_EDGE\", \"SAME_EDGE\" or \"SAME_EDGE_PIPELINED\" ",
" .DDR_CLK_EDGE(\"SAME_EDGE\"), ",
" .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1",
" .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1",
" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
"IDDR_inst (",
"IDDR #(",
" .Q1(rx_data_pos), // 1-bit output for positive edge of clock ",
" .Q2(rx_data_neg), // 1-bit output for negative edge of clock",
" .C(data_clk), // 1-bit clock input",
" .CE(1'b1), // 1-bit clock enable input",
" .D(rx_data_dly), // 1-bit DDR data input",
" .R(1'b0), // 1-bit reset",
" .S(1'b0) // 1-bit set",
");"
]
},
"ODDR": {
"prefix": "oddr",
"body" : [
"ODDR #(",
" .DDR_CLK_EDGE(\"SAME_EDGE\"), // \"OPPOSITE_EDGE\" or \"SAME_EDGE\" ",
" .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1",
" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
"ODDR_inst (",
" .Q(odata), // 1-bit DDR output",
" .C(data_clk), // 1-bit clock input",
" .CE(1'b1), // 1-bit clock enable input",
" .D1(data_p), // 1-bit data input (positive edge)",
" .D2(data_n), // 1-bit data input (negative edge)",
" .R(1'b0), // 1-bit reset",
" .S(1'b0) // 1-bit set",
");"
]
},
"OBUFDS": {
"prefix": "obuf",
"body" : [
"OBUFDS #(",
" .IOSTANDARD(\"LVDS18\"), // Specify the output I/O standard",
" .SLEW(\"SLOW\")) // Specify the output slew rate",
"OBUFDS_inst (",
" .O(tx_frame_p), // Diff_p output (connect directly to top-level port)",
" .OB(tx_frame_n), // Diff_n output (connect directly to top-level port)",
" .I(tx_frame) // Buffer input ",
");"
]
},
"IBUFDS": {
"prefix": "ibuf",
"body" : [
"IBUFDS #(",
" .DIFF_TERM(\"FALSE\"), // Differential Termination",
" .IBUF_LOW_PWR(\"TRUE\"), // Low power=\"TRUE\", Highest performance=\"FALSE\" ",
" .IOSTANDARD(\"DEFAULT\")) // Specify the input I/O standard",
"IBUFDS_inst (",
" .O(data_clk_tmp), // Buffer output",
" .I(data_clk_p), // Diff_p buffer input (connect directly to top-level port)",
" .IB(data_clk_n) // Diff_n buffer input (connect directly to top-level port)",
");"
]
},
"OSERDESE2": {
"prefix": "oserd",
"body" : [
"OSERDESE2 #(",
" .DATA_RATE_OQ(\"DDR\"), // DDR, SDR",
" .DATA_RATE_TQ(\"DDR\"), // DDR, BUF, SDR",
" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
" .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)",
" .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)",
" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
" .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)",
" .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)",
" .TBYTE_CTL(\"FALSE\"), // Enable tristate byte operation (FALSE, TRUE)",
" .TBYTE_SRC(\"FALSE\"), // Tristate byte source (FALSE, TRUE)",
" .TRISTATE_WIDTH(4) // 3-state converter width (1,4)",
")",
"OSERDESE2_inst (",
" .OFB(OFB), // 1-bit output: Feedback path for data",
" .OQ(OQ), // 1-bit output: Data path output",
" // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)",
" .SHIFTOUT1(SHIFTOUT1),",
" .SHIFTOUT2(SHIFTOUT2),",
" .TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate",
" .TFB(TFB), // 1-bit output: 3-state control",
" .TQ(TQ), // 1-bit output: 3-state control",
" .CLK(CLK), // 1-bit input: High speed clock",
" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
" // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)",
" .D1(D1),",
" .D2(D2),",
" .D3(D3),",
" .D4(D4),",
" .D5(D5),",
" .D6(D6),",
" .D7(D7),",
" .D8(D8),",
" .OCE(OCE), // 1-bit input: Output data clock enable",
" .RST(RST), // 1-bit input: Reset",
" // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)",
" .SHIFTIN1(SHIFTIN1),",
" .SHIFTIN2(SHIFTIN2),",
" // T1 - T4: 1-bit (each) input: Parallel 3-state inputs",
" .T1(T1),",
" .T2(T2),",
" .T3(T3),",
" .T4(T4),",
" .TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate",
" .TCE(TCE) // 1-bit input: 3-state clock enable",
");"
]
},
"ISERDESE2": {
"prefix": "iserd",
"body" : [
"ISERDESE2 #(",
" .DATA_RATE(\"DDR\"), // DDR, SDR",
" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
" .DYN_CLKDIV_INV_EN(\"FALSE\"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)",
" .DYN_CLK_INV_EN(\"FALSE\"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)",
" // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)",
" .INIT_Q1(1'b0),",
" .INIT_Q2(1'b0),",
" .INIT_Q3(1'b0),",
" .INIT_Q4(1'b0),",
" .INTERFACE_TYPE(\"MEMORY\"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE",
" .IOBDELAY(\"NONE\"), // NONE, BOTH, IBUF, IFD",
" .NUM_CE(2), // Number of clock enables (1,2)",
" .OFB_USED(\"FALSE\"), // Select OFB path (FALSE, TRUE)",
" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
" // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)",
" .SRVAL_Q1(1'b0),",
" .SRVAL_Q2(1'b0),",
" .SRVAL_Q3(1'b0),",
" .SRVAL_Q4(1'b0))",
"ISERDESE2_inst (",
" .O(O), // 1-bit output: Combinatorial output",
" // Q1 - Q8: 1-bit (each) output: Registered data outputs",
" .Q1(Q1),",
" .Q2(Q2),",
" .Q3(Q3),",
" .Q4(Q4),",
" .Q5(Q5),",
" .Q6(Q6),",
" .Q7(Q7),",
" .Q8(Q8),",
" // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports",
" .SHIFTOUT1(SHIFTOUT1),",
" .SHIFTOUT2(SHIFTOUT2),",
"\n",
" // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to",
" // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1",
" // to Q8 output ports will shift, as in a barrel-shifter operation, one",
" // position every time Bitslip is invoked (DDR operation is different from",
" // SDR).",
" .BITSLIP(BITSLIP), ",
"\n",
" // CE1, CE2: 1-bit (each) input: Data register clock enable inputs",
" .CE1(CE1),",
" .CE2(CE2),",
" .CLKDIVP(CLKDIVP), // 1-bit input: TBD",
" // Clocks: 1-bit (each) input: ISERDESE2 clock input ports",
" .CLK(CLK), // 1-bit input: High-speed clock",
" .CLKB(CLKB), // 1-bit input: High-speed secondary clock",
" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
" .OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE=\"MEMORY\" ",
" // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity",
" .DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion",
" .DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion",
" // Input Data: 1-bit (each) input: ISERDESE2 data input ports",
" .D(D), // 1-bit input: Data input",
" .DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2",
" .OFB(OFB), // 1-bit input: Data feedback from OSERDESE2",
" .OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock",
" .RST(RST), // 1-bit input: Active high asynchronous reset",
" // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports",
" .SHIFTIN1(SHIFTIN1),",
" .SHIFTIN2(SHIFTIN2)",
");"
]
},
"count": {
"prefix": "count",
"body": [ "body": [
"//define the time counter", "//define the time counter",
"reg [${1:32}:0] cnt$2 = 0;",
"reg ${3:impulse};",
"parameter SET_TIME = $1'd$4;", "parameter SET_TIME = $1'd$4;",
"always@(posedge clk) begin", "reg [${1:32}:0] count$2;",
" if (cnt$2 == SET_TIME) begin", "reg ${3:impulse};",
" cnt$2 <= $1'd0;", "always@(posedge clock) begin",
" if (count$2 == SET_TIME) begin",
" count$2 <= $1'd0;",
" $3 <= 1'd1;", " $3 <= 1'd1;",
" end", " end",
" else begin", " else begin",
" cnt$2 <= cnt$2 + 1'd1;", " count$2 <= count$2 + 1'd1;",
" $3 <= 1'd0;", " $3 <= 1'd0;",
" end", " end",
"end" "end"
@ -214,15 +22,15 @@
"divclk": { "divclk": {
"prefix": "div", "prefix": "div",
"body": [ "body": [
"reg [${1:3}:0] cnt$2 = 0;", "reg [${1:3}:0] count$2;",
"reg clk_div$2;", "reg clk_div$2;",
"always@(posedge ${3:clk}) begin", "always@(posedge ${3:clock}) begin",
" if (cnt$2 == ${4:3}) begin", " if (count$2 == ${4:3}) begin",
" cnt$2 <= $1'd0;", " count$2 <= $1'd0;",
" clk_div$2 <= ~clk_div$2;", " clk_div$2 <= ~clk_div$2;",
" end", " end",
" else begin", " else begin",
" cnt$2 <= cnt$2 + 1'd1;", " count$2 <= count$2 + 1'd1;",
" end", " end",
"end" "end"
] ]
@ -234,10 +42,10 @@
"reg gate$2;", "reg gate$2;",
"reg gate$2_buf;", "reg gate$2_buf;",
"wire gate$2_pose = gate$2 & ~gate$2_buf;", "wire gate$2_pos = gate$2 & ~gate$2_buf;",
"wire gate$2_nege = ~gate$2 & gate$2_buf;", "wire gate$2_neg = ~gate$2 & gate$2_buf;",
"always@(posedge clk) begin", "always@(posedge clock) begin",
" gate$2 <= ${1:signal};", " gate$2 <= ${1:signal};",
" gate$2_buf <= gate$2;", " gate$2_buf <= gate$2;",
"end" "end"
@ -262,9 +70,9 @@
"prefix": "resetn", "prefix": "resetn",
"body": [ "body": [
"reg rst_n_s1, rst_n_s2;", "reg rst_n_s1, rst_n_s2;",
"wire rst_n", "wire sys_rstn",
"always @ (posedge clk or negedge sys_rst_n) begin", "always @ (posedge clock or negedge rstn) begin",
" if (sys_rst_n) begin", " if (rstn) begin",
" rst_n_s2 <= 1'b0;", " rst_n_s2 <= 1'b0;",
" rst_n_s1 <= 1'b0;", " rst_n_s1 <= 1'b0;",
" end", " end",
@ -272,18 +80,18 @@
" rst_n_s2 <= rst_n_s1;", " rst_n_s2 <= rst_n_s1;",
" end", " end",
"end", "end",
"assign rst_n = rst_n_s2;" "assign sys_rstn = rst_n_s2;"
], ],
"description" : "Asynchronous sys_rst_n synchronous release (intel device)" "description" : "Asynchronous sys_rstn synchronous release (intel device)"
}, },
"reset": { "reset": {
"prefix": "reset", "prefix": "reset",
"body": [ "body": [
"reg rst_s1, rst_s2;", "reg rst_s1, rst_s2;",
"wire rst", "wire sys_rst",
"always @ (posedge clk or posedge sys_rst) begin", "always @ (posedge clock or posedge reset) begin",
" if (sys_rst) begin", " if (reset) begin",
" rst_s2 <= 1'b0;", " rst_s2 <= 1'b0;",
" rst_s1 <= 1'b0;", " rst_s1 <= 1'b0;",
" end", " end",
@ -291,9 +99,9 @@
" rst_s2 <= rst_s1;", " rst_s2 <= rst_s1;",
" end", " end",
"end", "end",
"assign rst = rst_s2;" "assign sys_rst = rst_s2;"
], ],
"description" : "Asynchronous sys_rst synchronous release (xilinx device)" "description" : "Asynchronous reset synchronous release (xilinx device)"
}, },
"initial sim": { "initial sim": {
@ -369,18 +177,18 @@
"alwaysposclk": { "alwaysposclk": {
"prefix": "alclk", "prefix": "alclk",
"body": [ "body": [
"always @(posedge clk) begin", "always @(posedge clock) begin",
" $1;", " $1;",
"end" "end"
], ],
"description": "always @(posedge clk) directly" "description": "always @(posedge clock) directly"
}, },
"alwayssyncrst": { "alwayssyncrst": {
"prefix": "alsync", "prefix": "alsync",
"body": [ "body": [
"always @(posedge clk) begin", "always @(posedge clock) begin",
" if(rst) begin", " if(reset) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
" else begin", " else begin",
@ -394,8 +202,8 @@
"alwaysasyncrst": { "alwaysasyncrst": {
"prefix": "alasync", "prefix": "alasync",
"body": [ "body": [
"always @(posedge clk or posedge rst) begin", "always @(posedge clock or posedge reset) begin",
" if(rst) begin", " if(reset) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
" else begin", " else begin",
@ -409,8 +217,8 @@
"alwayssyncrstn": { "alwayssyncrstn": {
"prefix": "alsyncn", "prefix": "alsyncn",
"body": [ "body": [
"always @(posedge clk) begin", "always @(posedge clock) begin",
" if(!rst_n) begin", " if(!rstn) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
" else begin", " else begin",
@ -418,14 +226,14 @@
" end", " end",
"end" "end"
], ],
"description": "synchronous rst_n (intel device)" "description": "synchronous rstn (intel device)"
}, },
"alwaysasyncrstn": { "alwaysasyncrstn": {
"prefix": "alasyncn", "prefix": "alasyncn",
"body": [ "body": [
"always @(posedge clk or negedge rst_n) begin", "always @(posedge clock or negedge rstn) begin",
" if(!rst_n) begin", " if(!rstn) begin",
" $1 <= 0;", " $1 <= 0;",
" end", " end",
" else begin", " else begin",
@ -433,7 +241,7 @@
" end", " end",
"end" "end"
], ],
"description": "asynchronous rst_n (intel device)" "description": "asynchronous rstn (intel device)"
}, },
"beginend": { "beginend": {
@ -461,13 +269,13 @@
"prefix": "modp", "prefix": "modp",
"body": [ "body": [
"module ${1:name} #(", "module ${1:name} #(",
" parameter INPUT_WIDTH = ${2:12},", " parameter IWIDTH = ${2:12},",
" parameter OUTPUT_WIDTH = $2", " parameter OWIDTH = $2",
") (", ") (",
" input clk,", " input clock,",
" input RST,", " input reset,",
" input [INPUT_WIDTH - 1 : 0] ${3:data_i},", " input [IWIDTH - 1 : 0] ${3:data_i},",
" output [OUTPUT_WIDTH - 1 : 0] ${4:data_o}", " output [OWIDTH - 1 : 0] ${4:data_o}",
");", ");",
" $5", " $5",
"endmodule //$1\n" "endmodule //$1\n"
@ -479,8 +287,8 @@
"prefix": "mod", "prefix": "mod",
"body": [ "body": [
"module ${1:moduleName} (", "module ${1:moduleName} (",
" input clk,", " input clock,",
" input rst,", " input reset,",
" $2", " $2",
");", ");",
" $3", " $3",
@ -488,6 +296,7 @@
], ],
"description": "Insert a module without parameter" "description": "Insert a module without parameter"
}, },
"simple module": { "simple module": {
"prefix": "module", "prefix": "module",
"body": [ "body": [
@ -497,6 +306,7 @@
], ],
"description": "Insert a common module" "description": "Insert a common module"
}, },
"generate_for": { "generate_for": {
"prefix": "genfor", "prefix": "genfor",
"body": [ "body": [
@ -903,18 +713,21 @@
"*/" "*/"
] ]
}, },
"dumpfile": { "dumpfile": {
"prefix": "$dumpfile", "prefix": "$dumpfile",
"body": [ "body": [
"\\$dumpfile(\"$1\");" "\\$dumpfile(\"$1\");"
] ]
}, },
"dumpvars": { "dumpvars": {
"prefix": "$dumpvars", "prefix": "$dumpvars",
"body": [ "body": [
"\\$dumpvars;" "\\$dumpvars;"
] ]
}, },
"finish": { "finish": {
"prefix": "$finish", "prefix": "$finish",
"body": [ "body": [

18
snippets/tcl.json
View File

@ -8,6 +8,7 @@
], ],
"description": "For Loop" "description": "For Loop"
}, },
"foreach": { "foreach": {
"prefix": "foreach", "prefix": "foreach",
"body": [ "body": [
@ -17,6 +18,7 @@
], ],
"description": "Foreach Loop" "description": "Foreach Loop"
}, },
"if": { "if": {
"prefix": "if", "prefix": "if",
"body": [ "body": [
@ -26,6 +28,7 @@
], ],
"description": "If Condition" "description": "If Condition"
}, },
"elseif": { "elseif": {
"prefix": "elseif", "prefix": "elseif",
"body": [ "body": [
@ -35,6 +38,7 @@
], ],
"description": "ElseIf Condition" "description": "ElseIf Condition"
}, },
"else": { "else": {
"prefix": "else", "prefix": "else",
"body": [ "body": [
@ -44,6 +48,7 @@
], ],
"description": "Else Block" "description": "Else Block"
}, },
"proc": { "proc": {
"prefix": "proc", "prefix": "proc",
"body": [ "body": [
@ -53,6 +58,7 @@
], ],
"description": "Proc Block" "description": "Proc Block"
}, },
"while": { "while": {
"prefix": "while", "prefix": "while",
"body": [ "body": [
@ -62,6 +68,7 @@
], ],
"description": "While Loop" "description": "While Loop"
}, },
"catch": { "catch": {
"prefix": "catch", "prefix": "catch",
"body": [ "body": [
@ -69,6 +76,7 @@
], ],
"description": "Catch Block" "description": "Catch Block"
}, },
"try": { "try": {
"prefix": "try", "prefix": "try",
"body": [ "body": [
@ -80,6 +88,7 @@
], ],
"description": "Try Block" "description": "Try Block"
}, },
"switch": { "switch": {
"prefix": "switch", "prefix": "switch",
"body": [ "body": [
@ -90,6 +99,7 @@
], ],
"description": "Switch Block" "description": "Switch Block"
}, },
"oo::class create": { "oo::class create": {
"prefix": "oo::class create", "prefix": "oo::class create",
"body": [ "body": [
@ -105,6 +115,7 @@
], ],
"description": "Class Create" "description": "Class Create"
}, },
"tk_chooseDirectory": { "tk_chooseDirectory": {
"prefix": "tk_chooseDirectory", "prefix": "tk_chooseDirectory",
"body": [ "body": [
@ -112,6 +123,7 @@
], ],
"description": "Choose Directory" "description": "Choose Directory"
}, },
"tk_getOpenFile": { "tk_getOpenFile": {
"prefix": "tk_getOpenFile", "prefix": "tk_getOpenFile",
"body": [ "body": [
@ -122,6 +134,7 @@
], ],
"description": "Open File Dialog" "description": "Open File Dialog"
}, },
"tk_getSaveFile": { "tk_getSaveFile": {
"prefix": "tk_getSaveFile", "prefix": "tk_getSaveFile",
"body": [ "body": [
@ -132,6 +145,7 @@
], ],
"description": "Save File Dialog" "description": "Save File Dialog"
}, },
"tk_messageBox": { "tk_messageBox": {
"prefix": "tk_messageBox", "prefix": "tk_messageBox",
"body": [ "body": [
@ -139,6 +153,7 @@
], ],
"description": "Message Box" "description": "Message Box"
}, },
"set_property": { "set_property": {
"prefix": "set_property", "prefix": "set_property",
"body": [ "body": [
@ -146,18 +161,21 @@
], ],
"description": "set property" "description": "set property"
}, },
"create_clock": { "create_clock": {
"prefix": "create_clock", "prefix": "create_clock",
"body": [ "body": [
"create_clock ${1:signal_name} ${2:clock_name} ${3:frequency} ${4:uncertainty}" "create_clock ${1:signal_name} ${2:clock_name} ${3:frequency} ${4:uncertainty}"
] ]
}, },
"set_initial_state": { "set_initial_state": {
"prefix": "set_initial_state", "prefix": "set_initial_state",
"body": [ "body": [
"set_initial_5state ${1:initial_state}" "set_initial_5state ${1:initial_state}"
] ]
}, },
"connect_port": { "connect_port": {
"prefix": "connect_port", "prefix": "connect_port",
"body": [ "body": [

20
snippets/vhdl.json
View File

@ -5,120 +5,140 @@
"description": "asynchronous process", "description": "asynchronous process",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"arch": { "arch": {
"prefix": "arch", "prefix": "arch",
"body": "architecture ${1:arch} of ${2:ent} is\n\n\tsignal $0\n\nbegin\n\nend ${1:arch} ; -- ${1:arch}", "body": "architecture ${1:arch} of ${2:ent} is\n\n\tsignal $0\n\nbegin\n\nend ${1:arch} ; -- ${1:arch}",
"description": "architecture", "description": "architecture",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"case": { "case": {
"prefix": "case", "prefix": "case",
"body": "case( ${1:signal_name} ) is\n\n\twhen ${2:IDLE} =>\n\t\t$0\n\n\twhen others =>\n\nend case ;", "body": "case( ${1:signal_name} ) is\n\n\twhen ${2:IDLE} =>\n\t\t$0\n\n\twhen others =>\n\nend case ;",
"description": "case", "description": "case",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"else": { "else": {
"prefix": "else", "prefix": "else",
"body": "else\n\t$0", "body": "else\n\t$0",
"description": "else", "description": "else",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"elsif": { "elsif": {
"prefix": "elsif", "prefix": "elsif",
"body": "elsif ${1:expression} then\n\t$0", "body": "elsif ${1:expression} then\n\t$0",
"description": "elsif", "description": "elsif",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"ent": { "ent": {
"prefix": "ent", "prefix": "ent",
"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent};", "body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent};",
"description": "entity", "description": "entity",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"entarch": { "entarch": {
"prefix": "entarch", "prefix": "entarch",
"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ;\n\narchitecture ${2:arch} of ${1:ent} is\n\n\n\nbegin\n\n\n\nend architecture ; -- ${2:arch}", "body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ;\n\narchitecture ${2:arch} of ${1:ent} is\n\n\n\nbegin\n\n\n\nend architecture ; -- ${2:arch}",
"description": "entity architecture", "description": "entity architecture",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"for": { "for": {
"prefix": "for", "prefix": "for",
"body": "${1:identifier} : for ${2:i} in ${3:0} to ${4:10} loop\n\t$0\nend loop ; -- ${1:identifier}", "body": "${1:identifier} : for ${2:i} in ${3:0} to ${4:10} loop\n\t$0\nend loop ; -- ${1:identifier}",
"description": "for loop", "description": "for loop",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"forg": { "forg": {
"prefix": "forg", "prefix": "forg",
"body": "${1:identifier} : for ${2:i} in ${3:x} to ${4:y} generate\n\t$0\nend generate ; -- ${1:identifier}", "body": "${1:identifier} : for ${2:i} in ${3:x} to ${4:y} generate\n\t$0\nend generate ; -- ${1:identifier}",
"description": "for generate", "description": "for generate",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"if": { "if": {
"prefix": "if", "prefix": "if",
"body": "if ${1:expression} then\n\t$0\nend if ;", "body": "if ${1:expression} then\n\t$0\nend if ;",
"description": "if", "description": "if",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"pack": { "pack": {
"prefix": "pack", "prefix": "pack",
"body": "package ${1:pkg} is\n\t$0\nend package ;", "body": "package ${1:pkg} is\n\t$0\nend package ;",
"description": "package", "description": "package",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"pro": { "pro": {
"prefix": "pro", "prefix": "pro",
"body": "${1:identifier} : process( ${2:sensitivity_list} )\nbegin\n\t$0\nend process ; -- ${1:identifier}", "body": "${1:identifier} : process( ${2:sensitivity_list} )\nbegin\n\t$0\nend process ; -- ${1:identifier}",
"description": "process", "description": "process",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"s": { "s": {
"prefix": "s", "prefix": "s",
"body": "signed(${1:x} downto ${2:0}) ;$0", "body": "signed(${1:x} downto ${2:0}) ;$0",
"description": "signed downto", "description": "signed downto",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"sr": { "sr": {
"prefix": "sr", "prefix": "sr",
"body": "signed(${1:signal}'range) ;$0", "body": "signed(${1:signal}'range) ;$0",
"description": "signed range", "description": "signed range",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"spro": { "spro": {
"prefix": "spro", "prefix": "spro",
"body": "${1:identifier} : process( ${2:clock} )\nbegin\n\tif( rising_edge(${2:clock}) ) then\n\t\t$0\n\tend if ;\nend process ; -- ${1:identifier}", "body": "${1:identifier} : process( ${2:clock} )\nbegin\n\tif( rising_edge(${2:clock}) ) then\n\t\t$0\n\tend if ;\nend process ; -- ${1:identifier}",
"description": "synchronous process", "description": "synchronous process",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"slv": { "slv": {
"prefix": "slv", "prefix": "slv",
"body": "std_logic_vector(${1:x} downto ${2:0}) ;$0", "body": "std_logic_vector(${1:x} downto ${2:0}) ;$0",
"description": "std_logic_vector downto", "description": "std_logic_vector downto",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"slvr": { "slvr": {
"prefix": "slvr", "prefix": "slvr",
"body": "std_logic_vector(${1:signal}'range) ;$0", "body": "std_logic_vector(${1:signal}'range) ;$0",
"description": "std_logic_vector range", "description": "std_logic_vector range",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"u": { "u": {
"prefix": "u", "prefix": "u",
"body": "unsigned(${1:x} downto ${2:0}) ;$0", "body": "unsigned(${1:x} downto ${2:0}) ;$0",
"description": "unsigned downto", "description": "unsigned downto",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"ur": { "ur": {
"prefix": "ur", "prefix": "ur",
"body": "unsigned(${1:signal}'range) ;$0", "body": "unsigned(${1:signal}'range) ;$0",
"description": "unsigned range", "description": "unsigned range",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"vhdl": { "vhdl": {
"prefix": "vhdl", "prefix": "vhdl",
"body": "library ieee ;\n\tuse ieee.std_logic_1164.all ;\n\tuse ieee.numeric_std.all ;\n\nentity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ; \n\narchitecture ${2:arch} of ${1:ent} is\n\nbegin\n\nend architecture ;", "body": "library ieee ;\n\tuse ieee.std_logic_1164.all ;\n\tuse ieee.numeric_std.all ;\n\nentity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ; \n\narchitecture ${2:arch} of ${1:ent} is\n\nbegin\n\nend architecture ;",
"description": "vhdl template", "description": "vhdl template",
"scope": "source.vhdl" "scope": "source.vhdl"
}, },
"while": { "while": {
"prefix": "while", "prefix": "while",
"body": "${1:identifier} : while ${2:expression} loop\n\t$0\nend loop ; -- ${1:identifier}", "body": "${1:identifier} : while ${2:expression} loop\n\t$0\nend loop ; -- ${1:identifier}",

4
src/function/dide-viewer/index.ts
View File

@ -71,7 +71,7 @@ class WaveViewer {
this.panel.iconPath = getIconConfig('view'); this.panel.iconPath = getIconConfig('view');
registerMessageEvent(this.panel, uri); registerMessageEvent(this.panel, uri);
} else { } else {
WaveViewOutput.report('preview html in <WaveViewer.create> is empty', ReportType.Warn); WaveViewOutput.report('preview html in <WaveViewer.create> is empty', { level: ReportType.Warn });
} }
} }
@ -138,7 +138,7 @@ class VcdViewerProvider implements vscode.CustomEditorProvider {
webviewPanel.webview.html = preprocessHtml; webviewPanel.webview.html = preprocessHtml;
webviewPanel.iconPath = getIconConfig('view'); webviewPanel.iconPath = getIconConfig('view');
} else { } else {
WaveViewOutput.report('preview html in <WaveViewer.create> is empty', ReportType.Warn); WaveViewOutput.report('preview html in <WaveViewer.create> is empty', { level: ReportType.Warn });
} }
} }

6
src/function/hdlDoc/markdown.ts
View File

@ -4,7 +4,7 @@ import * as fspath from 'path';
import { AbsPath, opeParam, MainOutput, ReportType } from '../../global'; import { AbsPath, opeParam, MainOutput, ReportType } from '../../global';
import { hdlParam, HdlModule, HdlFile, HdlInstance } from '../../hdlParser/core'; import { hdlParam, HdlModule, HdlFile, HdlInstance } from '../../hdlParser/core';
import { HdlModulePort, HdlModuleParam, InstModPathStatus } from '../../hdlParser/common'; import { HdlModulePort, HdlModuleParam, InstModPathStatus, HdlFileProjectType } from '../../hdlParser/common';
import { MarkdownString, RenderString, RenderType, import { MarkdownString, RenderString, RenderType,
mergeSortByLine, getWavedromsFromFile, Count, WavedromString } from './common'; mergeSortByLine, getWavedromsFromFile, Count, WavedromString } from './common';
@ -43,7 +43,7 @@ function selectFieldValue(obj: any, subName: string, ws: string, name: string, i
if (fs.existsSync(value)) { if (fs.existsSync(value)) {
// 判断 类型 // 判断 类型
const hdlFile = hdlParam.getHdlFile(value); const hdlFile = hdlParam.getHdlFile(value);
if (hdlFile && hdlFile.type === 'remote_lib') { if (hdlFile && hdlFile.projectType === HdlFileProjectType.RemoteLib) {
// 如果是 库 文件，做出更加自定义的字面量 // 如果是 库 文件，做出更加自定义的字面量
const libRelPath = value.replace(`${opeParam.extensionPath}/library/`, ''); const libRelPath = value.replace(`${opeParam.extensionPath}/library/`, '');
value = `<span class="source-lib-tag">library</span> [${libRelPath}](file://${value})`; value = `<span class="source-lib-tag">library</span> [${libRelPath}](file://${value})`;
@ -277,10 +277,12 @@ async function getDocsFromFile(path: AbsPath): Promise<MarkdownString[] | undefi
const standardPath = hdlPath.toSlash(path); const standardPath = hdlPath.toSlash(path);
const response = await doFastApi(standardPath, 'common'); const response = await doFastApi(standardPath, 'common');
const langID = hdlFile.getLanguageId(standardPath); const langID = hdlFile.getLanguageId(standardPath);
const projectType = hdlParam.getHdlFileProjectType(standardPath, 'common');
moduleFile = new HdlFile( moduleFile = new HdlFile(
standardPath, langID, standardPath, langID,
response?.macro || defaultMacro, response?.macro || defaultMacro,
response?.content || [], response?.content || [],
projectType,
'common' 'common'
); );
// 从 hdlParam 中去除，避免干扰全局 // 从 hdlParam 中去除，避免干扰全局

27
src/function/lsp/linter/vivado.ts
View File

@ -55,7 +55,10 @@ class VivadoLinter implements BaseLinter {
this.diagnostic.set(document.uri, diagnostics); this.diagnostic.set(document.uri, diagnostics);
} }
} else { } else {
LspOutput.report('vivado linter is not available, please check prj.vivado.install.path in your setting', ReportType.Error, true); LspOutput.report('vivado linter is not available, please check prj.vivado.install.path in your setting', {
level: ReportType.Error,
notify: true
});
} }
} }
@ -79,7 +82,9 @@ class VivadoLinter implements BaseLinter {
if (headerInfo === 'ERROR') { if (headerInfo === 'ERROR') {
const errorInfos = parsedPath.split(':'); const errorInfos = parsedPath.split(':');
const errorLine = Math.max(parseInt(errorInfos[errorInfos.length - 1]) - 1, 0); const errorLine = Math.max(parseInt(errorInfos[errorInfos.length - 1]) - 1, 0);
LspOutput.report(`<xvlog linter> line: ${errorLine}, info: ${syntaxInfo}`, ReportType.Run); LspOutput.report(`<xvlog linter> line: ${errorLine}, info: ${syntaxInfo}`, {
level: ReportType.Run
});
const range = this.makeCorrectRange(document, errorLine, syntaxInfo); const range = this.makeCorrectRange(document, errorLine, syntaxInfo);
const diag = new vscode.Diagnostic(range, syntaxInfo, vscode.DiagnosticSeverity.Error); const diag = new vscode.Diagnostic(range, syntaxInfo, vscode.DiagnosticSeverity.Error);
@ -136,8 +141,13 @@ class VivadoLinter implements BaseLinter {
const fullExecutorName = opeParam.os === 'win32' ? executorName + '.bat' : executorName; const fullExecutorName = opeParam.os === 'win32' ? executorName + '.bat' : executorName;
if (vivadoInstallPath.trim() === '' || !fs.existsSync(vivadoInstallPath)) { if (vivadoInstallPath.trim() === '' || !fs.existsSync(vivadoInstallPath)) {
LspOutput.report(`User's Vivado Install Path "${vivadoInstallPath}", which is invalid. Use ${executorName} in default.`, ReportType.Warn); LspOutput.report(`User's Vivado Install Path "${vivadoInstallPath}", which is invalid. Use ${executorName} in default.`, {
LspOutput.report('If you have doubts, check prj.vivado.install.path in setting', ReportType.Warn); level: ReportType.Warn
});
LspOutput.report('If you have doubts, check prj.vivado.install.path in setting', {
level: ReportType.Warn
});
return executorName; return executorName;
} else { } else {
LspOutput.report(`User's Vivado Install Path "${vivadoInstallPath}", which is invalid`); LspOutput.report(`User's Vivado Install Path "${vivadoInstallPath}", which is invalid`);
@ -161,11 +171,16 @@ class VivadoLinter implements BaseLinter {
const { stderr } = await easyExec(executorPath, []); const { stderr } = await easyExec(executorPath, []);
if (stderr.length === 0) { if (stderr.length === 0) {
this.executableInvokeNameMap.set(langID, executorPath); this.executableInvokeNameMap.set(langID, executorPath);
LspOutput.report(`success to verify ${executorPath}, linter from vivado is ready to go!`, ReportType.Launch); LspOutput.report(`success to verify ${executorPath}, linter from vivado is ready to go!`, {
level: ReportType.Launch
});
return true; return true;
} else { } else {
this.executableInvokeNameMap.set(langID, undefined); this.executableInvokeNameMap.set(langID, undefined);
LspOutput.report(`Fail to execute ${executorPath}! Reason: ${stderr}`, ReportType.Error, true); LspOutput.report(`Fail to execute ${executorPath}! Reason: ${stderr}`, {
level: ReportType.Error,
notify: true
});
return false; return false;
} }
} }

2
src/function/netlist/index.ts
View File

@ -31,10 +31,12 @@ class Netlist {
const standardPath = hdlPath.toSlash(path); const standardPath = hdlPath.toSlash(path);
const response = await doFastApi(standardPath, 'common'); const response = await doFastApi(standardPath, 'common');
const langID = hdlFile.getLanguageId(standardPath); const langID = hdlFile.getLanguageId(standardPath);
const projectType = hdlParam.getHdlFileProjectType(standardPath, 'common');
moduleFile = new HdlFile( moduleFile = new HdlFile(
standardPath, langID, standardPath, langID,
response?.macro || defaultMacro, response?.macro || defaultMacro,
response?.content || [], response?.content || [],
projectType,
'common' 'common'
); );
// 从 hdlParam 中去除，避免干扰全局 // 从 hdlParam 中去除，避免干扰全局

66
src/function/sim/simulate.ts
View File

@ -73,7 +73,10 @@ class Simulate {
}; };
let code = hdlFile.readFile(path); let code = hdlFile.readFile(path);
if (!code) { if (!code) {
MainOutput.report('error when read ' + path, ReportType.Error, true); MainOutput.report('error when read ' + path, {
level: ReportType.Error,
notify: true
});
return; return;
} }
@ -95,7 +98,9 @@ class Simulate {
if (!hdlFile.isDir(simConfig.simulationHome)) { if (!hdlFile.isDir(simConfig.simulationHome)) {
MainOutput.report('create dir ' + simConfig.simulationHome, ReportType.Info); MainOutput.report('create dir ' + simConfig.simulationHome, {
level: ReportType.Info
});
hdlDir.mkdir(simConfig.simulationHome); hdlDir.mkdir(simConfig.simulationHome);
} }
@ -113,7 +118,10 @@ class Simulate {
simConfig.installPath = setting.get('digital-ide.function.simulate.icarus.installPath', ''); simConfig.installPath = setting.get('digital-ide.function.simulate.icarus.installPath', '');
if (simConfig.installPath !== '' && !hdlFile.isDir(simConfig.installPath)) { if (simConfig.installPath !== '' && !hdlFile.isDir(simConfig.installPath)) {
MainOutput.report(`install path ${simConfig.installPath} is illegal`, ReportType.Error, true); MainOutput.report(`install path ${simConfig.installPath} is illegal`, {
level: ReportType.Error,
notify: true
});
return; return;
} }
@ -252,7 +260,9 @@ class IcarusSimulate extends Simulate {
// console.log(thirdLibraryFileArgs); // console.log(thirdLibraryFileArgs);
const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryDirArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryFileArgs}`; const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryDirArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryFileArgs}`;
MainOutput.report(cmd, ReportType.Run); MainOutput.report(cmd, {
level: ReportType.Run
});
return cmd; return cmd;
} }
@ -287,26 +297,42 @@ class IcarusSimulate extends Simulate {
} }
child_process.exec(command, { cwd }, (error, stdout, stderr) => { child_process.exec(command, { cwd }, (error, stdout, stderr) => {
if (error) { if (error) {
MainOutput.report('Error took place when run ' + command, ReportType.Error); MainOutput.report('Error took place when run ' + command, {
MainOutput.report('Reason: ' + stderr, ReportType.Error); level: ReportType.Error
});
MainOutput.report('Reason: ' + stderr, {
level: ReportType.Error
});
} else { } else {
MainOutput.report(stdout, ReportType.Info); MainOutput.report(stdout, {
level: ReportType.Info
});
const vvpOutFile = hdlPath.join(simConfig.simulationHome, 'out.vvp'); const vvpOutFile = hdlPath.join(simConfig.simulationHome, 'out.vvp');
MainOutput.report("Create vvp to " + vvpOutFile, ReportType.Run); MainOutput.report("Create vvp to " + vvpOutFile, {
level: ReportType.Run
});
const outVvpPath = hdlPath.join(simConfig.simulationHome, 'out.vvp'); const outVvpPath = hdlPath.join(simConfig.simulationHome, 'out.vvp');
const vvpPath = simConfig.vvpPath; const vvpPath = simConfig.vvpPath;
// run vvp to interrupt script // run vvp to interrupt script
const vvpCommand = `${vvpPath} ${outVvpPath}`; const vvpCommand = `${vvpPath} ${outVvpPath}`;
MainOutput.report(vvpCommand, ReportType.Run); MainOutput.report(vvpCommand, {
level: ReportType.Run
});
child_process.exec(vvpCommand, { cwd }, (error, stdout, stderr) => { child_process.exec(vvpCommand, { cwd }, (error, stdout, stderr) => {
if (error) { if (error) {
MainOutput.report('Error took place when run ' + vvpCommand, ReportType.Error); MainOutput.report('Error took place when run ' + vvpCommand, {
MainOutput.report('Reason: ' + stderr, ReportType.Error); level: ReportType.Error
});
MainOutput.report('Reason: ' + stderr, {
level: ReportType.Error
});
} else { } else {
MainOutput.report(stdout, ReportType.Info); MainOutput.report(stdout, {
level: ReportType.Info
});
} }
}); });
} }
@ -355,7 +381,10 @@ class IcarusSimulate extends Simulate {
this.exec(simulationCommand, cwd); this.exec(simulationCommand, cwd);
} else { } else {
const errorMsg = 'Fail to generate command'; const errorMsg = 'Fail to generate command';
MainOutput.report(errorMsg, ReportType.Error, true); MainOutput.report(errorMsg, {
level: ReportType.Error,
notify: true
});
return; return;
} }
} }
@ -386,15 +415,13 @@ class IcarusSimulate extends Simulate {
} }
const standardPath = hdlPath.toSlash(path); const standardPath = hdlPath.toSlash(path);
console.log('enter [doFastApi]');
const response = await doFastApi(standardPath, 'common'); const response = await doFastApi(standardPath, 'common');
console.log('response result: '); const projectType = hdlParam.getHdlFileProjectType(standardPath, 'common');
console.log(response);
const moduleFile = new HdlFile( const moduleFile = new HdlFile(
standardPath, langID, standardPath, langID,
response?.macro || defaultMacro, response?.macro || defaultMacro,
response?.content || [], response?.content || [],
projectType,
'common' 'common'
); );
// 从 hdlParam 中去除，避免干扰全局 // 从 hdlParam 中去除，避免干扰全局
@ -418,7 +445,10 @@ class IcarusSimulate extends Simulate {
if (targetModule !== undefined) { if (targetModule !== undefined) {
this.simulateByHdlModule(targetModule); this.simulateByHdlModule(targetModule);
} else { } else {
MainOutput.report('There is no module named ' + view.name + ' in ' + view.path, ReportType.Error, true); MainOutput.report('There is no module named ' + view.name + ' in ' + view.path, {
level: ReportType.Error,
notify: true
});
return; return;
} }
} }

8
src/function/treeView/index.ts
View File

@ -49,7 +49,9 @@ function openFileByUri(path: string, range: Range, element: ModuleDataItem) {
} }
} }
} }
MainOutput.report("invalid jump uri triggered in treeview, el: " + JSON.stringify(element, null, ' '), ReportType.Error); MainOutput.report("invalid jump uri triggered in treeview, el: " + JSON.stringify(element, null, ' '), {
level: ReportType.Error
});
} }
function gotoXilinxIPDefinition(element: ModuleDataItem) { function gotoXilinxIPDefinition(element: ModuleDataItem) {
@ -63,7 +65,9 @@ function gotoXilinxIPDefinition(element: ModuleDataItem) {
vscode.window.showInformationMessage(t('info.treeview.ip-no-active.message')); vscode.window.showInformationMessage(t('info.treeview.ip-no-active.message'));
} }
} else { } else {
MainOutput.report("[gotoXilinxIPDefinition] path is undefined", ReportType.Error); MainOutput.report("[gotoXilinxIPDefinition] path is undefined", {
level: ReportType.Error
});
} }
} }

6
src/function/treeView/tree.ts
View File

@ -3,7 +3,7 @@ import * as vscode from 'vscode';
import { AbsPath, MainOutput, opeParam, ReportType } from '../../global'; import { AbsPath, MainOutput, opeParam, ReportType } from '../../global';
import { SimPath, SrcPath } from '../../global/prjInfo'; import { SimPath, SrcPath } from '../../global/prjInfo';
import { HdlInstance, hdlParam } from '../../hdlParser/core'; import { HdlInstance, hdlParam } from '../../hdlParser/core';
import { HdlFileType, Range } from '../../hdlParser/common'; import { HdlFileProjectType, Range } from '../../hdlParser/common';
import { hdlFile, hdlPath } from '../../hdlFs'; import { hdlFile, hdlPath } from '../../hdlFs';
import { xilinx, itemModes, otherModes } from './common'; import { xilinx, itemModes, otherModes } from './common';
import { getIconConfig } from '../../hdlFs/icons'; import { getIconConfig } from '../../hdlFs/icons';
@ -71,7 +71,7 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
this.srcRootItem = { this.srcRootItem = {
icon: 'src', icon: 'src',
type: HdlFileType.Src, type: HdlFileProjectType.Src,
doFastFileType: undefined, doFastFileType: undefined,
name: 'src', name: 'src',
range: undefined, range: undefined,
@ -81,7 +81,7 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
this.simRootItem = { this.simRootItem = {
icon: 'sim', icon: 'sim',
type: HdlFileType.Sim, type: HdlFileProjectType.Sim,
doFastFileType: undefined, doFastFileType: undefined,
name: 'sim', name: 'sim',
range: undefined, range: undefined,

59
src/global/outputChannel.ts
View File

@ -2,16 +2,53 @@
import * as vscode from 'vscode'; import * as vscode from 'vscode';
enum ReportType { enum ReportType {
/**
* debug
*/
Debug = 'Debug', Debug = 'Debug',
/**
* 某些模块或者子进程启动函数中的输出，用来判断子模块是否正常启动
*/
Launch = 'Launch', Launch = 'Launch',
/**
* 测量性能相关的输出
*/
Performance = 'Performance', Performance = 'Performance',
/**
* debug 查看路径有效性相关的输出
*/
PathCheck = 'Path Check', PathCheck = 'Path Check',
/**
* 普通消息的信息
*/
Info = 'Info', Info = 'Info',
/**
* warn 等级的信息
*/
Warn = 'Warn', Warn = 'Warn',
/**
* error 等级的信息
*/
Error = 'Error', Error = 'Error',
/**
* 某些功能或者子进程在运行中产出的信息
*/
Run = 'Run' Run = 'Run'
}; };
interface ReportOption {
/**
* 汇报的等级，类似于日志系统中的 level，详见
* [ReportType](https://github.com/Digital-EDA/Digital-IDE/blob/main/src/global/outputChannel.ts#L4)
*/
level?: ReportType,
/**
* 用于控制是否同时也在窗口右下角展示信息。如果为 true，则同时会
* 调用 vscode.window.showInformationMessage 在右下角展示信息。默认为 false
*/
notify?: boolean
}
class Output { class Output {
private _output: vscode.OutputChannel; private _output: vscode.OutputChannel;
private _ignoreTypes: ReportType[]; private _ignoreTypes: ReportType[];
@ -51,19 +88,21 @@ class Output {
} }
/** /**
* * @description 信息汇报函数，用于将字符串显示在 Output 窗口中，也可可以同时显示右下角的窗口中
* @param message message * @param message message
* @param type report type * @param option 汇报的选项
* @param reportInWindows whether use vscode.windows.<api> to show info
*/ */
public report(message: string | unknown, type: ReportType = ReportType.Info, reportInWindows: boolean = false) { public report(message: string | unknown, option?: ReportOption) {
if (!this.skipMessage(type) && message) { option = option || { level: ReportType.Info, notify: false } as ReportOption;
// this._output.show(true); const level = option.level || ReportType.Info;
const currentTime = this.getCurrentTime(); const notify = option.notify || false;
this._output.appendLine('[' + type + ' - ' + currentTime + '] ' + message);
if (reportInWindows) { if (!this.skipMessage(level) && message) {
this.showInWindows('' + message, type); const currentTime = this.getCurrentTime();
this._output.appendLine('[' + level + ' - ' + currentTime + '] ' + message);
if (notify) {
this.showInWindows('' + message, level);
} }
} }
} }

35
src/global/prjInfo.ts
View File

@ -233,6 +233,7 @@ class PrjInfo implements PrjInfoMeta {
const psname = this.prjName.PS; const psname = this.prjName.PS;
// TODO : packaging the replacer // TODO : packaging the replacer
// TODO : 支持路径的正则表达式
return path.replace(/\$\{workspace\}/g, workspacePath) return path.replace(/\$\{workspace\}/g, workspacePath)
.replace(/\$\{plname\}/g, plname) .replace(/\$\{plname\}/g, plname)
.replace(/\$\{psname\}/g, psname); .replace(/\$\{psname\}/g, psname);
@ -593,6 +594,11 @@ class PrjInfo implements PrjInfoMeta {
return libPath; return libPath;
} }
/**
* @description 代表当前的 arch.hardware.sim 的值
* 标准结构下应为 user/sim 的绝对路径
* 空则返回默认值 workspace path
*/
public get hardwareSimPath(): AbsPath { public get hardwareSimPath(): AbsPath {
const simPath = this._arch.hardware.sim; const simPath = this._arch.hardware.sim;
const workspace = this._workspacePath; const workspace = this._workspacePath;
@ -604,6 +610,11 @@ class PrjInfo implements PrjInfoMeta {
return hdlPath.join(workspace, simPath); return hdlPath.join(workspace, simPath);
} }
/**
* @description 代表当前的 arch.hardware.src 的值
* 标准结构下应为 user/src 的绝对路径
* 空则返回默认值 workspace path
*/
public get hardwareSrcPath(): AbsPath { public get hardwareSrcPath(): AbsPath {
const srcPath = this._arch.hardware.src; const srcPath = this._arch.hardware.src;
const workspace = this._workspacePath; const workspace = this._workspacePath;
@ -617,6 +628,30 @@ class PrjInfo implements PrjInfoMeta {
return hdlPath.join(workspace, srcPath); return hdlPath.join(workspace, srcPath);
} }
/**
* @description user/ip 的绝对路径
*/
public get ipPath(): AbsPath {
const workspace = this._workspacePath;
return hdlPath.join(workspace, 'user', 'ip');
}
/**
* @description user/src/lib 绝对路径
*/
public get localLibPath(): AbsPath {
const workspace = this._workspacePath;
return hdlPath.join(workspace, 'user', 'src', 'lib');
}
/**
* @description ${extensionPath}/library 绝对路径
*/
public get remoteLibPath(): AbsPath {
const extensionPath = this._extensionPath;
return hdlPath.join(extensionPath, 'library');
}
public json(): RawPrjInfo { public json(): RawPrjInfo {
return { return {
toolChain: this._toolChain, toolChain: this._toolChain,

21
src/hdlFs/file.ts
View File

@ -5,7 +5,7 @@ import { AbsPath, RelPath } from '../global';
import { HdlLangID } from '../global/enum'; import { HdlLangID } from '../global/enum';
import { verilogExts, vhdlExts, systemVerilogExts, hdlExts } from '../global/lang'; import { verilogExts, vhdlExts, systemVerilogExts, hdlExts } from '../global/lang';
import * as hdlPath from './path'; import * as hdlPath from './path';
import { HdlFileType } from '../hdlParser/common'; import { HdlFileProjectType } from '../hdlParser/common';
import { opeParam } from '../global'; import { opeParam } from '../global';
/** /**
@ -139,24 +139,6 @@ function getLanguageId(path: AbsPath | RelPath): HdlLangID {
} }
function getHdlFileType(path: AbsPath) : HdlFileType {
const uniformPath = hdlPath.toSlash(path);
const arch = opeParam.prjInfo.arch;
const srcPath: AbsPath = arch.hardware.src;
const simPath: AbsPath = arch.hardware.sim;
const wsPath: AbsPath = opeParam.workspacePath;
if (uniformPath.includes(srcPath)) {
return HdlFileType.Src;
} else if (uniformPath.includes(simPath)) {
return HdlFileType.Sim;
} else if (uniformPath.includes(wsPath)) {
return HdlFileType.LocalLib;
} else {
return HdlFileType.RemoteLib;
}
}
function readFile(path: AbsPath): string | undefined { function readFile(path: AbsPath): string | undefined {
try { try {
const content = fs.readFileSync(path, 'utf-8'); const content = fs.readFileSync(path, 'utf-8');
@ -376,7 +358,6 @@ export {
readJSON, readJSON,
writeJSON, writeJSON,
rmSync, rmSync,
getHdlFileType,
pickFileRecursive, pickFileRecursive,
isHasAttr, isHasAttr,
isHasValue, isHasValue,

18
src/hdlParser/common.ts
View File

@ -32,11 +32,23 @@ enum HdlModulePortType {
enum HdlModuleParamType {LocalParam, Parameter, Unknown}; enum HdlModuleParamType {LocalParam, Parameter, Unknown};
enum HdlFileType { /**
* @description 用于描述当前的这个 HDL 文件是会被系统视为哪一种进行处理
* - Src: src 目录文件
* - Sim: sim 目录文件
* - LocalLib: 局部库文件
* - RemoteLib: 全局库文件
* - IP: IP 核
* - Primitive: 原语
*/
enum HdlFileProjectType {
Src = 'src', Src = 'src',
Sim = 'sim', Sim = 'sim',
LocalLib = 'local_lib', LocalLib = 'local_lib',
RemoteLib = 'remote_lib' RemoteLib = 'remote_lib',
IP = 'ip',
Primitive = 'primitive',
Unknown = 'unknown'
}; };
enum InstModPathStatus {Current, Include, Others, Unknown}; enum InstModPathStatus {Current, Include, Others, Unknown};
@ -214,7 +226,7 @@ export {
InstRange, InstRange,
HdlModulePortType, HdlModulePortType,
HdlModuleParamType, HdlModuleParamType,
HdlFileType, HdlFileProjectType,
InstModPathStatus, InstModPathStatus,
Error, Error,
Define, Define,

143
src/hdlParser/core.ts
View File

@ -58,7 +58,9 @@ class HdlParam {
await this.doHdlFast(path, 'common'); await this.doHdlFast(path, 'common');
const hdlFile = this.getHdlFile(path); const hdlFile = this.getHdlFile(path);
if (!hdlFile) { if (!hdlFile) {
MainOutput.report('error happen when we attempt to add file by path: ' + path, ReportType.Error); MainOutput.report('error happen when we attempt to add file by path: ' + path, {
level: ReportType.Error
});
} else { } else {
hdlFile.makeInstance(); hdlFile.makeInstance();
// when a new file is added, retry the solution of dependency // when a new file is added, retry the solution of dependency
@ -134,11 +136,11 @@ class HdlParam {
} }
public selectTopModuleSourceByFileType(hdlModule: HdlModule): Set<HdlModule> { public selectTopModuleSourceByFileType(hdlModule: HdlModule): Set<HdlModule> {
switch (hdlModule.file.type) { switch (hdlModule.file.projectType) {
case common.HdlFileType.Src: return this.srcTopModules; case common.HdlFileProjectType.Src: return this.srcTopModules;
case common.HdlFileType.Sim: return this.simTopModules; case common.HdlFileProjectType.Sim: return this.simTopModules;
case common.HdlFileType.LocalLib: return this.srcTopModules; case common.HdlFileProjectType.LocalLib: return this.srcTopModules;
case common.HdlFileType.RemoteLib: return this.srcTopModules; case common.HdlFileProjectType.RemoteLib: return this.srcTopModules;
default: return this.srcTopModules; default: return this.srcTopModules;
} }
} }
@ -152,6 +154,10 @@ class HdlParam {
topModuleSource.add(hdlModule); topModuleSource.add(hdlModule);
} }
/**
* @description 根据输入的 module 把它从所属的 src 或者 sim 的 topmodules 中去除
* @param hdlModule
*/
public deleteTopModuleToSource(hdlModule: HdlModule) { public deleteTopModuleToSource(hdlModule: HdlModule) {
const topModuleSource = this.selectTopModuleSourceByFileType(hdlModule); const topModuleSource = this.selectTopModuleSourceByFileType(hdlModule);
topModuleSource.delete(hdlModule); topModuleSource.delete(hdlModule);
@ -238,15 +244,21 @@ class HdlParam {
const fast = await HdlSymbol.fast(path, fileType); const fast = await HdlSymbol.fast(path, fileType);
if (fast) { if (fast) {
const languageId = this.getRealLanguageId(path, fast.fileType); const languageId = this.getRealLanguageId(path, fast.fileType);
const fileProjectType = this.getHdlFileProjectType(path, fast.fileType);
new HdlFile(path, new HdlFile(path,
languageId, languageId,
fast.macro, fast.macro,
fast.content, fast.content,
fileProjectType,
fast.fileType); fast.fileType);
} }
} catch (error) { } catch (error) {
MainOutput.report('Error happen when parse ' + path, ReportType.Error); MainOutput.report('Error happen when parse ' + path, {
MainOutput.report('Reason: ' + error, ReportType.Error); level: ReportType.Error
});
MainOutput.report('Reason: ' + error, {
level: ReportType.Error
});
} }
} }
@ -257,6 +269,32 @@ class HdlParam {
return hdlFile.getLanguageId(path); return hdlFile.getLanguageId(path);
} }
public getHdlFileProjectType(path: string, fileType: DoFastFileType): common.HdlFileProjectType {
switch (fileType) {
case 'common':
// 根据前缀来判断对应的类型
path = hdlPath.toSlash(path);
const prjInfo = opeParam.prjInfo;
if (path.startsWith(prjInfo.hardwareSrcPath)) {
return common.HdlFileProjectType.Src;
} else if (path.startsWith(prjInfo.hardwareSimPath)) {
return common.HdlFileProjectType.Sim;
} else if (path.startsWith(prjInfo.ipPath)) {
return common.HdlFileProjectType.IP;
} else if (path.startsWith(prjInfo.localLibPath)) {
return common.HdlFileProjectType.LocalLib;
} else if (path.startsWith(prjInfo.remoteLibPath)) {
return common.HdlFileProjectType.RemoteLib;
} else {
return common.HdlFileProjectType.Unknown;
}
case 'ip':
return common.HdlFileProjectType.IP;
case 'primitives':
return common.HdlFileProjectType.Primitive;
}
}
public async initializeHdlFiles(hdlFiles: AbsPath[], progress: vscode.Progress<IProgress>) { public async initializeHdlFiles(hdlFiles: AbsPath[], progress: vscode.Progress<IProgress>) {
let count: number = 0; let count: number = 0;
@ -343,8 +381,8 @@ class HdlParam {
} }
switch (type) { switch (type) {
case common.HdlFileType.Src: return this.getSrcTopModules(); case common.HdlFileProjectType.Src: return this.getSrcTopModules();
case common.HdlFileType.Sim: return this.getSimTopModules(); case common.HdlFileProjectType.Sim: return this.getSimTopModules();
default: return []; default: return [];
} }
} }
@ -399,7 +437,9 @@ class HdlParam {
// 初始化 // 初始化
const moduleFile = this.getHdlFile(path); const moduleFile = this.getHdlFile(path);
if (!moduleFile) { if (!moduleFile) {
MainOutput.report('error happen when create moduleFile ' + path, ReportType.Warn); MainOutput.report('error happen when create moduleFile ' + path, {
level: ReportType.Warn
});
} else { } else {
moduleFile.makeInstance(); moduleFile.makeInstance();
for (const module of moduleFile.getAllHdlModules()) { for (const module of moduleFile.getAllHdlModules()) {
@ -481,19 +521,25 @@ class HdlInstance {
this.locateHdlModule(); this.locateHdlModule();
} }
/**
* @description 定位出当前 instance 的模块是什么，并将模块对应的 HdlModule （普通 HDL、IP、原语） 赋值到 this.module 上
* 对于存在于结构树中的 HdlModule （普通 HDL & IP），改变这些 HdlModule 的 ref 并修改顶层模块相关的属性
*/
public locateHdlModule() { public locateHdlModule() {
const instModPath = this.instModPath; const instModPath = this.instModPath;
const instModName = this.type; const instModName = this.type;
if (instModPath) { if (instModPath) {
this.module = hdlParam.getHdlModule(instModPath, instModName); const module = hdlParam.getHdlModule(instModPath, instModName);
if (module) {
// add refer for module this.module = module;
this.module?.addGlobalReferedInstance(this); // 增加当前模块的 global ref
// if module and parent module share the same source (e.g both in src folder) this.module.addGlobalReferedInstance(this);
if (this.isSameSourceInstantiation()) { // 如果当前 instance 对应的例化是同源例化，则
// 增加当前 instance 的引用，并从对应类型的顶层模块中剔除 // 增加当前 instance 的 local ref，并从对应类型的顶层模块中剔除
this.module?.addLocalReferedInstance(this); if (this.isSameSourceInstantiation()) {
this.module?.addLocalReferedInstance(this);
}
} }
} else { } else {
doPrimitivesJudgeApi(instModName).then(isPrimitive => { doPrimitivesJudgeApi(instModName).then(isPrimitive => {
@ -503,6 +549,9 @@ class HdlInstance {
const fakeModule = new HdlModule( const fakeModule = new HdlModule(
XilinxPrimitivesHdlFile, instModName, defaultRange, [], [], []); XilinxPrimitivesHdlFile, instModName, defaultRange, [], [], []);
this.module = fakeModule; this.module = fakeModule;
// 原语在任何情况下都不是顶层模块
hdlParam.deleteTopModule(fakeModule);
hdlParam.deleteTopModuleToSource(fakeModule);
} }
} }
}); });
@ -513,24 +562,37 @@ class HdlInstance {
/** /**
* @description 判断当前的 `instance` 对应的例化行为是否为一个同源例化 (SSI, same source instantiation) * @description 判断当前的 `instance` 对应的例化行为是否为一个同源例化 (SSI, same source instantiation)
* *
* 对于标准项目结构，也就是 src + sim ，如果在 moduleA 中完成了 moduleB 的例化，且 moduleA 和 moduleB 都是 src 文件夹下的， * - 对于标准项目结构，也就是 src + sim ，如果在 moduleA 中完成了 moduleB 的例化，且 moduleA 和 moduleB 都是 src 文件夹下的，
* 那么这个例化就是一个同源例化；如果 moduleB 在 sim 下， moduleA 在 src 下，那么当前的例化就是一个非同源例化。 * 那么这个例化就是一个同源例化；如果 moduleB 在 sim 下， moduleA 在 src 下，那么当前的例化就是一个非同源例化。
* * - 对于 library 和 IP 这两种类型的 module，对于它们的例化一律视为同源引用。
* 同源例化造成的引用为 local ref，非同源例化 + 同源例化造成的引用为 global ref。在模块树下， src 文件夹下的只有 local ref 为空的 module 才是顶层模块 * - 同源例化造成的引用为 local ref，非同源例化 + 同源例化造成的引用为 global ref。在模块树下， src 文件夹下的只有 local ref 为空的 module 才是顶层模块
* 换句话说，非同源例化一定不会造成顶层模块的变化，但是同源例化有可能会。 * 换句话说，非同源例化一定不会造成顶层模块的变化，但是同源例化有可能会。
* @returns * @returns
*/ */
public isSameSourceInstantiation(): boolean { public isSameSourceInstantiation(): boolean {
const parentMod = this.parentMod; const parentModule = this.parentMod;
const instMod = this.module; const belongModule = this.module;
if (instMod) {
return parentMod.file.type === instMod.file.type; // 当前 instance 仍然是 unsolved 状态，返回 false 不参与后续的 ref 计算
if (!belongModule) {
return false;
} }
return false;
// instance 模块本身是 library / IP / 原语，一律视为 SSI
if (belongModule.file.projectType === common.HdlFileProjectType.IP ||
belongModule.file.projectType === common.HdlFileProjectType.Primitive ||
belongModule.file.projectType === common.HdlFileProjectType.LocalLib ||
belongModule.file.projectType === common.HdlFileProjectType.RemoteLib
) {
return true;
}
// 剩余情况下，一律根据 type 判断
return parentModule.file.projectType === belongModule.file.projectType;
} }
/** /**
* @description update Instance of each time * @description 更新当前的 instance
* @param newInstance * @param newInstance
*/ */
public update(newInstance: common.RawHdlInstance) { public update(newInstance: common.RawHdlInstance) {
@ -685,8 +747,9 @@ class HdlModule {
} }
// this.rawInstances = undefined; // this.rawInstances = undefined;
} else { } else {
MainOutput.report('call makeNameToInstances but this.rawInstances is undefined', MainOutput.report('call makeNameToInstances but this.rawInstances is undefined', {
ReportType.Warn); level: ReportType.Warn
});
} }
} }
@ -885,23 +948,30 @@ class HdlModule {
}; };
export class HdlFile { export class HdlFile {
// 标准化的文件绝对路径
public path: string; public path: string;
// 对应的 HDL 语言 ID
public languageId: HdlLangID; public languageId: HdlLangID;
public type: common.HdlFileType; // 文件的项目类型
public projectType: common.HdlFileProjectType;
// 文件的解析模式
public doFastType: DoFastFileType; public doFastType: DoFastFileType;
// 当前文件的宏
public macro: common.Macro; public macro: common.Macro;
// 维护当前文件内部 module 的 map
private readonly nameToModule: Map<string, HdlModule>; private readonly nameToModule: Map<string, HdlModule>;
constructor(path: string, constructor(path: string,
languageId: HdlLangID, languageId: HdlLangID,
macro: common.Macro, macro: common.Macro,
modules: common.RawHdlModule[], modules: common.RawHdlModule[],
projectType: common.HdlFileProjectType,
doFastType: DoFastFileType) { doFastType: DoFastFileType) {
this.path = path; this.path = path;
this.languageId = languageId; this.languageId = languageId;
this.macro = macro; this.macro = macro;
this.type = hdlFile.getHdlFileType(path); this.projectType = projectType;
this.doFastType = doFastType; this.doFastType = doFastType;
// add to global hdlParam // add to global hdlParam
@ -987,8 +1057,13 @@ export class HdlFile {
} }
} }
export const XilinxPrimitivesHdlFile = new HdlFile('xilinx-primitives', HdlLangID.Verilog, defaultMacro, [], 'primitives'); export const XilinxPrimitivesHdlFile = new HdlFile(
'xilinx-primitives',
HdlLangID.Verilog,
defaultMacro,
[],
common.HdlFileProjectType.Primitive,
'primitives');
export { export {

22
src/manager/PL/index.ts
View File

@ -10,7 +10,7 @@ import { opeParam } from '../../global';
import { ToolChainType } from '../../global/enum'; import { ToolChainType } from '../../global/enum';
import { hdlFile, hdlPath } from '../../hdlFs'; import { hdlFile, hdlPath } from '../../hdlFs';
import { moduleTreeProvider, ModuleDataItem } from '../../function/treeView/tree'; import { moduleTreeProvider, ModuleDataItem } from '../../function/treeView/tree';
import { HdlFileType } from '../../hdlParser/common'; import { HdlFileProjectType } from '../../hdlParser/common';
import { PropertySchema } from '../../global/propertySchema'; import { PropertySchema } from '../../global/propertySchema';
import { HardwareOutput, ReportType } from '../../global/outputChannel'; import { HardwareOutput, ReportType } from '../../global/outputChannel';
import { t } from '../../i18n'; import { t } from '../../i18n';
@ -31,15 +31,7 @@ class PlManage extends BaseManage {
const curToolChain = this.context.tool; const curToolChain = this.context.tool;
if (curToolChain === ToolChainType.Xilinx) { if (curToolChain === ToolChainType.Xilinx) {
const vivadoPath = vscode.workspace.getConfiguration('digital-ide.prj.vivado.install').get('path', ''); this.context.path = this.context.ope.updateVivadoPath();
if (hdlFile.isDir(vivadoPath)) {
this.context.path = hdlPath.join(hdlPath.toSlash(vivadoPath), 'vivado');
if (opeParam.os === 'win32') {
this.context.path += '.bat';
}
} else {
this.context.path = 'vivado';
}
} }
} }
@ -104,7 +96,7 @@ class PlManage extends BaseManage {
HardwareOutput.show(); HardwareOutput.show();
this.context.process.stdin.write('exit\n'); this.context.process.stdin.write('exit\n');
HardwareOutput.report(t('info.pl.exit.title'), ReportType.Info); HardwareOutput.report(t('info.pl.exit.title'));
this.context.process = undefined; this.context.process = undefined;
} }
@ -112,8 +104,8 @@ class PlManage extends BaseManage {
public setSrcTop(item: ModuleDataItem) { public setSrcTop(item: ModuleDataItem) {
this.context.ope.setSrcTop(item.name, this.context); this.context.ope.setSrcTop(item.name, this.context);
const type = moduleTreeProvider.getItemType(item); const type = moduleTreeProvider.getItemType(item);
if (type === HdlFileType.Src) { if (type === HdlFileProjectType.Src) {
moduleTreeProvider.setFirstTop(HdlFileType.Src, item.name, item.path); moduleTreeProvider.setFirstTop(HdlFileProjectType.Src, item.name, item.path);
moduleTreeProvider.refreshSrc(); moduleTreeProvider.refreshSrc();
} }
} }
@ -121,8 +113,8 @@ class PlManage extends BaseManage {
public setSimTop(item: ModuleDataItem) { public setSimTop(item: ModuleDataItem) {
this.context.ope.setSimTop(item.name, this.context); this.context.ope.setSimTop(item.name, this.context);
const type = moduleTreeProvider.getItemType(item); const type = moduleTreeProvider.getItemType(item);
if (type === HdlFileType.Sim) { if (type === HdlFileProjectType.Sim) {
moduleTreeProvider.setFirstTop(HdlFileType.Sim, item.name, item.path); moduleTreeProvider.setFirstTop(HdlFileProjectType.Sim, item.name, item.path);
moduleTreeProvider.refreshSim(); moduleTreeProvider.refreshSim();
} }
} }

104
src/manager/PL/xilinx.ts
View File

@ -13,6 +13,7 @@ import { XilinxIP } from '../../global/enum';
import { HardwareOutput, MainOutput, ReportType } from '../../global/outputChannel'; import { HardwareOutput, MainOutput, ReportType } from '../../global/outputChannel';
import { debounce } from '../../global/util'; import { debounce } from '../../global/util';
import { t } from '../../i18n'; import { t } from '../../i18n';
import { HdlFileProjectType } from '../../hdlParser/common';
interface XilinxCustom { interface XilinxCustom {
ipRepo: AbsPath, ipRepo: AbsPath,
@ -172,15 +173,15 @@ class XilinxOperation {
} }
const tclPath = hdlPath.join(this.xilinxPath, 'launch.tcl'); const tclPath = hdlPath.join(this.xilinxPath, 'launch.tcl');
scripts.push(this.getRefreshCmd()); scripts.push(this.getRefreshXprDesignSourceCommand());
scripts.push(`file delete ${tclPath} -force`); scripts.push(`file delete ${tclPath} -force`);
const tclCommands = scripts.join('\n') + '\n'; const tclCommands = scripts.join('\n') + '\n';
hdlFile.writeFile(tclPath, tclCommands); hdlFile.writeFile(tclPath, tclCommands);
const argu = `-notrace -nolog -nojournal`; const argu = `-notrace -nolog -nojournal`;
context.path = this.updateVivadoPath();
const cmd = `${context.path} -mode tcl -s ${tclPath} ${argu}`; const cmd = `${context.path} -mode tcl -s ${tclPath} ${argu}`;
const _this = this; const _this = this;
const onVivadoClose = debounce(() => { const onVivadoClose = debounce(() => {
@ -193,6 +194,7 @@ class XilinxOperation {
} }
// 执行 cmd 启动 // 执行 cmd 启动
const vivadoProcess = spawn(cmd, [], { shell: true, stdio: 'pipe', cwd: opeParam.workspacePath }); const vivadoProcess = spawn(cmd, [], { shell: true, stdio: 'pipe', cwd: opeParam.workspacePath });
let status: 'pending' | 'fulfilled' = 'pending';
vivadoProcess.on('close', () => { vivadoProcess.on('close', () => {
onVivadoClose(); onVivadoClose();
@ -204,13 +206,6 @@ class XilinxOperation {
onVivadoClose(); onVivadoClose();
}); });
vivadoProcess.stderr.on('data', data => {
HardwareOutput.report(data.toString(), ReportType.Error);
HardwareOutput.show();
});
let status: 'pending' | 'fulfilled' = 'pending';
return new Promise(resolve => { return new Promise(resolve => {
vivadoProcess.stdout.on('data', data => { vivadoProcess.stdout.on('data', data => {
const message: string = _this.handleMessage(data.toString(), status); const message: string = _this.handleMessage(data.toString(), status);
@ -219,15 +214,42 @@ class XilinxOperation {
HardwareOutput.show(); HardwareOutput.show();
resolve(vivadoProcess); resolve(vivadoProcess);
} }
HardwareOutput.report(message, ReportType.Info); HardwareOutput.report(message, {
level: ReportType.Info
});
status = 'fulfilled'; status = 'fulfilled';
}); });
vivadoProcess.stderr.on('data', async data => {
HardwareOutput.report(data.toString(), {
level: ReportType.Error
});
HardwareOutput.show();
if (status === 'pending') {
// pending 阶段就出现 stderr 说明启动失败
resolve(undefined);
const vivadoInstallPath = vscode.workspace.getConfiguration('digital-ide').get<string>('prj.vivado.install.path') || '';
const res = await vscode.window.showErrorMessage(
t('error.pl.launch.not-valid-vivado-path', data.toString(), vivadoInstallPath.toString()),
{
title: t('info.pl.launch.set-vivado-path'),
value: true
}
);
if (res?.value) {
await vscode.commands.executeCommand('workbench.action.openSettings', 'digital-ide.prj.vivado.install.path');
}
}
});
}); });
} }
const process = await vscode.window.withProgress({ const process = await vscode.window.withProgress({
title: t('info.pl.launch.progress.launch-tcl.title'), title: t('info.pl.launch.progress.launch-tcl.title'),
location: vscode.ProgressLocation.Notification location: vscode.ProgressLocation.Notification,
cancellable: true
}, async () => { }, async () => {
return await launchScript(); return await launchScript();
}); });
@ -280,7 +302,11 @@ class XilinxOperation {
scripts.push(`open_project ${path} -quiet`); scripts.push(`open_project ${path} -quiet`);
} }
private getRefreshCmd(): string { /**
* @description 更新 xpr 设计源的命令
* @returns
*/
private getRefreshXprDesignSourceCommand(): string {
const scripts: string[] = []; const scripts: string[] = [];
// 清除所有源文件 // 清除所有源文件
scripts.push(`remove_files -quiet [get_files]`); scripts.push(`remove_files -quiet [get_files]`);
@ -358,13 +384,25 @@ class XilinxOperation {
}); });
// 导入非本地的设计源文件 // 导入非本地的设计源文件
const HDLFiles = hdlParam.getAllHdlFiles(); for (const hdlFile of hdlParam.getAllHdlFiles()) {
for (const file of HDLFiles) { switch (hdlFile.projectType) {
// TODO: 新增library的add_files case HdlFileProjectType.Src:
if (file.type === "src") { case HdlFileProjectType.LocalLib:
scripts.push(`add_files ${file.path} -quiet`); case HdlFileProjectType.RemoteLib:
// src 和 library 加入 source_1 设计源
scripts.push(`add_file ${hdlFile.path} -quiet`);
break;
case HdlFileProjectType.Sim:
// sim 加入 sim_1 设计源
scripts.push(`add_file -fileset sim_1 ${hdlFile.path} -quiet`);
break;
case HdlFileProjectType.IP:
case HdlFileProjectType.Primitive:
// IP 和 原语不用管
break;
default:
break;
} }
scripts.push(`add_files -fileset sim_1 ${file.path} -quiet`);
} }
scripts.push(`add_files -fileset constrs_1 ${this.datPath} -quiet`); scripts.push(`add_files -fileset constrs_1 ${this.datPath} -quiet`);
@ -389,8 +427,12 @@ class XilinxOperation {
return cmd; return cmd;
} }
/**
* @description 【Xilinx Vivado 操作】更新 xpr 文件
* @param context
*/
public refresh(context: PLContext) { public refresh(context: PLContext) {
const cmd = this.getRefreshCmd(); const cmd = this.getRefreshXprDesignSourceCommand();
context.process?.stdin.write(cmd + '\n'); context.process?.stdin.write(cmd + '\n');
} }
@ -590,7 +632,9 @@ file delete ${scriptPath} -force\n`;
if (context.process) { if (context.process) {
context.process.stdin.write('start_gui -quiet\n'); context.process.stdin.write('start_gui -quiet\n');
HardwareOutput.report(t('info.pl.gui.report-title'), ReportType.Info); HardwareOutput.report(t('info.pl.gui.report-title'), {
level: ReportType.Info
});
HardwareOutput.show(); HardwareOutput.show();
this.guiLaunched = true; this.guiLaunched = true;
} }
@ -600,7 +644,7 @@ file delete ${scriptPath} -force\n`;
if (!this.guiLaunched && files.length > 0) { if (!this.guiLaunched && files.length > 0) {
const filesString = files.join("\n"); const filesString = files.join("\n");
HardwareOutput.report(t('info.pl.add-files.title') + '\n' + filesString); HardwareOutput.report(t('info.pl.add-files.title') + '\n' + filesString);
this.processFileInPrj(files, context, "add_file"); this.execCommandToFilesInTclInterpreter(files, context, "add_file");
} }
} }
@ -608,7 +652,7 @@ file delete ${scriptPath} -force\n`;
if (!this.guiLaunched && files.length > 0) { if (!this.guiLaunched && files.length > 0) {
const filesString = files.join("\n"); const filesString = files.join("\n");
HardwareOutput.report(t('info.pl.del-files.title') + '\n' + filesString); HardwareOutput.report(t('info.pl.del-files.title') + '\n' + filesString);
this.processFileInPrj(files, context, "remove_files"); this.execCommandToFilesInTclInterpreter(files, context, "remove_files");
} }
} }
@ -638,7 +682,7 @@ file delete ${scriptPath} -force\n`;
* @param context * @param context
* @param command * @param command
*/ */
public processFileInPrj(files: string[], context: PLContext, command: string) { public execCommandToFilesInTclInterpreter(files: string[], context: PLContext, command: string) {
if (context.process === undefined) { if (context.process === undefined) {
return; return;
} }
@ -681,6 +725,20 @@ file delete ${scriptPath} -force\n`;
MainOutput.report(log); MainOutput.report(log);
} }
public updateVivadoPath(): string {
const vivadoBinFolder = vscode.workspace.getConfiguration('digital-ide.prj.vivado.install').get<string>('path') || '';
if (hdlFile.isDir(vivadoBinFolder)) {
let vivadoPath = hdlPath.join(hdlPath.toSlash(vivadoBinFolder), 'vivado');
if (opeParam.os === 'win32') {
vivadoPath += '.bat';
}
return vivadoPath;
} else {
// 没有设置 vivado bin 文件夹，就认为用户已经把对应的路径加入环境变量了
return 'vivado';
}
}
} }
class XilinxBd { class XilinxBd {

4
src/manager/index.ts
View File

@ -13,7 +13,9 @@ function registerManagerCommands(context: vscode.ExtensionContext) {
// const psManage = prjManage.ps; // const psManage = prjManage.ps;
vscode.commands.registerCommand('digital-ide.property-json.generate', prjManage.generatePropertyJson); vscode.commands.registerCommand('digital-ide.property-json.generate', prjManage.generatePropertyJson);
vscode.commands.registerCommand('digital-ide.property-json.overwrite', prjManage.overwritePropertyJson);
// 丢弃原因：插件更新后，用户修改的部分会被覆盖，没有存在必要了
// vscode.commands.registerCommand('digital-ide.property-json.overwrite', prjManage.overwritePropertyJson);
// libpick // libpick
vscode.commands.registerCommand('digital-ide.pickLibrary', pickLibrary); vscode.commands.registerCommand('digital-ide.pickLibrary', pickLibrary);

34
src/monitor/event.ts
View File

@ -33,7 +33,9 @@ abstract class BaseAction {
public listenChange(m: HdlMonitor) { public listenChange(m: HdlMonitor) {
const fSWatcher = this.selectFSWatcher(m); const fSWatcher = this.selectFSWatcher(m);
if (!fSWatcher) { if (!fSWatcher) {
MainOutput.report("FSWatcher hasn't been made!", ReportType.Error); MainOutput.report("FSWatcher hasn't been made!", {
level: ReportType.Error
});
return; return;
} }
fSWatcher.on(Event.Change, path => this.change(path, m)); fSWatcher.on(Event.Change, path => this.change(path, m));
@ -42,7 +44,9 @@ abstract class BaseAction {
public listenAdd(m: HdlMonitor) { public listenAdd(m: HdlMonitor) {
const fSWatcher = this.selectFSWatcher(m); const fSWatcher = this.selectFSWatcher(m);
if (!fSWatcher) { if (!fSWatcher) {
MainOutput.report("FSWatcher hasn't been made!", ReportType.Error); MainOutput.report("FSWatcher hasn't been made!", {
level: ReportType.Error
});
return; return;
} }
fSWatcher.on(Event.Add, path => this.add(path, m)); fSWatcher.on(Event.Add, path => this.add(path, m));
@ -51,7 +55,9 @@ abstract class BaseAction {
public listenUnlink(m: HdlMonitor) { public listenUnlink(m: HdlMonitor) {
const fSWatcher = this.selectFSWatcher(m); const fSWatcher = this.selectFSWatcher(m);
if (!fSWatcher) { if (!fSWatcher) {
MainOutput.report("FSWatcher hasn't been made!", ReportType.Error); MainOutput.report("FSWatcher hasn't been made!", {
level: ReportType.Error
});
return; return;
} }
fSWatcher.on(Event.Unlink, path => this.unlink(path, m)); fSWatcher.on(Event.Unlink, path => this.unlink(path, m));
@ -75,7 +81,9 @@ class HdlAction extends BaseAction {
// check if it has been created // check if it has been created
if (hdlParam.hasHdlFile(path)) { if (hdlParam.hasHdlFile(path)) {
MainOutput.report('<HdlAction Add Event> HdlFile ' + path + ' has been created', ReportType.Warn); MainOutput.report('<HdlAction Add Event> HdlFile ' + path + ' has been created', {
level: ReportType.Warn
});
return; return;
} }
@ -247,7 +255,9 @@ class PpyAction extends BaseAction {
// skip hdl remake // skip hdl remake
if (originalLibState !== currentLibState) { if (originalLibState !== currentLibState) {
const fileChange = await libManage.processLibFiles(opeParam.prjInfo.library); const fileChange = await libManage.processLibFiles(opeParam.prjInfo.library);
MainOutput.report(`libManage finish process, add ${fileChange.add.length} files, del ${fileChange.del.length} files`, ReportType.Info); MainOutput.report(`libManage finish process, add ${fileChange.add.length} files, del ${fileChange.del.length} files`, {
level: ReportType.Info
});
} }
} else { } else {
// update hdl monitor // update hdl monitor
@ -308,8 +318,6 @@ class PpyAction extends BaseAction {
for (const path of delFiles) { for (const path of delFiles) {
hdlParam.deleteHdlFile(path); hdlParam.deleteHdlFile(path);
} }
// 判断新加入的 module 是否还是顶层模块
} }
@ -320,7 +328,9 @@ class PpyAction extends BaseAction {
const delfileActionTag = '(del files) '; const delfileActionTag = '(del files) ';
if (addFiles.length > 0) { if (addFiles.length > 0) {
const reportMsg = ['', ...addFiles].join('\n\t'); const reportMsg = ['', ...addFiles].join('\n\t');
MainOutput.report(addfileActionTag + t('info.pl.xilinx.update-addfiles') + reportMsg, ReportType.Run); MainOutput.report(addfileActionTag + t('info.pl.xilinx.update-addfiles') + reportMsg, {
level: ReportType.Run
});
await prjManage.pl.addFiles(addFiles); await prjManage.pl.addFiles(addFiles);
} else { } else {
MainOutput.report(addfileActionTag + t('info.pl.xilinx.no-need-add-files')); MainOutput.report(addfileActionTag + t('info.pl.xilinx.no-need-add-files'));
@ -328,14 +338,18 @@ class PpyAction extends BaseAction {
if (delFiles.length > 0) { if (delFiles.length > 0) {
const reportMsg = ['', ...delFiles].join('\n\t'); const reportMsg = ['', ...delFiles].join('\n\t');
MainOutput.report(delfileActionTag + t('info.pl.xilinx.update-delfiles') + reportMsg, ReportType.Run); MainOutput.report(delfileActionTag + t('info.pl.xilinx.update-delfiles') + reportMsg, {
level: ReportType.Run
});
await prjManage.pl.delFiles(delFiles); await prjManage.pl.delFiles(delFiles);
} else { } else {
MainOutput.report(delfileActionTag + t('info.pl.xilinx.no-need-del-files')); MainOutput.report(delfileActionTag + t('info.pl.xilinx.no-need-del-files'));
} }
} else { } else {
MainOutput.report('PL is not registered', ReportType.Warn); MainOutput.report('PL is not registered', {
level: ReportType.Warn
});
} }
} }
} }