reconstruct prj & lib partly | test

This commit is contained in:
锦恢 2023-02-08 23:59:14 +08:00
parent 74d6353019
commit 9c02033c41
22 changed files with 520 additions and 506 deletions

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@ -11,4 +11,5 @@ dist/**/*.map
webpack.config.js
node_modules
src/**
vsixmake.js
vsixmake.js
script

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@ -1,226 +0,0 @@
{
"content": {
"error": [],
"modules": [
{
"instances": [
{
"instparams": null,
"instports": {
"end": {
"character": 10,
"line": 21
},
"start": {
"character": 4,
"line": 18
}
},
"name": "u_dependence_1",
"range": {
"end": {
"character": 0,
"line": 22
},
"start": {
"character": 13,
"line": 17
}
},
"type": "dependence_1"
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"instparams": null,
"instports": {
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},
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},
"start": {
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"line": 24
}
},
"type": "dependence_2"
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{
"instparams": null,
"instports": {
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"line": 35
},
"start": {
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"line": 32
}
},
"name": "u_dependence_3",
"range": {
"end": {
"character": 0,
"line": 36
},
"start": {
"character": 13,
"line": 31
}
},
"type": "dependence_3"
}
],
"name": "Main",
"params": [],
"ports": [
{
"name": "a",
"range": {
"end": {
"character": 11,
"line": 13
},
"start": {
"character": 10,
"line": 13
}
},
"type": "input",
"width": "Unknown"
},
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"start": {
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}
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"type": "input",
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"type": "input",
"width": "Unknown"
},
{
"name": "Qus",
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"line": 14
},
"start": {
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}
},
"type": "output",
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{
"name": "Qs",
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"line": 14
},
"start": {
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}
},
"type": "output",
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{
"name": "`main",
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"line": 38
},
"start": {
"character": 0,
"line": 12
}
}
}
]
},
"languageId": "verilog",
"macro": {
"defines": [
{
"name": "main",
"range": {
"end": {
"character": 17,
"line": 10
},
"start": {
"character": 1,
"line": 10
}
},
"value": "out"
}
],
"error": [],
"includes": [
{
"path": "child_1.v",
"range": {
"end": {
"character": 9,
"line": 9
},
"start": {
"character": 1,
"line": 9
}
}
}
],
"invalid": []
}
}

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@ -16,7 +16,8 @@
"onLanguage:verilog",
"onLanguage:vhdl",
"onLanguage:systemverilog",
"onCommand:TOOL.generate.property",
"onCommand:digital-ide.property-json.generate",
"onCommand:digital-ide.property-json.overwrite",
"workspaceContains:.vscode/property.json"
],
"contributes": {
@ -33,155 +34,161 @@
},
"commands": [
{
"command": "digital-ide.helloWorld",
"title": "Hello World"
"command": "digital-ide.property-json.generate",
"title": "%digital-ide.property-json.generate.title%",
"category": "Digital-IDE"
},
{
"command": "digital-ide.property-json.overwrite",
"title": "%digital-ide.property-json.overwrite.title%",
"category": "Digital-IDE"
}
],
"languages": [
{
"id": "tcl",
"aliases": [
"TCL",
"Xilinx Constraints File",
"Synopsis Constraints File"
],
"extensions": [
".tcl",
".sdc",
".xdc",
".fdc"
],
"configuration": "./config/tcl.configuration.json"
},
{
"id": "bd",
"extensions": [
".bd"
]
},
{
"id": "vhdl",
"aliases": [
"VHDL",
"vhdl"
],
"extensions": [
".vhd",
".vhdl",
".vho",
".vht"
],
"configuration": "./config/vhdl.configuration.json"
},
{
"id": "verilog",
"aliases": [
"Verilog",
"verilog"
],
"extensions": [
".v",
".V",
".vh",
".vl"
],
"configuration": "./config/verilog.configuration.json"
},
{
"id": "systemverilog",
"aliases": [
"System Verilog",
"systemverilog"
],
"extensions": [
".sv",
".SV"
],
"configuration": "./config/systemverilog.configuration.json"
},
{
"id": "arm",
"aliases": [
"ARM",
"arm"
],
"extensions": [
".s",
".S",
".asm",
".sx"
],
"configuration": "./config/arm.configuration.json"
},
{
"id": "linkerscript",
"aliases": [
"LinkerScript",
"linkerscript"
],
"extensions": [
".ld",
".dld"
],
"configuration": "./config/link.configuration.json"
}
],
"jsonValidation": [
{
"fileMatch": "property.json",
"url": "./project/property-schema.json"
}
],
"grammars": [
{
"language": "linkerscript",
"scopeName": "source.ld",
"path": "./syntaxes/link.json"
},
{
"language": "arm",
"scopeName": "source.arm",
"path": "./syntaxes/arm.json"
},
{
"language": "tcl",
"scopeName": "source.tcl",
"path": "./syntaxes/tcl.json"
},
{
"language": "vhdl",
"scopeName": "source.vhdl",
"path": "./syntaxes/vhdl.json"
},
{
"language": "verilog",
"scopeName": "source.verilog",
"path": "./syntaxes/verilog.json"
},
{
"language": "systemverilog",
"scopeName": "source.systemverilog",
"path": "./syntaxes/systemverilog.json"
}
],
"snippets": [
{
"language": "tcl",
"path": "snippets/tcl.json"
},
{
"language": "vhdl",
"path": "snippets/vhdl.json"
},
{
"language": "verilog",
"path": "snippets/svlog.json"
},
{
"language": "systemverilog",
"path": "snippets/svlog.json"
}
]
{
"id": "tcl",
"aliases": [
"TCL",
"Xilinx Constraints File",
"Synopsis Constraints File"
],
"extensions": [
".tcl",
".sdc",
".xdc",
".fdc"
],
"configuration": "./config/tcl.configuration.json"
},
{
"id": "bd",
"extensions": [
".bd"
]
},
{
"id": "vhdl",
"aliases": [
"VHDL",
"vhdl"
],
"extensions": [
".vhd",
".vhdl",
".vho",
".vht"
],
"configuration": "./config/vhdl.configuration.json"
},
{
"id": "verilog",
"aliases": [
"Verilog",
"verilog"
],
"extensions": [
".v",
".V",
".vh",
".vl"
],
"configuration": "./config/verilog.configuration.json"
},
{
"id": "systemverilog",
"aliases": [
"System Verilog",
"systemverilog"
],
"extensions": [
".sv",
".SV"
],
"configuration": "./config/systemverilog.configuration.json"
},
{
"id": "arm",
"aliases": [
"ARM",
"arm"
],
"extensions": [
".s",
".S",
".asm",
".sx"
],
"configuration": "./config/arm.configuration.json"
},
{
"id": "linkerscript",
"aliases": [
"LinkerScript",
"linkerscript"
],
"extensions": [
".ld",
".dld"
],
"configuration": "./config/link.configuration.json"
}
],
"jsonValidation": [
{
"fileMatch": "property.json",
"url": "./project/property-schema.json"
}
],
"grammars": [
{
"language": "linkerscript",
"scopeName": "source.ld",
"path": "./syntaxes/link.json"
},
{
"language": "arm",
"scopeName": "source.arm",
"path": "./syntaxes/arm.json"
},
{
"language": "tcl",
"scopeName": "source.tcl",
"path": "./syntaxes/tcl.json"
},
{
"language": "vhdl",
"scopeName": "source.vhdl",
"path": "./syntaxes/vhdl.json"
},
{
"language": "verilog",
"scopeName": "source.verilog",
"path": "./syntaxes/verilog.json"
},
{
"language": "systemverilog",
"scopeName": "source.systemverilog",
"path": "./syntaxes/systemverilog.json"
}
],
"snippets": [
{
"language": "tcl",
"path": "snippets/tcl.json"
},
{
"language": "vhdl",
"path": "snippets/vhdl.json"
},
{
"language": "verilog",
"path": "snippets/svlog.json"
},
{
"language": "systemverilog",
"path": "snippets/svlog.json"
}
]
},
"scripts": {
"vscode:prepublish": "npm run compile",

4
package.nls.json Normal file
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@ -0,0 +1,4 @@
{
"digital-ide.property-json.generate.title": "generate property.json",
"digital-ide.property-json.overwrite.title": "overwrite property.json template"
}

4
package.nls.zh-cn.json Normal file
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@ -0,0 +1,4 @@
{
"digital-ide.property-json.generate.title": "生成 property.json 配置文件",
"digital-ide.property-json.overwrite.title": "修改默认的 property.json 模板文件"
}

4
package.nls.zh-tw.json Normal file
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@ -0,0 +1,4 @@
{
"digital-ide.property-json.generate.title": "",
"digital-ide.property-json.overwrite.title": ""
}

5
script/.gitignore vendored Normal file
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@ -0,0 +1,5 @@
__pycache__
dist
*.pyc
*.pyd
*.pyi

5
script/README.md Normal file
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@ -0,0 +1,5 @@
Some scripts for config generation, batch processing etc.
Please run the all the scripts in the `extensionPath`.
command: scripts for `commands` in package.json

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@ -0,0 +1,46 @@
from typing import List
import sys
import os
sys.path.append(os.path.abspath('.'))
from script.util import read_json, write_json
PACKAGE_FILE = './package.json'
LANG_PACKGE_FILES = {
'en': './package.nls.json',
'zh-cn': './package.nls.zh-cn.json',
'zh-tw': './package.nls.zh-tw.json'
}
def generate_title_token(command_name: str) -> str:
names = command_name.split('.')
prj_name = names[0]
main_names = names[1:]
title_token_name = [prj_name] + main_names + ['title']
return '.'.join(title_token_name)
def merge_tokens(lang_package_path: str, tokens: List[str]):
config = read_json(lang_package_path)
for token in tokens:
if token not in config:
config[token] = ""
write_json(lang_package_path, config)
if __name__ == '__main__':
# adjust main package
config = read_json(PACKAGE_FILE)
commands = config['contributes']['commands']
token_names = []
for c_item in commands:
if 'command' in c_item:
token_name = generate_title_token(c_item['command'])
token_names.append(token_name)
c_item['title'] = '%' + token_name + '%'
write_json(PACKAGE_FILE, config)
# cover in lang package
for name, lang_path in LANG_PACKGE_FILES.items():
merge_tokens(lang_path, token_names)

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@ -0,0 +1,6 @@
import sys
import os
sys.path.append(os.path.abspath('.'))
from script.util import read_json, write_json

12
script/util.py Normal file
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@ -0,0 +1,12 @@
import json
from typing import Any
def read_json(path: str) -> Any:
with open(path, 'r', encoding='utf-8') as fp:
config = json.load(fp=fp)
return config
def write_json(path: str, obj: object):
with open(path, 'w', encoding='utf-8') as fp:
json.dump(obj, fp=fp, indent=4, ensure_ascii=False)

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@ -12,6 +12,7 @@ function launch(context: vscode.ExtensionContext) {
export function activate(context: vscode.ExtensionContext) {
console.log('Digital-IDE 0.3.0 is launched');
launch(context);
}
export function deactivate() {}

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@ -1,7 +1,7 @@
import * as assert from 'assert';
import * as fs from 'fs';
import { Arch, PrjInfo, RawPrjInfo, PrjInfoDefaults } from './prjInfo';
import { Arch, PrjInfo, RawPrjInfo, resolve, toSlash } from './prjInfo';
type AbsPath = string;
type RelPath = string;
@ -125,6 +125,22 @@ class OpeParam {
public mergePrjInfo(rawPrjInfo: RawPrjInfo) {
this.prjInfo.merge(rawPrjInfo);
}
/**
* return the absolute path based on workspacePath
* @param relPath
*/
public resolvePathWorkspace(relPath: RelPath): AbsPath {
return resolve(this._workspacePath, relPath);
}
/**
* return the absolute path based on extensionPath
* @param relPath
*/
public resolvePathExtension(relPath: RelPath): AbsPath {
return resolve(this._extensionPath, relPath);
}
};
const opeParam: OpeParam = new OpeParam();

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@ -7,6 +7,7 @@ import * as fspath from 'path';
import { ToolChainType, LibraryState, XilinxIP,
validToolChainType, validXilinxIP, validLibraryState } from './enum';
import { PrjInfoSchema } from './propertySchema';
import assert = require('assert');
type AbsPath = string;
type RelPath = string;
@ -101,34 +102,43 @@ interface RawPrjInfo extends RawPrjInfoMeta {
function toSlash(path: Path): Path {
return path.replace(/\\/g,"\/");
}
}
function resolve(...paths: Path[]): AbsPath {
const absPath = fspath.resolve(...paths);
return toSlash(absPath);
}
function join(...paths: string[]): AbsPath {
const joinedPath = fspath.join(...paths);
return toSlash(joinedPath);
}
class PrjInfo implements PrjInfoMeta {
private _extensionPath: AbsPath = '';
private _workspacePath: AbsPath = '';
private _libCommonPath: AbsPath = '';
private _libCustomPath: AbsPath = '';
// toolChain is the tool chain used in the project
// which is supposed to support xilinx, intel, custom
private _toolChain: ToolChainType = PrjInfoDefaults.toolChain;
// project name, include pl and ps
private _prjName: PrjName = PrjInfoDefaults.prjName;
private readonly _prjName: PrjName = PrjInfoDefaults.prjName;
private _IP_REPO: XilinxIP[] = PrjInfoDefaults.IP_REPO;
private _soc: Soc = PrjInfoDefaults.soc;
private readonly _soc: Soc = PrjInfoDefaults.soc;
private _enableShowLog: boolean = PrjInfoDefaults.enableShowLog;
private _device: string = PrjInfoDefaults.device;
// structure of the project, including path of source of hardware design, testBench
private _arch: Arch = PrjInfoDefaults.arch;
private readonly _arch: Arch = PrjInfoDefaults.arch;
// library to manage
private _library: Library = PrjInfoDefaults.library;
private readonly _library: Library = PrjInfoDefaults.library;
public get toolChain(): ToolChainType {
return this._toolChain;
@ -166,7 +176,41 @@ class PrjInfo implements PrjInfoMeta {
return 'microphase';
}
// resolve path with workspacePath as root
/**
* replace token like ${workspace} in path
* @param path
*/
private replacePathToken(path: AbsPath): AbsPath {
const workspacePath = this._workspacePath;
assert(workspacePath);
this.setDefaultValue(this.prjName, 'PL', 'template');
this.setDefaultValue(this.prjName, 'PS', 'template');
const plname = this.prjName.PL;
const psname = this.prjName.PS;
// TODO : packaging the replacer
return path.replace(new RegExp('${workspace}', 'g'), workspacePath)
.replace(new RegExp('${plname}', 'g'), plname)
.replace(new RegExp('${psname}', 'g'), psname);
}
/**
* uniform a absolute path
* @param path
*/
public uniformisePath(path: AbsPath): AbsPath {
const slashPath = toSlash(path);
const replacedPath = this.replacePathToken(path);
return replacedPath;
}
/**
* resolve path with workspacePath as root
* @param path
* @param check if true, check the existence of path
* @param root root of path, root and path will be joined
* @returns
*/
private resolvePath(path: Path, check: boolean = false, root?: AbsPath): AbsPath | undefined {
let uniformPath = '';
if (fspath.isAbsolute(path)) {
@ -178,6 +222,7 @@ class PrjInfo implements PrjInfoMeta {
uniformPath = toSlash(uniformPath);
if (check) {
if (fs.existsSync(uniformPath)) {
return uniformPath;
@ -278,7 +323,29 @@ class PrjInfo implements PrjInfoMeta {
}
}
/**
* assign defaultValue to obj[attr] if boolean of obj[attr] is false or 'none'
* @param obj
* @param attr
* @param defaultValue
*/
private setDefaultValue<T extends string, K>(obj: Record<T, K>,
attr: T,
defaultValue: K) {
const value: K = obj[attr];
let isNull = !Boolean(value);
if (typeof value === 'string') {
isNull &&= value === 'none';
}
if (isNull) {
obj[attr] = defaultValue;
}
}
public updateArch(arch?: Arch) {
const workspacePath = this._workspacePath;
if (arch) {
this.updatePathWisely(this.arch, 'prjPath', arch.prjPath);
if (arch.hardware) {
@ -291,7 +358,30 @@ class PrjInfo implements PrjInfoMeta {
this.updatePathWisely(this.arch.software, 'src', arch.software.src);
this.updatePathWisely(this.arch.software, 'data', arch.software.data);
}
} else {
let hardwarePath: AbsPath = join(workspacePath, 'user');
let softwarePath: AbsPath = join(workspacePath, 'user', 'Software');
const socCore = this._soc.core;
if (socCore && socCore !== 'none') {
hardwarePath = join(hardwarePath, 'Hardware');
}
this.arch.prjPath = join(workspacePath, 'prj');
this.arch.hardware.src = join(hardwarePath, 'src');
this.arch.hardware.sim = join(hardwarePath, 'sim');
this.arch.hardware.data = join(hardwarePath, 'data');
this.arch.software.src = join(softwarePath, 'src');
this.arch.software.data = join(softwarePath, 'data');
}
// if path is '', set as workspace
this.setDefaultValue(this.arch.hardware, 'src', workspacePath);
this.setDefaultValue(this.arch.hardware, 'sim', workspacePath);
this.setDefaultValue(this.arch.hardware, 'data', workspacePath);
this.setDefaultValue(this.arch.software, 'src', workspacePath);
this.setDefaultValue(this.arch.software, 'data', workspacePath);
}
public updateLibrary(library?: Library) {
@ -306,8 +396,8 @@ class PrjInfo implements PrjInfoMeta {
}
if (library.hardware) {
// TODO : finish this when you can require root of common and custom
const commonPath = this._libCommonPath;
const customPath = this._libCustomPath;
const commonPath = this.libCommonPath;
const customPath = this.libCustomPath;
this.updatePathWisely(this.library.hardware, 'common', library.hardware.common, commonPath);
this.updatePathWisely(this.library.hardware, 'custom', library.hardware.custom, customPath);
}
@ -339,9 +429,14 @@ class PrjInfo implements PrjInfoMeta {
public initContextPath(extensionPath: AbsPath, workspacePath: AbsPath) {
this._extensionPath = toSlash(extensionPath);
this._workspacePath = toSlash(workspacePath);
}
this._libCommonPath = toSlash(fspath.join(extensionPath, 'lib', 'common'));
this._libCustomPath = vscode.workspace.getConfiguration().get('lib.custom.path', this._workspacePath);
public get libCommonPath(): AbsPath {
return join(this._extensionPath, 'lib', 'common');
}
public get libCustomPath(): AbsPath {
return vscode.workspace.getConfiguration().get('lib.custom.path', this._workspacePath);
}
};
@ -355,5 +450,7 @@ export {
Arch,
Soc,
Library,
RawPrjInfo
RawPrjInfo,
toSlash,
resolve
};

22
src/global/util.ts Normal file
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@ -0,0 +1,22 @@
import * as fs from 'fs';
import { AbsPath } from ".";
class PathSet {
files: Set<AbsPath> = new Set<AbsPath>();
add(path: AbsPath) {
this.files.add(path);
}
checkAdd(path: AbsPath | AbsPath[]) {
if (path instanceof Array) {
path.forEach(p => this.checkAdd(p));
} else if (fs.existsSync(path)) {
this.files.add(path);
}
}
}
export {
PathSet
};

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@ -74,15 +74,14 @@ function isHDLFile(path: AbsPath): boolean {
}
function getHDLFiles(path: AbsPath, ignores?: AbsPath[]) {
return pickFileRecursive(path, ignores, (filePath) => {
return isHDLFile(filePath);
});
function getHDLFiles(path: AbsPath | AbsPath[] | Set<AbsPath>, ignores?: AbsPath[]) {
return pickFileRecursive(path, ignores, filePath => isHDLFile(filePath));
}
function pickFileRecursive(path: AbsPath | AbsPath[], ignores?: AbsPath[], condition?: (filePath: string) => boolean | undefined | void): AbsPath[] {
if (path instanceof Array) {
function pickFileRecursive(path: AbsPath | AbsPath[] | Set<AbsPath>, ignores?: AbsPath[], condition?: (filePath: string) => boolean | undefined | void): AbsPath[] {
if ((path instanceof Array) ||
(path instanceof Set)) {
const hdlFiles: AbsPath[] = [];
path.forEach(p => hdlFiles.push(...pickFileRecursive(p)));
return hdlFiles;

0
src/hdlParser/parser/index.d.ts vendored Normal file
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@ -13,7 +13,7 @@ import { XilinxIP } from '../../global/enum';
import { MainOutput } from '../../global/outputChannel';
interface XilinxCustom {
ip_repo: AbsPath,
ipRepo: AbsPath,
bdRepo: AbsPath
};
@ -49,88 +49,77 @@ interface BootInfo {
* xilinx operation under PL
*/
class XilinxOperation {
public setting: vscode.WorkspaceConfiguration;
public xipRepo: XilinxIP[];
public xipPath: AbsPath;
public xbdPath: AbsPath;
public xilinxPath: AbsPath;
public prjPath: AbsPath;
public srcPath: AbsPath;
public simPath: AbsPath;
public datPath: AbsPath;
public softSrc: AbsPath;
public HWPath: AbsPath;
public extensionPath: AbsPath;
public prjConfig: PrjInfo;
public get xipRepo(): XilinxIP[] {
return opeParam.prjInfo.IP_REPO;
}
public custom: XilinxCustom;
public topMod: TopMod;
public prjInfo: PLPrjInfo;
public get xipPath(): AbsPath {
return hdlPath.join(opeParam.extensionPath, 'IP_repo');
}
constructor() {
this.setting = vscode.workspace.getConfiguration();
public get xbdPath(): AbsPath {
return hdlPath.join(opeParam.extensionPath, 'lib', 'xilinx', 'bd');
}
this.xipRepo = opeParam.prjInfo.IP_REPO;
this.xipPath = hdlPath.join(opeParam.extensionPath, 'IP_repo');
this.xbdPath = hdlPath.join(opeParam.extensionPath, 'lib', 'xilinx', 'bd');
this.xilinxPath = hdlPath.join(opeParam.extensionPath, 'resources', 'script', 'xilinx');
this.prjPath = opeParam.prjInfo.arch.prjPath;
this.srcPath = opeParam.prjInfo.arch.hardware.src;
this.simPath = opeParam.prjInfo.arch.hardware.sim;
this.datPath = opeParam.prjInfo.arch.hardware.data;
public get xilinxPath(): AbsPath {
return hdlPath.join(opeParam.extensionPath, 'resources', 'script', 'xilinx');
}
this.softSrc = opeParam.prjInfo.arch.software.src;
this.HWPath = fspath.dirname(this.srcPath);
this.extensionPath = opeParam.extensionPath;
this.prjConfig = opeParam.prjInfo;
public get prjPath(): AbsPath {
return opeParam.prjInfo.arch.prjPath;
}
this.custom = {
ip_repo : this.setting.get('PRJ.xilinx.IP.repo.path', ''),
bdRepo : this.setting.get('PRJ.xilinx.BD.repo.path', ''),
public get srcPath(): AbsPath {
return opeParam.prjInfo.arch.hardware.src;
}
public get simPath(): AbsPath {
return opeParam.prjInfo.arch.hardware.sim;
}
public get datPath(): AbsPath {
return opeParam.prjInfo.arch.hardware.data;
}
public get softSrc(): AbsPath {
return opeParam.prjInfo.arch.software.src;
}
public get HWPath(): AbsPath {
return fspath.dirname(this.srcPath);
}
public get extensionPath(): AbsPath {
return opeParam.extensionPath;
}
public get prjConfig(): PrjInfo {
return opeParam.prjInfo;
}
public get custom(): XilinxCustom {
return {
ipRepo: vscode.workspace.getConfiguration().get('PRJ.xilinx.IP.repo.path', ''),
bdRepo: vscode.workspace.getConfiguration().get('PRJ.xilinx.BD.repo.path', '')
};
}
this.topMod = {
public get topMod(): TopMod {
return {
src : opeParam.firstSrcTopModule.name,
sim : opeParam.firstSimTopModule.name,
};
}
this.prjInfo = {
public get prjInfo(): PLPrjInfo {
return {
path : hdlPath.join(this.prjPath, 'xilinx'),
name : opeParam.prjInfo.prjName.PL,
device : opeParam.prjInfo.device
};
const _this = this;
vscode.workspace.onDidChangeConfiguration(e => _this.getConfig());
}
getConfig() {
this.xipRepo = opeParam.prjInfo.IP_REPO;
this.xipPath = hdlPath.join(opeParam.extensionPath, 'IP_repo');
this.xbdPath = hdlPath.join(opeParam.extensionPath, 'lib', 'xilinx', 'bd');
this.xilinxPath = hdlPath.join(opeParam.extensionPath, 'resources', 'script', 'xilinx');
this.prjPath = opeParam.prjInfo.arch.prjPath;
this.srcPath = opeParam.prjInfo.arch.hardware.src;
this.simPath = opeParam.prjInfo.arch.hardware.sim;
this.datPath = opeParam.prjInfo.arch.hardware.data;
this.softSrc = opeParam.prjInfo.arch.software.src;
this.HWPath = fspath.dirname(this.srcPath);
this.extensionPath = opeParam.extensionPath;
this.prjConfig = opeParam.prjInfo;
this.custom = {
ip_repo : this.setting.get('PRJ.xilinx.IP.repo.path', ''),
bdRepo : this.setting.get('PRJ.xilinx.BD.repo.path', ''),
};
this.topMod = {
src : opeParam.firstSrcTopModule.name,
sim : opeParam.firstSimTopModule.name,
};
}
/**
* xilinx下的launch运行
@ -196,8 +185,8 @@ class XilinxOperation {
// 导入 IP_repo_paths
scripts.push(`set xip_repo_paths {}`);
if (fs.existsSync(this.custom.ip_repo)) {
scripts.push(`lappend xip_repo_paths ${this.custom.ip_repo}`);
if (fs.existsSync(this.custom.ipRepo)) {
scripts.push(`lappend xip_repo_paths ${this.custom.ipRepo}`);
}
this.xipRepo.forEach(

View File

@ -26,9 +26,8 @@ interface PSConfig {
* @descriptionCn xilinx工具链下PS端的操作类
*/
class XilinxOperation {
config: XilinxOperationConfig;
constructor() {
this.config = {
public get config(): XilinxOperationConfig {
return {
path : hdlPath.join(opeParam.extensionPath, 'resources', 'script', 'xilinx', 'soft'),
hw : "SDK_Platform",
bsp: "BSP_package",
@ -43,33 +42,7 @@ class XilinxOperation {
};
}
getConfig() {
this.config = {
path : hdlPath.join(opeParam.extensionPath, 'resources', 'script', 'xilinx', 'soft'),
hw : "SDK_Platform",
bsp: "BSP_package",
dat: opeParam.prjInfo.arch.software.data,
src: opeParam.prjInfo.arch.software.src,
soc: {
core: "ps7_cortexa9_0",
bd: "template",
app: "Hello World",
os: "standalone"
}
};
if (hdlFile.isHasAttr(opeParam.prjInfo, "soc")) {
this.config.soc = opeParam.prjInfo.soc;
}
if (hdlFile.isHasAttr(opeParam.prjInfo, "prjName.PS")) {
this.config.soc.bd = opeParam.prjInfo.prjName.PS;
}
}
launch(config: PSConfig) {
this.getConfig();
const hdfs = hdlFile.pickFileRecursive(this.config.dat, [],
p => p.endsWith('.hdf'));
@ -110,9 +83,7 @@ file delete ${scriptPath} -force\n`;
config.terminal?.sendText(`${config.path} ${scriptPath}`);
}
build(config: PSConfig) {
this.getConfig();
build(config: PSConfig) {
const scriptPath = `${this.config.path}/build.tcl`;
const script = `
setws ${this.config.src}
@ -124,9 +95,7 @@ file delete ${scriptPath} -force\n`;
config.terminal?.sendText(`${config.path} ${scriptPath}`);
}
program(config: PSConfig) {
this.getConfig();
program(config: PSConfig) {
const len = this.config.soc.core.length;
const index = this.config.soc.core.slice(len-1, len);
const scriptPath = `${this.config.path}/program.tcl`;

View File

@ -0,0 +1,39 @@
import * as vscode from 'vscode';
import { AbsPath, opeParam } from '../global';
import { hdlFile, hdlPath } from '../hdlFs';
class LibManage {
constructor() {
}
public get srcPath(): AbsPath {
return opeParam.prjInfo.arch.hardware.src;
}
public get simPath(): AbsPath {
return opeParam.prjInfo.arch.hardware.sim;
}
public get prjPath(): AbsPath {
return opeParam.prjInfo.arch.prjPath;
}
public get localLibPath(): AbsPath {
return hdlPath.join(this.srcPath, 'lib');
}
public get sourceLibPath(): AbsPath {
return hdlPath.join(opeParam.extensionPath, 'lib');
}
public get libCustomPath(): AbsPath {
return opeParam.prjInfo.libCustomPath;
}
public processLibFiles() {
}
};

View File

@ -3,17 +3,12 @@ import * as vscode from 'vscode';
import * as fs from 'fs';
import { AbsPath, opeParam } from '../global';
import { PathSet } from '../global/util';
import { RawPrjInfo } from '../global/prjInfo';
import { ToolChainType } from '../global/enum';
import { hdlFile, hdlDir, hdlPath } from '../hdlFs';
import { hdlFile, hdlPath } from '../hdlFs';
class PrjManage {
setting: vscode.WorkspaceConfiguration;
constructor() {
this.setting = vscode.workspace.getConfiguration();
constructor() {
vscode.commands.registerCommand('digital-ide.property-json.generate',
this.generatePropertyJson);
vscode.commands.registerCommand('digital-ide.property-json.overwrite',
@ -31,7 +26,6 @@ class PrjManage {
}
// overwrite content in current property.json to property-init.json
// TODO test me :D
private async overwritePropertyJson() {
const options = {
preview: false,
@ -79,6 +73,26 @@ class PrjManage {
}
}
public getPrjHardwareFiles(): AbsPath[] {
const searchPathSet = new PathSet();
const hardwareInfo = opeParam.prjInfo.arch.hardware;
// TODO : make something like .gitignore
// search src
searchPathSet.checkAdd(hardwareInfo.src);
// search sim
searchPathSet.checkAdd(hardwareInfo.sim);
const searchPaths = searchPathSet.files;
return hdlFile.getHDLFiles(searchPaths, []);
}
public initialise() {
}
}
const prjManage = new PrjManage();