修复 netlist 跳转的 range 错误

This commit is contained in:
锦恢 2025-01-05 16:27:54 +08:00
parent ce5e69e6f0
commit a143ec8573
3 changed files with 34 additions and 15 deletions

View File

@ -125,7 +125,7 @@ export async function gotoDefinition(data: any, panel: vscode.WebviewPanel) {
const uri = vscode.Uri.file(getRealPath(path));
await vscode.commands.executeCommand('vscode.open', uri, {
selection: new vscode.Range(
new vscode.Position(range.start.line, range.end.character),
new vscode.Position(range.start.line, range.start.character),
new vscode.Position(range.end.line, range.end.character)
)
});

View File

@ -189,7 +189,6 @@ class IcarusSimulate extends Simulate {
/**
* @description 仿
* @param dependences
* @returns
*/
private makeDependenceArguments(dependences: string[]): string {
@ -236,9 +235,6 @@ class IcarusSimulate extends Simulate {
/**
* @description iverilog 仿
* @param name name of top module
* @param path path of the simulated file
* @param dependences dependence that not specified in `include macro
* @returns
*/
private getCommand(name: string, path: AbsPath, dependences: string[]): string | undefined {
@ -276,9 +272,38 @@ class IcarusSimulate extends Simulate {
const argu = '-g' + iverilogCompileOptions.standard;
const outVvpPath = makeSafeArgPath(hdlPath.join(simConfig.simulationHome, name + '.vvp'));
const mainPath = makeSafeArgPath(path);
const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryDirArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryFileArgs}`;
return cmd;
const args = [];
if (macroIncludeArgs) {
args.push(macroIncludeArgs);
}
if (thirdLibraryDirArgs) {
args.push(thirdLibraryDirArgs);
}
if (mainPath) {
args.push(mainPath);
}
if (dependenceArgs) {
args.push(dependenceArgs);
}
if (thirdLibraryFileArgs) {
args.push(thirdLibraryFileArgs);
}
const extaArgs = args.join(' ');
let command = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name}`;
if (extaArgs) {
command += ' ' + extaArgs;
}
const parent = fspath.dirname(path);
command += ' ' + '-I"' + parent + '"';
return command;
}
private execInTerminal(command: string, cwd: AbsPath, hdlModule: HdlModule) {
@ -332,10 +357,6 @@ class IcarusSimulate extends Simulate {
/**
* @description iverilog xxx
* @param simConfig
* @param command
* @param cwd
* @param hdlModule
*/
private runIverilog(simConfig: SimulateConfig, command: string, cwd: string, hdlModule: HdlModule) {
child_process.exec(command, (error, stdout, stderr) => {
@ -369,8 +390,6 @@ class IcarusSimulate extends Simulate {
/**
* @description vvp xxx
* @param command
* @param cwd
*/
private runVvp(command: string, cwd: string) {
child_process.exec(command, { cwd }, (error, stdout, stderr) => {

View File

@ -885,7 +885,7 @@ class HdlModule {
const instModName = rawHdlInstance.type;
if (this.languageId === HdlLangID.Verilog || this.languageId === HdlLangID.SystemVerilog) {
const searchResult = this.searchInstModPath(instModName);
const searchResult = this.searchInstModPath(instModName);
const hdlInstance = new HdlInstance(rawHdlInstance.name,
rawHdlInstance.type,
searchResult.path,