From b949289eceaf880d8445b353129dbabc501f387a Mon Sep 17 00:00:00 2001
From: Nitcloud <sterben.nitcloud@gmail.com>
Date: Sun, 16 Mar 2025 15:11:48 +0800
Subject: [PATCH] fix clean command

---
 resources/script/xilinx/launch.tcl  |  7 -------
 resources/script/xilinx/refresh.tcl | 17 -----------------
 src/function/treeView/command.ts    |  8 ++++++--
 3 files changed, 6 insertions(+), 26 deletions(-)
 delete mode 100644 resources/script/xilinx/launch.tcl
 delete mode 100644 resources/script/xilinx/refresh.tcl

diff --git a/resources/script/xilinx/launch.tcl b/resources/script/xilinx/launch.tcl
deleted file mode 100644
index f2f2d27..0000000
--- a/resources/script/xilinx/launch.tcl
+++ /dev/null
@@ -1,7 +0,0 @@
-set_param general.maxThreads 8
-create_project template d:/Project/FPGA/Design/TCL_project/Test/Efinity/prj/xilinx -part none -force
-set_property SOURCE_SET sources_1   [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-update_compile_order -fileset sim_1 -quiet
-source d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -quiet
-file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/launch.tcl -force
diff --git a/resources/script/xilinx/refresh.tcl b/resources/script/xilinx/refresh.tcl
deleted file mode 100644
index efe7589..0000000
--- a/resources/script/xilinx/refresh.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-remove_files -quiet [get_files]
-set xip_repo_paths {}
-set_property ip_repo_paths $xip_repo_paths [current_project] -quiet
-update_ip_catalog -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/async_fifo.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/DPRAM.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_decode.sv -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_encode.sv -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_pkg.sv -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_controller.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_ctrl.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hyper_bus.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram_test.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/spi_slave.v -quiet
-add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/test.v -quiet
-add_files -fileset constrs_1 d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/data -quiet
-file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -force
diff --git a/src/function/treeView/command.ts b/src/function/treeView/command.ts
index 3643028..3798666 100644
--- a/src/function/treeView/command.ts
+++ b/src/function/treeView/command.ts
@@ -245,8 +245,12 @@ export async function clean() {
     const plName = opeParam.prjInfo.prjName.PL;
     const targetPath = fspath.dirname(opeParam.prjInfo.arch.hardware.src);
 
-    const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/ip`;
-    const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/bd`;
+    let type = 'srcs';
+    if (hdlDir.isDir(`${workspacePath}/prj/xilinx/${plName}.gen`)) {
+        type = 'gen';
+    }
+    const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/ip`;
+    const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/bd`;
 
     hdlDir.mvdir(sourceIpPath, targetPath, true);
     MainOutput.report("move dir from " + sourceIpPath + " to " + targetPath);