#fix sim args process

package.json

@@ -956,7 +956,6 @@
 		"typescript": "^4.8.4"
 	},
 	"dependencies": {
-		"@vscode/wasm-wasi": "^0.8.2",
 		"chokidar": "^3.5.3",
 		"puppeteer-core": "^19.4.1",
 		"showdown": "^2.1.0",

src/function/lsp/core/vlog.ts

@@ -15,6 +15,11 @@ class VlogSymbolStorage {
 
     public async getSymbol(path: AbsPath): ThenableAll {
         path = hdlPath.toSlash(path);
+        const allP = this.symbolMap.get(path);
+        if (allP) {
+            return await allP;
+        }
+        this.updateSymbol(path);
         const all = await this.symbolMap.get(path);
         return all;
     }

src/function/sim/simulate.ts

@@ -166,16 +166,17 @@ class IcarusSimulate extends Simulate {
         return args.join(' ').trim();
     }
 
-    private makeThirdLibraryArguments(simLibPaths: string[]): string {
+    private makeThirdLibraryArguments(simLibPaths: string[]): { fileArgs: string[], dirArgs: string[] } {
-        const args = [];
+        const fileArgs = [];
+        const dirArgs = [];
         for (const libPath of simLibPaths) {
             if(!hdlFile.isDir(libPath)) {
-                args.push(libPath);
+                fileArgs.push(libPath);
             } else {
-                args.push('-y ' + libPath);
+                dirArgs.push('-y ' + libPath);
             }
         }
-        return args.join(' ').trim();
+        return { fileArgs, dirArgs };
     }
 
     /**
@@ -210,13 +211,16 @@ class IcarusSimulate extends Simulate {
         const dependenceArgs = this.makeDependenceArguments(dependences);
         const thirdLibraryArgs = this.makeThirdLibraryArguments(simLibPaths);
 
+        const thirdLibraryFileArgs = thirdLibraryArgs.fileArgs;
+        const thirdLibraryDirArgs = thirdLibraryArgs.dirArgs;
+
         const iverilogPath = simConfig.iverilogPath;
         // default is -g2012
         const argu = '-g' + iverilogCompileOptions.standard;
         const outVvpPath = '"' + hdlPath.join(simConfig.simulationHome, 'out.vvp') + '"';      
         const mainPath = '"' + path + '"';
 
-        const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryArgs} ${mainPath} ${dependenceArgs}`;
+        const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryDirArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryFileArgs}`;
         MainOutput.report(cmd, ReportType.Run);
         return cmd;
     }

src/test/user/Hardware/src/Cordic.v

@@ -78,6 +78,8 @@ initial begin
 	end    
 end
 
+
+
 integer n;
 initial begin
 	for (n = 0; n<=ITERATIONS; n=n+1) begin
@@ -99,6 +101,9 @@ initial begin
 	end    
 end
 
+
+
+
 genvar i;
 generate for(i=0;i<ITERATIONS;i=i+1) begin : CORDIC
 always @ (posedge clk) begin

src/test/user/Hardware/src/mult_module.v

@@ -0,0 +1,80 @@
+// template
+module  template  #(
+        parameter    INPUT_WIDTH  = 12,
+        parameter    OUTPUT_WIDTH = 12
+    )(
+        input [INPUT_WIDTH
+               - 1 : 0]data_in,
+        output reg clk_in = (INPUT_WIDTH -
+                             OUTPUT_WIDTH) ,
+        clk=9'hd0,
+        input rst_n, RST,
+        output [OUTPUT_WIDTH - 1 : 0] data_out
+    );
+
+endmodule  //template
+
+
+module test # (
+        parameter    INPUT_WIDTH  = 12,
+        parameter    OUTPUT_WIDTH = 12
+    )(
+        input                           clk_in,
+        input                           rst_n,
+        input  [INPUT_WIDTH - 1 : 0]    data_in , 
+        input  [3:2] dasta_ff,
+
+        output reg signed [OUTPUT_WIDTH - 1 : 0]   data_out,
+        output reg signed [OUTPUT_WIDTH - 1 : 0]   data_ff
+    );
+
+    wire               	valid_out;
+
+    Cordic #(
+               .XY_BITS      		( 12       		),
+               .PH_BITS      		( 32       		),
+               .ITERATIONS   		( 32       		),
+               .CORDIC_STYLE 		( "ROTATE" 		),
+               .PHASE_ACC    		( "ON"     		))
+           u_Cordic(
+               //input
+               .clk_in    		( clk_in    		),
+               .RST       		( RST       		),
+               .x_i       		( x_i       		),
+               .y_i       		( y_i       		),
+               .phase_in  		( phase_in  		),
+               .valid_in  		( valid_in  		),
+
+               //output
+               .x_o       		( x_o       		),
+               .y_o       		( y_o       		),
+               .phase_out 		( phase_out 		),
+               .valid_out 		( valid_out 		)
+
+               //inout
+           );
+
+    wire [3 : 0] 	count_high;
+    wire [3 : 0] 	count_low;
+    wire              	over;
+
+    template u_template(
+                 //input
+                 .clk        		( clk        		),
+                 .data       		( data       		),
+                 .en         		( en         		),
+                 .load       		( load       		),
+                 .rst        		( rst        		),
+                 .switch     		( switch     		),
+
+                 //output
+                 .count_high 		( count_high 		),
+                 .count_low  		( count_low  		),
+                 .over       		( over       		)
+
+                 //inout
+             );
+
+
+
+endmodule  //test

src/test/vlog/dependence_test/parent.v

@@ -40,6 +40,7 @@ dependence_3 u_dependence_3(
 
 endmodule
 
+
 /* @wavedrom this is wavedrom demo1
 {
     signal : [

src/test/vlog/parse_test/Cordic.v

@@ -12,13 +12,12 @@ module Cordic #(
 	input   signed [XY_BITS-1:0] x_i,
 	input   signed [XY_BITS-1:0] y_i,
 	input   signed [PH_BITS-1:0] phase_in,
+	input   valid_in, 
 
+	output  valid_out,
 	output  signed [XY_BITS-1:0] x_o,
 	output  signed [XY_BITS-1:0] y_o,
-	output  signed [PH_BITS-1:0] phase_out,
+	output  signed [PH_BITS-1:0] phase_out
-
-	input   valid_in, 
-	output  valid_out
 );
 
 localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2;

src/test/vlog/parse_test/mult_module.v

@@ -21,9 +21,11 @@ module test # (
     )(
         input                           clk_in,
         input                           rst_n,
-        input  [INPUT_WIDTH - 1 : 0]    data_in , [3:2] dasta_ff,
+        input  [INPUT_WIDTH - 1 : 0]    data_in , 
+        input  [3:2] dasta_ff,
+
         output reg signed [OUTPUT_WIDTH - 1 : 0]   data_out,
-        reg signed [OUTPUT_WIDTH - 1 : 0]   data_ff
+        output reg signed [OUTPUT_WIDTH - 1 : 0]   data_ff
     );
 
     wire               	valid_out;

syntaxes/verilog.tmLanguage.json

@@ -10,10 +10,10 @@
             "include": "#comments"
         },
         {
-            "include": "#keywords"
+            "include": "#module_pattern"
         },
         {
-            "include": "#module_pattern"
+            "include": "#keywords"
         },
         {
             "include": "#constants"
@@ -116,7 +116,7 @@
                             "name": "entity.name.class.module.reference.verilog"
                         },
                         "2": {
-                            "name": "entity.name.tag.module.identifier.verilog"
+                            "name": "entity.name.function.module.identifier.verilog"
                         }
                     },
                     "end": ";",