diff --git a/package.json b/package.json index 85d3dd2..da5fc1e 100644 --- a/package.json +++ b/package.json @@ -1278,9 +1278,9 @@ "chokidar": "^4.0.1", "minimatch": "^10.0.1", "pako": "^2.1.0", - "puppeteer-core": "^24.4.0", + "puppeteer-core": "^19.4.1", "showdown": "^2.1.0", - "state-machine-cat": "^12.0.21", + "state-machine-cat": "^9.2.5", "tar": "^7.4.3", "temp": "^0.9.4", "vscode-jsonrpc": "^8.2.1", diff --git a/project/property-schema.json b/project/property-schema.json index 364c338..2323299 100644 --- a/project/property-schema.json +++ b/project/property-schema.json @@ -198,7 +198,8 @@ "xc7a35tftg256-1", "xc7a35tcsg324-1", "xc7z035ffg676-2", - "xc7z020clg484-1" + "xc7z020clg484-1", + "Ti60F100S3F2-C4" ] } }, diff --git a/resources/script/xilinx/launch.tcl b/resources/script/xilinx/launch.tcl new file mode 100644 index 0000000..f2f2d27 --- /dev/null +++ b/resources/script/xilinx/launch.tcl @@ -0,0 +1,7 @@ +set_param general.maxThreads 8 +create_project template d:/Project/FPGA/Design/TCL_project/Test/Efinity/prj/xilinx -part none -force +set_property SOURCE_SET sources_1 [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +update_compile_order -fileset sim_1 -quiet +source d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -quiet +file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/launch.tcl -force diff --git a/resources/script/xilinx/refresh.tcl b/resources/script/xilinx/refresh.tcl new file mode 100644 index 0000000..efe7589 --- /dev/null +++ b/resources/script/xilinx/refresh.tcl @@ -0,0 +1,17 @@ +remove_files -quiet [get_files] +set xip_repo_paths {} +set_property ip_repo_paths $xip_repo_paths [current_project] -quiet +update_ip_catalog -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/async_fifo.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/DPRAM.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_decode.sv -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_encode.sv -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_pkg.sv -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_controller.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_ctrl.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hyper_bus.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram_test.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/spi_slave.v -quiet +add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/test.v -quiet +add_files -fileset constrs_1 d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/data -quiet +file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -force diff --git a/src/function/treeView/tree.ts b/src/function/treeView/tree.ts index 4736481..061970b 100644 --- a/src/function/treeView/tree.ts +++ b/src/function/treeView/tree.ts @@ -288,9 +288,15 @@ class ModuleTreeProvider implements vscode.TreeDataProvider { public setFirstTop(type: keyof FirstTop, name: string, path: AbsPath | undefined) { this.firstTop[type] = {name, path}; + if (type == "src") { + opeParam.firstSrcTopModule.name = name; + opeParam.firstSrcTopModule.path = path; + } else if (type == "sim") { + opeParam.firstSimTopModule.name = name; + opeParam.firstSimTopModule.path = path; + } } - private makeFirstTopIconName(type: string): string { return 'current-' + type + '-top'; } diff --git a/src/global/enum.ts b/src/global/enum.ts index 247403b..fdcdb61 100644 --- a/src/global/enum.ts +++ b/src/global/enum.ts @@ -34,6 +34,7 @@ function validToolChainType(name: ToolChainType) { const allTypes = [ 'xilinx', 'intel', + 'efinity', 'custom' ]; return allTypes.includes(name); diff --git a/src/global/opeParam.ts b/src/global/opeParam.ts index 5d4d204..a3c0a6f 100644 --- a/src/global/opeParam.ts +++ b/src/global/opeParam.ts @@ -22,7 +22,7 @@ const OpeParamDefaults = { interface FirstTopModuleDesc { name: string - path: AbsPath + path: AbsPath | undefined }; function readJSON(path: AbsPath): object { diff --git a/src/manager/PL/efinity.ts b/src/manager/PL/efinity.ts index cc05dbe..c380034 100644 --- a/src/manager/PL/efinity.ts +++ b/src/manager/PL/efinity.ts @@ -96,13 +96,25 @@ const security = ` `; +export interface ePLContext { + // 保留启动上下文 + terminal? : vscode.Terminal, + // 目前使用的启动上下文 + process?: ChildProcessWithoutNullStreams, + // 工具类型 + tool? : string, + // 第三方工具运行路径 + path? : string, + // 操作类 + ope : EfinityOperation, +}; export class EfinityOperation { script: string; efxPath: string; constructor() { this.script = ''; - this.efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName}.xml`); + this.efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName.PL}.xml`); } private getDeviceInfo(device: string): string { @@ -120,12 +132,22 @@ export class EfinityOperation { } private getDesignInfo(): string { - let designFile = ` \n`; for (const hdlFile of hdlParam.getAllHdlFiles()) { - // ${hdlFile.path} - designFile += ` \n`; - + switch (hdlFile.projectType) { + case HdlFileProjectType.Src: + case HdlFileProjectType.LocalLib: + case HdlFileProjectType.RemoteLib: + case HdlFileProjectType.Sim: + designFile += ` \n`; + break; + case HdlFileProjectType.IP: + case HdlFileProjectType.Primitive: + // IP 和 原语不用管 + break; + default: + break; + } } designFile += ` ` return ` \n${designFile} @@ -136,25 +158,24 @@ export class EfinityOperation { let constraintFile = ''; hdlFile.pickFileRecursive(opeParam.prjInfo.arch.hardware.data, filePath => { if (filePath.endsWith('.sdc')) { - constraintFile += ` \n`; + constraintFile += ` \n`; } }); constraintFile += ` \n`; - return ` \n${constraintFile} `; + return ` \n${constraintFile} `; } public launch() { - this.script = `\n${this.getDeviceInfo}\n${this.getDesignInfo}\n${this.getConstraintInfo}\n \n \n \n${syn}\n${pnr}\n${bit}\n${debug}\n${security}\n`; + this.script = `\n${this.getDeviceInfo(opeParam.prjInfo.device)}\n${this.getDesignInfo()}\n${this.getConstraintInfo()}\n \n \n \n${syn}\n${pnr}\n${bit}\n${debug}\n${security}\n`; fs.writeFileSync(this.efxPath, this.script); } public build() { - const efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName}.xml`); - exec(`${this.updateEfinixPath()} ${efxPath} --flow compile --work_dir=${opeParam.workspacePath}/prj/efinix --output_dir ${opeParam.workspacePath}/prj/efinix/outflow --cleanup_work_dir work_pt`, (error, stdout, stderr) => { + exec(`${this.updateEfinixPath()} ${this.efxPath} --flow compile --work_dir=${opeParam.workspacePath}/prj/efinix --output_dir ${opeParam.workspacePath}/prj/efinix/outflow --cleanup_work_dir work_pt`, (error, stdout, stderr) => { console.log(error); }) diff --git a/src/manager/PL/index.ts b/src/manager/PL/index.ts index a141436..fa86600 100644 --- a/src/manager/PL/index.ts +++ b/src/manager/PL/index.ts @@ -16,6 +16,7 @@ import { PropertySchema } from '../../global/propertySchema'; import { HardwareOutput, MainOutput, ReportType } from '../../global/outputChannel'; import { AbsPath } from '../../global'; import { t } from '../../i18n'; +import { EfinityOperation } from './efinity'; class PlManage extends BaseManage { context: PLContext; @@ -24,7 +25,7 @@ class PlManage extends BaseManage { super(); this.context = { - tool: opeParam.prjInfo.toolChain || 'xilinx', + tool: opeParam.prjInfo.toolChain, path: '', ope: new XilinxOperation(), terminal: undefined, @@ -34,7 +35,10 @@ class PlManage extends BaseManage { const curToolChain = this.context.tool; if (curToolChain === ToolChainType.Xilinx) { this.context.path = this.context.ope.updateVivadoPath(); - } + } else if (curToolChain === ToolChainType.Efinity) { + this.context.ope = new EfinityOperation(); + this.context.path = this.context.ope.updateEfinixPath(); + } } public launch() { diff --git a/src/manager/PL/xilinx.ts b/src/manager/PL/xilinx.ts index d52b63b..6b28751 100644 --- a/src/manager/PL/xilinx.ts +++ b/src/manager/PL/xilinx.ts @@ -36,7 +36,7 @@ interface PLContext { // 第三方工具运行路径 path? : string, // 操作类 - ope : XilinxOperation, + ope : Record }; interface PLPrjInfo { @@ -54,7 +54,6 @@ interface BootInfo { fsblPath : AbsPath }; - /** * xilinx operation under PL */ @@ -394,7 +393,6 @@ class XilinxOperation { }); // 导入非本地的设计源文件 - console.log(hdlParam.getAllHdlFiles()); for (const hdlFile of hdlParam.getAllHdlFiles()) { switch (hdlFile.projectType) { case HdlFileProjectType.Src: @@ -620,7 +618,6 @@ file delete ${scriptPath} -force\n`; context.process?.stdin.write(cmd + '\n'); } - generateBit(context: PLContext) { vscode.window.showInformationMessage( "Xilinx: BitStream",