initialize
This commit is contained in:
commit
dad5927849
24
.eslintrc.json
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24
.eslintrc.json
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@ -0,0 +1,24 @@
|
||||
{
|
||||
"root": true,
|
||||
"parser": "@typescript-eslint/parser",
|
||||
"parserOptions": {
|
||||
"ecmaVersion": 6,
|
||||
"sourceType": "module"
|
||||
},
|
||||
"plugins": [
|
||||
"@typescript-eslint"
|
||||
],
|
||||
"rules": {
|
||||
"@typescript-eslint/naming-convention": "warn",
|
||||
"@typescript-eslint/semi": "warn",
|
||||
"curly": "warn",
|
||||
"eqeqeq": "warn",
|
||||
"no-throw-literal": "warn",
|
||||
"semi": "off"
|
||||
},
|
||||
"ignorePatterns": [
|
||||
"out",
|
||||
"dist",
|
||||
"**/*.d.ts"
|
||||
]
|
||||
}
|
||||
5
.gitignore
vendored
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5
.gitignore
vendored
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@ -0,0 +1,5 @@
|
||||
out
|
||||
dist
|
||||
node_modules
|
||||
.vscode-test/
|
||||
*.vsix
|
||||
7
.vscode/extensions.json
vendored
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7
.vscode/extensions.json
vendored
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@ -0,0 +1,7 @@
|
||||
{
|
||||
// See http://go.microsoft.com/fwlink/?LinkId=827846
|
||||
// for the documentation about the extensions.json format
|
||||
"recommendations": [
|
||||
"dbaeumer.vscode-eslint"
|
||||
]
|
||||
}
|
||||
34
.vscode/launch.json
vendored
Normal file
34
.vscode/launch.json
vendored
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@ -0,0 +1,34 @@
|
||||
// A launch configuration that compiles the extension and then opens it inside a new window
|
||||
// Use IntelliSense to learn about possible attributes.
|
||||
// Hover to view descriptions of existing attributes.
|
||||
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
|
||||
{
|
||||
"version": "0.2.0",
|
||||
"configurations": [
|
||||
{
|
||||
"name": "Run Extension",
|
||||
"type": "extensionHost",
|
||||
"request": "launch",
|
||||
"args": [
|
||||
"--extensionDevelopmentPath=${workspaceFolder}"
|
||||
],
|
||||
"outFiles": [
|
||||
"${workspaceFolder}/out/**/*.js"
|
||||
],
|
||||
"preLaunchTask": "${defaultBuildTask}"
|
||||
},
|
||||
{
|
||||
"name": "Extension Tests",
|
||||
"type": "extensionHost",
|
||||
"request": "launch",
|
||||
"args": [
|
||||
"--extensionDevelopmentPath=${workspaceFolder}",
|
||||
"--extensionTestsPath=${workspaceFolder}/out/test/suite/index"
|
||||
],
|
||||
"outFiles": [
|
||||
"${workspaceFolder}/out/test/**/*.js"
|
||||
],
|
||||
"preLaunchTask": "${defaultBuildTask}"
|
||||
}
|
||||
]
|
||||
}
|
||||
11
.vscode/settings.json
vendored
Normal file
11
.vscode/settings.json
vendored
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@ -0,0 +1,11 @@
|
||||
// Place your settings in this file to overwrite default and user settings.
|
||||
{
|
||||
"files.exclude": {
|
||||
"out": false // set this to true to hide the "out" folder with the compiled JS files
|
||||
},
|
||||
"search.exclude": {
|
||||
"out": true // set this to false to include "out" folder in search results
|
||||
},
|
||||
// Turn off tsc task auto detection since we have the necessary tasks as npm scripts
|
||||
"typescript.tsc.autoDetect": "off"
|
||||
}
|
||||
20
.vscode/tasks.json
vendored
Normal file
20
.vscode/tasks.json
vendored
Normal file
@ -0,0 +1,20 @@
|
||||
// See https://go.microsoft.com/fwlink/?LinkId=733558
|
||||
// for the documentation about the tasks.json format
|
||||
{
|
||||
"version": "2.0.0",
|
||||
"tasks": [
|
||||
{
|
||||
"type": "npm",
|
||||
"script": "watch",
|
||||
"problemMatcher": "$tsc-watch",
|
||||
"isBackground": true,
|
||||
"presentation": {
|
||||
"reveal": "never"
|
||||
},
|
||||
"group": {
|
||||
"kind": "build",
|
||||
"isDefault": true
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
14
.vscodeignore
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14
.vscodeignore
Normal file
@ -0,0 +1,14 @@
|
||||
.vscode/**
|
||||
.vscode-test/**
|
||||
test/**
|
||||
.gitignore
|
||||
.yarnrc
|
||||
vsc-extension-quickstart.md
|
||||
**/jsconfig.json
|
||||
**/*.map
|
||||
**/.eslintrc.json
|
||||
dist/**/*.map
|
||||
webpack.config.js
|
||||
node_modules
|
||||
src/**
|
||||
vsixmake.js
|
||||
9
CHANGELOG.md
Normal file
9
CHANGELOG.md
Normal file
@ -0,0 +1,9 @@
|
||||
# Change Log
|
||||
|
||||
All notable changes to the "digital-ide" extension will be documented in this file.
|
||||
|
||||
Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how to structure this file.
|
||||
|
||||
## [Unreleased]
|
||||
|
||||
- Initial release
|
||||
71
README.md
Normal file
71
README.md
Normal file
@ -0,0 +1,71 @@
|
||||
# digital-ide README
|
||||
|
||||
This is the README for your extension "digital-ide". After writing up a brief description, we recommend including the following sections.
|
||||
|
||||
## Features
|
||||
|
||||
Describe specific features of your extension including screenshots of your extension in action. Image paths are relative to this README file.
|
||||
|
||||
For example if there is an image subfolder under your extension project workspace:
|
||||
|
||||
\!\[feature X\]\(images/feature-x.png\)
|
||||
|
||||
> Tip: Many popular extensions utilize animations. This is an excellent way to show off your extension! We recommend short, focused animations that are easy to follow.
|
||||
|
||||
## Requirements
|
||||
|
||||
If you have any requirements or dependencies, add a section describing those and how to install and configure them.
|
||||
|
||||
## Extension Settings
|
||||
|
||||
Include if your extension adds any VS Code settings through the `contributes.configuration` extension point.
|
||||
|
||||
For example:
|
||||
|
||||
This extension contributes the following settings:
|
||||
|
||||
* `myExtension.enable`: Enable/disable this extension.
|
||||
* `myExtension.thing`: Set to `blah` to do something.
|
||||
|
||||
## Known Issues
|
||||
|
||||
Calling out known issues can help limit users opening duplicate issues against your extension.
|
||||
|
||||
## Release Notes
|
||||
|
||||
Users appreciate release notes as you update your extension.
|
||||
|
||||
### 1.0.0
|
||||
|
||||
Initial release of ...
|
||||
|
||||
### 1.0.1
|
||||
|
||||
Fixed issue #.
|
||||
|
||||
### 1.1.0
|
||||
|
||||
Added features X, Y, and Z.
|
||||
|
||||
---
|
||||
|
||||
## Following extension guidelines
|
||||
|
||||
Ensure that you've read through the extensions guidelines and follow the best practices for creating your extension.
|
||||
|
||||
* [Extension Guidelines](https://code.visualstudio.com/api/references/extension-guidelines)
|
||||
|
||||
## Working with Markdown
|
||||
|
||||
You can author your README using Visual Studio Code. Here are some useful editor keyboard shortcuts:
|
||||
|
||||
* Split the editor (`Cmd+\` on macOS or `Ctrl+\` on Windows and Linux).
|
||||
* Toggle preview (`Shift+Cmd+V` on macOS or `Shift+Ctrl+V` on Windows and Linux).
|
||||
* Press `Ctrl+Space` (Windows, Linux, macOS) to see a list of Markdown snippets.
|
||||
|
||||
## For more information
|
||||
|
||||
* [Visual Studio Code's Markdown Support](http://code.visualstudio.com/docs/languages/markdown)
|
||||
* [Markdown Syntax Reference](https://help.github.com/articles/markdown-basics/)
|
||||
|
||||
**Enjoy!**
|
||||
4124
package-lock.json
generated
Normal file
4124
package-lock.json
generated
Normal file
File diff suppressed because it is too large
Load Diff
196
package.json
Normal file
196
package.json
Normal file
@ -0,0 +1,196 @@
|
||||
{
|
||||
"name": "digital-ide",
|
||||
"displayName": "digital-ide",
|
||||
"description": "all in one vscode plugin for Verilog/VHDL development",
|
||||
"version": "0.0.1",
|
||||
"engines": {
|
||||
"vscode": "^1.72.0"
|
||||
},
|
||||
"main": "./out/extension.js",
|
||||
"categories": [
|
||||
"Extension Packs",
|
||||
"Programming Languages",
|
||||
"Snippets"
|
||||
],
|
||||
"activationEvents": [
|
||||
"onLanguage:verilog",
|
||||
"onLanguage:vhdl",
|
||||
"onLanguage:systemverilog",
|
||||
"onCommand:TOOL.generate.property",
|
||||
"workspaceContains:.vscode/property.json"
|
||||
],
|
||||
"contributes": {
|
||||
"commands": [
|
||||
{
|
||||
"command": "digital-ide.helloWorld",
|
||||
"title": "Hello World"
|
||||
}
|
||||
],
|
||||
"languages": [
|
||||
{
|
||||
"id": "tcl",
|
||||
"aliases": [
|
||||
"TCL",
|
||||
"Xilinx Constraints File",
|
||||
"Synopsis Constraints File"
|
||||
],
|
||||
"extensions": [
|
||||
".tcl",
|
||||
".sdc",
|
||||
".xdc",
|
||||
".fdc"
|
||||
],
|
||||
"configuration": "./config/tcl.configuration.json"
|
||||
},
|
||||
{
|
||||
"id": "bd",
|
||||
"extensions": [
|
||||
".bd"
|
||||
]
|
||||
},
|
||||
{
|
||||
"id": "vhdl",
|
||||
"aliases": [
|
||||
"VHDL",
|
||||
"vhdl"
|
||||
],
|
||||
"extensions": [
|
||||
".vhd",
|
||||
".vhdl",
|
||||
".vho",
|
||||
".vht"
|
||||
],
|
||||
"configuration": "./config/vhdl.configuration.json"
|
||||
},
|
||||
{
|
||||
"id": "verilog",
|
||||
"aliases": [
|
||||
"Verilog",
|
||||
"verilog"
|
||||
],
|
||||
"extensions": [
|
||||
".v",
|
||||
".V",
|
||||
".vh",
|
||||
".vl"
|
||||
],
|
||||
"configuration": "./config/verilog.configuration.json"
|
||||
},
|
||||
{
|
||||
"id": "systemverilog",
|
||||
"aliases": [
|
||||
"System Verilog",
|
||||
"systemverilog"
|
||||
],
|
||||
"extensions": [
|
||||
".sv",
|
||||
".SV"
|
||||
],
|
||||
"configuration": "./config/systemverilog.configuration.json"
|
||||
},
|
||||
{
|
||||
"id": "arm",
|
||||
"aliases": [
|
||||
"ARM",
|
||||
"arm"
|
||||
],
|
||||
"extensions": [
|
||||
".s",
|
||||
".S",
|
||||
".asm",
|
||||
".sx"
|
||||
],
|
||||
"configuration": "./config/arm.configuration.json"
|
||||
},
|
||||
{
|
||||
"id": "linkerscript",
|
||||
"aliases": [
|
||||
"LinkerScript",
|
||||
"linkerscript"
|
||||
],
|
||||
"extensions": [
|
||||
".ld",
|
||||
".dld"
|
||||
],
|
||||
"configuration": "./config/link.configuration.json"
|
||||
}
|
||||
],
|
||||
"jsonValidation": [
|
||||
{
|
||||
"fileMatch": "property.json",
|
||||
"url": "./validation/property-schema.json"
|
||||
}
|
||||
],
|
||||
"grammars": [
|
||||
{
|
||||
"language": "linkerscript",
|
||||
"scopeName": "source.ld",
|
||||
"path": "./syntaxes/link.json"
|
||||
},
|
||||
{
|
||||
"language": "arm",
|
||||
"scopeName": "source.arm",
|
||||
"path": "./syntaxes/arm.json"
|
||||
},
|
||||
{
|
||||
"language": "tcl",
|
||||
"scopeName": "source.tcl",
|
||||
"path": "./syntaxes/tcl.json"
|
||||
},
|
||||
{
|
||||
"language": "vhdl",
|
||||
"scopeName": "source.vhdl",
|
||||
"path": "./syntaxes/vhdl.json"
|
||||
},
|
||||
{
|
||||
"language": "verilog",
|
||||
"scopeName": "source.verilog",
|
||||
"path": "./syntaxes/verilog.json"
|
||||
},
|
||||
{
|
||||
"language": "systemverilog",
|
||||
"scopeName": "source.systemverilog",
|
||||
"path": "./syntaxes/systemverilog.json"
|
||||
}
|
||||
],
|
||||
"snippets": [
|
||||
{
|
||||
"language": "tcl",
|
||||
"path": "snippets/tcl.json"
|
||||
},
|
||||
{
|
||||
"language": "vhdl",
|
||||
"path": "snippets/vhdl.json"
|
||||
},
|
||||
{
|
||||
"language": "verilog",
|
||||
"path": "snippets/svlog.json"
|
||||
},
|
||||
{
|
||||
"language": "systemverilog",
|
||||
"path": "snippets/svlog.json"
|
||||
}
|
||||
]
|
||||
},
|
||||
"scripts": {
|
||||
"vscode:prepublish": "npm run compile",
|
||||
"compile": "tsc -p ./",
|
||||
"watch": "tsc -watch -p ./",
|
||||
"pretest": "npm run compile && npm run lint",
|
||||
"lint": "eslint src --ext ts",
|
||||
"test": "node ./out/test/runTest.js"
|
||||
},
|
||||
"devDependencies": {
|
||||
"@types/vscode": "^1.74.0",
|
||||
"@types/glob": "^8.0.0",
|
||||
"@types/mocha": "^10.0.0",
|
||||
"@types/node": "16.x",
|
||||
"@typescript-eslint/eslint-plugin": "^5.42.0",
|
||||
"@typescript-eslint/parser": "^5.42.0",
|
||||
"eslint": "^8.26.0",
|
||||
"glob": "^8.0.3",
|
||||
"mocha": "^10.1.0",
|
||||
"typescript": "^4.8.4",
|
||||
"@vscode/test-electron": "^2.2.0"
|
||||
}
|
||||
}
|
||||
35
snippets/sdc.json
Normal file
35
snippets/sdc.json
Normal file
@ -0,0 +1,35 @@
|
||||
{
|
||||
"ILA_CORE": {
|
||||
"prefix": "create_ILA_CORE",
|
||||
"body": [
|
||||
"set_property C_CLK_INPUT_FREQ_HZ ${1:100000000} [get_debug_cores dbg_hub]",
|
||||
"set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]",
|
||||
"set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]",
|
||||
"connect_debug_port dbg_hub/clk [get_nets [list CLK_Global_u/clk_out${2:3}]]"
|
||||
]
|
||||
},
|
||||
"Debug_CORE": {
|
||||
"prefix": "create_Debug_CORE",
|
||||
"body": [
|
||||
"create_debug_core u_ila_${1:0} ila",
|
||||
"set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_$1]",
|
||||
"set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_$1]",
|
||||
"set_property C_ADV_TRIGGER true [get_debug_cores u_ila_$1]",
|
||||
"set_property C_DATA_DEPTH ${2:1024} [get_debug_cores u_ila_$1]",
|
||||
"set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_$1]",
|
||||
"set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_$1]",
|
||||
"set_property C_TRIGIN_EN false [get_debug_cores u_ila_$1]",
|
||||
"set_property C_TRIGOUT_EN false [get_debug_cores u_ila_$1]",
|
||||
"set_property port_width 1 [get_debug_ports u_ila_$1/clk]",
|
||||
"connect_debug_port u_ila_$1/clk [get_nets [list CLK_Global_u/clk_out${3:3}]]"
|
||||
]
|
||||
},
|
||||
"Debug_add_port": {
|
||||
"prefix": "add_port",
|
||||
"body": [
|
||||
"set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_${1:0}/probe0]",
|
||||
"set_property port_width 12 [get_debug_ports u_ila_$1/probe0]",
|
||||
"connect_debug_port u_ila_$1/probe${2:0} [get_nets [list ${3:}]]"
|
||||
]
|
||||
}
|
||||
}
|
||||
906
snippets/svlog.json
Normal file
906
snippets/svlog.json
Normal file
@ -0,0 +1,906 @@
|
||||
{
|
||||
"IDDR": {
|
||||
"prefix": "iddr",
|
||||
"body" : [
|
||||
"IDDR #(",
|
||||
" // \"OPPOSITE_EDGE\", \"SAME_EDGE\" or \"SAME_EDGE_PIPELINED\" ",
|
||||
" .DDR_CLK_EDGE(\"SAME_EDGE\"), ",
|
||||
" .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1",
|
||||
" .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1",
|
||||
" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
|
||||
"IDDR_inst (",
|
||||
"IDDR #(",
|
||||
" .Q1(rx_data_pos), // 1-bit output for positive edge of clock ",
|
||||
" .Q2(rx_data_neg), // 1-bit output for negative edge of clock",
|
||||
" .C(data_clk), // 1-bit clock input",
|
||||
" .CE(1'b1), // 1-bit clock enable input",
|
||||
" .D(rx_data_dly), // 1-bit DDR data input",
|
||||
" .R(1'b0), // 1-bit reset",
|
||||
" .S(1'b0) // 1-bit set",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"ODDR": {
|
||||
"prefix": "oddr",
|
||||
"body" : [
|
||||
"ODDR #(",
|
||||
" .DDR_CLK_EDGE(\"SAME_EDGE\"), // \"OPPOSITE_EDGE\" or \"SAME_EDGE\" ",
|
||||
" .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1",
|
||||
" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
|
||||
"ODDR_inst (",
|
||||
" .Q(odata), // 1-bit DDR output",
|
||||
" .C(data_clk), // 1-bit clock input",
|
||||
" .CE(1'b1), // 1-bit clock enable input",
|
||||
" .D1(data_p), // 1-bit data input (positive edge)",
|
||||
" .D2(data_n), // 1-bit data input (negative edge)",
|
||||
" .R(1'b0), // 1-bit reset",
|
||||
" .S(1'b0) // 1-bit set",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"OBUFDS": {
|
||||
"prefix": "obuf",
|
||||
"body" : [
|
||||
"OBUFDS #(",
|
||||
" .IOSTANDARD(\"LVDS18\"), // Specify the output I/O standard",
|
||||
" .SLEW(\"SLOW\")) // Specify the output slew rate",
|
||||
"OBUFDS_inst (",
|
||||
" .O(tx_frame_p), // Diff_p output (connect directly to top-level port)",
|
||||
" .OB(tx_frame_n), // Diff_n output (connect directly to top-level port)",
|
||||
" .I(tx_frame) // Buffer input ",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"IBUFDS": {
|
||||
"prefix": "ibuf",
|
||||
"body" : [
|
||||
"IBUFDS #(",
|
||||
" .DIFF_TERM(\"FALSE\"), // Differential Termination",
|
||||
" .IBUF_LOW_PWR(\"TRUE\"), // Low power=\"TRUE\", Highest performance=\"FALSE\" ",
|
||||
" .IOSTANDARD(\"DEFAULT\")) // Specify the input I/O standard",
|
||||
"IBUFDS_inst (",
|
||||
" .O(data_clk_tmp), // Buffer output",
|
||||
" .I(data_clk_p), // Diff_p buffer input (connect directly to top-level port)",
|
||||
" .IB(data_clk_n) // Diff_n buffer input (connect directly to top-level port)",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"OSERDESE2": {
|
||||
"prefix": "oserd",
|
||||
"body" : [
|
||||
"OSERDESE2 #(",
|
||||
" .DATA_RATE_OQ(\"DDR\"), // DDR, SDR",
|
||||
" .DATA_RATE_TQ(\"DDR\"), // DDR, BUF, SDR",
|
||||
" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
|
||||
" .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)",
|
||||
" .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)",
|
||||
" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
|
||||
" .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)",
|
||||
" .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)",
|
||||
" .TBYTE_CTL(\"FALSE\"), // Enable tristate byte operation (FALSE, TRUE)",
|
||||
" .TBYTE_SRC(\"FALSE\"), // Tristate byte source (FALSE, TRUE)",
|
||||
" .TRISTATE_WIDTH(4) // 3-state converter width (1,4)",
|
||||
")",
|
||||
"OSERDESE2_inst (",
|
||||
" .OFB(OFB), // 1-bit output: Feedback path for data",
|
||||
" .OQ(OQ), // 1-bit output: Data path output",
|
||||
" // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)",
|
||||
" .SHIFTOUT1(SHIFTOUT1),",
|
||||
" .SHIFTOUT2(SHIFTOUT2),",
|
||||
" .TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate",
|
||||
" .TFB(TFB), // 1-bit output: 3-state control",
|
||||
" .TQ(TQ), // 1-bit output: 3-state control",
|
||||
" .CLK(CLK), // 1-bit input: High speed clock",
|
||||
" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
|
||||
" // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)",
|
||||
" .D1(D1),",
|
||||
" .D2(D2),",
|
||||
" .D3(D3),",
|
||||
" .D4(D4),",
|
||||
" .D5(D5),",
|
||||
" .D6(D6),",
|
||||
" .D7(D7),",
|
||||
" .D8(D8),",
|
||||
" .OCE(OCE), // 1-bit input: Output data clock enable",
|
||||
" .RST(RST), // 1-bit input: Reset",
|
||||
" // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)",
|
||||
" .SHIFTIN1(SHIFTIN1),",
|
||||
" .SHIFTIN2(SHIFTIN2),",
|
||||
" // T1 - T4: 1-bit (each) input: Parallel 3-state inputs",
|
||||
" .T1(T1),",
|
||||
" .T2(T2),",
|
||||
" .T3(T3),",
|
||||
" .T4(T4),",
|
||||
" .TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate",
|
||||
" .TCE(TCE) // 1-bit input: 3-state clock enable",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"ISERDESE2": {
|
||||
"prefix": "iserd",
|
||||
"body" : [
|
||||
"ISERDESE2 #(",
|
||||
" .DATA_RATE(\"DDR\"), // DDR, SDR",
|
||||
" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
|
||||
" .DYN_CLKDIV_INV_EN(\"FALSE\"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)",
|
||||
" .DYN_CLK_INV_EN(\"FALSE\"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)",
|
||||
" // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)",
|
||||
" .INIT_Q1(1'b0),",
|
||||
" .INIT_Q2(1'b0),",
|
||||
" .INIT_Q3(1'b0),",
|
||||
" .INIT_Q4(1'b0),",
|
||||
" .INTERFACE_TYPE(\"MEMORY\"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE",
|
||||
" .IOBDELAY(\"NONE\"), // NONE, BOTH, IBUF, IFD",
|
||||
" .NUM_CE(2), // Number of clock enables (1,2)",
|
||||
" .OFB_USED(\"FALSE\"), // Select OFB path (FALSE, TRUE)",
|
||||
" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
|
||||
" // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)",
|
||||
" .SRVAL_Q1(1'b0),",
|
||||
" .SRVAL_Q2(1'b0),",
|
||||
" .SRVAL_Q3(1'b0),",
|
||||
" .SRVAL_Q4(1'b0))",
|
||||
"ISERDESE2_inst (",
|
||||
" .O(O), // 1-bit output: Combinatorial output",
|
||||
" // Q1 - Q8: 1-bit (each) output: Registered data outputs",
|
||||
" .Q1(Q1),",
|
||||
" .Q2(Q2),",
|
||||
" .Q3(Q3),",
|
||||
" .Q4(Q4),",
|
||||
" .Q5(Q5),",
|
||||
" .Q6(Q6),",
|
||||
" .Q7(Q7),",
|
||||
" .Q8(Q8),",
|
||||
" // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports",
|
||||
" .SHIFTOUT1(SHIFTOUT1),",
|
||||
" .SHIFTOUT2(SHIFTOUT2),",
|
||||
"\n",
|
||||
" // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to",
|
||||
" // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1",
|
||||
" // to Q8 output ports will shift, as in a barrel-shifter operation, one",
|
||||
" // position every time Bitslip is invoked (DDR operation is different from",
|
||||
" // SDR).",
|
||||
" .BITSLIP(BITSLIP), ",
|
||||
"\n",
|
||||
" // CE1, CE2: 1-bit (each) input: Data register clock enable inputs",
|
||||
" .CE1(CE1),",
|
||||
" .CE2(CE2),",
|
||||
" .CLKDIVP(CLKDIVP), // 1-bit input: TBD",
|
||||
" // Clocks: 1-bit (each) input: ISERDESE2 clock input ports",
|
||||
" .CLK(CLK), // 1-bit input: High-speed clock",
|
||||
" .CLKB(CLKB), // 1-bit input: High-speed secondary clock",
|
||||
" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
|
||||
" .OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE=\"MEMORY\" ",
|
||||
" // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity",
|
||||
" .DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion",
|
||||
" .DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion",
|
||||
" // Input Data: 1-bit (each) input: ISERDESE2 data input ports",
|
||||
" .D(D), // 1-bit input: Data input",
|
||||
" .DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2",
|
||||
" .OFB(OFB), // 1-bit input: Data feedback from OSERDESE2",
|
||||
" .OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock",
|
||||
" .RST(RST), // 1-bit input: Active high asynchronous reset",
|
||||
" // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports",
|
||||
" .SHIFTIN1(SHIFTIN1),",
|
||||
" .SHIFTIN2(SHIFTIN2)",
|
||||
");"
|
||||
]
|
||||
},
|
||||
|
||||
"count": {
|
||||
"prefix": "count",
|
||||
"body": [
|
||||
"//define the time counter",
|
||||
"reg [${1:32}:0] cnt$2 = 0;",
|
||||
"reg ${3:impulse};",
|
||||
"parameter SET_TIME = $1'd$4;",
|
||||
"always@(posedge clk) begin",
|
||||
" if (cnt$2 == SET_TIME) begin",
|
||||
" cnt$2 <= $1'd0;",
|
||||
" $3 <= 1'd1;",
|
||||
" end",
|
||||
" else begin",
|
||||
" cnt$2 <= cnt$2 + 1'd1;",
|
||||
" $3 <= 1'd0;",
|
||||
" end",
|
||||
"end"
|
||||
]
|
||||
},
|
||||
|
||||
"divclk": {
|
||||
"prefix": "div",
|
||||
"body": [
|
||||
"reg [${1:3}:0] cnt$2 = 0;",
|
||||
"reg clk_div$2;",
|
||||
"always@(posedge ${3:clk}) begin",
|
||||
" if (cnt$2 == ${4:3}) begin",
|
||||
" cnt$2 <= $1'd0;",
|
||||
" clk_div$2 <= ~clk_div$2;",
|
||||
" end",
|
||||
" else begin",
|
||||
" cnt$2 <= cnt$2 + 1'd1;",
|
||||
" end",
|
||||
"end"
|
||||
]
|
||||
},
|
||||
|
||||
"lock": {
|
||||
"prefix": "lock",
|
||||
"body": [
|
||||
"reg gate$2;",
|
||||
"reg gate$2_buf;",
|
||||
|
||||
"wire gate$2_pose = gate$2 & ~gate$2_buf;",
|
||||
"wire gate$2_nege = ~gate$2 & gate$2_buf;",
|
||||
|
||||
"always@(posedge clk) begin",
|
||||
" gate$2 <= ${1:signal};",
|
||||
" gate$2_buf <= gate$2;",
|
||||
"end"
|
||||
]
|
||||
},
|
||||
|
||||
"posedge": {
|
||||
"prefix": "pos",
|
||||
"body": [
|
||||
"posedge"
|
||||
]
|
||||
},
|
||||
|
||||
"negedge": {
|
||||
"prefix": "neg",
|
||||
"body": [
|
||||
"negedge"
|
||||
]
|
||||
},
|
||||
|
||||
"resetn": {
|
||||
"prefix": "resetn",
|
||||
"body": [
|
||||
"reg rst_n_s1, rst_n_s2;",
|
||||
"wire rst_n",
|
||||
"always @ (posedge clk or negedge sys_rst_n) begin",
|
||||
" if (sys_rst_n) begin",
|
||||
" rst_n_s2 <= 1'b0;",
|
||||
" rst_n_s1 <= 1'b0;",
|
||||
" end",
|
||||
" rst_n_s1 <= 1'b1;",
|
||||
" rst_n_s2 <= rst_n_s1;",
|
||||
" end",
|
||||
"end",
|
||||
"assign rst_n = rst_n_s2;"
|
||||
],
|
||||
"description" : "Asynchronous sys_rst_n synchronous release (intel device)"
|
||||
},
|
||||
|
||||
"reset": {
|
||||
"prefix": "reset",
|
||||
"body": [
|
||||
"reg rst_s1, rst_s2;",
|
||||
"wire rst",
|
||||
"always @ (posedge clk or posedge sys_rst) begin",
|
||||
" if (sys_rst) begin",
|
||||
" rst_s2 <= 1'b0;",
|
||||
" rst_s1 <= 1'b0;",
|
||||
" end",
|
||||
" rst_s1 <= 1'b1;",
|
||||
" rst_s2 <= rst_s1;",
|
||||
" end",
|
||||
"end",
|
||||
"assign rst = rst_s2;"
|
||||
],
|
||||
"description" : "Asynchronous sys_rst synchronous release (xilinx device)"
|
||||
},
|
||||
|
||||
"initial sim": {
|
||||
"prefix": "inits",
|
||||
"body": [
|
||||
"initial begin",
|
||||
" \\$dumpfile(\"wave.vcd\");",
|
||||
" \\$dumpvars(0, ${1:testbench});",
|
||||
" #6000 \\$finish;",
|
||||
"end"
|
||||
],
|
||||
"description": "initial for simulation"
|
||||
},
|
||||
|
||||
"initial array": {
|
||||
"prefix": "inita",
|
||||
"body": [
|
||||
"integer ${1:i};",
|
||||
"initial begin",
|
||||
" for ($1 = 0; $1<${2:range}; $1=$1+1) begin",
|
||||
" ${3:data}[$1] = 0;",
|
||||
" end",
|
||||
"end"
|
||||
],
|
||||
"description": "initial for a array"
|
||||
},
|
||||
|
||||
"debug": {
|
||||
"prefix": "debug",
|
||||
"body": ["(* mark_debug = \"true\" *)"]
|
||||
},
|
||||
|
||||
"time": {
|
||||
"prefix": "time",
|
||||
"body": ["`timescale 1ns / 1ps"]
|
||||
},
|
||||
|
||||
"assign": {
|
||||
"prefix": "assign",
|
||||
"body": ["assign $1 = $2;"]
|
||||
},
|
||||
|
||||
"always_ff block": {
|
||||
"prefix": "ff",
|
||||
"body": [
|
||||
"always_ff @( ${1:clock} ) begin : ${2:blockName}",
|
||||
" $0;",
|
||||
"end"
|
||||
],
|
||||
"description": "Insert an always_ff block"
|
||||
},
|
||||
|
||||
"always_comb block": {
|
||||
"prefix": "comb",
|
||||
"body": [
|
||||
"always_comb begin : ${1:blockName}",
|
||||
" $0;",
|
||||
"end"
|
||||
],
|
||||
"description": "Insert an always_comb block"
|
||||
},
|
||||
|
||||
"always": {
|
||||
"prefix": "alw",
|
||||
"body": [
|
||||
"always @(*) begin",
|
||||
" $1;",
|
||||
"end"
|
||||
],
|
||||
"description": "always @(*)"
|
||||
},
|
||||
|
||||
"alwaysposclk": {
|
||||
"prefix": "alclk",
|
||||
"body": [
|
||||
"always @(posedge clk) begin",
|
||||
" $1;",
|
||||
"end"
|
||||
],
|
||||
"description": "always @(posedge clk) directly"
|
||||
},
|
||||
|
||||
"alwayssyncrst": {
|
||||
"prefix": "alsync",
|
||||
"body": [
|
||||
"always @(posedge clk) begin",
|
||||
" if(rst) begin",
|
||||
" $1 <= 0;",
|
||||
" end",
|
||||
" else begin",
|
||||
" $2 <= $3;",
|
||||
" end",
|
||||
"end"
|
||||
],
|
||||
"description": "synchronous rst (xilinx device)"
|
||||
},
|
||||
|
||||
"alwaysasyncrst": {
|
||||
"prefix": "alasync",
|
||||
"body": [
|
||||
"always @(posedge clk or posedge rst) begin",
|
||||
" if(rst) begin",
|
||||
" $1 <= 0;",
|
||||
" end",
|
||||
" else begin",
|
||||
" $2 <= $3;",
|
||||
" end",
|
||||
"end"
|
||||
],
|
||||
"description": "asynchronous rst (xilinx device)"
|
||||
},
|
||||
|
||||
"alwayssyncrstn": {
|
||||
"prefix": "alsyncn",
|
||||
"body": [
|
||||
"always @(posedge clk) begin",
|
||||
" if(!rst_n) begin",
|
||||
" $1 <= 0;",
|
||||
" end",
|
||||
" else begin",
|
||||
" $2 <= $3;",
|
||||
" end",
|
||||
"end"
|
||||
],
|
||||
"description": "synchronous rst_n (intel device)"
|
||||
},
|
||||
|
||||
"alwaysasyncrstn": {
|
||||
"prefix": "alasyncn",
|
||||
"body": [
|
||||
"always @(posedge clk or negedge rst_n) begin",
|
||||
" if(!rst_n) begin",
|
||||
" $1 <= 0;",
|
||||
" end",
|
||||
" else begin",
|
||||
" $2 <= $3;",
|
||||
" end",
|
||||
"end"
|
||||
],
|
||||
"description": "asynchronous rst_n (intel device)"
|
||||
},
|
||||
|
||||
"beginend": {
|
||||
"prefix": "beginend",
|
||||
"body": [
|
||||
"begin",
|
||||
" $1",
|
||||
"end"
|
||||
],
|
||||
"description": "begin ... end"
|
||||
},
|
||||
|
||||
"case": {
|
||||
"prefix": "case",
|
||||
"body": [
|
||||
"case (${1:conditions})",
|
||||
" $2: $3",
|
||||
"\tdefault: $4",
|
||||
"endcase"
|
||||
],
|
||||
"description": "case () ... endcase"
|
||||
},
|
||||
|
||||
"module with parameters": {
|
||||
"prefix": "modp",
|
||||
"body": [
|
||||
"module ${1:name} #(",
|
||||
" parameter INPUT_WIDTH = ${2:12},",
|
||||
" parameter OUTPUT_WIDTH = $2",
|
||||
") (",
|
||||
" input clk,",
|
||||
" input RST,",
|
||||
" input [INPUT_WIDTH - 1 : 0] ${3:data_i},",
|
||||
" output [OUTPUT_WIDTH - 1 : 0] ${4:data_o}",
|
||||
");",
|
||||
" $5",
|
||||
"endmodule //$1\n"
|
||||
],
|
||||
"description": "Insert a module with parameter"
|
||||
},
|
||||
|
||||
"module without parameters": {
|
||||
"prefix": "mod",
|
||||
"body": [
|
||||
"module ${1:moduleName} (",
|
||||
" input clk,",
|
||||
" input rst,",
|
||||
" $2",
|
||||
");",
|
||||
" $3",
|
||||
"endmodule //$1\n"
|
||||
],
|
||||
"description": "Insert a module without parameter"
|
||||
},
|
||||
"simple module": {
|
||||
"prefix": "module",
|
||||
"body": [
|
||||
"module ${1:moduleName}($2);",
|
||||
" $3",
|
||||
"endmodule //$1\n"
|
||||
],
|
||||
"description": "Insert a common module"
|
||||
},
|
||||
"generate_for": {
|
||||
"prefix": "genfor",
|
||||
"body": [
|
||||
"genvar ${1:i};",
|
||||
"generate for($1 = 0 ; $1 < $2; $1 = $1 + 1) begin : ${3:U}",
|
||||
" $4",
|
||||
"end",
|
||||
"endgenerate"
|
||||
]
|
||||
},
|
||||
|
||||
"generate_if": {
|
||||
"prefix": "genif",
|
||||
"body": [
|
||||
"generate if(${1:conditional}) begin : ${2:U}",
|
||||
" ${3:}",
|
||||
"end",
|
||||
"endgenerate"
|
||||
]
|
||||
},
|
||||
|
||||
"generate_case": {
|
||||
"prefix": "gencase",
|
||||
"body": [
|
||||
"generate",
|
||||
"case (${1:NUM})",
|
||||
"32'd1 : begin : ${2:case1_name}",
|
||||
"$3",
|
||||
" end",
|
||||
"32'd2 : begin : ${4:case1_name}",
|
||||
"$5",
|
||||
" end",
|
||||
"default : begin : NOP end",
|
||||
"endcase",
|
||||
"endgenerate"
|
||||
]
|
||||
},
|
||||
|
||||
"if block": {
|
||||
"prefix": "if",
|
||||
"body": [
|
||||
"if (${1:conditions}) begin",
|
||||
" $0",
|
||||
"end"
|
||||
],
|
||||
"description": "Insert a if block"
|
||||
},
|
||||
|
||||
"include": {
|
||||
"prefix": "inc",
|
||||
"body": [
|
||||
"`include \"$1\""
|
||||
],
|
||||
"description": "`include \"..\""
|
||||
},
|
||||
|
||||
"define": {
|
||||
"prefix": "def",
|
||||
"body": [
|
||||
"`def $1 = $2"
|
||||
],
|
||||
"description": "`define var = val"
|
||||
},
|
||||
|
||||
"parameter": {
|
||||
"prefix": "param",
|
||||
"body": [
|
||||
"parameter $1 = $2;"
|
||||
],
|
||||
"description": "paramter var = val;"
|
||||
},
|
||||
|
||||
"localparam": {
|
||||
"prefix": "param",
|
||||
"body": [
|
||||
"localparam $1 = $2;"
|
||||
],
|
||||
"description": "localparam var = val;"
|
||||
},
|
||||
|
||||
"ifelse": {
|
||||
"prefix": "ifelse",
|
||||
"body": [
|
||||
"if (${1:conditions}) begin",
|
||||
" $2",
|
||||
"end",
|
||||
"else begin",
|
||||
" $3",
|
||||
"end"
|
||||
],
|
||||
"description": "if (...) begin ... end else begin ... end"
|
||||
},
|
||||
|
||||
"else": {
|
||||
"prefix": "else",
|
||||
"body": [
|
||||
"else begin",
|
||||
" $1",
|
||||
"end"
|
||||
],
|
||||
"description": "else begin ... end"
|
||||
},
|
||||
|
||||
"elseif": {
|
||||
"prefix": "elif",
|
||||
"body": [
|
||||
"else if(${1:conditions}) begin",
|
||||
" $2",
|
||||
"end"
|
||||
],
|
||||
"description": "else if(conditions) begin ... end"
|
||||
},
|
||||
|
||||
"for loop": {
|
||||
"prefix": "for",
|
||||
"body": [
|
||||
"for ($1 = $2; $3; $4) begin",
|
||||
" $0",
|
||||
"end"
|
||||
],
|
||||
"description": "for (...) begin ... end"
|
||||
},
|
||||
|
||||
"while loop": {
|
||||
"prefix": "while",
|
||||
"body": [
|
||||
"while ($1) begin",
|
||||
" $2",
|
||||
"end"
|
||||
],
|
||||
"description": "while (...) begin ... end"
|
||||
},
|
||||
|
||||
"function": {
|
||||
"prefix": "function",
|
||||
"body": [
|
||||
"function $1;",
|
||||
" $2;",
|
||||
" $3",
|
||||
"endfunction"
|
||||
],
|
||||
"description": "function (...) ... endfunction"
|
||||
},
|
||||
|
||||
"bit":{
|
||||
"prefix":"bit",
|
||||
"body":"bit"
|
||||
},
|
||||
|
||||
"int":{
|
||||
"prefix":"int",
|
||||
"body":"int"
|
||||
},
|
||||
|
||||
"byte":{
|
||||
"prefix":"byte",
|
||||
"body":"byte"
|
||||
},
|
||||
|
||||
"logic":{
|
||||
"prefix":"logic",
|
||||
"body":"logic"
|
||||
},
|
||||
|
||||
"reg": {
|
||||
"prefix": "reg",
|
||||
"body": [
|
||||
"reg $1;"
|
||||
],
|
||||
"description": "reg reg_name;"
|
||||
},
|
||||
|
||||
"regarray": {
|
||||
"prefix": "rega",
|
||||
"body": [
|
||||
"reg [$1:$2] $3;"
|
||||
],
|
||||
"description": "reg [N:0] reg_name;"
|
||||
},
|
||||
|
||||
"regmemory": {
|
||||
"prefix": "regm",
|
||||
"body": [
|
||||
"reg [$1:$2] $3 [$4:$5];"
|
||||
],
|
||||
"description": "reg [N:0] reg_name [0:M];"
|
||||
},
|
||||
|
||||
"wire": {
|
||||
"prefix": "wire",
|
||||
"body": [
|
||||
"wire $1;"
|
||||
],
|
||||
"description": "wire wire_name;"
|
||||
},
|
||||
|
||||
"wirearray": {
|
||||
"prefix": "wirea",
|
||||
"body": [
|
||||
"wire [$1:$2] $3;"
|
||||
],
|
||||
"description": "wire [N:0] wire_name;"
|
||||
},
|
||||
|
||||
"packed":{
|
||||
"prefix":"packed",
|
||||
"body":"packed"
|
||||
},
|
||||
|
||||
"this":{
|
||||
"prefix": "this",
|
||||
"body": "this"
|
||||
},
|
||||
|
||||
"array":{
|
||||
"prefix":"array",
|
||||
"body":"[${1:8}:${2:0}]$0",
|
||||
"description":"insert [x:y]"
|
||||
},
|
||||
|
||||
"typedef struct packed":{
|
||||
"prefix":"typedefstructpacked",
|
||||
"body":[
|
||||
"typedef struct packed {",
|
||||
" $0",
|
||||
"} ${1:struct_name};"
|
||||
],
|
||||
"description":"typedef struct packed { ... } name"
|
||||
},
|
||||
|
||||
"class":{
|
||||
"prefix":"class",
|
||||
"body":[
|
||||
"class ${1:className};",
|
||||
"\tfunction new();",
|
||||
" $0",
|
||||
"\tendfunction //new()",
|
||||
"endclass //${1}"
|
||||
],
|
||||
"description":"class name; ... endclass"
|
||||
},
|
||||
|
||||
"class extends":{
|
||||
"prefix":"classextends",
|
||||
"body":[
|
||||
"class ${1:className} extends ${2:superClass};",
|
||||
"\tfunction new();",
|
||||
" $0",
|
||||
"\tendfunction //new()",
|
||||
"endclass //${1} extends ${2}"
|
||||
],
|
||||
"description":"class name extends super; ... endclass"
|
||||
},
|
||||
|
||||
"task":{
|
||||
"prefix":"task",
|
||||
"body":[
|
||||
"task ${1:automatic} ${2:taskName}(${3:arguments});",
|
||||
" $0",
|
||||
"endtask //${1}"
|
||||
],
|
||||
"description":"task name; ... endtask"
|
||||
},
|
||||
|
||||
"interface":{
|
||||
"prefix":"interface",
|
||||
"body":[
|
||||
"interface ${1:interfacename};",
|
||||
" $0",
|
||||
"endinterface //${1}"
|
||||
],
|
||||
"description":"interface name; ... endinterface"
|
||||
},
|
||||
|
||||
"display":{
|
||||
"prefix":"$display",
|
||||
"body":[
|
||||
"$$display(\"${1}\"$2);$0"
|
||||
],
|
||||
"description":"$display(\"...\", params...)"
|
||||
},
|
||||
|
||||
"set Module":{
|
||||
"prefix":"setmodule",
|
||||
"body":[
|
||||
"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
|
||||
],
|
||||
"description":"set module, mod i0 (.*);"
|
||||
},
|
||||
|
||||
"typedef enum":{
|
||||
"prefix":"typedefenum",
|
||||
"body":[
|
||||
"typedef enum ${1:data_type} { $0 } ${2:name};"
|
||||
],
|
||||
"description":"typedef enum (data_type) { ... } name"
|
||||
},
|
||||
|
||||
"enum":{
|
||||
"prefix":"enum",
|
||||
"body":[
|
||||
"enum ${1:data_type} { $0 } ${2:name}"
|
||||
],
|
||||
"description":"enum (data_type) { ... } name"
|
||||
},
|
||||
|
||||
"queue":{
|
||||
"prefix":"queue",
|
||||
"body":"${1:data_type} ${2:queue_name}[$];",
|
||||
"description":"insert queue."
|
||||
},
|
||||
|
||||
"mailbox":{
|
||||
"prefix":"mailbox",
|
||||
"body":[
|
||||
"mailbox mbx",
|
||||
"${1:mbx = new();}"
|
||||
],
|
||||
"description":"insert mailbox instance"
|
||||
},
|
||||
|
||||
"Associative array":{
|
||||
"prefix":"AA",
|
||||
"body":"${1:data_type} ${2:name}[${3:index_type}];$0",
|
||||
"description":"insert Associative array(AA)."
|
||||
},
|
||||
|
||||
"assert":{
|
||||
"prefix": "assert",
|
||||
"body": [
|
||||
"assert (${1:condition}) ${2}",
|
||||
"else ${3:error_process}"
|
||||
],
|
||||
"description": "insert assert() ... else ..."
|
||||
},
|
||||
|
||||
"fork-join":{
|
||||
"prefix": "forkjoin",
|
||||
"body": [
|
||||
"fork",
|
||||
" $0",
|
||||
"join"
|
||||
],
|
||||
"description": "fork ... join"
|
||||
},
|
||||
|
||||
"forever":{
|
||||
"prefix": "forever",
|
||||
"body": [
|
||||
"forever begin",
|
||||
" $0",
|
||||
"end"
|
||||
],
|
||||
"description": "forever begin ... end"
|
||||
},
|
||||
|
||||
"write":{
|
||||
"prefix": "$write",
|
||||
"body": [
|
||||
"\\$write($1)"
|
||||
],
|
||||
"description": ""
|
||||
},
|
||||
|
||||
"clog2":{
|
||||
"prefix": "$clog2",
|
||||
"body": [
|
||||
"\\$clog2($1)"
|
||||
],
|
||||
"description": ""
|
||||
},
|
||||
|
||||
"signed":{
|
||||
"prefix": "$signed",
|
||||
"body": [
|
||||
"\\$signed($1)"
|
||||
],
|
||||
"description": ""
|
||||
},
|
||||
|
||||
"unsigned":{
|
||||
"prefix": "$unsigned",
|
||||
"body": [
|
||||
"\\$unsigned($1)"
|
||||
],
|
||||
"description": ""
|
||||
},
|
||||
|
||||
"random" : {
|
||||
"prefix": "$random",
|
||||
"body": [
|
||||
"\\$random($1)"
|
||||
],
|
||||
"description": ""
|
||||
},
|
||||
|
||||
"wavedrom comment": {
|
||||
"prefix" : "wavedrom",
|
||||
"body": [
|
||||
"/* @wavedrom",
|
||||
"{",
|
||||
" $1",
|
||||
"}",
|
||||
"*/"
|
||||
]
|
||||
}
|
||||
}
|
||||
142
snippets/tcl.json
Normal file
142
snippets/tcl.json
Normal file
@ -0,0 +1,142 @@
|
||||
{
|
||||
"for": {
|
||||
"prefix": "for",
|
||||
"body": [
|
||||
"for {set ${1:index} ${2:0}} {\\$${1:index} < ${3:length}} {incr ${1:index}} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "For Loop"
|
||||
},
|
||||
"foreach": {
|
||||
"prefix": "foreach",
|
||||
"body": [
|
||||
"foreach ${1:var} ${2:list} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "Foreach Loop"
|
||||
},
|
||||
"if": {
|
||||
"prefix": "if",
|
||||
"body": [
|
||||
"if {${1:var}} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "If Condition"
|
||||
},
|
||||
"elseif": {
|
||||
"prefix": "elseif",
|
||||
"body": [
|
||||
"elseif {${1:var}} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "ElseIf Condition"
|
||||
},
|
||||
"else": {
|
||||
"prefix": "else",
|
||||
"body": [
|
||||
"else {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "Else Block"
|
||||
},
|
||||
"proc": {
|
||||
"prefix": "proc",
|
||||
"body": [
|
||||
"proc ${1:name} {${2:args}} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "Proc Block"
|
||||
},
|
||||
"while": {
|
||||
"prefix": "while",
|
||||
"body": [
|
||||
"while {${1:var}} {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "While Loop"
|
||||
},
|
||||
"catch": {
|
||||
"prefix": "catch",
|
||||
"body": [
|
||||
"catch {${1:body}} ${2:var}"
|
||||
],
|
||||
"description": "Catch Block"
|
||||
},
|
||||
"try": {
|
||||
"prefix": "try",
|
||||
"body": [
|
||||
"try {",
|
||||
"\t$1",
|
||||
"} finally {",
|
||||
"\t$0",
|
||||
"}"
|
||||
],
|
||||
"description": "Try Block"
|
||||
},
|
||||
"switch": {
|
||||
"prefix": "switch",
|
||||
"body": [
|
||||
"switch ${1:var} {",
|
||||
"\t${2:case} {$3}",
|
||||
"\tdefault {$0}",
|
||||
"}"
|
||||
],
|
||||
"description": "Switch Block"
|
||||
},
|
||||
"oo::class create": {
|
||||
"prefix": "oo::class create",
|
||||
"body": [
|
||||
"oo::class create ${1:name} {",
|
||||
"\t${2:superclass s}",
|
||||
"\tconstructor {} {",
|
||||
"\t\t$3",
|
||||
"\t}",
|
||||
"\tmethod ${4:m} {} {",
|
||||
"\t\t$0",
|
||||
"\t}",
|
||||
"}"
|
||||
],
|
||||
"description": "Class Create"
|
||||
},
|
||||
"tk_chooseDirectory": {
|
||||
"prefix": "tk_chooseDirectory",
|
||||
"body": [
|
||||
"tk_chooseDirectory ${-initialdir dirname -mustexist boolean -title titleString}"
|
||||
],
|
||||
"description": "Choose Directory"
|
||||
},
|
||||
"tk_getOpenFile": {
|
||||
"prefix": "tk_getOpenFile",
|
||||
"body": [
|
||||
"tk_getOpenFile -filetypes {",
|
||||
"\t\t{{Text Files} {.txt} }",
|
||||
"\t\t{{All Files} * }",
|
||||
"\t}"
|
||||
],
|
||||
"description": "Open File Dialog"
|
||||
},
|
||||
"tk_getSaveFile": {
|
||||
"prefix": "tk_getSaveFile",
|
||||
"body": [
|
||||
"tk_getSaveFile -filetypes {",
|
||||
"\t\t{{Text Files} {.txt} }",
|
||||
"\t\t{{All Files} * }",
|
||||
"\t}"
|
||||
],
|
||||
"description": "Save File Dialog"
|
||||
},
|
||||
"tk_messageBox": {
|
||||
"prefix": "tk_messageBox",
|
||||
"body": [
|
||||
"tk_messageBox ${-message msg}"
|
||||
],
|
||||
"description": "Message Box"
|
||||
}
|
||||
}
|
||||
128
snippets/vhdl.json
Normal file
128
snippets/vhdl.json
Normal file
@ -0,0 +1,128 @@
|
||||
{
|
||||
"apro": {
|
||||
"prefix": "apro",
|
||||
"body": "\n${1:identifier} : process( ${2:clock}, ${3:reset} )\nbegin\n if( ${3:reset} = '1' ) then\n $0\n elsif( rising_edge(${2:clock}) ) then\n\n end if ;\nend process ; -- ${1:identifier}\n",
|
||||
"description": "asynchronous process",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"arch": {
|
||||
"prefix": "arch",
|
||||
"body": "architecture ${1:arch} of ${2:ent} is\n\n\tsignal $0\n\nbegin\n\nend ${1:arch} ; -- ${1:arch}",
|
||||
"description": "architecture",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"case": {
|
||||
"prefix": "case",
|
||||
"body": "case( ${1:signal_name} ) is\n\n\twhen ${2:IDLE} =>\n\t\t$0\n\n\twhen others =>\n\nend case ;",
|
||||
"description": "case",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"else": {
|
||||
"prefix": "else",
|
||||
"body": "else\n\t$0",
|
||||
"description": "else",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"elsif": {
|
||||
"prefix": "elsif",
|
||||
"body": "elsif ${1:expression} then\n\t$0",
|
||||
"description": "elsif",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"ent": {
|
||||
"prefix": "ent",
|
||||
"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent};",
|
||||
"description": "entity",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"entarch": {
|
||||
"prefix": "entarch",
|
||||
"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ;\n\narchitecture ${2:arch} of ${1:ent} is\n\n\n\nbegin\n\n\n\nend architecture ; -- ${2:arch}",
|
||||
"description": "entity architecture",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"for": {
|
||||
"prefix": "for",
|
||||
"body": "${1:identifier} : for ${2:i} in ${3:0} to ${4:10} loop\n\t$0\nend loop ; -- ${1:identifier}",
|
||||
"description": "for loop",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"forg": {
|
||||
"prefix": "forg",
|
||||
"body": "${1:identifier} : for ${2:i} in ${3:x} to ${4:y} generate\n\t$0\nend generate ; -- ${1:identifier}",
|
||||
"description": "for generate",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"if": {
|
||||
"prefix": "if",
|
||||
"body": "if ${1:expression} then\n\t$0\nend if ;",
|
||||
"description": "if",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"pack": {
|
||||
"prefix": "pack",
|
||||
"body": "package ${1:pkg} is\n\t$0\nend package ;",
|
||||
"description": "package",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"pro": {
|
||||
"prefix": "pro",
|
||||
"body": "${1:identifier} : process( ${2:sensitivity_list} )\nbegin\n\t$0\nend process ; -- ${1:identifier}",
|
||||
"description": "process",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"s": {
|
||||
"prefix": "s",
|
||||
"body": "signed(${1:x} downto ${2:0}) ;$0",
|
||||
"description": "signed downto",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"sr": {
|
||||
"prefix": "sr",
|
||||
"body": "signed(${1:signal}'range) ;$0",
|
||||
"description": "signed range",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"spro": {
|
||||
"prefix": "spro",
|
||||
"body": "${1:identifier} : process( ${2:clock} )\nbegin\n\tif( rising_edge(${2:clock}) ) then\n\t\t$0\n\tend if ;\nend process ; -- ${1:identifier}",
|
||||
"description": "synchronous process",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"slv": {
|
||||
"prefix": "slv",
|
||||
"body": "std_logic_vector(${1:x} downto ${2:0}) ;$0",
|
||||
"description": "std_logic_vector downto",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"slvr": {
|
||||
"prefix": "slvr",
|
||||
"body": "std_logic_vector(${1:signal}'range) ;$0",
|
||||
"description": "std_logic_vector range",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"u": {
|
||||
"prefix": "u",
|
||||
"body": "unsigned(${1:x} downto ${2:0}) ;$0",
|
||||
"description": "unsigned downto",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"ur": {
|
||||
"prefix": "ur",
|
||||
"body": "unsigned(${1:signal}'range) ;$0",
|
||||
"description": "unsigned range",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"vhdl": {
|
||||
"prefix": "vhdl",
|
||||
"body": "library ieee ;\n\tuse ieee.std_logic_1164.all ;\n\tuse ieee.numeric_std.all ;\n\nentity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ; \n\narchitecture ${2:arch} of ${1:ent} is\n\nbegin\n\nend architecture ;",
|
||||
"description": "vhdl template",
|
||||
"scope": "source.vhdl"
|
||||
},
|
||||
"while": {
|
||||
"prefix": "while",
|
||||
"body": "${1:identifier} : while ${2:expression} loop\n\t$0\nend loop ; -- ${1:identifier}",
|
||||
"description": "while",
|
||||
"scope": "source.vhdl"
|
||||
}
|
||||
}
|
||||
12
src/extension.ts
Normal file
12
src/extension.ts
Normal file
@ -0,0 +1,12 @@
|
||||
import * as vscode from 'vscode';
|
||||
|
||||
export function activate(context: vscode.ExtensionContext) {
|
||||
console.log('Congratulations, your extension "digital-ide" is now active!');
|
||||
let disposable = vscode.commands.registerCommand('digital-ide.helloWorld', () => {
|
||||
vscode.window.showInformationMessage('Hello World from digital-ide!');
|
||||
});
|
||||
|
||||
context.subscriptions.push(disposable);
|
||||
}
|
||||
|
||||
export function deactivate() {}
|
||||
23
src/test/runTest.ts
Normal file
23
src/test/runTest.ts
Normal file
@ -0,0 +1,23 @@
|
||||
import * as path from 'path';
|
||||
|
||||
import { runTests } from '@vscode/test-electron';
|
||||
|
||||
async function main() {
|
||||
try {
|
||||
// The folder containing the Extension Manifest package.json
|
||||
// Passed to `--extensionDevelopmentPath`
|
||||
const extensionDevelopmentPath = path.resolve(__dirname, '../../');
|
||||
|
||||
// The path to test runner
|
||||
// Passed to --extensionTestsPath
|
||||
const extensionTestsPath = path.resolve(__dirname, './suite/index');
|
||||
|
||||
// Download VS Code, unzip it and run the integration test
|
||||
await runTests({ extensionDevelopmentPath, extensionTestsPath });
|
||||
} catch (err) {
|
||||
console.error('Failed to run tests');
|
||||
process.exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
main();
|
||||
15
src/test/suite/extension.test.ts
Normal file
15
src/test/suite/extension.test.ts
Normal file
@ -0,0 +1,15 @@
|
||||
import * as assert from 'assert';
|
||||
|
||||
// You can import and use all API from the 'vscode' module
|
||||
// as well as import your extension to test it
|
||||
import * as vscode from 'vscode';
|
||||
// import * as myExtension from '../../extension';
|
||||
|
||||
suite('Extension Test Suite', () => {
|
||||
vscode.window.showInformationMessage('Start all tests.');
|
||||
|
||||
test('Sample test', () => {
|
||||
assert.strictEqual(-1, [1, 2, 3].indexOf(5));
|
||||
assert.strictEqual(-1, [1, 2, 3].indexOf(0));
|
||||
});
|
||||
});
|
||||
38
src/test/suite/index.ts
Normal file
38
src/test/suite/index.ts
Normal file
@ -0,0 +1,38 @@
|
||||
import * as path from 'path';
|
||||
import * as Mocha from 'mocha';
|
||||
import * as glob from 'glob';
|
||||
|
||||
export function run(): Promise<void> {
|
||||
// Create the mocha test
|
||||
const mocha = new Mocha({
|
||||
ui: 'tdd',
|
||||
color: true
|
||||
});
|
||||
|
||||
const testsRoot = path.resolve(__dirname, '..');
|
||||
|
||||
return new Promise((c, e) => {
|
||||
glob('**/**.test.js', { cwd: testsRoot }, (err, files) => {
|
||||
if (err) {
|
||||
return e(err);
|
||||
}
|
||||
|
||||
// Add files to the test suite
|
||||
files.forEach(f => mocha.addFile(path.resolve(testsRoot, f)));
|
||||
|
||||
try {
|
||||
// Run the mocha test
|
||||
mocha.run(failures => {
|
||||
if (failures > 0) {
|
||||
e(new Error(`${failures} tests failed.`));
|
||||
} else {
|
||||
c();
|
||||
}
|
||||
});
|
||||
} catch (err) {
|
||||
console.error(err);
|
||||
e(err);
|
||||
}
|
||||
});
|
||||
});
|
||||
}
|
||||
319
syntaxes/arm.json
Normal file
319
syntaxes/arm.json
Normal file
@ -0,0 +1,319 @@
|
||||
{
|
||||
"$schema": "https://raw.githubusercontent.com/martinring/tmlanguage/master/tmlanguage.json",
|
||||
"scopeName": "source.arm",
|
||||
"name": "ARM",
|
||||
"fileTypes": [
|
||||
"s",
|
||||
"S",
|
||||
"asm",
|
||||
"sx"
|
||||
],
|
||||
"patterns": [
|
||||
{
|
||||
"match": "^\\s*[#\\.](define|include|(end|el|else)?if|if(def|ndef)?|else)(\\s(defined\\([a-zA-Z_]+\\)|[a-zA-Z_]+))?$",
|
||||
"name": "meta.preprocessor"
|
||||
},
|
||||
{
|
||||
"match": "^\\s*\\.?\\w+:\\s*(?=$|;)",
|
||||
"name": "routine.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\b(?i)(?:v?(?:add|cvt|bic|sub|trn|cmp|div|qdmulh|mrs|mul|ld1|qadd|qshrun|st[1234]|addw|mull|mlal|rshrn|swp|qmovunand|m(?:rs|sr)|eor|sub|rsb|adc|sbc|rsc|and|tst|teq|cmp|cmn|orr|mov|bic|mvn|neg|lsr|lsl|ror|asr)|mul|mla|mull|smlabb|rev(?:8|16)?|pld|adr|adrl|vswp)(?:(?:(?=s)s(\\w{2})?)|(\\w{2})s?)?(?-i)\\b",
|
||||
"name": "support.function.mnemonic.arithmetic.arm",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.arithmetic.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"2": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.arithmetic.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"match": "\\b(?i)v?(?:ldr|str)(?:d(\\w{2})?|(?:(?:s?b|s?h)(\\w{2})?|(\\w{2})(?:s?b|s?h)?))(?-i)\\b",
|
||||
"name": "support.function.mnemonic.memory.arm",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.memory.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"2": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.memory.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"3": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.memory.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"match": "\\b(?i)(?:mov(?:w|t)?|pac(?:dz?[a|b]|ga|i(?:[a|b](?:1716|sp|z)?)|z[a|b])|swi|svc|wfi|dmb|clrex|dsb|isb|v?(?:push|pop)|b(?:l|l?x|l?r)?|(?:i|e)?ret(?:aa|ab)?|(?:st|ld)(?:p|r(?:ex|s?(?:h|b)|d)?|m(?:(?:f|e)(?:d|a)|(?:d|i)(?:b|a))?))(?:(?:(?=s)s(\\w{2})?)|(\\w{2})s?)?(?-i)\\b",
|
||||
"name": "support.function.mnemonic.memory.arm",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.memory.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"2": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "support.function.mnemonic.memory.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w{2}",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"match": "\\b(?i)(def(b|w|s)|equ|align\\s.+\\.s)(?-i)\\b",
|
||||
"name": "keyword.control.define.arm"
|
||||
},
|
||||
{
|
||||
"name": "keyword.control.directive.arm",
|
||||
"match": "\\.(?i)(globl|global|extern|weak|macro|endm|purgem|section|text|data|bss|arm|align|balign|irp|rept|endr|(un)?req|error|short|(end)?func|hidden|type|cpu|fpu|arch|code|syntax|altmacro|object_arch|word|int|string|thumb(_set)?|set|pragma|undef|line|get)(?-i)\\b"
|
||||
},
|
||||
{
|
||||
"match": "\\b\\=",
|
||||
"name": "keyword.control.evaluation"
|
||||
},
|
||||
{
|
||||
"match": "\\b(?i)nop(\\w+)?(?-i)\\b",
|
||||
"name": "comment.nop.arm",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#conditions",
|
||||
"name": "comment.nop.arm"
|
||||
},
|
||||
{
|
||||
"match": "\\w+",
|
||||
"name": "invalid.illegal.condition.arm"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "storage.memaddress.arm",
|
||||
"match": "\\[[ \\t]*(\\w+),[ \\t]*([a-zA-Z0-9#-]+)[ \\t]*\\]!?",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#registers"
|
||||
}
|
||||
]
|
||||
},
|
||||
"2": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#numerics"
|
||||
},
|
||||
{
|
||||
"include": "#registers"
|
||||
},
|
||||
{
|
||||
"include": "#variables"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "storage.stack.arm",
|
||||
"begin": "\\{\\h*",
|
||||
"end": "\\h*\\}\\^?",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#registers_list"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"include": "#registers"
|
||||
},
|
||||
{
|
||||
"include": "#variables"
|
||||
},
|
||||
{
|
||||
"include": "#numerics"
|
||||
},
|
||||
{
|
||||
"include": "#strings"
|
||||
},
|
||||
{
|
||||
"include": "#comments"
|
||||
}
|
||||
],
|
||||
"repository": {
|
||||
"comments": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "([;@]|//|#).*$",
|
||||
"name": "comment.arm"
|
||||
},
|
||||
{
|
||||
"begin": "\\/\\*",
|
||||
"beginCaptures": {
|
||||
"0": {
|
||||
"name": "comment.begin.arm"
|
||||
}
|
||||
},
|
||||
"endCaptures": {
|
||||
"0": {
|
||||
"name": "comment.end.arm"
|
||||
}
|
||||
},
|
||||
"end": "\\*\\/",
|
||||
"name": "comment.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"conditions": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "ne|eq|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|lt|le|gt|ge|al"
|
||||
}
|
||||
]
|
||||
},
|
||||
"numerics": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "#?-?(0x|&)[0-9a-fA-F_]+\\b",
|
||||
"name": "constant.numeric.hex.arm"
|
||||
},
|
||||
{
|
||||
"match": "#?[0-9]+\\b",
|
||||
"name": "constant.numeric.dec.arm"
|
||||
},
|
||||
{
|
||||
"match": "#?0b[01]+\\b",
|
||||
"name": "constant.numeric.bin.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"registers": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\b(?i)([rcp]([0-9]|1[0-5])|[xwbhsdq]([0-9]|1[0-9]|2[0-9]|3[0-1])|wzr|xzr|wsp|fpsr|fpcr|a[1-4]|v([0-9]|1[0-9]|2[0-9]|3[0-1])\\.(16b|8[b|h]|4[s|h]|2[s|d])|sl|sb|fp|ip|sp|lr|(c|s)psr(_c)?|pc|fpsid|fpscr|fpexc|APSR_nzcv|sy)(?-i)(!|\\b)",
|
||||
"name": "storage.register.arm"
|
||||
}
|
||||
]
|
||||
},
|
||||
"registers_list": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "(\\w+)(?:\\h*\\-\\h*(\\w+))?(?:,\\h*([a-zA-Z0-9,\\-\\h]+))?",
|
||||
"captures": {
|
||||
"1": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#registers"
|
||||
}
|
||||
]
|
||||
},
|
||||
"2": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#registers"
|
||||
}
|
||||
]
|
||||
},
|
||||
"3": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#registers_list"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
"strings": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "string.quoted.arm",
|
||||
"begin": "\"",
|
||||
"end": "\""
|
||||
},
|
||||
{
|
||||
"match": "\\'\\S\\'",
|
||||
"name": "string.char.arm"
|
||||
},
|
||||
{
|
||||
"name": "invalid.illegal.string.arm",
|
||||
"match": "\"[^\"]+$"
|
||||
},
|
||||
{
|
||||
"name": "invalid.illegal.char.arm",
|
||||
"match": "\\'\\S{2,}\\'"
|
||||
}
|
||||
]
|
||||
},
|
||||
"variables": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "(?<!^)\\b#?-?[a-zA-Z_][0-9a-zA-Z_]*\\b",
|
||||
"name": "variable.named.arm"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
327
syntaxes/link.json
Normal file
327
syntaxes/link.json
Normal file
@ -0,0 +1,327 @@
|
||||
{
|
||||
"name":"LinkerScript",
|
||||
"scopeName":"source.ld",
|
||||
"fileTypes":["ld"],
|
||||
"patterns":[
|
||||
{"include":"#comments"},
|
||||
{"include":"#simple_commands"},
|
||||
{"include":"#assignments"},
|
||||
{"include":"#sections"},
|
||||
{"include":"#memory"},
|
||||
{"include":"#phdrs"},
|
||||
{"include":"#version"},
|
||||
{"include":"#expressions"}
|
||||
],
|
||||
"repository":{
|
||||
"comments":{
|
||||
"name":"comment.block.ld",
|
||||
"begin":"/\\*",
|
||||
"beginCaptures":{
|
||||
"0":{
|
||||
"name":"punctuation.definition.comment.begin.ld"
|
||||
}
|
||||
},
|
||||
"end":"\\*/",
|
||||
"endCaptures":{
|
||||
"0":{
|
||||
"name":"punctuation.definition.comment.end.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
"simple_commands":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: ENTRY )\\b"
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: INCLUDE |INPUT |GROUP |OUTPUT |SEARCH_DIR |STARTUP )\\b"
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: OUTPUT_FORMAT |TARGET )\\b"
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: ASSERT |EXTERN |FORCE_COMMON_ALLOCATION |INHIBIT_COMMON_ALLOCATION |NOCROSSREFS |OUTPUT_ARCH )\\b"
|
||||
}
|
||||
]
|
||||
},
|
||||
"assignments":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"=|\\+=|-=|\\*=|/=|<<=|>>=|&=|\\|="
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: PROVIDE |HIDDEN |PROVIDE_HIDDEN )\\b"
|
||||
}
|
||||
]
|
||||
},
|
||||
"sections":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?:SECTIONS)\\b"
|
||||
},
|
||||
{
|
||||
"name":"section.input.ld",
|
||||
"match":"(?x) (\\S+)((?:\\s*\\(\\s*)(((\\.[\\.\\*\\w]+)(?:\\s*))+)(?:\\s*\\)))",
|
||||
"captures":{
|
||||
"1":{
|
||||
"name":"support.function.builtin.ld"
|
||||
},
|
||||
"3":{
|
||||
"name":"variable.other.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"section.output.prepart.ld",
|
||||
"match":"(?mx) (\\B\\.[\\.\\*\\w]+\\b)(?:\\s*)(\\w*)(?:\\s*)((\\(\\s*[\\w]*\\s*\\))?)(?:\\s*)(\\:)(?:\\s*)((AT)?)(?:\\s*\\(?)(\\w*)(?:\\s*\\)?)",
|
||||
"captures":{
|
||||
"1":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"constant.numeric.ld"
|
||||
},
|
||||
"4":{
|
||||
"name":"keyword.control.ld"
|
||||
},
|
||||
"5":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"7":{
|
||||
"name":"support.function.builtin.ld"
|
||||
},
|
||||
"8":{
|
||||
"name":"constant.numeric.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"section.output.postpart.ld",
|
||||
"match":"(?:\\}\\s*)((\\>)(\\s*\\w*)?)(?:\\s*)((AT)(?:\\s*)(\\>)(?:\\s*)(\\w*))?(?:\\s*)(((\\:\\w*)(?:\\s*))*)(((\\=)(?:\\s*)(\\w*))?)",
|
||||
"captures":{
|
||||
"2":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"3":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"5":{
|
||||
"name":"support.function.builtin.ld"
|
||||
},
|
||||
"6":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"7":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"8":{
|
||||
"name":"keyword.control.ld"
|
||||
},
|
||||
"13":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"14":{
|
||||
"name":"constant.numeric.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: EXCLUDE_FILE |CREATE_OBJECT_SYMBOLS |CONSTRUCTORS )\\b"
|
||||
},
|
||||
{
|
||||
"name":"datatypes.ld",
|
||||
"match":"(?x) (BYTE|SHORT|LONG|QUAD|SQUAD)(?:\\s*\\(\\s*)([^\\(\\)]*)(?:\\s*\\))",
|
||||
"captures":{
|
||||
"1":{
|
||||
"name":"support.type.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"constant.numeric.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"section.discard.ld",
|
||||
"match":"(/DISCARD/)(?:\\s*)(\\:)",
|
||||
"captures":{
|
||||
"1":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"keyword.operand.ld"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
"memory":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?:MEMORY)\\b"
|
||||
},
|
||||
{
|
||||
"name":"memory.config.ld",
|
||||
"match":"(\\S*)(?:\\s*\\(\\s*)((R|r|W|w|X|x|A|a|I|i|L|l|\\!)+)(?:\\s*\\)\\s*)(\\:)((?:\\s*)(ORIGIN|org|o|LENGTH|len|l)(?:\\s*)(\\=)(?:\\s*)(\\w*)(,?))((?:\\s*)(ORIGIN|org|o|LENGTH|len|l)(?:\\s*)(\\=)(?:\\s*)(\\w*))",
|
||||
"captures":
|
||||
{
|
||||
"1":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"keyword.control.ld"
|
||||
},
|
||||
"4":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"6":{
|
||||
"name":"support.variable.ld"
|
||||
},
|
||||
"7":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"8":{
|
||||
"name":"constant.numeric.ld"
|
||||
},
|
||||
"11":{
|
||||
"name":"support.variable.ld"
|
||||
},
|
||||
"12":{
|
||||
"name":"keyword.operand.ld"
|
||||
},
|
||||
"13":{
|
||||
"name":"constant.numeric.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: LENGTH |len |l |ORIGIN |org |o )\\b"
|
||||
}
|
||||
]
|
||||
},
|
||||
"phdrs":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?:PHDRS)\\b"
|
||||
},
|
||||
{
|
||||
"name":"phdrs.config.ld",
|
||||
"match":"(\\w*)(?:\\s*)(PT_NULL|PT_LOAD|PT_DYNAMIC|PT_INTERP|PT_NOTE|PT_SHLIB|PT_PHDR)(?:\\s*)((FILEHDR)?)(?:\\s*)((PHDRS)?)(?:\\s*)((((AT)?)(?:\\s*\\(\\s*)(\\w*)(?:\\s*\\)\\s*))?)((((FLAGS)?)(?:\\s*\\(\\s*)(\\w*)(?:\\s*\\)\\s*))?)(\\;)",
|
||||
"captures":{
|
||||
"1":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"constant.numeric.ld"
|
||||
},
|
||||
"4":{
|
||||
"name":"keyword.control.ld"
|
||||
},
|
||||
"6":{
|
||||
"name":"keyword.control.ld"
|
||||
},
|
||||
"10":{
|
||||
"name":"support.function.builtin.ld"
|
||||
},
|
||||
"11":{
|
||||
"name":"constant.numeric.ld"
|
||||
},
|
||||
"15":{
|
||||
"name":"support.function.builtin.ld"
|
||||
},
|
||||
"16":{
|
||||
"name":"constant.numeric.ld"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
"version":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?:VERSION)\\b"
|
||||
}
|
||||
]
|
||||
},
|
||||
"expressions":{
|
||||
"patterns":[
|
||||
{
|
||||
"name":"expression.ld",
|
||||
"match":"(\\w*)(?:\\s*)(=|\\+=|-=|\\*=|/=|<<=|>>=|&=|\\|=)",
|
||||
"captures":
|
||||
{
|
||||
"1":{
|
||||
"name":"variable.other.ld"
|
||||
},
|
||||
"2":{
|
||||
"name":"keyword.operand.ld"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name":"constant.numeric.ld",
|
||||
"match":"(?x) \\b(?:(MAXPAGESIZE)|(COMMONPAGESIZE))\\b"
|
||||
},
|
||||
{
|
||||
"name":"variable.other.ld",
|
||||
"match":"\\."
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"!|-|~"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"\\*|/|%"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"\\+|\\-"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"<<|>>"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"==|!=|>|<|>=|<="
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"&"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"\\|"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"&&"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"\\|\\|"
|
||||
},
|
||||
{
|
||||
"name":"keyword.operand.ld",
|
||||
"match":"\\?|\\:"
|
||||
},
|
||||
{
|
||||
"name":"support.function.builtin.ld",
|
||||
"match":"(?x) \\b(?: ABSOLUTE |ADDR |ALIGN |BLOCK |DATA_SEGMENT_ALIGN |DATA_SEGMENT_END |DEFINED |LOADADDR |MAX |MIN |NEXT |SIZEOF |SIZEOF_HEADERS |sizeof_headers )\\b"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
1044
syntaxes/systemverilog.json
Normal file
1044
syntaxes/systemverilog.json
Normal file
File diff suppressed because it is too large
Load Diff
888
syntaxes/tcl.json
Normal file
888
syntaxes/tcl.json
Normal file
@ -0,0 +1,888 @@
|
||||
{
|
||||
"name": "tcl",
|
||||
"scopeName": "source.tcl",
|
||||
"fileTypes": [
|
||||
"tcl",
|
||||
"fdc",
|
||||
"xdc",
|
||||
"sdc"
|
||||
],
|
||||
"uuid": "45aff42e-4fcd-4717-829b-4cdaf9d707aa",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comment"
|
||||
},
|
||||
{
|
||||
"include": "#command"
|
||||
}
|
||||
],
|
||||
"repository": {
|
||||
"comment": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "comment.line.tcl",
|
||||
"match": "\\s*\\#.*"
|
||||
}
|
||||
]
|
||||
},
|
||||
"command": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#tcl_commands"
|
||||
},
|
||||
{
|
||||
"include": "#default_command"
|
||||
}
|
||||
]
|
||||
},
|
||||
"expression": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"name": "constant.numeric.tcl",
|
||||
"match": "(?:0(?:x|o|b))?\\d+(?!\\.)"
|
||||
},
|
||||
{
|
||||
"name": "constant.numeric.tcl",
|
||||
"match": "\\d+\\.(?:\\d+(?:[eE][+-]?\\d+)?)?"
|
||||
},
|
||||
{
|
||||
"name": "keyword.operator.tcl",
|
||||
"match": "(?:\\+|\\-|\\~|\\!|\\*\\*|\\*|\\%|\\<\\<|\\>\\>|\\<\\=|\\>\\=|\\<|\\>|\\=\\=|\\!\\=|eq|ne|in|ni|\\&\\&|\\&|\\|\\||\\||\\^|\\?|\\:)"
|
||||
}
|
||||
]
|
||||
},
|
||||
"double_quotes": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "string.quoted.double.tcl",
|
||||
"begin": "\"",
|
||||
"end": "\"",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"variable": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(\\$(?:(?:\\:\\:)?[a-zA-Z0-9_]+)+)\\(",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "variable.other.tcl"
|
||||
}
|
||||
},
|
||||
"end": "\\)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#variable"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "variable.other.tcl",
|
||||
"match": "\\$(?:(?:\\:\\:)?[a-zA-Z0-9_]+)+"
|
||||
},
|
||||
{
|
||||
"name": "variable.other.tcl",
|
||||
"begin": "\\$\\{",
|
||||
"end": "\\}"
|
||||
}
|
||||
]
|
||||
},
|
||||
"braces": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.word.generic.tcl",
|
||||
"begin": "\\{",
|
||||
"end": "\\}",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"tcl_braces": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.word.tcl.tcl",
|
||||
"begin": "\\{",
|
||||
"end": "\\}",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comment"
|
||||
},
|
||||
{
|
||||
"include": "#command"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"expr_braces": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.word.expr.tcl",
|
||||
"begin": "\\{",
|
||||
"end": "\\}",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#expression"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"brackets": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\\[",
|
||||
"end": "\\]",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comment"
|
||||
},
|
||||
{
|
||||
"include": "#command"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"proc": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.proc.tcl",
|
||||
"begin": "\\b(proc)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "storage.type.function.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?<=proc)(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"name": "entity.name.function.tcl",
|
||||
"match": "[^\\\"\\$\\[\\s]+"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"for": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.for.tcl",
|
||||
"begin": "\\b(for)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.for.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#expr_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"foreach": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.foreach.tcl",
|
||||
"begin": "\\b(foreach)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.foreach.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"name": "variable.parameter.tcl",
|
||||
"match": "\\S+"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"if": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.if.tcl",
|
||||
"begin": "\\b(if)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.if.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#expr_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\\b(else)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.else.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"while": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.while.tcl",
|
||||
"begin": "\\b(while)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.while.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#expr_braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"break": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.break.tcl",
|
||||
"begin": "\\b(break)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.break.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:\\s+|\\\\)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
"continue": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.continue.tcl",
|
||||
"begin": "\\b(continue)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "keyword.control.continue.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:\\s+|\\\\)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
"namespace": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.namespace.tcl",
|
||||
"begin": "\\b(namespace)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "support.function.namespace.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(eval)",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "support.constant.eval.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
},
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"expr": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.expr.tcl",
|
||||
"begin": "\\b(expr)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "support.function.expr.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#expr_braces"
|
||||
},
|
||||
{
|
||||
"include": "#expression"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"dict": {
|
||||
"patterns": [
|
||||
{
|
||||
"name": "meta.command.dict.tcl",
|
||||
"begin": "\\b(dict)\\b",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "support.function.dict.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\\b(?:for)\\b",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"begin": "\\b(?:map)\\b",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
},
|
||||
{
|
||||
"begin": "(?:\\s+|\\\\)",
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#tcl_braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"default_command": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(?:([^\\{\\}\\[\\]\\$\\;\\s]+)|(?=\\{|\\[|\\$|\\\"))",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "entity.name.function.tcl"
|
||||
}
|
||||
},
|
||||
"end": "(?:(;)|(?=\\})|(?=\\])|$)",
|
||||
"endCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.end.semicolon.tcl"
|
||||
}
|
||||
},
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#variable"
|
||||
},
|
||||
{
|
||||
"include": "#double_quotes"
|
||||
},
|
||||
{
|
||||
"include": "#brackets"
|
||||
},
|
||||
{
|
||||
"include": "#braces"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"tcl_commands": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#proc"
|
||||
},
|
||||
{
|
||||
"include": "#for"
|
||||
},
|
||||
{
|
||||
"include": "#foreach"
|
||||
},
|
||||
{
|
||||
"include": "#if"
|
||||
},
|
||||
{
|
||||
"include": "#while"
|
||||
},
|
||||
{
|
||||
"include": "#break"
|
||||
},
|
||||
{
|
||||
"include": "#continue"
|
||||
},
|
||||
{
|
||||
"include": "#namespace"
|
||||
},
|
||||
{
|
||||
"include": "#expr"
|
||||
},
|
||||
{
|
||||
"include": "#dict"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
1111
syntaxes/verilog.json
Normal file
1111
syntaxes/verilog.json
Normal file
File diff suppressed because it is too large
Load Diff
1345
syntaxes/vhdl.json
Normal file
1345
syntaxes/vhdl.json
Normal file
File diff suppressed because it is too large
Load Diff
17
tsconfig.json
Normal file
17
tsconfig.json
Normal file
@ -0,0 +1,17 @@
|
||||
{
|
||||
"compilerOptions": {
|
||||
"module": "commonjs",
|
||||
"target": "ES2020",
|
||||
"outDir": "out",
|
||||
"lib": [
|
||||
"ES2020"
|
||||
],
|
||||
"sourceMap": true,
|
||||
"rootDir": "src",
|
||||
"strict": true /* enable all strict type-checking options */
|
||||
/* Additional Checks */
|
||||
// "noImplicitReturns": true, /* Report error when not all code paths in function return a value. */
|
||||
// "noFallthroughCasesInSwitch": true, /* Report errors for fallthrough cases in switch statement. */
|
||||
// "noUnusedParameters": true, /* Report errors on unused parameters. */
|
||||
}
|
||||
}
|
||||
215
validation/property-schema.json
Normal file
215
validation/property-schema.json
Normal file
@ -0,0 +1,215 @@
|
||||
{
|
||||
"title": "property",
|
||||
"description": "A property file for project of DIDE",
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"TOOL_CHAIN": {
|
||||
"type": "string",
|
||||
"description": "The tool chain you need",
|
||||
"enum": [
|
||||
"xilinx"
|
||||
]
|
||||
},
|
||||
"PRJ_NAME": {
|
||||
"type": "object",
|
||||
"default": {
|
||||
"PL": "template"
|
||||
},
|
||||
"properties": {
|
||||
"PL": {
|
||||
"type": "string",
|
||||
"description": "project name of FPGA",
|
||||
"default": "template"
|
||||
},
|
||||
"PS": {
|
||||
"type": "string",
|
||||
"description": "project name of SOC",
|
||||
"default": "test"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ARCH": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"PRJ_Path": {
|
||||
"type": "string"
|
||||
},
|
||||
"Hardware": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"src": {
|
||||
"type": "string"
|
||||
},
|
||||
"sim": {
|
||||
"type": "string"
|
||||
},
|
||||
"data": {
|
||||
"type": "string"
|
||||
}
|
||||
}
|
||||
},
|
||||
"Software": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"src": {
|
||||
"type": "string"
|
||||
},
|
||||
"data": {
|
||||
"type": "string"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"library": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"state": {
|
||||
"type": "string",
|
||||
"enum": [
|
||||
"local",
|
||||
"remote"
|
||||
]
|
||||
},
|
||||
"Hardware": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"common": {
|
||||
"type": "array"
|
||||
},
|
||||
"custom": {
|
||||
"type": "array"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_REPO": {
|
||||
"type": "array"
|
||||
},
|
||||
"INSIDE_BOOT_TYPE": {
|
||||
"type": "string",
|
||||
"enum": [
|
||||
"microphase"
|
||||
]
|
||||
},
|
||||
"SOC": {
|
||||
"type": "object",
|
||||
"default": {
|
||||
"core": "none"
|
||||
},
|
||||
"properties": {
|
||||
"core": {
|
||||
"type": "string",
|
||||
"description": "Supported CPU for SOC",
|
||||
"enum": [
|
||||
"none",
|
||||
"cortexM3",
|
||||
"microblaze",
|
||||
"ps7_cortexa9_0",
|
||||
"ps7_cortexa9_1",
|
||||
"psu_cortexr5",
|
||||
"psu_cortexa53"
|
||||
]
|
||||
},
|
||||
"bd": {
|
||||
"type": "string",
|
||||
"description": "The bd_file for FPGA Designed",
|
||||
"enum": [
|
||||
"zynq_default",
|
||||
"m3_xIP_default",
|
||||
"MicroBlaze_default",
|
||||
"PCIe_Test"
|
||||
]
|
||||
},
|
||||
"os": {
|
||||
"type": "string",
|
||||
"default": "standalone",
|
||||
"description": "the os for SOC application",
|
||||
"enum": [
|
||||
"linux",
|
||||
"xilkernel",
|
||||
"standalone",
|
||||
"freertos10_xilinx"
|
||||
]
|
||||
},
|
||||
"app": {
|
||||
"type": "string",
|
||||
"default": "Hello World",
|
||||
"description": "the app for SOC application",
|
||||
"enum": [
|
||||
"Hello World",
|
||||
"Empty Application",
|
||||
"Zynq FSBL",
|
||||
"Zynq MP FSBL",
|
||||
"SREC SPI Bootloader",
|
||||
"SREC Bootloader",
|
||||
"Zynq DRAM tests",
|
||||
"Zynq MP DRAM tests",
|
||||
"ZynqMP PMU Firmware",
|
||||
"RSA Authentication App",
|
||||
"Libmetal AMP Demo",
|
||||
"lwIP Echo Server",
|
||||
"lwIP TCP Perf Client",
|
||||
"lwIP TCP Perf Server",
|
||||
"lwIP UDP Perf Client",
|
||||
"lwIP UDP Perf Server",
|
||||
"Memory Tests",
|
||||
"OpenAMP echo-test",
|
||||
"OpenAMP matrix multiplication Demo",
|
||||
"OpenAMP RPC Demo",
|
||||
"Peripheral Tests",
|
||||
"DDR self refresh",
|
||||
"Dhrystone",
|
||||
"Xilkernel POSIX Threads Demo",
|
||||
"FreeRTOS Hello World",
|
||||
"FreeRTOS lwIP Echo Server",
|
||||
"FreeRTOS lwIP TCP Perf Client",
|
||||
"FreeRTOS lwIP TCP Perf Server",
|
||||
"FreeRTOS lwIP UDP Perf Client",
|
||||
"FreeRTOS lwIP UDP Perf Server",
|
||||
"Linux Empty Application",
|
||||
"Linux Hello World"
|
||||
]
|
||||
}
|
||||
},
|
||||
"dependencies": {
|
||||
"bd": [
|
||||
"core"
|
||||
],
|
||||
"os": [
|
||||
"core"
|
||||
],
|
||||
"app": [
|
||||
"core"
|
||||
]
|
||||
}
|
||||
},
|
||||
"enableShowlog": {
|
||||
"type": "boolean",
|
||||
"description": "Whether to display logs during compilation",
|
||||
"default": false,
|
||||
"enum": [
|
||||
true,
|
||||
false
|
||||
]
|
||||
},
|
||||
"Device": {
|
||||
"type": "string",
|
||||
"description": "The device type",
|
||||
"enum": [
|
||||
"none",
|
||||
"xc7z020clg400-2",
|
||||
"xc7a35tftg256-1",
|
||||
"xc7a35tcsg324-1",
|
||||
"xc7z035ffg676-2",
|
||||
"xc7z020clg484-1"
|
||||
]
|
||||
}
|
||||
},
|
||||
"required": [
|
||||
"TOOL_CHAIN",
|
||||
"SOC",
|
||||
"Device"
|
||||
]
|
||||
}
|
||||
44
vsixmake.js
Normal file
44
vsixmake.js
Normal file
@ -0,0 +1,44 @@
|
||||
const { execSync } = require('child_process');
|
||||
const fs = require('fs');
|
||||
const path = require('path');
|
||||
const HDLFile = require('./src/HDLfilesys/operation/files');
|
||||
const HDLPath = require('./src/HDLfilesys/operation/path');
|
||||
|
||||
const PACKAGE_PATH = './package.json';
|
||||
const SAVE_FOLDER = 'dist';
|
||||
const WEBPACK_OUT_FOLDER = 'out';
|
||||
|
||||
function changeMain(path) {
|
||||
const packageJS = HDLFile.pullJsonInfo(PACKAGE_PATH);
|
||||
packageJS.main = path;
|
||||
HDLFile.pushJsonInfo(PACKAGE_PATH, packageJS);
|
||||
}
|
||||
|
||||
function findVsix() {
|
||||
for (const file of fs.readdirSync(__dirname)) {
|
||||
if (file.endsWith('.vsix') && file.includes('digital-ide')) {
|
||||
return file;
|
||||
}
|
||||
}
|
||||
return null;
|
||||
}
|
||||
|
||||
if (!fs.existsSync(SAVE_FOLDER)) {
|
||||
fs.mkdirSync(SAVE_FOLDER);
|
||||
}
|
||||
|
||||
changeMain('./out/extension');
|
||||
execSync('vsce package');
|
||||
changeMain('./src/extension');
|
||||
|
||||
// remove orginal digital ide
|
||||
execSync('code --uninstall-extension sterben.digital-ide');
|
||||
|
||||
const vsix = findVsix();
|
||||
const targetPath = path.join(SAVE_FOLDER, vsix);
|
||||
HDLFile.moveFile(vsix, targetPath, true);
|
||||
HDLPath.deleteFolder(WEBPACK_OUT_FOLDER);
|
||||
|
||||
const vsixPath = HDLPath.join(SAVE_FOLDER, vsix);
|
||||
// install new one
|
||||
execSync('code --install-extension ' + vsixPath);
|
||||
Loading…
x
Reference in New Issue
Block a user