diff --git a/config/systemverilog.configuration.json b/config/systemverilog.configuration.json index 5645c86..d09bf49 100644 --- a/config/systemverilog.configuration.json +++ b/config/systemverilog.configuration.json @@ -27,5 +27,8 @@ {"open":"[", "close":"]", "notIn":["string", "comment"]}, {"open":"{", "close":"}", "notIn":["string", "comment"]}, {"open":"\"", "close":"\"", "notIn":["string", "comment"]} - ] + ], + "onTypeFormatting": { + "autoFormatTriggerCharacters": ["\n"] + } } \ No newline at end of file diff --git a/config/verilog.configuration.json b/config/verilog.configuration.json index 96f1c94..66effd5 100644 --- a/config/verilog.configuration.json +++ b/config/verilog.configuration.json @@ -13,11 +13,13 @@ ["module", "endmodule"], ["task", "endtask"] ], - "autoClosingPairs": [ {"open":"(", "close":")", "notIn":["string", "comment"]}, {"open":"[", "close":"]", "notIn":["string", "comment"]}, {"open":"{", "close":"}", "notIn":["string", "comment"]}, {"open":"\"", "close":"\"", "notIn":["string", "comment"]} - ] + ], + "onTypeFormatting": { + "autoFormatTriggerCharacters": ["\n"] + } } \ No newline at end of file diff --git a/config/vhdl.configuration.json b/config/vhdl.configuration.json index ef4af8d..eb603b8 100644 --- a/config/vhdl.configuration.json +++ b/config/vhdl.configuration.json @@ -22,5 +22,8 @@ ["(", ")"], ["\"", "\""], ["'", "'"] - ] + ], + "onTypeFormatting": { + "autoFormatTriggerCharacters": ["\n"] + } } diff --git a/package.json b/package.json index 9091eee..4f19c0b 100644 --- a/package.json +++ b/package.json @@ -293,6 +293,11 @@ "description": "auto declare output type nets in the scope when instantiation happens.", "type": "boolean", "default": true + }, + "fpga-support.onTypeFormattingTriggerCharacters": { + "type": "array", + "default": ["\n"], + "description": "Trigger characters for onTypeFormatting" } } }, @@ -788,7 +793,7 @@ "activitybar": [ { "id": "TreeView", - "title": "Digital-IDE: TreeView", + "title": "%digital-ide.treeview%", "icon": "images/svg/view.svg" } ] diff --git a/package.nls.json b/package.nls.json index 59af08b..cfa9ff6 100644 --- a/package.nls.json +++ b/package.nls.json @@ -46,5 +46,6 @@ "digital-ide.lsp.svlog.linter.pick.title": "select a diagnostic for systemverilog verilog", "digital-ide.lsp.vhdl.linter.pick.title": "select a diagnostic for vhdl", "digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog", - "digital-ide.tool.export-filelist.title": "export filelist" + "digital-ide.tool.export-filelist.title": "export filelist", + "digital-ide.treeview": "Digital IDE: TreeView" } \ No newline at end of file diff --git a/package.nls.zh-cn.json b/package.nls.zh-cn.json index 88a6f4b..d57708a 100644 --- a/package.nls.zh-cn.json +++ b/package.nls.zh-cn.json @@ -7,18 +7,18 @@ "digital-ide.tool.instance.title": "生成选中 module 的例化模板", "digital-ide.tool.testbench.title": "从当前文件中选择 module 生成 testbench", "digital-ide.tool.icarus.simulateFile.title": "对当前文件进行仿真", - "digital-ide.treeView.arch.expand.title": "扩大树视图中的所有项目", - "digital-ide.treeView.arch.collapse.title": "崩溃树视图中的所有项目", + "digital-ide.treeView.arch.expand.title": "展开视图中的所有项目", + "digital-ide.treeView.arch.collapse.title": "收起视图中的所有项目", "digital-ide.treeView.arch.refresh.title": "刷新树视图", "digital-ide.treeView.arch.openFile.title": "在树视图打开相应的文件", - "digital-ide.tool.clean.title": "干净的当前项目", + "digital-ide.tool.clean.title": "清理的当前项目", "digital-ide.soft.launch.title": "启动SDK开发辅助功能", "digital-ide.soft.build.title": "建立项目当前的SDK", "digital-ide.soft.download.title": "下载文件到设备引导", "digital-ide.hard.launch.title": "启动FPGA开发辅助功能", "digital-ide.hard.simulate.title": "启动生产仿真", - "digital-ide.hard.simulate.cli.title": "在CLI推出制造商模拟", - "digital-ide.hard.simulate.gui.title": "在GUI推出制造商模拟", + "digital-ide.hard.simulate.cli.title": "CLI", + "digital-ide.hard.simulate.gui.title": "GUI", "digital-ide.hard.refresh.title": "刷新当前的项目文件", "digital-ide.hard.build.title": "fpga构建当前项目", "digital-ide.hard.build.synth.title": "Synth当前项目", @@ -27,7 +27,7 @@ "digital-ide.hard.program.title": "下载文件到设备", "digital-ide.hard.gui.title": "打开界面", "digital-ide.hard.exit.title": "退出当前项目", - "digital-ide.pickLibrary.title": "从自定义选择自由和普遍", + "digital-ide.pickLibrary.title": "选择库文件", "digital-ide.pl.setSrcTop.title": "设置为 src 的顶层文件", "digital-ide.pl.setSimTop.title": "设置为 sim 的顶层文件", "digital-ide.pl.addDevice.title": "添加 device", @@ -46,5 +46,6 @@ "digital-ide.lsp.svlog.linter.pick.title": "选择 System Verilog 的诊断", "digital-ide.lsp.vhdl.linter.pick.title": "选择 VHDL 的诊断", "digital-ide.lsp.systemverilog.linter.pick.title": "选择 SystemVerilog 的诊断", - "digital-ide.tool.export-filelist.title": "导出 filelist" + "digital-ide.tool.export-filelist.title": "导出 filelist", + "digital-ide.treeview": "Digital IDE: 模块树" } \ No newline at end of file diff --git a/package.nls.zh-tw.json b/package.nls.zh-tw.json index 97645ad..444479d 100644 --- a/package.nls.zh-tw.json +++ b/package.nls.zh-tw.json @@ -46,5 +46,6 @@ "digital-ide.lsp.svlog.linter.pick.title": "選擇 System Verilog 的診斷", "digital-ide.lsp.vhdl.linter.pick.title": "選擇 VHDL 的診斷", "digital-ide.lsp.systemverilog.linter.pick.title": "選擇 SystemVerilog 的診斷", - "digital-ide.tool.export-filelist.title": "導出 filelist" + "digital-ide.tool.export-filelist.title": "導出 filelist", + "digital-ide.treeview": "Digital IDE: 模块树" } \ No newline at end of file diff --git a/src/extension.ts b/src/extension.ts index 4d8f4a3..c491336 100644 --- a/src/extension.ts +++ b/src/extension.ts @@ -21,7 +21,7 @@ async function registerCommand(context: vscode.ExtensionContext) { func.registerWaveViewer(context); lspClient.activate(context); - await LspClient.MainClient?.onReady(); + await LspClient.DigitalIDE?.onReady(); } async function launch(context: vscode.ExtensionContext) { diff --git a/src/function/index.ts b/src/function/index.ts index ba09c90..93a9942 100644 --- a/src/function/index.ts +++ b/src/function/index.ts @@ -85,10 +85,10 @@ function registerLsp(context: vscode.ExtensionContext) { // vhdl lsp - vscode.languages.registerDocumentSymbolProvider(vhdlSelector, lspDocSymbol.vhdlDocSymbolProvider); - vscode.languages.registerDefinitionProvider(vhdlSelector, lspDefinition.vhdlDefinitionProvider); - vscode.languages.registerHoverProvider(vhdlSelector, lspHover.vhdlHoverProvider); - vscode.languages.registerCompletionItemProvider(vhdlSelector, lspCompletion.vhdlCompletionProvider); + // vscode.languages.registerDocumentSymbolProvider(vhdlSelector, lspDocSymbol.vhdlDocSymbolProvider); + // vscode.languages.registerDefinitionProvider(vhdlSelector, lspDefinition.vhdlDefinitionProvider); + // vscode.languages.registerHoverProvider(vhdlSelector, lspHover.vhdlHoverProvider); + // vscode.languages.registerCompletionItemProvider(vhdlSelector, lspCompletion.vhdlCompletionProvider); // tcl lsp diff --git a/src/function/lsp-client/index.ts b/src/function/lsp-client/index.ts index 74891a7..b697005 100644 --- a/src/function/lsp-client/index.ts +++ b/src/function/lsp-client/index.ts @@ -59,6 +59,9 @@ export function activate(context: vscode.ExtensionContext) { language: 'vhdl' } ], + markdown: { + isTrusted: true + } }; const client = new LanguageClient( @@ -67,15 +70,15 @@ export function activate(context: vscode.ExtensionContext) { serverOptions, clientOptions ); - LspClient.MainClient = client; + LspClient.DigitalIDE = client; client.start(); } export function deactivate(): Thenable | undefined { - if (!LspClient.MainClient) { + if (!LspClient.DigitalIDE) { return undefined; } - return LspClient.MainClient.stop(); + return LspClient.DigitalIDE.stop(); } diff --git a/src/global/lsp.ts b/src/global/lsp.ts index 329fe0e..bb5ded5 100644 --- a/src/global/lsp.ts +++ b/src/global/lsp.ts @@ -4,12 +4,12 @@ import { Fast } from '../../resources/hdlParser'; interface IDigitalIDELspClient { - MainClient?: LanguageClient, + DigitalIDE?: LanguageClient, VhdlClient?: LanguageClient } export const LspClient: IDigitalIDELspClient = { - MainClient: undefined, + DigitalIDE: undefined, VhdlClient: undefined }; diff --git a/src/hdlParser/core.ts b/src/hdlParser/core.ts index 9532cd0..345ba68 100644 --- a/src/hdlParser/core.ts +++ b/src/hdlParser/core.ts @@ -257,6 +257,15 @@ class HdlParam { progress?.report({ message: reportTitle + ` ${1}/${fileNum}`, increment: 0 }); + // for (const path of hdlFiles) { + // count ++; + // console.log('send request: ' + path); + + // await this.doHdlFast(path); + // const increment = Math.floor(count / fileNum * 100); + // progress?.report({ message: reportTitle + ` ${count}/${fileNum}`, increment }); + // } + async function consumePools() { for (const p of pools) { const increment = Math.floor(p.id / fileNum * 100); @@ -575,7 +584,7 @@ class HdlModule { this.path, common.InstModPathStatus.Current, rawHdlInstance.instparams, - this.ports[0].range, + rawHdlInstance.instports, rawHdlInstance.range, this); hdlInstance.module = this; diff --git a/src/hdlParser/util.ts b/src/hdlParser/util.ts index e4ac909..c10420f 100644 --- a/src/hdlParser/util.ts +++ b/src/hdlParser/util.ts @@ -1,5 +1,5 @@ import * as vscode from 'vscode'; -import { Fast, vlogAll, vhdlAll, svAll, vhdlFast, All } from '../../resources/hdlParser'; +import { Fast, vlogAll, vhdlAll, svAll, All } from '../../resources/hdlParser'; import { hdlFile } from '../hdlFs'; import { HdlLangID } from '../global/enum'; import { AbsPath, LspClient } from '../global'; @@ -8,7 +8,7 @@ import { RawHdlModule } from './common'; async function doFastApi(path: string): Promise { try { - const client = LspClient.MainClient; + const client = LspClient.DigitalIDE; const langID = hdlFile.getLanguageId(path); if (client) { const response = await client.sendRequest(DoFastRequestType, { path }); @@ -32,6 +32,11 @@ async function svFast(path: string): Promise { return fast; } +async function vhdlFast(path: string): Promise { + const fast = await doFastApi(path); + return fast; +} + namespace HdlSymbol { /** * @description 计算出模块级的信息 diff --git a/src/manager/prj.ts b/src/manager/prj.ts index d234208..a110c50 100644 --- a/src/manager/prj.ts +++ b/src/manager/prj.ts @@ -155,7 +155,7 @@ class PrjManage { MainOutput.report(`finish analyse ${hdlFiles.length} hdl files, find ${unhandleNum} unsolved instances`, ReportType.Info); // 完成后端向前端发送消息的注册 - const mainClient = LspClient.MainClient; + const mainClient = LspClient.DigitalIDE; if (mainClient !== undefined) { await mainClient.onReady(); mainClient.onNotification('update/fast', async (params: any) => { diff --git a/syntaxes/systemverilog.backup.json b/syntaxes/systemverilog.backup.json new file mode 100644 index 0000000..330267c --- /dev/null +++ b/syntaxes/systemverilog.backup.json @@ -0,0 +1,1044 @@ +{ + "fileTypes": [ + "sv", + "svh", + "v", + "vh" + ], + "hidden": true, + "name": "SystemVerilog", + "patterns": [ + { + "begin": "\\s*\\b(function|task)\\b(\\s+automatic)?", + "beginCaptures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "keyword.control.systemverilog" + } + }, + "end": ";", + "patterns": [ + { + "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*\\s+)?([a-zA-Z_][a-zA-Z0-9_:]*)\\s*(?=\\(|;)", + "captures": { + "1": { + "name": "storage.type.systemverilog" + }, + "2": { + "name": "entity.name.function.systemverilog" + } + } + }, + { + "include": "#port-dir" + }, + { + "include": "#base-grammar" + } + ], + "name": "meta.function.systemverilog" + }, + { + "match": "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;", + "captures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "keyword.control.systemverilog" + }, + "3": { + "name": "entity.name.function.systemverilog" + } + }, + "name": "meta.task.simple.systemverilog" + }, + { + "begin": "\\s*\\b(typedef\\s+(struct|enum|union)\\b)\\s*(packed)?\\s*([a-zA-Z_][a-zA-Z0-9_]*)?", + "beginCaptures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "keyword.control.systemverilog" + }, + "3": { + "name": "keyword.control.systemverilog" + }, + "4": { + "name": "storage.type.systemverilog" + } + }, + "end": "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;", + "endCaptures": { + "1": { + "name": "keyword.operator.other.systemverilog" + }, + "2": { + "name": "entity.name.function.systemverilog" + } + }, + "patterns": [ + { + "include": "#struct-anonymous" + }, + { + "include": "#base-grammar" + } + ], + "name": "meta.typedef.struct.systemverilog" + }, + { + "match": "\\s*\\b(typedef\\s+class)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\s*;", + "captures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "entity.name.declaration.systemverilog" + } + }, + "name": "meta.typedef.class.systemverilog" + }, + { + "begin": "\\s*\\b(typedef)\\b", + "beginCaptures": { + "1": { + "name": "keyword.control.systemverilog" + } + }, + "end": "([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=(\\[[a-zA-Z0-9_:\\$\\-\\+]*\\])?;)", + "endCaptures": { + "1": { + "name": "entity.name.function.systemverilog" + } + }, + "patterns": [ + { + "match": "\\b([a-zA-Z_]\\w*)\\s*(#)\\(", + "captures": { + "1": { + "name": "storage.type.userdefined.systemverilog" + }, + "2": { + "name": "keyword.operator.param.systemverilog" + } + }, + "name": "meta.typedef.class.systemverilog" + }, + { + "include": "#base-grammar" + }, + { + "include": "#module-binding" + } + ], + "name": "meta.typedef.simple.systemverilog" + }, + { + "begin": "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b", + "beginCaptures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "entity.name.type.module.systemverilog" + } + }, + "end": ";", + "endCaptures": { + "1": { + "name": "entity.name.function.systemverilog" + } + }, + "patterns": [ + { + "include": "#port-dir" + }, + { + "match": "\\s*(parameter)", + "name": "keyword.other.systemverilog" + }, + { + "include": "#base-grammar" + }, + { + "include": "#ifmodport" + } + ], + "name": "meta.module.systemverilog" + }, + { + "captures": { + "1": { + "name": "keyword.control.systemverilog" + }, + "2": { + "name": "entity.name.function.systemverilog" + } + }, + "match": "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)", + "name": "meta.sequence.systemverilog" + }, + { + "match": "\\b(bind)\\s+([a-zA-Z_][a-zA-Z0-9_\\.]*)\\b", + "captures": { + "1": { + "name": "keyword.control.systemverilog" + } + } + }, + { + "captures": { + "0": { + "name": "meta.section.begin.systemverilog" + }, + "1": { + "name": "keyword.other.block.systemverilog" + }, + "3": { + "name": "keyword.operator.systemverilog" + }, + "4": { + "name": "entity.name.section.systemverilog" + } + }, + "match": "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b", + "name": "meta.definition.systemverilog" + }, + { + "match": "\\b(property)\\s+(\\w+)", + "captures": { + "1": { + "name": "keyword.sva.systemverilog" + }, + "2": { + "name": "entity.name.sva.systemverilog" + } + } + }, + { + "match": "\\b(\\w+)\\s*(:)\\s*(assert)\\b", + "captures": { + "1": { + "name": "entity.name.sva.systemverilog" + }, + "2": { + "name": "keyword.operator.systemverilog" + }, + "3": { + "name": "keyword.sva.systemverilog" + } + } + }, + { + "begin": "\\s*(//)\\s*(psl)\\s+((\\w+)\\s*(:))?\\s*(default|assert|assume)", + "beginCaptures": { + "0": { + "name": "meta.psl.systemverilog" + }, + "1": { + "name": "comment.line.double-slash.systemverilog" + }, + "2": { + "name": "keyword.psl.systemverilog" + }, + "4": { + "name": "entity.psl.name.systemverilog" + }, + "5": { + "name": "keyword.operator.systemverilog" + }, + "6": { + "name": "keyword.psl.systemverilog" + } + }, + "end": ";", + "patterns": [ + { + "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b", + "name": "keyword.psl.systemverilog" + }, + { + "include": "#operators" + }, + { + "include": "#functions" + }, + { + "include": "#constants" + } + ], + "name": "meta.psl.systemverilog" + }, + { + "begin": "\\s*(/\\*)\\s*(psl)", + "beginCaptures": { + "0": { + "name": "meta.psl.systemverilog" + }, + "1": { + "name": "comment.block.systemverilog" + }, + "2": { + "name": "keyword.psl.systemverilog" + } + }, + "end": "(\\*/)", + "endCaptures": { + "1": { + "name": "comment.block.systemverilog" + } + }, + "patterns": [ + { + "match": "^\\s*((\\w+)\\s*(:))?\\s*(default|assert|assume)", + "captures": { + "0": { + "name": "meta.psl.systemverilog" + }, + "2": { + "name": "entity.psl.name.systemverilog" + }, + "3": { + "name": "keyword.operator.systemverilog" + }, + "4": { + "name": "keyword.psl.systemverilog" + } + } + }, + { + "match": "\\b(property)\\s+(\\w+)", + "captures": { + "1": { + "name": "keyword.psl.systemverilog" + }, + "2": { + "name": "entity.psl.name.systemverilog" + } + } + }, + { + "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge|negedge)\\b", + "name": "keyword.psl.systemverilog" + }, + { + "include": "#operators" + }, + { + "include": "#functions" + }, + { + "include": "#constants" + } + ], + "name": "meta.psl.systemverilog" + }, + { + "match": "\\s*\\b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|event|generate|genvar|ifnone|incdir|instance|liblist|library|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|scalared|showcancelled|specify|specparam|table|use|vectored)\\b", + "captures": { + "1": { + "name": "keyword.other.systemverilog" + } + } + }, + { + "match": "\\s*\\b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|new|typedef|enum|this|super|begin|fork|forkjoin|unique|unique0|priority)\\b", + "captures": { + "1": { + "name": "keyword.control.systemverilog" + } + } + }, + { + "match": "\\s*\\b(end|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface|join|join_any|join_none)\\b(\\s*(:)\\s*(\\w+))?", + "captures": { + "1": { + "name": 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