From e363c4c50bb65b6cc8f807936941b23d48714f3f Mon Sep 17 00:00:00 2001 From: LSTM-Kirigaya <1193466151@qq.com> Date: Sun, 22 Sep 2024 21:44:04 +0800 Subject: [PATCH] save --- resources/script/xilinx/launch.tcl | 7 ++++ resources/script/xilinx/refresh.tcl | 55 +++++++++++++++++++++++++++++ script/test/svlogAll.js | 2 +- src/function/hdlDoc/diagram.ts | 1 - src/function/hdlDoc/markdown.ts | 8 +++-- src/function/lsp/util/feature.ts | 11 +++++- 6 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 resources/script/xilinx/launch.tcl create mode 100644 resources/script/xilinx/refresh.tcl diff --git a/resources/script/xilinx/launch.tcl b/resources/script/xilinx/launch.tcl new file mode 100644 index 0000000..72e4539 --- /dev/null +++ b/resources/script/xilinx/launch.tcl @@ -0,0 +1,7 @@ +set_param general.maxThreads 8 +create_project template /home/dide/project/Digital-Test/MipsDesign/prj/xilinx -part none -force +set_property SOURCE_SET source_1 [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +update_compile_order -fileset sim_1 -quiet +source /home/dide/project/Digital-IDE/resources/script/xilinx/refresh.tcl -quiet +file delete /home/dide/project/Digital-IDE/resources/script/xilinx/launch.tcl -force diff --git a/resources/script/xilinx/refresh.tcl b/resources/script/xilinx/refresh.tcl new file mode 100644 index 0000000..db1fd32 --- /dev/null +++ b/resources/script/xilinx/refresh.tcl @@ -0,0 +1,55 @@ +remove_files -quiet [get_files] +set xip_repo_paths {} +set_property ip_repo_paths $xip_repo_paths [current_project] -quiet +update_ip_catalog -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/Controller/controller.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/Controller/controller.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Hazard/ForwardUnit.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Hazard/ForwardUnit.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Hazard/HDU.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Hazard/HDU.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Memory/dm_8k.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Memory/dm_8k.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Memory/im_8k.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Memory/im_8k.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/EX_MEM.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/EX_MEM.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/ID_EX.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/ID_EX.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/IF_ID.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/IF_ID.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/MEM_WB.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Pipe/MEM_WB.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/BU.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/BU.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/Ext.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/Ext.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/FU.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/FU.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/OR.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/OR.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/alu.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/alu.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/alu_ctrl.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/alu_ctrl.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/mux.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/mux.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/npc.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/npc.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/pc.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/pc.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/pc_add.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/pc_add.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/regfile.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/Utils/regfile.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/DataPath/datapath.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/DataPath/datapath.v -quiet +add_files /home/dide/project/Digital-Test/MipsDesign/src/MyCpu.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/src/MyCpu.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-Test/MipsDesign/sim/testBench.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-IDE/library/Apply/Comm/FDE/AGC/AGC.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-IDE/library/Apply/Comm/MDS/Modulation/AnalogMod.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-IDE/library/Apply/Comm/MDS/Modulation/DigitalMod.v -quiet +add_files -fileset sim_1 /home/dide/project/Digital-IDE/library/Basic/Math/FixedPoint/accuml.v -quiet +add_files -fileset constrs_1 /home/dide/project/Digital-Test/MipsDesign -quiet +file delete /home/dide/project/Digital-IDE/resources/script/xilinx/refresh.tcl -force diff --git a/script/test/svlogAll.js b/script/test/svlogAll.js index e545415..a8486b1 100644 --- a/script/test/svlogAll.js +++ b/script/test/svlogAll.js @@ -4,5 +4,5 @@ const testFile = '../Digital-Test/svlog/user/src/hello.sv'; (async () => { const all = await svAll(testFile); - console.log(JSON.stringify(all, null, ' ')); + (JSON.stringify(all, null, ' ')); })(); \ No newline at end of file diff --git a/src/function/hdlDoc/diagram.ts b/src/function/hdlDoc/diagram.ts index 3730e92..0a9875f 100644 --- a/src/function/hdlDoc/diagram.ts +++ b/src/function/hdlDoc/diagram.ts @@ -190,7 +190,6 @@ function makeRightDirection(rightPorts: HdlModulePort[]): string { const portCaption = makePortCaption(port, 'right'); let portArrow = makePortArrow(port, 'right'); portArrow = portArrow.replace('-0.5 -0.5 125 45', '20 -0.5 125 45'); - console.log(portArrow); const arrow = `