#fix all the bugs
This commit is contained in:
parent
77f743e1a3
commit
f970d25548
66
package-lock.json
generated
66
package-lock.json
generated
@ -8,6 +8,7 @@
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"name": "digital-ide",
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"version": "0.3.0",
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"dependencies": {
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"@vscode/wasm-wasi": "^0.8.2",
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"chokidar": "^3.5.3",
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"puppeteer-core": "^19.4.1",
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"showdown": "^2.1.0",
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@ -343,6 +344,26 @@
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"node": "^12.22.0 || ^14.17.0 || >=16.0.0"
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}
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},
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"node_modules/@vscode/sync-api-client": {
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"version": "0.8.1",
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"resolved": "https://registry.npmmirror.com/@vscode/sync-api-client/-/sync-api-client-0.8.1.tgz",
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"integrity": "sha512-82NRZpZlvRtlFoqi/J8xGw964F8ZfJJeJu2D9QMAAzq8BMDCXqkhO2qHApnyEV4gG2mQSaHtfw0f30GOPExgUg==",
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"dependencies": {
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"@vscode/sync-api-common": "0.8.1",
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"vscode-uri": "^3.0.6"
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},
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"engines": {
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"node": ">=16.14.2"
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}
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},
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"node_modules/@vscode/sync-api-common": {
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"version": "0.8.1",
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"resolved": "https://registry.npmmirror.com/@vscode/sync-api-common/-/sync-api-common-0.8.1.tgz",
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"integrity": "sha512-XfanQNxkUlCpAsQ2+1SzNEdoY7jtcu48jYBR0n864ZWAWrH7m2QBK32YoNlrDN2V0eh8tdF0WH1NuHOm3Y021A==",
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"engines": {
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"node": ">=16.14.2"
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}
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},
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"node_modules/@vscode/test-electron": {
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"version": "2.2.2",
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"resolved": "https://registry.npmmirror.com/@vscode/test-electron/-/test-electron-2.2.2.tgz",
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@ -358,6 +379,18 @@
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"node": ">=16"
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}
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},
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"node_modules/@vscode/wasm-wasi": {
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"version": "0.8.2",
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"resolved": "https://registry.npmmirror.com/@vscode/wasm-wasi/-/wasm-wasi-0.8.2.tgz",
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"integrity": "sha512-TazXvphINUEoXVX2dEPdXhrwrQ9I6Z6t9LCDfALTmL43D/2Zmlc89KfNE/cO36n2uo+SDlPPP/6vWyF9TBbnnw==",
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"dependencies": {
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"@vscode/sync-api-client": "0.8.1",
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"vscode-uri": "^3.0.6"
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},
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"engines": {
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"vscode": "^1.71.0"
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}
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},
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"node_modules/acorn": {
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"version": "8.8.1",
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"resolved": "https://registry.npmmirror.com/acorn/-/acorn-8.8.1.tgz",
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@ -2835,6 +2868,11 @@
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"resolved": "https://registry.npmmirror.com/vscode-textmate/-/vscode-textmate-9.0.0.tgz",
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"integrity": "sha512-Cl65diFGxz7gpwbav10HqiY/eVYTO1sjQpmRmV991Bj7wAoOAjGQ97PpQcXorDE2Uc4hnGWLY17xme+5t6MlSg=="
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},
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"node_modules/vscode-uri": {
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"version": "3.0.7",
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"resolved": "https://registry.npmmirror.com/vscode-uri/-/vscode-uri-3.0.7.tgz",
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"integrity": "sha512-eOpPHogvorZRobNqJGhapa0JdwaxpjVvyBp0QIUMRMSf8ZAlqOdEquKuRmw9Qwu0qXtJIWqFtMkmvJjUZmMjVA=="
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},
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"node_modules/wavedrom": {
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"version": "2.9.1",
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"resolved": "https://registry.npmmirror.com/wavedrom/-/wavedrom-2.9.1.tgz",
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@ -3239,6 +3277,20 @@
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"eslint-visitor-keys": "^3.3.0"
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}
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},
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"@vscode/sync-api-client": {
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"version": "0.8.1",
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"resolved": "https://registry.npmmirror.com/@vscode/sync-api-client/-/sync-api-client-0.8.1.tgz",
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"integrity": "sha512-82NRZpZlvRtlFoqi/J8xGw964F8ZfJJeJu2D9QMAAzq8BMDCXqkhO2qHApnyEV4gG2mQSaHtfw0f30GOPExgUg==",
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"requires": {
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"@vscode/sync-api-common": "0.8.1",
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"vscode-uri": "^3.0.6"
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}
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},
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"@vscode/sync-api-common": {
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"version": "0.8.1",
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"resolved": "https://registry.npmmirror.com/@vscode/sync-api-common/-/sync-api-common-0.8.1.tgz",
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"integrity": "sha512-XfanQNxkUlCpAsQ2+1SzNEdoY7jtcu48jYBR0n864ZWAWrH7m2QBK32YoNlrDN2V0eh8tdF0WH1NuHOm3Y021A=="
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},
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"@vscode/test-electron": {
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"version": "2.2.2",
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"resolved": "https://registry.npmmirror.com/@vscode/test-electron/-/test-electron-2.2.2.tgz",
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@ -3251,6 +3303,15 @@
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"unzipper": "^0.10.11"
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}
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},
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"@vscode/wasm-wasi": {
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"version": "0.8.2",
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"resolved": "https://registry.npmmirror.com/@vscode/wasm-wasi/-/wasm-wasi-0.8.2.tgz",
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"integrity": "sha512-TazXvphINUEoXVX2dEPdXhrwrQ9I6Z6t9LCDfALTmL43D/2Zmlc89KfNE/cO36n2uo+SDlPPP/6vWyF9TBbnnw==",
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"requires": {
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"@vscode/sync-api-client": "0.8.1",
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"vscode-uri": "^3.0.6"
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}
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},
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"acorn": {
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"version": "8.8.1",
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"resolved": "https://registry.npmmirror.com/acorn/-/acorn-8.8.1.tgz",
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@ -5227,6 +5288,11 @@
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"resolved": "https://registry.npmmirror.com/vscode-textmate/-/vscode-textmate-9.0.0.tgz",
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"integrity": "sha512-Cl65diFGxz7gpwbav10HqiY/eVYTO1sjQpmRmV991Bj7wAoOAjGQ97PpQcXorDE2Uc4hnGWLY17xme+5t6MlSg=="
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},
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"vscode-uri": {
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"version": "3.0.7",
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"resolved": "https://registry.npmmirror.com/vscode-uri/-/vscode-uri-3.0.7.tgz",
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"integrity": "sha512-eOpPHogvorZRobNqJGhapa0JdwaxpjVvyBp0QIUMRMSf8ZAlqOdEquKuRmw9Qwu0qXtJIWqFtMkmvJjUZmMjVA=="
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},
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"wavedrom": {
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"version": "2.9.1",
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"resolved": "https://registry.npmmirror.com/wavedrom/-/wavedrom-2.9.1.tgz",
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@ -780,7 +780,7 @@
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{
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"language": "verilog",
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"scopeName": "source.verilog",
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"path": "./syntaxes/verilog.json"
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"path": "./syntaxes/verilog.tmLanguage.json"
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},
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{
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"language": "systemverilog",
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@ -956,6 +956,7 @@
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"typescript": "^4.8.4"
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},
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"dependencies": {
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"@vscode/wasm-wasi": "^0.8.2",
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"chokidar": "^3.5.3",
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"puppeteer-core": "^19.4.1",
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"showdown": "^2.1.0",
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@ -199,6 +199,21 @@
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"xc7z035ffg676-2",
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"xc7z020clg484-1"
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]
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},
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"iverilogCompileOptions": {
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"type": "object",
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"description": "options to define iverilog arguments",
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"properties": {
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"standard": {
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"type": "string",
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"description": "value of argument -g, default is -g2012",
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"default": "2012"
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},
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"includes": {
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"type": "array",
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"description": "value of argument -I"
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}
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}
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}
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},
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"required": [
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@ -1,5 +1,4 @@
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import * as vscode from 'vscode';
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import * as vsctm from 'vscode-textmate';
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import { hdlPath } from '../../../hdlFs';
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import { hdlParam } from '../../../hdlParser';
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@ -1,15 +1,51 @@
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import * as vscode from 'vscode';
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import { All } from '../../../../resources/hdlParser';
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import { HdlSymbol } from '../../../hdlParser';
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import { vlogSymbolStorage } from '../core';
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import { transformRange } from '../util';
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const tokenTypes = ['class', 'interface', 'enum', 'function', 'variable'];
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const tokenTypes = ['class', 'function', 'variable'];
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const tokenModifiers = ['declaration', 'documentation'];
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const vlogLegend = new vscode.SemanticTokensLegend(tokenTypes, tokenModifiers);
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class VlogDocSenmanticProvider implements vscode.DocumentSemanticTokensProvider {
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public async provideDocumentSemanticTokens(document: vscode.TextDocument, token: vscode.CancellationToken): Promise<vscode.SemanticTokens | null | undefined> {
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// TODO : finish this
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// const tokensBuilder = new vscode.SemanticTokensBuilder(vlogLegend);
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return null;
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const tokensBuilder = new vscode.SemanticTokensBuilder(vlogLegend);
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// const filePath = document.fileName;
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// const vlogAll = await HdlSymbol.all(filePath);
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// if (vlogAll) {
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// this.prepareTokensBuilder(tokensBuilder, vlogAll);
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// }
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return tokensBuilder.build();
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}
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private prepareTokensBuilder(builder: vscode.SemanticTokensBuilder, all: All){
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for (const rawSymbol of all.content) {
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const semanticRange = transformRange(rawSymbol.range, -1, 0);
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const tokenType = this.getTokenTypes(rawSymbol.type);
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if (tokenType) {
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builder.push(semanticRange, tokenType);
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}
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}
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}
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private getTokenTypes(type: string): string | undefined {
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switch (type) {
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case 'input':
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return 'variable';
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case 'output':
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return 'variable';
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case 'wire':
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return 'variable';
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case 'reg':
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return 'variable';
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default:
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return;
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}
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}
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}
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const vlogDocSenmanticProvider = new VlogDocSenmanticProvider();
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@ -106,7 +106,7 @@ class Simulate {
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* @description 获取自带仿真库的路径
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* @param toolChain
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*/
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getSimLibArr(toolChain: ToolChainType): AbsPath[] {
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public getSimLibArr(toolChain: ToolChainType): AbsPath[] {
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let libPath: AbsPath[] = [];
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const setting = vscode.workspace.getConfiguration();
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@ -146,6 +146,38 @@ class IcarusSimulate extends Simulate {
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this.toolChain = opeParam.prjInfo.toolChain;
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}
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private makeMacroIncludeArguments(includes: string[]): string {
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const args = [];
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for (const includePath of includes) {
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if(!hdlFile.isDir(includePath)) {
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args.push(includePath);
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} else {
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args.push('-I ' + includePath);
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}
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}
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return args.join(' ').trim();
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}
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private makeDependenceArguments(dependences: string[]): string {
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const args = [];
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for (const dep of dependences) {
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args.push('"' + dep + '"');
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}
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return args.join(' ').trim();
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}
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private makeThirdLibraryArguments(simLibPaths: string[]): string {
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const args = [];
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for (const libPath of simLibPaths) {
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if(!hdlFile.isDir(libPath)) {
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args.push(libPath);
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} else {
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args.push('-y ' + libPath);
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}
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}
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return args.join(' ').trim();
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}
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/**
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* generate acutal iverlog simulation command
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* @param name name of top module
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@ -160,6 +192,7 @@ class IcarusSimulate extends Simulate {
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}
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this.simConfig = simConfig;
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const installPath = simConfig.installPath;
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const iverilogCompileOptions = opeParam.prjInfo.iverilogCompileOptions;
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if (this.os === 'win32') {
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simConfig.iverilogPath += '.exe';
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@ -171,25 +204,19 @@ class IcarusSimulate extends Simulate {
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simConfig.vvpPath = hdlPath.join(installPath, simConfig.vvpPath);
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}
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let dependenceArgs = '';
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dependences.forEach(d => dependenceArgs += '"' + d + '" ');
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dependenceArgs = dependenceArgs.trim();
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const simLibPaths = this.getSimLibArr(this.toolChain);
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let thirdLibPath = ' ';
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this.getSimLibArr(this.toolChain).forEach(element => {
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if(!hdlFile.isDir(element)) {
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thirdLibPath += element + " ";
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} else {
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thirdLibPath += `-y ${element}`;
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}
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});
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const macroIncludeArgs = this.makeMacroIncludeArguments(iverilogCompileOptions.includes);
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const dependenceArgs = this.makeDependenceArguments(dependences);
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const thirdLibraryArgs = this.makeThirdLibraryArguments(simLibPaths);
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const iverilogPath = simConfig.iverilogPath;
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const argu = '-g2012';
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// default is -g2012
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const argu = '-g' + iverilogCompileOptions.standard;
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const outVvpPath = '"' + hdlPath.join(simConfig.simulationHome, 'out.vvp') + '"';
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const mainPath = '"' + path + '"';
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const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${mainPath} ${dependenceArgs} ${thirdLibPath}`;
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const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryArgs}`;
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MainOutput.report(cmd, ReportType.Run);
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return cmd;
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}
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@ -263,6 +290,7 @@ class IcarusSimulate extends Simulate {
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if (runInTerminal) {
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this.execInTerminal(command, cwd);
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} else {
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MainOutput.show();
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this.execInOutput(command, cwd);
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}
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}
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@ -288,7 +316,7 @@ class IcarusSimulate extends Simulate {
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const dependences = this.getAllOtherDependences(path, name);
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const simulationCommand = this.getCommand(name, path, dependences);
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if (simulationCommand) {
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const cwd = hdlPath.resolve(hdlModule.path, '..');
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const cwd = hdlPath.resolve(path, '..');
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this.exec(simulationCommand, cwd);
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} else {
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const errorMsg = 'Fail to generate command';
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@ -67,6 +67,10 @@ class Output {
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}
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}
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}
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public show() {
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this._output.show(true);
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}
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}
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const MainOutput = new Output('Digital-IDE');
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@ -79,6 +79,13 @@ const PrjInfoDefaults: PrjInfoMeta = {
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custom: []
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}
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};
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},
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get iverilogCompileOptions() {
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return {
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standard: "2012",
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includes: []
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};
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}
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};
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@ -108,6 +115,11 @@ interface Library {
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}
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}
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interface IverilogCompileOptions {
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standard: string,
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includes: Path[]
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}
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interface RawPrjInfo extends RawPrjInfoMeta {
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toolChain?: ToolChainType
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prjName?: PrjName
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@ -160,6 +172,9 @@ class PrjInfo implements PrjInfoMeta {
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// library to manage
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private readonly _library: Library = PrjInfoDefaults.library;
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// compile for iverilog
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private readonly _iverilogCompileOptions: IverilogCompileOptions = PrjInfoDefaults.iverilogCompileOptions;
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public get toolChain(): ToolChainType {
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return this._toolChain;
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}
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@ -196,6 +211,10 @@ class PrjInfo implements PrjInfoMeta {
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return 'microphase';
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}
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public get iverilogCompileOptions(): IverilogCompileOptions {
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return this._iverilogCompileOptions;
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}
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/**
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* replace token like ${workspace} in path
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* @param path
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@ -209,9 +228,9 @@ class PrjInfo implements PrjInfoMeta {
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const psname = this.prjName.PS;
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// TODO : packaging the replacer
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return path.replace(new RegExp('${workspace}', 'g'), workspacePath)
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.replace(new RegExp('${plname}', 'g'), plname)
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.replace(new RegExp('${psname}', 'g'), psname);
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return path.replace(/\$\{workspace\}/g, workspacePath)
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.replace(/\$\{plname\}/g, plname)
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.replace(/\$\{psname\}/g, psname);
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}
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/**
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@ -452,6 +471,21 @@ class PrjInfo implements PrjInfoMeta {
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}
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}
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public updateIverilogCompileOptions(iverilogCompileOptions?: IverilogCompileOptions) {
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if (iverilogCompileOptions) {
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if (iverilogCompileOptions.standard) {
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this._iverilogCompileOptions.standard = iverilogCompileOptions.standard;
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}
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if (iverilogCompileOptions.includes && iverilogCompileOptions.includes instanceof Array<Path>) {
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this._iverilogCompileOptions.includes = [];
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for (const includePath of iverilogCompileOptions.includes) {
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const realIncludePath = includePath.replace(/\$\{workspace\}/g, this._workspacePath);
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this._iverilogCompileOptions.includes.push(realIncludePath);
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}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public appendLibraryCommonPath(relPath: RelPath) {
|
||||
this._library.hardware.common.push(relPath);
|
||||
}
|
||||
@ -502,6 +536,7 @@ class PrjInfo implements PrjInfoMeta {
|
||||
this.updateDevice(rawPrjInfo.device);
|
||||
this.updateArch(rawPrjInfo.arch);
|
||||
this.updateLibrary(rawPrjInfo.library);
|
||||
this.updateIverilogCompileOptions(rawPrjInfo.iverilogCompileOptions);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -76,6 +76,10 @@ interface PrjInfoSchema {
|
||||
|
||||
enableShowLog: Type & Desc & Default<boolean> & Enum<boolean>
|
||||
device: Type & Desc & Enum<string>
|
||||
iverilogCompileOptions: {
|
||||
standard: string
|
||||
includes: string[]
|
||||
}
|
||||
};
|
||||
|
||||
interface PropertySchema {
|
||||
|
||||
@ -4,7 +4,8 @@ module mux2to1(
|
||||
input wire a,
|
||||
input wire b,
|
||||
input wire sel,
|
||||
output wire outp
|
||||
output wire outp,
|
||||
output wire test_port
|
||||
);
|
||||
|
||||
|
||||
|
||||
361
syntaxes/verilog.tmLanguage.json
Normal file
361
syntaxes/verilog.tmLanguage.json
Normal file
@ -0,0 +1,361 @@
|
||||
{
|
||||
"fileTypes": [
|
||||
"v",
|
||||
"vh"
|
||||
],
|
||||
"keyEquivalent": "^~V",
|
||||
"name": "Verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comments"
|
||||
},
|
||||
{
|
||||
"include": "#module_pattern"
|
||||
},
|
||||
{
|
||||
"include": "#keywords"
|
||||
},
|
||||
{
|
||||
"include": "#constants"
|
||||
},
|
||||
{
|
||||
"include": "#strings"
|
||||
},
|
||||
{
|
||||
"include": "#operators"
|
||||
},
|
||||
{
|
||||
"include": "#macro_definition"
|
||||
},
|
||||
{
|
||||
"include": "#macro_quote"
|
||||
},
|
||||
{
|
||||
"include": "#common_variable"
|
||||
}
|
||||
],
|
||||
"repository": {
|
||||
"comments": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "(^[ \\t]+)?(?=//)",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "punctuation.whitespace.comment.leading.verilog"
|
||||
}
|
||||
},
|
||||
"end": "(?!\\G)",
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "//",
|
||||
"beginCaptures": {
|
||||
"0": {
|
||||
"name": "punctuation.definition.comment.verilog"
|
||||
}
|
||||
},
|
||||
"end": "\\n",
|
||||
"name": "comment.line.double-slash.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"begin": "/\\*",
|
||||
"end": "\\*/",
|
||||
"name": "comment.block.c-style.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"constants": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\b[0-9]+'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b",
|
||||
"name": "constant.numeric.sized_integer.verilog"
|
||||
},
|
||||
{
|
||||
"captures": {
|
||||
"1": {
|
||||
"name": "constant.numeric.integer.verilog"
|
||||
},
|
||||
"2": {
|
||||
"name": "punctuation.separator.range.verilog"
|
||||
},
|
||||
"3": {
|
||||
"name": "constant.numeric.integer.verilog"
|
||||
}
|
||||
},
|
||||
"match": "\\b(\\d+)(:)(\\d+)\\b",
|
||||
"name": "meta.block.numeric.range.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\b\\d+(?i:e\\d+)?\\b",
|
||||
"name": "constant.numeric.integer.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\b\\d+\\.\\d+(?i:e\\d+)?\\b",
|
||||
"name": "constant.numeric.real.verilog"
|
||||
},
|
||||
{
|
||||
"match": "#\\d+",
|
||||
"name": "constant.numeric.delay.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\b[01xXzZ]+\\b",
|
||||
"name": "constant.numeric.logic.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"instantiation_patterns": {
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#keywords"
|
||||
},
|
||||
{
|
||||
"begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "entity.name.class.module.reference.verilog"
|
||||
},
|
||||
"2": {
|
||||
"name": "entity.name.tag.module.identifier.verilog"
|
||||
}
|
||||
},
|
||||
"end": ";",
|
||||
"endCaptures": {
|
||||
"0": {
|
||||
"name": "punctuation.terminator.expression.verilog"
|
||||
}
|
||||
},
|
||||
"name": "meta.block.instantiation.parameterless.verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comments"
|
||||
},
|
||||
{
|
||||
"include": "#constants"
|
||||
},
|
||||
{
|
||||
"include": "#strings"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s*(#)(?=\\s*\\()",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "entity.name.class.module.reference.verilog"
|
||||
}
|
||||
},
|
||||
"end": ";",
|
||||
"endCaptures": {
|
||||
"0": {
|
||||
"name": "punctuation.terminator.expression.verilog"
|
||||
}
|
||||
},
|
||||
"name": "support.block.instantiation.with.parameters.verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#parenthetical_list"
|
||||
},
|
||||
{
|
||||
"match": "[a-zA-Z][a-zA-Z0-9_]*",
|
||||
"name": "entity.name.function.module.identifier.verilog"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"keywords": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|output|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
|
||||
"name": "keyword.other.verilog"
|
||||
},
|
||||
{
|
||||
"match": "^\\s*`((cell)?define|default_(decay_time|nettype|trireg_strength)|delay_mode_(path|unit|zero)|ifdef|include|end(if|celldefine)|else|(no)?unconnected_drive|resetall|timescale|undef)\\b",
|
||||
"name": "keyword.other.compiler.directive.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(f(open|close)|readmem(b|h)|timeformat|printtimescale|stop|finish|(s|real)?time|realtobits|bitstoreal|rtoi|itor|(f)?(display|write(h|b)))\\b",
|
||||
"name": "support.function.system.console.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(random|dist_(chi_square|erlang|exponential|normal|poisson|t|uniform))\\b",
|
||||
"name": "support.function.system.random_number.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$((a)?sync\\$((n)?and|(n)or)\\$(array|plane))\\b",
|
||||
"name": "support.function.system.pld_modeling.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(q_(initialize|add|remove|full|exam))\\b",
|
||||
"name": "support.function.system.stochastic.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(hold|nochange|period|recovery|setup(hold)?|skew|width)\\b",
|
||||
"name": "support.function.system.timing.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(dump(file|vars|off|on|all|limit|flush))\\b",
|
||||
"name": "support.function.system.vcd.tasks.verilog"
|
||||
},
|
||||
{
|
||||
"match": "\\$(countdrivers|list|input|scope|showscopes|(no)?(key|log)|reset(_count|_value)?|(inc)?save|restart|showvars|getpattern|sreadmem(b|h)|scale)",
|
||||
"name": "support.function.non-standard.tasks.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"module_pattern": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\\b(module)\\s+([a-zA-Z][a-zA-Z0-9_]*)",
|
||||
"beginCaptures": {
|
||||
"1": {
|
||||
"name": "storage.type.module.verilog"
|
||||
},
|
||||
"2": {
|
||||
"name": "entity.name.type.module.verilog"
|
||||
}
|
||||
},
|
||||
"end": "\\bendmodule\\b",
|
||||
"endCaptures": {
|
||||
"0": {
|
||||
"name": "storage.type.module.verilog"
|
||||
}
|
||||
},
|
||||
"name": "meta.block.module.verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#comments"
|
||||
},
|
||||
{
|
||||
"include": "#keywords"
|
||||
},
|
||||
{
|
||||
"include": "#constants"
|
||||
},
|
||||
{
|
||||
"include": "#strings"
|
||||
},
|
||||
{
|
||||
"include": "#instantiation_patterns"
|
||||
},
|
||||
{
|
||||
"include": "#operators"
|
||||
},
|
||||
{
|
||||
"include": "#position_ports"
|
||||
},
|
||||
{
|
||||
"include": "#macro_quote"
|
||||
},
|
||||
{
|
||||
"include": "#common_variable"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"operators": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\+|-|\\*|/|%|(<|>)=?|(!|=)?==?|!|&&?|\\|\\|?|\\^?~|~\\^?",
|
||||
"name": "keyword.operator.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"parenthetical_list": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\\(",
|
||||
"beginCaptures": {
|
||||
"0": {
|
||||
"name": "punctuation.section.list.verilog"
|
||||
}
|
||||
},
|
||||
"end": "\\)",
|
||||
"endCaptures": {
|
||||
"0": {
|
||||
"name": "punctuation.section.list.verilog"
|
||||
}
|
||||
},
|
||||
"name": "support.block.parenthetical_list.verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"include": "#parenthetical_list"
|
||||
},
|
||||
{
|
||||
"include": "#comments"
|
||||
},
|
||||
{
|
||||
"include": "#keywords"
|
||||
},
|
||||
{
|
||||
"include": "#constants"
|
||||
},
|
||||
{
|
||||
"include": "#strings"
|
||||
},
|
||||
{
|
||||
"include": "#position_ports"
|
||||
},
|
||||
{
|
||||
"include": "#macro_quote"
|
||||
},
|
||||
{
|
||||
"include": "#common_variable"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"position_ports": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\.[a-zA-Z_][a-zA-Z_0-9]*",
|
||||
"name": "variable.inst.port.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"strings": {
|
||||
"patterns": [
|
||||
{
|
||||
"begin": "\"",
|
||||
"end": "\"",
|
||||
"name": "string.quoted.double.verilog",
|
||||
"patterns": [
|
||||
{
|
||||
"match": "\\\\.",
|
||||
"name": "constant.character.escape.verilog"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
"macro_definition": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "(?<=`define\\s)\\w+",
|
||||
"name": "support.function.macro.definition.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"macro_quote": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "`[a-zA-Z_][a-zA-Z_0-9]*",
|
||||
"name": "support.function.macro.quote.verilog"
|
||||
}
|
||||
]
|
||||
},
|
||||
"common_variable": {
|
||||
"patterns": [
|
||||
{
|
||||
"match": "[a-zA-Z_][a-zA-Z_0-9]*",
|
||||
"name": "variable.other.constant.verilog"
|
||||
}
|
||||
]
|
||||
}
|
||||
},
|
||||
"scopeName": "source.verilog",
|
||||
"uuid": "7F4396B3-A33E-44F0-8502-98CA6C25971F"
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user